Adding 72 MHz clock support for mk20dx256vlh7

diff --git a/Lib/CMake/arm.cmake b/Lib/CMake/arm.cmake
index 3efbe7c0169955ae1ec45bd9b08881e300def093..be04de2afe4eb46d7cc979b71fc5c919d7945020 100644 (file)
--- a/Lib/CMake/arm.cmake
+++ b/Lib/CMake/arm.cmake
@@ -46,26 +46,35 @@ message( "${CHIP}" )
 set( MCU "${CHIP}" ) # For loading script compatibility
 
 
 set( MCU "${CHIP}" ) # For loading script compatibility
 
 

-#| Chip Size Database
+#| Chip Size and CPU Frequency Database
+#| Processor frequency.
+#|   Normally the first thing your program should do is set the clock prescaler,
+#|   so your program will run at the correct speed.  You should also set this
+#|   variable to same clock speed.  The _delay_ms() macro uses this, and many
+#|   examples use this variable to calculate timings.  Do not add a "UL" here.

 #| MCHCK Based / Kiibohd-dfu
 if ( "${CHIP}" MATCHES "mk20dx128vlf5" )
        set( SIZE_RAM    16384 )
        set( SIZE_FLASH 126976 )
 #| MCHCK Based / Kiibohd-dfu
 if ( "${CHIP}" MATCHES "mk20dx128vlf5" )
        set( SIZE_RAM    16384 )
        set( SIZE_FLASH 126976 )

+       set( F_CPU "48000000" )

 
 #| Kiibohd-dfu
 elseif ( "${CHIP}" MATCHES "mk20dx256vlh7" )
        set( SIZE_RAM    65536 )
        set( SIZE_FLASH 253952 )
 
 #| Kiibohd-dfu
 elseif ( "${CHIP}" MATCHES "mk20dx256vlh7" )
        set( SIZE_RAM    65536 )
        set( SIZE_FLASH 253952 )

+       set( F_CPU "72000000" )

 
 #| Teensy 3.0
 elseif ( "${CHIP}" MATCHES "mk20dx128" )
        set( SIZE_RAM    16384 )
        set( SIZE_FLASH 131072 )
 
 #| Teensy 3.0
 elseif ( "${CHIP}" MATCHES "mk20dx128" )
        set( SIZE_RAM    16384 )
        set( SIZE_FLASH 131072 )

+       set( F_CPU "48000000" )

 
 #| Teensy 3.1
 elseif ( "${CHIP}" MATCHES "mk20dx256" )
        set( SIZE_RAM    65536 )
        set( SIZE_FLASH 262144 )
 
 #| Teensy 3.1
 elseif ( "${CHIP}" MATCHES "mk20dx256" )
        set( SIZE_RAM    65536 )
        set( SIZE_FLASH 262144 )

+       set( F_CPU "48000000" ) # XXX Also supports 72 MHz, but may requires code changes

 
 #| Unknown ARM
 else ()
 
 #| Unknown ARM
 else ()


@@ -159,14 +168,6 @@ endif()
 set( OPT "s" )
 
 
 set( OPT "s" )
 
 

-#| Processor frequency.
-#|   Normally the first thing your program should do is set the clock prescaler,
-#|   so your program will run at the correct speed.  You should also set this
-#|   variable to same clock speed.  The _delay_ms() macro uses this, and many
-#|   examples use this variable to calculate timings.  Do not add a "UL" here.
-set( F_CPU "48000000" )
-
-

 #| Dependency Files
 #| Compiler flags to generate dependency files.
 set( GENDEPFLAGS "-MMD" )
 #| Dependency Files
 #| Compiler flags to generate dependency files.
 set( GENDEPFLAGS "-MMD" )

diff --git a/Lib/delay.h b/Lib/delay.h
index 17b62cc911b82eb6ff3947636db47e5df65cc501..992fcdac8e94695fdd4d11bd7280eeb305e11413 100644 (file)
--- a/Lib/delay.h
+++ b/Lib/delay.h
@@ -63,6 +63,8 @@ static inline void delayMicroseconds(uint32_t usec)
 {
 #if F_CPU == 96000000
        uint32_t n = usec << 5;
 {
 #if F_CPU == 96000000
        uint32_t n = usec << 5;

+#elif F_CPU == 72000000
+       uint32_t n = usec << 5; // XXX Not accurate, assembly snippet needs to be updated

 #elif F_CPU == 48000000
        uint32_t n = usec << 4;
 #elif F_CPU == 24000000
 #elif F_CPU == 48000000
        uint32_t n = usec << 4;
 #elif F_CPU == 24000000

diff --git a/Lib/mk20dx.c b/Lib/mk20dx.c
index eb45b9727dac5f698932c1e8c7f87818a97ba3ea..1fa3e1510719b8a7c5740bc12ef08c8a8f129ab1 100644 (file)
--- a/Lib/mk20dx.c
+++ b/Lib/mk20dx.c
@@ -572,11 +572,21 @@ void ResetHandler()
        while ( (MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST( 2 ) );
 
        // now we're in FBE mode
        while ( (MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST( 2 ) );
 
        // now we're in FBE mode

+#if F_CPU == 72000000
+       // config PLL input for 16 MHz Crystal / 8 = 2 MHz
+       MCG_C5 = MCG_C5_PRDIV0( 7 );
+#else

        // config PLL input for 16 MHz Crystal / 4 = 4 MHz
        MCG_C5 = MCG_C5_PRDIV0( 3 );
        // config PLL input for 16 MHz Crystal / 4 = 4 MHz
        MCG_C5 = MCG_C5_PRDIV0( 3 );

+#endif

 
 

+#if F_CPU == 72000000
+       // config PLL for 72 MHz output (36 * 2 MHz Ext PLL)
+       MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0( 12 );
+#else

        // config PLL for 96 MHz output
        MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0( 0 );
        // config PLL for 96 MHz output
        MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0( 0 );

+#endif

 
        // wait for PLL to start using xtal as its input
        while ( !(MCG_S & MCG_S_PLLST) );
 
        // wait for PLL to start using xtal as its input
        while ( !(MCG_S & MCG_S_PLLST) );


@@ -588,6 +598,9 @@ void ResetHandler()
 #if F_CPU == 96000000
        // config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash
        SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 0 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 3 );
 #if F_CPU == 96000000
        // config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash
        SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 0 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 3 );

+#elif F_CPU == 72000000
+       // config divisors: 72 MHz core, 36 MHz bus, 24 MHz flash
+       SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 0 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 2 );

 #elif F_CPU == 48000000
        // config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash
        SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 1 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 3 );
 #elif F_CPU == 48000000
        // config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash
        SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 1 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 3 );


@@ -595,7 +608,7 @@ void ResetHandler()
        // config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash
        SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 3 ) | SIM_CLKDIV1_OUTDIV2( 3 ) | SIM_CLKDIV1_OUTDIV4( 3 );
 #else
        // config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash
        SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 3 ) | SIM_CLKDIV1_OUTDIV2( 3 ) | SIM_CLKDIV1_OUTDIV4( 3 );
 #else

-#error "Error, F_CPU must be 96000000, 48000000, or 24000000"
+#error "Error, F_CPU must be 96000000, 72000000, 48000000, or 24000000"

 #endif
        // switch to PLL as clock source, FLL input = 16 MHz / 512
        MCG_C1 = MCG_C1_CLKS( 0 ) | MCG_C1_FRDIV( 4 );
 #endif
        // switch to PLL as clock source, FLL input = 16 MHz / 512
        MCG_C1 = MCG_C1_CLKS( 0 ) | MCG_C1_FRDIV( 4 );


@@ -604,8 +617,13 @@ void ResetHandler()
        while ( (MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST( 3 ) );
 
        // now we're in PEE mode
        while ( (MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST( 3 ) );
 
        // now we're in PEE mode

+#if F_CPU == 72000000
+       // configure USB for 48 MHz clock
+       SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV( 2 ) | SIM_CLKDIV2_USBFRAC; // USB = 72 MHz PLL / 1.5
+#else

        // configure USB for 48 MHz clock
        SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV( 1 ); // USB = 96 MHz PLL / 2
        // configure USB for 48 MHz clock
        SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV( 1 ); // USB = 96 MHz PLL / 2

+#endif

 
        // USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0
        SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL( 6 );
 
        // USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0
        SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL( 6 );

diff --git a/Lib/mk20dx.h b/Lib/mk20dx.h
index a8433636d3dd1922a86cd99cca47b9833d29e3c2..0109f7f0d3f2babbd3411fc149bcef3a1a234577 100644 (file)
--- a/Lib/mk20dx.h
+++ b/Lib/mk20dx.h
@@ -35,14 +35,17 @@
 // ----- Defines -----
 
 #if (F_CPU == 96000000)
 // ----- Defines -----
 
 #if (F_CPU == 96000000)

- #define F_BUS 48000000
- #define F_MEM 24000000
+       #define F_BUS 48000000
+       #define F_MEM 24000000
+#elif (F_CPU == 72000000)
+       #define F_BUS 36000000
+       #define F_MEM 24000000

 #elif (F_CPU == 48000000)
 #elif (F_CPU == 48000000)

- #define F_BUS 48000000
- #define F_MEM 24000000
+       #define F_BUS 48000000
+       #define F_MEM 24000000

 #elif (F_CPU == 24000000)
 #elif (F_CPU == 24000000)

- #define F_BUS 24000000
- #define F_MEM 24000000
+       #define F_BUS 24000000
+       #define F_MEM 24000000

 #endif
 
 
 #endif