4 //#define F_CPU 96000000
5 //#define F_CPU 48000000
6 //#define F_CPU 24000000
7 //#define F_BUS 48000000
8 //#define F_BUS 24000000
9 //#define F_MEM 24000000
11 #if (F_CPU == 96000000)
12 #define F_BUS 48000000
13 #define F_MEM 24000000
14 #elif (F_CPU == 48000000)
15 #define F_BUS 48000000
16 #define F_MEM 24000000
17 #elif (F_CPU == 24000000)
18 #define F_BUS 24000000
19 #define F_MEM 24000000
24 #define NULL ((void *)0)
32 // chapter 11: Port control and interrupts (PORT)
33 #define PORTA_PCR0 *(volatile uint32_t *)0x40049000 // Pin Control Register n
34 #define PORT_PCR_ISF (uint32_t)0x01000000 // Interrupt Status Flag
35 #define PORT_PCR_IRQC(n) (uint32_t)(((n) & 15) << 16) // Interrupt Configuration
36 #define PORT_PCR_IRQC_MASK (uint32_t)0x000F0000
37 #define PORT_PCR_LK (uint32_t)0x00008000 // Lock Register
38 #define PORT_PCR_MUX(n) (uint32_t)(((n) & 7) << 8) // Pin Mux Control
39 #define PORT_PCR_MUX_MASK (uint32_t)0x00000700
40 #define PORT_PCR_DSE (uint32_t)0x00000040 // Drive Strength Enable
41 #define PORT_PCR_ODE (uint32_t)0x00000020 // Open Drain Enable
42 #define PORT_PCR_PFE (uint32_t)0x00000010 // Passive Filter Enable
43 #define PORT_PCR_SRE (uint32_t)0x00000004 // Slew Rate Enable
44 #define PORT_PCR_PE (uint32_t)0x00000002 // Pull Enable
45 #define PORT_PCR_PS (uint32_t)0x00000001 // Pull Select
46 #define PORTA_PCR1 *(volatile uint32_t *)0x40049004 // Pin Control Register n
47 #define PORTA_PCR2 *(volatile uint32_t *)0x40049008 // Pin Control Register n
48 #define PORTA_PCR3 *(volatile uint32_t *)0x4004900C // Pin Control Register n
49 #define PORTA_PCR4 *(volatile uint32_t *)0x40049010 // Pin Control Register n
50 #define PORTA_PCR5 *(volatile uint32_t *)0x40049014 // Pin Control Register n
51 #define PORTA_PCR6 *(volatile uint32_t *)0x40049018 // Pin Control Register n
52 #define PORTA_PCR7 *(volatile uint32_t *)0x4004901C // Pin Control Register n
53 #define PORTA_PCR8 *(volatile uint32_t *)0x40049020 // Pin Control Register n
54 #define PORTA_PCR9 *(volatile uint32_t *)0x40049024 // Pin Control Register n
55 #define PORTA_PCR10 *(volatile uint32_t *)0x40049028 // Pin Control Register n
56 #define PORTA_PCR11 *(volatile uint32_t *)0x4004902C // Pin Control Register n
57 #define PORTA_PCR12 *(volatile uint32_t *)0x40049030 // Pin Control Register n
58 #define PORTA_PCR13 *(volatile uint32_t *)0x40049034 // Pin Control Register n
59 #define PORTA_PCR14 *(volatile uint32_t *)0x40049038 // Pin Control Register n
60 #define PORTA_PCR15 *(volatile uint32_t *)0x4004903C // Pin Control Register n
61 #define PORTA_PCR16 *(volatile uint32_t *)0x40049040 // Pin Control Register n
62 #define PORTA_PCR17 *(volatile uint32_t *)0x40049044 // Pin Control Register n
63 #define PORTA_PCR18 *(volatile uint32_t *)0x40049048 // Pin Control Register n
64 #define PORTA_PCR19 *(volatile uint32_t *)0x4004904C // Pin Control Register n
65 #define PORTA_PCR20 *(volatile uint32_t *)0x40049050 // Pin Control Register n
66 #define PORTA_PCR21 *(volatile uint32_t *)0x40049054 // Pin Control Register n
67 #define PORTA_PCR22 *(volatile uint32_t *)0x40049058 // Pin Control Register n
68 #define PORTA_PCR23 *(volatile uint32_t *)0x4004905C // Pin Control Register n
69 #define PORTA_PCR24 *(volatile uint32_t *)0x40049060 // Pin Control Register n
70 #define PORTA_PCR25 *(volatile uint32_t *)0x40049064 // Pin Control Register n
71 #define PORTA_PCR26 *(volatile uint32_t *)0x40049068 // Pin Control Register n
72 #define PORTA_PCR27 *(volatile uint32_t *)0x4004906C // Pin Control Register n
73 #define PORTA_PCR28 *(volatile uint32_t *)0x40049070 // Pin Control Register n
74 #define PORTA_PCR29 *(volatile uint32_t *)0x40049074 // Pin Control Register n
75 #define PORTA_PCR30 *(volatile uint32_t *)0x40049078 // Pin Control Register n
76 #define PORTA_PCR31 *(volatile uint32_t *)0x4004907C // Pin Control Register n
77 #define PORTA_GPCLR *(volatile uint32_t *)0x40049080 // Global Pin Control Low Register
78 #define PORTA_GPCHR *(volatile uint32_t *)0x40049084 // Global Pin Control High Register
79 #define PORTA_ISFR *(volatile uint32_t *)0x400490A0 // Interrupt Status Flag Register
80 #define PORTB_PCR0 *(volatile uint32_t *)0x4004A000 // Pin Control Register n
81 #define PORTB_PCR1 *(volatile uint32_t *)0x4004A004 // Pin Control Register n
82 #define PORTB_PCR2 *(volatile uint32_t *)0x4004A008 // Pin Control Register n
83 #define PORTB_PCR3 *(volatile uint32_t *)0x4004A00C // Pin Control Register n
84 #define PORTB_PCR4 *(volatile uint32_t *)0x4004A010 // Pin Control Register n
85 #define PORTB_PCR5 *(volatile uint32_t *)0x4004A014 // Pin Control Register n
86 #define PORTB_PCR6 *(volatile uint32_t *)0x4004A018 // Pin Control Register n
87 #define PORTB_PCR7 *(volatile uint32_t *)0x4004A01C // Pin Control Register n
88 #define PORTB_PCR8 *(volatile uint32_t *)0x4004A020 // Pin Control Register n
89 #define PORTB_PCR9 *(volatile uint32_t *)0x4004A024 // Pin Control Register n
90 #define PORTB_PCR10 *(volatile uint32_t *)0x4004A028 // Pin Control Register n
91 #define PORTB_PCR11 *(volatile uint32_t *)0x4004A02C // Pin Control Register n
92 #define PORTB_PCR12 *(volatile uint32_t *)0x4004A030 // Pin Control Register n
93 #define PORTB_PCR13 *(volatile uint32_t *)0x4004A034 // Pin Control Register n
94 #define PORTB_PCR14 *(volatile uint32_t *)0x4004A038 // Pin Control Register n
95 #define PORTB_PCR15 *(volatile uint32_t *)0x4004A03C // Pin Control Register n
96 #define PORTB_PCR16 *(volatile uint32_t *)0x4004A040 // Pin Control Register n
97 #define PORTB_PCR17 *(volatile uint32_t *)0x4004A044 // Pin Control Register n
98 #define PORTB_PCR18 *(volatile uint32_t *)0x4004A048 // Pin Control Register n
99 #define PORTB_PCR19 *(volatile uint32_t *)0x4004A04C // Pin Control Register n
100 #define PORTB_PCR20 *(volatile uint32_t *)0x4004A050 // Pin Control Register n
101 #define PORTB_PCR21 *(volatile uint32_t *)0x4004A054 // Pin Control Register n
102 #define PORTB_PCR22 *(volatile uint32_t *)0x4004A058 // Pin Control Register n
103 #define PORTB_PCR23 *(volatile uint32_t *)0x4004A05C // Pin Control Register n
104 #define PORTB_PCR24 *(volatile uint32_t *)0x4004A060 // Pin Control Register n
105 #define PORTB_PCR25 *(volatile uint32_t *)0x4004A064 // Pin Control Register n
106 #define PORTB_PCR26 *(volatile uint32_t *)0x4004A068 // Pin Control Register n
107 #define PORTB_PCR27 *(volatile uint32_t *)0x4004A06C // Pin Control Register n
108 #define PORTB_PCR28 *(volatile uint32_t *)0x4004A070 // Pin Control Register n
109 #define PORTB_PCR29 *(volatile uint32_t *)0x4004A074 // Pin Control Register n
110 #define PORTB_PCR30 *(volatile uint32_t *)0x4004A078 // Pin Control Register n
111 #define PORTB_PCR31 *(volatile uint32_t *)0x4004A07C // Pin Control Register n
112 #define PORTB_GPCLR *(volatile uint32_t *)0x4004A080 // Global Pin Control Low Register
113 #define PORTB_GPCHR *(volatile uint32_t *)0x4004A084 // Global Pin Control High Register
114 #define PORTB_ISFR *(volatile uint32_t *)0x4004A0A0 // Interrupt Status Flag Register
115 #define PORTC_PCR0 *(volatile uint32_t *)0x4004B000 // Pin Control Register n
116 #define PORTC_PCR1 *(volatile uint32_t *)0x4004B004 // Pin Control Register n
117 #define PORTC_PCR2 *(volatile uint32_t *)0x4004B008 // Pin Control Register n
118 #define PORTC_PCR3 *(volatile uint32_t *)0x4004B00C // Pin Control Register n
119 #define PORTC_PCR4 *(volatile uint32_t *)0x4004B010 // Pin Control Register n
120 #define PORTC_PCR5 *(volatile uint32_t *)0x4004B014 // Pin Control Register n
121 #define PORTC_PCR6 *(volatile uint32_t *)0x4004B018 // Pin Control Register n
122 #define PORTC_PCR7 *(volatile uint32_t *)0x4004B01C // Pin Control Register n
123 #define PORTC_PCR8 *(volatile uint32_t *)0x4004B020 // Pin Control Register n
124 #define PORTC_PCR9 *(volatile uint32_t *)0x4004B024 // Pin Control Register n
125 #define PORTC_PCR10 *(volatile uint32_t *)0x4004B028 // Pin Control Register n
126 #define PORTC_PCR11 *(volatile uint32_t *)0x4004B02C // Pin Control Register n
127 #define PORTC_PCR12 *(volatile uint32_t *)0x4004B030 // Pin Control Register n
128 #define PORTC_PCR13 *(volatile uint32_t *)0x4004B034 // Pin Control Register n
129 #define PORTC_PCR14 *(volatile uint32_t *)0x4004B038 // Pin Control Register n
130 #define PORTC_PCR15 *(volatile uint32_t *)0x4004B03C // Pin Control Register n
131 #define PORTC_PCR16 *(volatile uint32_t *)0x4004B040 // Pin Control Register n
132 #define PORTC_PCR17 *(volatile uint32_t *)0x4004B044 // Pin Control Register n
133 #define PORTC_PCR18 *(volatile uint32_t *)0x4004B048 // Pin Control Register n
134 #define PORTC_PCR19 *(volatile uint32_t *)0x4004B04C // Pin Control Register n
135 #define PORTC_PCR20 *(volatile uint32_t *)0x4004B050 // Pin Control Register n
136 #define PORTC_PCR21 *(volatile uint32_t *)0x4004B054 // Pin Control Register n
137 #define PORTC_PCR22 *(volatile uint32_t *)0x4004B058 // Pin Control Register n
138 #define PORTC_PCR23 *(volatile uint32_t *)0x4004B05C // Pin Control Register n
139 #define PORTC_PCR24 *(volatile uint32_t *)0x4004B060 // Pin Control Register n
140 #define PORTC_PCR25 *(volatile uint32_t *)0x4004B064 // Pin Control Register n
141 #define PORTC_PCR26 *(volatile uint32_t *)0x4004B068 // Pin Control Register n
142 #define PORTC_PCR27 *(volatile uint32_t *)0x4004B06C // Pin Control Register n
143 #define PORTC_PCR28 *(volatile uint32_t *)0x4004B070 // Pin Control Register n
144 #define PORTC_PCR29 *(volatile uint32_t *)0x4004B074 // Pin Control Register n
145 #define PORTC_PCR30 *(volatile uint32_t *)0x4004B078 // Pin Control Register n
146 #define PORTC_PCR31 *(volatile uint32_t *)0x4004B07C // Pin Control Register n
147 #define PORTC_GPCLR *(volatile uint32_t *)0x4004B080 // Global Pin Control Low Register
148 #define PORTC_GPCHR *(volatile uint32_t *)0x4004B084 // Global Pin Control High Register
149 #define PORTC_ISFR *(volatile uint32_t *)0x4004B0A0 // Interrupt Status Flag Register
150 #define PORTD_PCR0 *(volatile uint32_t *)0x4004C000 // Pin Control Register n
151 #define PORTD_PCR1 *(volatile uint32_t *)0x4004C004 // Pin Control Register n
152 #define PORTD_PCR2 *(volatile uint32_t *)0x4004C008 // Pin Control Register n
153 #define PORTD_PCR3 *(volatile uint32_t *)0x4004C00C // Pin Control Register n
154 #define PORTD_PCR4 *(volatile uint32_t *)0x4004C010 // Pin Control Register n
155 #define PORTD_PCR5 *(volatile uint32_t *)0x4004C014 // Pin Control Register n
156 #define PORTD_PCR6 *(volatile uint32_t *)0x4004C018 // Pin Control Register n
157 #define PORTD_PCR7 *(volatile uint32_t *)0x4004C01C // Pin Control Register n
158 #define PORTD_PCR8 *(volatile uint32_t *)0x4004C020 // Pin Control Register n
159 #define PORTD_PCR9 *(volatile uint32_t *)0x4004C024 // Pin Control Register n
160 #define PORTD_PCR10 *(volatile uint32_t *)0x4004C028 // Pin Control Register n
161 #define PORTD_PCR11 *(volatile uint32_t *)0x4004C02C // Pin Control Register n
162 #define PORTD_PCR12 *(volatile uint32_t *)0x4004C030 // Pin Control Register n
163 #define PORTD_PCR13 *(volatile uint32_t *)0x4004C034 // Pin Control Register n
164 #define PORTD_PCR14 *(volatile uint32_t *)0x4004C038 // Pin Control Register n
165 #define PORTD_PCR15 *(volatile uint32_t *)0x4004C03C // Pin Control Register n
166 #define PORTD_PCR16 *(volatile uint32_t *)0x4004C040 // Pin Control Register n
167 #define PORTD_PCR17 *(volatile uint32_t *)0x4004C044 // Pin Control Register n
168 #define PORTD_PCR18 *(volatile uint32_t *)0x4004C048 // Pin Control Register n
169 #define PORTD_PCR19 *(volatile uint32_t *)0x4004C04C // Pin Control Register n
170 #define PORTD_PCR20 *(volatile uint32_t *)0x4004C050 // Pin Control Register n
171 #define PORTD_PCR21 *(volatile uint32_t *)0x4004C054 // Pin Control Register n
172 #define PORTD_PCR22 *(volatile uint32_t *)0x4004C058 // Pin Control Register n
173 #define PORTD_PCR23 *(volatile uint32_t *)0x4004C05C // Pin Control Register n
174 #define PORTD_PCR24 *(volatile uint32_t *)0x4004C060 // Pin Control Register n
175 #define PORTD_PCR25 *(volatile uint32_t *)0x4004C064 // Pin Control Register n
176 #define PORTD_PCR26 *(volatile uint32_t *)0x4004C068 // Pin Control Register n
177 #define PORTD_PCR27 *(volatile uint32_t *)0x4004C06C // Pin Control Register n
178 #define PORTD_PCR28 *(volatile uint32_t *)0x4004C070 // Pin Control Register n
179 #define PORTD_PCR29 *(volatile uint32_t *)0x4004C074 // Pin Control Register n
180 #define PORTD_PCR30 *(volatile uint32_t *)0x4004C078 // Pin Control Register n
181 #define PORTD_PCR31 *(volatile uint32_t *)0x4004C07C // Pin Control Register n
182 #define PORTD_GPCLR *(volatile uint32_t *)0x4004C080 // Global Pin Control Low Register
183 #define PORTD_GPCHR *(volatile uint32_t *)0x4004C084 // Global Pin Control High Register
184 #define PORTD_ISFR *(volatile uint32_t *)0x4004C0A0 // Interrupt Status Flag Register
185 #define PORTE_PCR0 *(volatile uint32_t *)0x4004D000 // Pin Control Register n
186 #define PORTE_PCR1 *(volatile uint32_t *)0x4004D004 // Pin Control Register n
187 #define PORTE_PCR2 *(volatile uint32_t *)0x4004D008 // Pin Control Register n
188 #define PORTE_PCR3 *(volatile uint32_t *)0x4004D00C // Pin Control Register n
189 #define PORTE_PCR4 *(volatile uint32_t *)0x4004D010 // Pin Control Register n
190 #define PORTE_PCR5 *(volatile uint32_t *)0x4004D014 // Pin Control Register n
191 #define PORTE_PCR6 *(volatile uint32_t *)0x4004D018 // Pin Control Register n
192 #define PORTE_PCR7 *(volatile uint32_t *)0x4004D01C // Pin Control Register n
193 #define PORTE_PCR8 *(volatile uint32_t *)0x4004D020 // Pin Control Register n
194 #define PORTE_PCR9 *(volatile uint32_t *)0x4004D024 // Pin Control Register n
195 #define PORTE_PCR10 *(volatile uint32_t *)0x4004D028 // Pin Control Register n
196 #define PORTE_PCR11 *(volatile uint32_t *)0x4004D02C // Pin Control Register n
197 #define PORTE_PCR12 *(volatile uint32_t *)0x4004D030 // Pin Control Register n
198 #define PORTE_PCR13 *(volatile uint32_t *)0x4004D034 // Pin Control Register n
199 #define PORTE_PCR14 *(volatile uint32_t *)0x4004D038 // Pin Control Register n
200 #define PORTE_PCR15 *(volatile uint32_t *)0x4004D03C // Pin Control Register n
201 #define PORTE_PCR16 *(volatile uint32_t *)0x4004D040 // Pin Control Register n
202 #define PORTE_PCR17 *(volatile uint32_t *)0x4004D044 // Pin Control Register n
203 #define PORTE_PCR18 *(volatile uint32_t *)0x4004D048 // Pin Control Register n
204 #define PORTE_PCR19 *(volatile uint32_t *)0x4004D04C // Pin Control Register n
205 #define PORTE_PCR20 *(volatile uint32_t *)0x4004D050 // Pin Control Register n
206 #define PORTE_PCR21 *(volatile uint32_t *)0x4004D054 // Pin Control Register n
207 #define PORTE_PCR22 *(volatile uint32_t *)0x4004D058 // Pin Control Register n
208 #define PORTE_PCR23 *(volatile uint32_t *)0x4004D05C // Pin Control Register n
209 #define PORTE_PCR24 *(volatile uint32_t *)0x4004D060 // Pin Control Register n
210 #define PORTE_PCR25 *(volatile uint32_t *)0x4004D064 // Pin Control Register n
211 #define PORTE_PCR26 *(volatile uint32_t *)0x4004D068 // Pin Control Register n
212 #define PORTE_PCR27 *(volatile uint32_t *)0x4004D06C // Pin Control Register n
213 #define PORTE_PCR28 *(volatile uint32_t *)0x4004D070 // Pin Control Register n
214 #define PORTE_PCR29 *(volatile uint32_t *)0x4004D074 // Pin Control Register n
215 #define PORTE_PCR30 *(volatile uint32_t *)0x4004D078 // Pin Control Register n
216 #define PORTE_PCR31 *(volatile uint32_t *)0x4004D07C // Pin Control Register n
217 #define PORTE_GPCLR *(volatile uint32_t *)0x4004D080 // Global Pin Control Low Register
218 #define PORTE_GPCHR *(volatile uint32_t *)0x4004D084 // Global Pin Control High Register
219 #define PORTE_ISFR *(volatile uint32_t *)0x4004D0A0 // Interrupt Status Flag Register
221 // Chapter 12: System Integration Module (SIM)
222 #define SIM_SOPT1 *(volatile uint32_t *)0x40047000 // System Options Register 1
223 #define SIM_SOPT1CFG *(volatile uint32_t *)0x40047004 // SOPT1 Configuration Register
224 #define SIM_SOPT2 *(volatile uint32_t *)0x40048004 // System Options Register 2
225 #define SIM_SOPT2_USBSRC (uint32_t)0x00040000 // 0=USB_CLKIN, 1=FFL/PLL
226 #define SIM_SOPT2_PLLFLLSEL (uint32_t)0x00010000 // 0=FLL, 1=PLL
227 #define SIM_SOPT2_TRACECLKSEL (uint32_t)0x00001000 // 0=MCGOUTCLK, 1=CPU
228 #define SIM_SOPT2_PTD7PAD (uint32_t)0x00000800 // 0=normal, 1=double drive PTD7
229 #define SIM_SOPT2_CLKOUTSEL(n) (uint32_t)(((n) & 7) << 5) // Selects the clock to output on the CLKOUT pin.
230 #define SIM_SOPT2_RTCCLKOUTSEL (uint32_t)0x00000010 // RTC clock out select
231 #define SIM_SOPT4 *(volatile uint32_t *)0x4004800C // System Options Register 4
232 #define SIM_SOPT5 *(volatile uint32_t *)0x40048010 // System Options Register 5
233 #define SIM_SOPT7 *(volatile uint32_t *)0x40048018 // System Options Register 7
234 #define SIM_SDID *(const uint32_t *)0x40048024 // System Device Identification Register
235 #define SIM_SCGC4 *(volatile uint32_t *)0x40048034 // System Clock Gating Control Register 4
236 #define SIM_SCGC4_VREF (uint32_t)0x00100000 // VREF Clock Gate Control
237 #define SIM_SCGC4_CMP (uint32_t)0x00080000 // Comparator Clock Gate Control
238 #define SIM_SCGC4_USBOTG (uint32_t)0x00040000 // USB Clock Gate Control
239 #define SIM_SCGC4_UART2 (uint32_t)0x00001000 // UART2 Clock Gate Control
240 #define SIM_SCGC4_UART1 (uint32_t)0x00000800 // UART1 Clock Gate Control
241 #define SIM_SCGC4_UART0 (uint32_t)0x00000400 // UART0 Clock Gate Control
242 #define SIM_SCGC4_I2C0 (uint32_t)0x00000040 // I2C0 Clock Gate Control
243 #define SIM_SCGC4_CMT (uint32_t)0x00000004 // CMT Clock Gate Control
244 #define SIM_SCGC4_EWM (uint32_t)0x00000002 // EWM Clock Gate Control
245 #define SIM_SCGC5 *(volatile uint32_t *)0x40048038 // System Clock Gating Control Register 5
246 #define SIM_SCGC5_PORTE (uint32_t)0x00002000 // Port E Clock Gate Control
247 #define SIM_SCGC5_PORTD (uint32_t)0x00001000 // Port D Clock Gate Control
248 #define SIM_SCGC5_PORTC (uint32_t)0x00000800 // Port C Clock Gate Control
249 #define SIM_SCGC5_PORTB (uint32_t)0x00000400 // Port B Clock Gate Control
250 #define SIM_SCGC5_PORTA (uint32_t)0x00000200 // Port A Clock Gate Control
251 #define SIM_SCGC5_TSI (uint32_t)0x00000020 // Touch Sense Input TSI Clock Gate Control
252 #define SIM_SCGC5_LPTIMER (uint32_t)0x00000001 // Low Power Timer Access Control
253 #define SIM_SCGC6 *(volatile uint32_t *)0x4004803C // System Clock Gating Control Register 6
254 #define SIM_SCGC6_RTC (uint32_t)0x20000000 // RTC Access
255 #define SIM_SCGC6_ADC0 (uint32_t)0x08000000 // ADC0 Clock Gate Control
256 #define SIM_SCGC6_FTM1 (uint32_t)0x02000000 // FTM1 Clock Gate Control
257 #define SIM_SCGC6_FTM0 (uint32_t)0x01000000 // FTM0 Clock Gate Control
258 #define SIM_SCGC6_PIT (uint32_t)0x00800000 // PIT Clock Gate Control
259 #define SIM_SCGC6_PDB (uint32_t)0x00400000 // PDB Clock Gate Control
260 #define SIM_SCGC6_USBDCD (uint32_t)0x00200000 // USB DCD Clock Gate Control
261 #define SIM_SCGC6_CRC (uint32_t)0x00040000 // CRC Clock Gate Control
262 #define SIM_SCGC6_I2S (uint32_t)0x00008000 // I2S Clock Gate Control
263 #define SIM_SCGC6_SPI0 (uint32_t)0x00001000 // SPI0 Clock Gate Control
264 #define SIM_SCGC6_DMAMUX (uint32_t)0x00000002 // DMA Mux Clock Gate Control
265 #define SIM_SCGC6_FTFL (uint32_t)0x00000001 // Flash Memory Clock Gate Control
266 #define SIM_SCGC7 *(volatile uint32_t *)0x40048040 // System Clock Gating Control Register 7
267 #define SIM_CLKDIV1 *(volatile uint32_t *)0x40048044 // System Clock Divider Register 1
268 #define SIM_CLKDIV1_OUTDIV1(n) (uint32_t)(((n) & 0x0F) << 28) // divide value for the core/system clock
269 #define SIM_CLKDIV1_OUTDIV2(n) (uint32_t)(((n) & 0x0F) << 24) // divide value for the peripheral clock
270 #define SIM_CLKDIV1_OUTDIV4(n) (uint32_t)(((n) & 0x0F) << 16) // divide value for the flash clock
271 #define SIM_CLKDIV2 *(volatile uint32_t *)0x40048048 // System Clock Divider Register 2
272 #define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1)
273 #define SIM_CLKDIV2_USBFRAC (uint32_t)0x01
274 #define SIM_FCFG1 *(const uint32_t *)0x4004804C // Flash Configuration Register 1
275 #define SIM_FCFG2 *(const uint32_t *)0x40048050 // Flash Configuration Register 2
276 #define SIM_UIDH *(const uint32_t *)0x40048054 // Unique Identification Register High
277 #define SIM_UIDMH *(const uint32_t *)0x40048058 // Unique Identification Register Mid-High
278 #define SIM_UIDML *(const uint32_t *)0x4004805C // Unique Identification Register Mid Low
279 #define SIM_UIDL *(const uint32_t *)0x40048060 // Unique Identification Register Low
281 // Chapter 13: Reset Control Module (RCM)
282 #define RCM_SRS0 *(volatile uint8_t *)0x4007F000 // System Reset Status Register 0
283 #define RCM_SRS1 *(volatile uint8_t *)0x4007F001 // System Reset Status Register 1
284 #define RCM_RPFC *(volatile uint8_t *)0x4007F004 // Reset Pin Filter Control Register
285 #define RCM_RPFW *(volatile uint8_t *)0x4007F005 // Reset Pin Filter Width Register
286 #define RCM_MR *(volatile uint8_t *)0x4007F007 // Mode Register
288 // Chapter 14: System Mode Controller
289 #define SMC_PMPROT *(volatile uint8_t *)0x4007E000 // Power Mode Protection Register
290 #define SMC_PMCTRL *(volatile uint8_t *)0x4007E001 // Power Mode Control Register
291 #define SMC_VLLSCTRL *(volatile uint8_t *)0x4007E002 // VLLS Control Register
292 #define SMC_PMSTAT *(volatile uint8_t *)0x4007E003 // Power Mode Status Register
294 // Chapter 15: Power Management Controller
295 #define PMC_LVDSC1 *(volatile uint8_t *)0x4007D000 // Low Voltage Detect Status And Control 1 register
296 #define PMC_LVDSC2 *(volatile uint8_t *)0x4007D001 // Low Voltage Detect Status And Control 2 register
297 #define PMC_REGSC *(volatile uint8_t *)0x4007D002 // Regulator Status And Control register
299 // Chapter 16: Low-Leakage Wakeup Unit (LLWU)
300 #define LLWU_PE1 *(volatile uint8_t *)0x4007C000 // LLWU Pin Enable 1 register
301 #define LLWU_PE2 *(volatile uint8_t *)0x4007C001 // LLWU Pin Enable 2 register
302 #define LLWU_PE3 *(volatile uint8_t *)0x4007C002 // LLWU Pin Enable 3 register
303 #define LLWU_PE4 *(volatile uint8_t *)0x4007C003 // LLWU Pin Enable 4 register
304 #define LLWU_ME *(volatile uint8_t *)0x4007C004 // LLWU Module Enable register
305 #define LLWU_F1 *(volatile uint8_t *)0x4007C005 // LLWU Flag 1 register
306 #define LLWU_F2 *(volatile uint8_t *)0x4007C006 // LLWU Flag 2 register
307 #define LLWU_F3 *(volatile uint8_t *)0x4007C007 // LLWU Flag 3 register
308 #define LLWU_FILT1 *(volatile uint8_t *)0x4007C008 // LLWU Pin Filter 1 register
309 #define LLWU_FILT2 *(volatile uint8_t *)0x4007C009 // LLWU Pin Filter 2 register
310 #define LLWU_RST *(volatile uint8_t *)0x4007C00A // LLWU Reset Enable register
312 // Chapter 17: Miscellaneous Control Module (MCM)
313 #define MCM_PLASC *(volatile uint16_t *)0xE0080008 // Crossbar Switch (AXBS) Slave Configuration
314 #define MCM_PLAMC *(volatile uint16_t *)0xE008000A // Crossbar Switch (AXBS) Master Configuration
315 #define MCM_PLACR *(volatile uint32_t *)0xE008000C // Crossbar Switch (AXBS) Control Register
317 // Chapter 20: Direct Memory Access Multiplexer (DMAMUX)
318 #define DMAMUX0_CHCFG0 *(volatile uint8_t *)0x40021000 // Channel Configuration register
319 #define DMAMUX0_CHCFG1 *(volatile uint8_t *)0x40021001 // Channel Configuration register
320 #define DMAMUX0_CHCFG2 *(volatile uint8_t *)0x40021002 // Channel Configuration register
321 #define DMAMUX0_CHCFG3 *(volatile uint8_t *)0x40021003 // Channel Configuration register
322 #define DMAMUX0_CHCFG4 *(volatile uint8_t *)0x40021004 // Channel Configuration register
323 #define DMAMUX0_CHCFG5 *(volatile uint8_t *)0x40021005 // Channel Configuration register
324 #define DMAMUX0_CHCFG6 *(volatile uint8_t *)0x40021006 // Channel Configuration register
325 #define DMAMUX0_CHCFG7 *(volatile uint8_t *)0x40021007 // Channel Configuration register
326 #define DMAMUX0_CHCFG8 *(volatile uint8_t *)0x40021008 // Channel Configuration register
327 #define DMAMUX0_CHCFG9 *(volatile uint8_t *)0x40021009 // Channel Configuration register
328 #define DMAMUX0_CHCFG10 *(volatile uint8_t *)0x4002100A // Channel Configuration register
329 #define DMAMUX0_CHCFG11 *(volatile uint8_t *)0x4002100B // Channel Configuration register
330 #define DMAMUX0_CHCFG12 *(volatile uint8_t *)0x4002100C // Channel Configuration register
331 #define DMAMUX0_CHCFG13 *(volatile uint8_t *)0x4002100D // Channel Configuration register
332 #define DMAMUX0_CHCFG14 *(volatile uint8_t *)0x4002100E // Channel Configuration register
333 #define DMAMUX0_CHCFG15 *(volatile uint8_t *)0x4002100F // Channel Configuration register
335 // Chapter 21: Direct Memory Access Controller (eDMA)
336 #define DMA_CR *(volatile uint32_t *)0x40008000 // Control Register
337 #define DMA_ES *(volatile uint32_t *)0x40008004 // Error Status Register
338 #define DMA_ERQ *(volatile uint32_t *)0x4000800C // Enable Request Register
339 #define DMA_EEI *(volatile uint32_t *)0x40008014 // Enable Error Interrupt Register
340 #define DMA_CEEI *(volatile uint8_t *)0x40008018 // Clear Enable Error Interrupt Register
341 #define DMA_SEEI *(volatile uint8_t *)0x40008019 // Set Enable Error Interrupt Register
342 #define DMA_CERQ *(volatile uint8_t *)0x4000801A // Clear Enable Request Register
343 #define DMA_SERQ *(volatile uint8_t *)0x4000801B // Set Enable Request Register
344 #define DMA_CDNE *(volatile uint8_t *)0x4000801C // Clear DONE Status Bit Register
345 #define DMA_SSRT *(volatile uint8_t *)0x4000801D // Set START Bit Register
346 #define DMA_CERR *(volatile uint8_t *)0x4000801E // Clear Error Register
347 #define DMA_CINT *(volatile uint8_t *)0x4000801F // Clear Interrupt Request Register
348 #define DMA_INT *(volatile uint32_t *)0x40008024 // Interrupt Request Register
349 #define DMA_ERR *(volatile uint32_t *)0x4000802C // Error Register
350 #define DMA_HRS *(volatile uint32_t *)0x40008034 // Hardware Request Status Register
351 #define DMA_DCHPRI3 *(volatile uint8_t *)0x40008100 // Channel n Priority Register
352 #define DMA_DCHPRI2 *(volatile uint8_t *)0x40008101 // Channel n Priority Register
353 #define DMA_DCHPRI1 *(volatile uint8_t *)0x40008102 // Channel n Priority Register
354 #define DMA_DCHPRI0 *(volatile uint8_t *)0x40008103 // Channel n Priority Register
356 #define DMA_TCD0_SADDR *(volatile uint32_t *)0x40009000 // TCD Source Address
357 #define DMA_TCD0_SOFF *(volatile uint16_t *)0x40009004 // TCD Signed Source Address Offset
358 #define DMA_TCD0_ATTR *(volatile uint16_t *)0x40009006 // TCD Transfer Attributes
359 #define DMA_TCD0_NBYTES_MLNO *(volatile uint32_t *)0x40009008 // TCD Minor Byte Count (Minor Loop Disabled)
360 #define DMA_TCD0_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
361 #define DMA_TCD0_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
362 #define DMA_TCD0_SLAST *(volatile uint32_t *)0x4000900C // TCD Last Source Address Adjustment
363 #define DMA_TCD0_DADDR *(volatile uint32_t *)0x40009010 // TCD Destination Address
365 #define DMA_TCD0_DOFF 0x40009014 // TCD Signed Destination Address Offset
366 #define DMA_TCD0_DLASTSGA 0x40009018 // TCD Last Destination Address Adjustment/Scatter Gather Address
367 #define DMA_TCD0_CSR 0x4000901C // TCD Control and Status
368 #define DMA_TCD0_BITER_ELINKYES 0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
369 #define DMA_TCD0_BITER_ELINKNO 0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
370 #define DMA_TCD1_SADDR 0x40009020 // TCD Source Address
371 #define DMA_TCD1_SOFF 0x40009024 // TCD Signed Source Address Offset
372 #define DMA_TCD1_ATTR 0x40009026 // TCD Transfer Attributes
373 #define DMA_TCD1_NBYTES_MLNO 0x40009028 // TCD Minor Byte Count, Minor Loop Disabled
374 #define DMA_TCD1_NBYTES_MLOFFNO 0x40009028 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
375 #define DMA_TCD1_NBYTES_MLOFFYES 0x40009028 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
376 #define DMA_TCD1_SLAST 0x4000902C // TCD Last Source Address Adjustment
377 #define DMA_TCD1_DADDR 0x40009030 // TCD Destination Address
378 #define DMA_TCD1_DOFF 0x40009034 // TCD Signed Destination Address Offset
379 #define DMA_TCD1_CITER_ELINKYES 0x40009036 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
380 #define DMA_TCD1_CITER_ELINKNO 0x40009036 // ??
381 #define DMA_TCD1_DLASTSGA 0x40009038 // TCD Last Destination Address Adjustment/Scatter Gather Address
382 #define DMA_TCD1_CSR 0x4000903C // TCD Control and Status
383 #define DMA_TCD1_BITER_ELINKYES 0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled
384 #define DMA_TCD1_BITER_ELINKNO 0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
385 #define DMA_TCD2_SADDR 0x40009040 // TCD Source Address
386 #define DMA_TCD2_SOFF 0x40009044 // TCD Signed Source Address Offset
387 #define DMA_TCD2_ATTR 0x40009046 // TCD Transfer Attributes
388 #define DMA_TCD2_NBYTES_MLNO 0x40009048 // TCD Minor Byte Count, Minor Loop Disabled
389 #define DMA_TCD2_NBYTES_MLOFFNO 0x40009048 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
390 #define DMA_TCD2_NBYTES_MLOFFYES 0x40009048 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
391 #define DMA_TCD2_SLAST 0x4000904C // TCD Last Source Address Adjustment
392 #define DMA_TCD2_DADDR 0x40009050 // TCD Destination Address
393 #define DMA_TCD2_DOFF 0x40009054 // TCD Signed Destination Address Offset
394 #define DMA_TCD2_CITER_ELINKYES 0x40009056 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
395 #define DMA_TCD2_CITER_ELINKNO 0x40009056 // ??
396 #define DMA_TCD2_DLASTSGA 0x40009058 // TCD Last Destination Address Adjustment/Scatter Gather Address
397 #define DMA_TCD2_CSR 0x4000905C // TCD Control and Status
398 #define DMA_TCD2_BITER_ELINKYES 0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
399 #define DMA_TCD2_BITER_ELINKNO 0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
400 #define DMA_TCD3_SADDR 0x40009060 // TCD Source Address
401 #define DMA_TCD3_SOFF 0x40009064 // TCD Signed Source Address Offset
402 #define DMA_TCD3_ATTR 0x40009066 // TCD Transfer Attributes
403 #define DMA_TCD3_NBYTES_MLOFFNO 0x40009068 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
404 #define DMA_TCD3_NBYTES_MLOFFYES 0x40009068 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
405 #define DMA_TCD3_SLAST 0x4000906C // TCD Last Source Address Adjustment
406 #define DMA_TCD3_DADDR 0x40009070 // TCD Destination Address
407 #define DMA_TCD3_DOFF 0x40009074 // TCD Signed Destination Address Offset
408 #define DMA_TCD3_CITER_ELINKYES 0x40009076 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
409 #define DMA_TCD3_CITER_ELINKNO 0x40009076 // ??
410 #define DMA_TCD3_DLASTSGA 0x40009078 // TCD Last Destination Address Adjustment/Scatter Gather Address
411 #define DMA_TCD3_CSR 0x4000907C // TCD Control and Status
412 #define DMA_TCD3_BITER_ELINKYES 0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled
413 #define DMA_TCD3_BITER_ELINKNO 0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled
414 #define DMA_TCD4_BITER_ELINKYES 0x4000909E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled
416 // Chapter 22: External Watchdog Monitor (EWM)
417 #define EWM_CTRL *(volatile uint8_t *)0x40061000 // Control Register
418 #define EWM_SERV *(volatile uint8_t *)0x40061001 // Service Register
419 #define EWM_CMPL *(volatile uint8_t *)0x40061002 // Compare Low Register
420 #define EWM_CMPH *(volatile uint8_t *)0x40061003 // Compare High Register
422 // Chapter 23: Watchdog Timer (WDOG)
423 #define WDOG_STCTRLH *(volatile uint16_t *)0x40052000 // Watchdog Status and Control Register High
424 #define WDOG_STCTRLH_DISTESTWDOG (uint16_t)0x4000 // Allows the WDOG's functional test mode to be disabled permanently.
425 #define WDOG_STCTRLH_BYTESEL(n) (uint16_t)(((n) & 3) << 12) // selects the byte to be tested when the watchdog is in the byte test mode.
426 #define WDOG_STCTRLH_TESTSEL (uint16_t)0x0800
427 #define WDOG_STCTRLH_TESTWDOG (uint16_t)0x0400
428 #define WDOG_STCTRLH_WAITEN (uint16_t)0x0080
429 #define WDOG_STCTRLH_STOPEN (uint16_t)0x0040
430 #define WDOG_STCTRLH_DBGEN (uint16_t)0x0020
431 #define WDOG_STCTRLH_ALLOWUPDATE (uint16_t)0x0010
432 #define WDOG_STCTRLH_WINEN (uint16_t)0x0008
433 #define WDOG_STCTRLH_IRQRSTEN (uint16_t)0x0004
434 #define WDOG_STCTRLH_CLKSRC (uint16_t)0x0002
435 #define WDOG_STCTRLH_WDOGEN (uint16_t)0x0001
436 #define WDOG_STCTRLL *(volatile uint16_t *)0x40052002 // Watchdog Status and Control Register Low
437 #define WDOG_TOVALH *(volatile uint16_t *)0x40052004 // Watchdog Time-out Value Register High
438 #define WDOG_TOVALL *(volatile uint16_t *)0x40052006 // Watchdog Time-out Value Register Low
439 #define WDOG_WINH *(volatile uint16_t *)0x40052008 // Watchdog Window Register High
440 #define WDOG_WINL *(volatile uint16_t *)0x4005200A // Watchdog Window Register Low
441 #define WDOG_REFRESH *(volatile uint16_t *)0x4005200C // Watchdog Refresh register
442 #define WDOG_UNLOCK *(volatile uint16_t *)0x4005200E // Watchdog Unlock register
443 #define WDOG_UNLOCK_SEQ1 (uint16_t)0xC520
444 #define WDOG_UNLOCK_SEQ2 (uint16_t)0xD928
445 #define WDOG_TMROUTH *(volatile uint16_t *)0x40052010 // Watchdog Timer Output Register High
446 #define WDOG_TMROUTL *(volatile uint16_t *)0x40052012 // Watchdog Timer Output Register Low
447 #define WDOG_RSTCNT *(volatile uint16_t *)0x40052014 // Watchdog Reset Count register
448 #define WDOG_PRESC *(volatile uint16_t *)0x40052016 // Watchdog Prescaler register
450 // Chapter 24: Multipurpose Clock Generator (MCG)
451 #define MCG_C1 *(volatile uint8_t *)0x40064000 // MCG Control 1 Register
452 #define MCG_C1_IREFSTEN (uint8_t)0x01 // Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.
453 #define MCG_C1_IRCLKEN (uint8_t)0x02 // Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK.
454 #define MCG_C1_IREFS (uint8_t)0x04 // Internal Reference Select, Selects the reference clock source for the FLL.
455 #define MCG_C1_FRDIV(n) (uint8_t)(((n) & 0x07) << 3) // FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL
456 #define MCG_C1_CLKS(n) (uint8_t)(((n) & 0x03) << 6) // Clock Source Select, Selects the clock source for MCGOUTCLK
457 #define MCG_C2 *(volatile uint8_t *)0x40064001 // MCG Control 2 Register
458 #define MCG_C2_IRCS (uint8_t)0x01 // Internal Reference Clock Select, Selects between the fast or slow internal reference clock source.
459 #define MCG_C2_LP (uint8_t)0x02 // Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes.
460 #define MCG_C2_EREFS (uint8_t)0x04 // External Reference Select, Selects the source for the external reference clock.
461 #define MCG_C2_HGO0 (uint8_t)0x08 // High Gain Oscillator Select, Controls the crystal oscillator mode of operation
462 #define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator
463 #define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
464 #define MCG_C3 *(volatile uint8_t *)0x40064002 // MCG Control 3 Register
465 #define MCG_C3_SCTRIM(n) (uint8_t)(n) // Slow Internal Reference Clock Trim Setting
466 #define MCG_C4 *(volatile uint8_t *)0x40064003 // MCG Control 4 Register
467 #define MCG_C4_SCFTRIM (uint8_t)0x01 // Slow Internal Reference Clock Fine Trim
468 #define MCG_C4_FCTRIM(n) (uint8_t)(((n) & 0x0F) << 1) // Fast Internal Reference Clock Trim Setting
469 #define MCG_C4_DRST_DRS(n) (uint8_t)(((n) & 0x03) << 5) // DCO Range Select
470 #define MCG_C4_DMX32 (uint8_t)0x80 // DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed
471 #define MCG_C5 *(volatile uint8_t *)0x40064004 // MCG Control 5 Register
472 #define MCG_C5_PRDIV0(n) (uint8_t)((n) & 0x1F) // PLL External Reference Divider
473 #define MCG_C5_PLLSTEN0 (uint8_t)0x20 // PLL Stop Enable
474 #define MCG_C5_PLLCLKEN0 (uint8_t)0x40 // PLL Clock Enable
475 #define MCG_C6 *(volatile uint8_t *)0x40064005 // MCG Control 6 Register
476 #define MCG_C6_VDIV0(n) (uint8_t)((n) & 0x1F) // VCO 0 Divider
477 #define MCG_C6_CME0 (uint8_t)0x20 // Clock Monitor Enable
478 #define MCG_C6_PLLS (uint8_t)0x40 // PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00.
479 #define MCG_C6_LOLIE0 (uint8_t)0x80 // Loss of Lock Interrrupt Enable
480 #define MCG_S *(volatile uint8_t *)0x40064006 // MCG Status Register
481 #define MCG_S_IRCST (uint8_t)0x01 // Internal Reference Clock Status
482 #define MCG_S_OSCINIT0 (uint8_t)0x02 // OSC Initialization, resets to 0, is set to 1 after the initialization cycles of the crystal oscillator
483 #define MCG_S_CLKST(n) (uint8_t)(((n) & 0x03) << 2) // Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL
484 #define MCG_S_CLKST_MASK (uint8_t)0x0C
485 #define MCG_S_IREFST (uint8_t)0x10 // Internal Reference Status
486 #define MCG_S_PLLST (uint8_t)0x20 // PLL Select Status
487 #define MCG_S_LOCK0 (uint8_t)0x40 // Lock Status, 0=PLL Unlocked, 1=PLL Locked
488 #define MCG_S_LOLS0 (uint8_t)0x80 // Loss of Lock Status
489 #define MCG_SC *(volatile uint8_t *)0x40064008 // MCG Status and Control Register
490 #define MCG_SC_LOCS0 (uint8_t)0x01 // OSC0 Loss of Clock Status
491 #define MCG_SC_FCRDIV(n) (uint8_t)(((n) & 0x07) << 1) // Fast Clock Internal Reference Divider
492 #define MCG_SC_FLTPRSRV (uint8_t)0x10 // FLL Filter Preserve Enable
493 #define MCG_SC_ATMF (uint8_t)0x20 // Automatic Trim Machine Fail Flag
494 #define MCG_SC_ATMS (uint8_t)0x40 // Automatic Trim Machine Select
495 #define MCG_SC_ATME (uint8_t)0x80 // Automatic Trim Machine Enable
496 #define MCG_ATCVH *(volatile uint8_t *)0x4006400A // MCG Auto Trim Compare Value High Register
497 #define MCG_ATCVL *(volatile uint8_t *)0x4006400B // MCG Auto Trim Compare Value Low Register
498 #define MCG_C7 *(volatile uint8_t *)0x4006400C // MCG Control 7 Register
499 #define MCG_C8 *(volatile uint8_t *)0x4006400D // MCG Control 8 Register
501 // Chapter 25: Oscillator (OSC)
502 #define OSC0_CR *(volatile uint8_t *)0x40065000 // OSC Control Register
503 #define OSC_SC16P (uint8_t)0x01 // Oscillator 16 pF Capacitor Load Configure
504 #define OSC_SC8P (uint8_t)0x02 // Oscillator 8 pF Capacitor Load Configure
505 #define OSC_SC4P (uint8_t)0x04 // Oscillator 4 pF Capacitor Load Configure
506 #define OSC_SC2P (uint8_t)0x08 // Oscillator 2 pF Capacitor Load Configure
507 #define OSC_EREFSTEN (uint8_t)0x20 // External Reference Stop Enable, Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode.
508 #define OSC_ERCLKEN (uint8_t)0x80 // External Reference Enable, Enables external reference clock (OSCERCLK).
510 // Chapter 27: Flash Memory Controller (FMC)
511 #define FMC_PFAPR *(volatile uint32_t *)0x4001F000 // Flash Access Protection
512 #define FMC_PFB0CR *(volatile uint32_t *)0x4001F004 // Flash Control
513 #define FMC_TAGVDW0S0 *(volatile uint32_t *)0x4001F100 // Cache Tag Storage
514 #define FMC_TAGVDW0S1 *(volatile uint32_t *)0x4001F104 // Cache Tag Storage
515 #define FMC_TAGVDW1S0 *(volatile uint32_t *)0x4001F108 // Cache Tag Storage
516 #define FMC_TAGVDW1S1 *(volatile uint32_t *)0x4001F10C // Cache Tag Storage
517 #define FMC_TAGVDW2S0 *(volatile uint32_t *)0x4001F110 // Cache Tag Storage
518 #define FMC_TAGVDW2S1 *(volatile uint32_t *)0x4001F114 // Cache Tag Storage
519 #define FMC_TAGVDW3S0 *(volatile uint32_t *)0x4001F118 // Cache Tag Storage
520 #define FMC_TAGVDW3S1 *(volatile uint32_t *)0x4001F11C // Cache Tag Storage
521 #define FMC_DATAW0S0 *(volatile uint32_t *)0x4001F200 // Cache Data Storage
522 #define FMC_DATAW0S1 *(volatile uint32_t *)0x4001F204 // Cache Data Storage
523 #define FMC_DATAW1S0 *(volatile uint32_t *)0x4001F208 // Cache Data Storage
524 #define FMC_DATAW1S1 *(volatile uint32_t *)0x4001F20C // Cache Data Storage
525 #define FMC_DATAW2S0 *(volatile uint32_t *)0x4001F210 // Cache Data Storage
526 #define FMC_DATAW2S1 *(volatile uint32_t *)0x4001F214 // Cache Data Storage
527 #define FMC_DATAW3S0 *(volatile uint32_t *)0x4001F218 // Cache Data Storage
528 #define FMC_DATAW3S1 *(volatile uint32_t *)0x4001F21C // Cache Data Storage
530 // Chapter 28: Flash Memory Module (FTFL)
531 #define FTFL_FSTAT *(volatile uint8_t *)0x40020000 // Flash Status Register
532 #define FTFL_FSTAT_CCIF (uint8_t)0x80 // Command Complete Interrupt Flag
533 #define FTFL_FSTAT_RDCOLERR (uint8_t)0x40 // Flash Read Collision Error Flag
534 #define FTFL_FSTAT_ACCERR (uint8_t)0x20 // Flash Access Error Flag
535 #define FTFL_FSTAT_FPVIOL (uint8_t)0x10 // Flash Protection Violation Flag
536 #define FTFL_FSTAT_MGSTAT0 (uint8_t)0x01 // Memory Controller Command Completion Status Flag
537 #define FTFL_FCNFG *(volatile uint8_t *)0x40020001 // Flash Configuration Register
538 #define FTFL_FCNFG_CCIE (uint8_t)0x80 // Command Complete Interrupt Enable
539 #define FTFL_FCNFG_RDCOLLIE (uint8_t)0x40 // Read Collision Error Interrupt Enable
540 #define FTFL_FCNFG_ERSAREQ (uint8_t)0x20 // Erase All Request
541 #define FTFL_FCNFG_ERSSUSP (uint8_t)0x10 // Erase Suspend
542 #define FTFL_FCNFG_PFLSH (uint8_t)0x04 // Flash memory configuration
543 #define FTFL_FCNFG_RAMRDY (uint8_t)0x02 // RAM Ready
544 #define FTFL_FCNFG_EEERDY (uint8_t)0x01 // EEPROM Ready
545 #define FTFL_FSEC *(const uint8_t *)0x40020002 // Flash Security Register
546 #define FTFL_FOPT *(const uint8_t *)0x40020003 // Flash Option Register
547 #define FTFL_FCCOB3 *(volatile uint8_t *)0x40020004 // Flash Common Command Object Registers
548 #define FTFL_FCCOB2 *(volatile uint8_t *)0x40020005
549 #define FTFL_FCCOB1 *(volatile uint8_t *)0x40020006
550 #define FTFL_FCCOB0 *(volatile uint8_t *)0x40020007
551 #define FTFL_FCCOB7 *(volatile uint8_t *)0x40020008
552 #define FTFL_FCCOB6 *(volatile uint8_t *)0x40020009
553 #define FTFL_FCCOB5 *(volatile uint8_t *)0x4002000A
554 #define FTFL_FCCOB4 *(volatile uint8_t *)0x4002000B
555 #define FTFL_FCCOBB *(volatile uint8_t *)0x4002000C
556 #define FTFL_FCCOBA *(volatile uint8_t *)0x4002000D
557 #define FTFL_FCCOB9 *(volatile uint8_t *)0x4002000E
558 #define FTFL_FCCOB8 *(volatile uint8_t *)0x4002000F
559 #define FTFL_FPROT3 *(volatile uint8_t *)0x40020010 // Program Flash Protection Registers
560 #define FTFL_FPROT2 *(volatile uint8_t *)0x40020011 // Program Flash Protection Registers
561 #define FTFL_FPROT1 *(volatile uint8_t *)0x40020012 // Program Flash Protection Registers
562 #define FTFL_FPROT0 *(volatile uint8_t *)0x40020013 // Program Flash Protection Registers
563 #define FTFL_FEPROT *(volatile uint8_t *)0x40020016 // EEPROM Protection Register
564 #define FTFL_FDPROT *(volatile uint8_t *)0x40020017 // Data Flash Protection Register
566 // Chapter 30: Cyclic Redundancy Check (CRC)
567 #define CRC_CRC *(volatile uint32_t *)0x40032000 // CRC Data register
568 #define CRC_GPOLY *(volatile uint32_t *)0x40032004 // CRC Polynomial register
569 #define CRC_CTRL *(volatile uint32_t *)0x40032008 // CRC Control register
571 // Chapter 31: Analog-to-Digital Converter (ADC)
572 #define ADC0_SC1A *(volatile uint32_t *)0x4003B000 // ADC status and control registers 1
573 #define ADC0_SC1B *(volatile uint32_t *)0x4003B004 // ADC status and control registers 1
574 #define ADC_SC1_COCO (uint32_t)0x80 // Conversion complete flag
575 #define ADC_SC1_AIEN (uint32_t)0x40 // Interrupt enable
576 #define ADC_SC1_DIFF (uint32_t)0x20 // Differential mode enable
577 #define ADC_SC1_ADCH(n) (uint32_t)((n) & 0x1F) // Input channel select
578 #define ADC0_CFG1 *(volatile uint32_t *)0x4003B008 // ADC configuration register 1
579 #define ADC_CFG1_ADLPC (uint32_t)0x80 // Low-power configuration
580 #define ADC_CFG1_ADIV(n) (uint32_t)(((n) & 3) << 5) // Clock divide select, 0=direct, 1=div2, 2=div4, 3=div8
581 #define ADC_CFG1_ADLSMP (uint32_t)0x10 // Sample time configuration, 0=Short, 1=Long
582 #define ADC_CFG1_MODE(n) (uint32_t)(((n) & 3) << 2) // Conversion mode, 0=8 bit, 1=12 bit, 2=10 bit, 3=16 bit
583 #define ADC_CFG1_ADICLK(n) (uint32_t)(((n) & 3) << 0) // Input clock, 0=bus, 1=bus/2, 2=OSCERCLK, 3=async
584 #define ADC0_CFG2 *(volatile uint32_t *)0x4003B00C // Configuration register 2
585 #define ADC_CFG2_MUXSEL (uint32_t)0x10 // 0=a channels, 1=b channels
586 #define ADC_CFG2_ADACKEN (uint32_t)0x08 // async clock enable
587 #define ADC_CFG2_ADHSC (uint32_t)0x04 // High speed configuration
588 #define ADC_CFG2_ADLSTS(n) (uint32_t)(((n) & 3) << 0) // Sample time, 0=24 cycles, 1=12 cycles, 2=6 cycles, 3=2 cycles
589 #define ADC0_RA *(volatile uint32_t *)0x4003B010 // ADC data result register
590 #define ADC0_RB *(volatile uint32_t *)0x4003B014 // ADC data result register
591 #define ADC0_CV1 *(volatile uint32_t *)0x4003B018 // Compare value registers
592 #define ADC0_CV2 *(volatile uint32_t *)0x4003B01C // Compare value registers
593 #define ADC0_SC2 *(volatile uint32_t *)0x4003B020 // Status and control register 2
594 #define ADC_SC2_ADACT (uint32_t)0x80 // Conversion active
595 #define ADC_SC2_ADTRG (uint32_t)0x40 // Conversion trigger select, 0=software, 1=hardware
596 #define ADC_SC2_ACFE (uint32_t)0x20 // Compare function enable
597 #define ADC_SC2_ACFGT (uint32_t)0x10 // Compare function greater than enable
598 #define ADC_SC2_ACREN (uint32_t)0x08 // Compare function range enable
599 #define ADC_SC2_DMAEN (uint32_t)0x04 // DMA enable
600 #define ADC_SC2_REFSEL(n) (uint32_t)(((n) & 3) << 0) // Voltage reference, 0=vcc/external, 1=1.2 volts
601 #define ADC0_SC3 *(volatile uint32_t *)0x4003B024 // Status and control register 3
602 #define ADC_SC3_CAL (uint32_t)0x80 // Calibration, 1=begin, stays set while cal in progress
603 #define ADC_SC3_CALF (uint32_t)0x40 // Calibration failed flag
604 #define ADC_SC3_ADCO (uint32_t)0x08 // Continuous conversion enable
605 #define ADC_SC3_AVGE (uint32_t)0x04 // Hardware average enable
606 #define ADC_SC3_AVGS(n) (uint32_t)(((n) & 3) << 0) // avg select, 0=4 samples, 1=8 samples, 2=16 samples, 3=32 samples
607 #define ADC0_OFS *(volatile uint32_t *)0x4003B028 // ADC offset correction register
608 #define ADC0_PG *(volatile uint32_t *)0x4003B02C // ADC plus-side gain register
609 #define ADC0_MG *(volatile uint32_t *)0x4003B030 // ADC minus-side gain register
610 #define ADC0_CLPD *(volatile uint32_t *)0x4003B034 // ADC plus-side general calibration value register
611 #define ADC0_CLPS *(volatile uint32_t *)0x4003B038 // ADC plus-side general calibration value register
612 #define ADC0_CLP4 *(volatile uint32_t *)0x4003B03C // ADC plus-side general calibration value register
613 #define ADC0_CLP3 *(volatile uint32_t *)0x4003B040 // ADC plus-side general calibration value register
614 #define ADC0_CLP2 *(volatile uint32_t *)0x4003B044 // ADC plus-side general calibration value register
615 #define ADC0_CLP1 *(volatile uint32_t *)0x4003B048 // ADC plus-side general calibration value register
616 #define ADC0_CLP0 *(volatile uint32_t *)0x4003B04C // ADC plus-side general calibration value register
617 #define ADC0_CLMD *(volatile uint32_t *)0x4003B054 // ADC minus-side general calibration value register
618 #define ADC0_CLMS *(volatile uint32_t *)0x4003B058 // ADC minus-side general calibration value register
619 #define ADC0_CLM4 *(volatile uint32_t *)0x4003B05C // ADC minus-side general calibration value register
620 #define ADC0_CLM3 *(volatile uint32_t *)0x4003B060 // ADC minus-side general calibration value register
621 #define ADC0_CLM2 *(volatile uint32_t *)0x4003B064 // ADC minus-side general calibration value register
622 #define ADC0_CLM1 *(volatile uint32_t *)0x4003B068 // ADC minus-side general calibration value register
623 #define ADC0_CLM0 *(volatile uint32_t *)0x4003B06C // ADC minus-side general calibration value register
624 //#define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator
625 //#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
627 // Chapter 32: Comparator (CMP)
628 #define CMP0_CR0 *(volatile uint8_t *)0x40073000 // CMP Control Register 0
629 #define CMP0_CR1 *(volatile uint8_t *)0x40073001 // CMP Control Register 1
630 #define CMP0_FPR *(volatile uint8_t *)0x40073002 // CMP Filter Period Register
631 #define CMP0_SCR *(volatile uint8_t *)0x40073003 // CMP Status and Control Register
632 #define CMP0_DACCR *(volatile uint8_t *)0x40073004 // DAC Control Register
633 #define CMP0_MUXCR *(volatile uint8_t *)0x40073005 // MUX Control Register
634 #define CMP1_CR0 *(volatile uint8_t *)0x40073008 // CMP Control Register 0
635 #define CMP1_CR1 *(volatile uint8_t *)0x40073009 // CMP Control Register 1
636 #define CMP1_FPR *(volatile uint8_t *)0x4007300A // CMP Filter Period Register
637 #define CMP1_SCR *(volatile uint8_t *)0x4007300B // CMP Status and Control Register
638 #define CMP1_DACCR *(volatile uint8_t *)0x4007300C // DAC Control Register
639 #define CMP1_MUXCR *(volatile uint8_t *)0x4007300D // MUX Control Register
641 // Chapter 33: Voltage Reference (VREFV1)
642 #define VREF_TRM *(volatile uint8_t *)0x40074000 // VREF Trim Register
643 #define VREF_SC *(volatile uint8_t *)0x40074001 // VREF Status and Control Register
645 // Chapter 34: Programmable Delay Block (PDB)
646 #define PDB0_SC *(volatile uint32_t *)0x40036000 // Status and Control Register
647 #define PDB_SC_LDMOD(n) (((n) & 3) << 18) // Load Mode Select
648 #define PDB_SC_PDBEIE 0x00020000 // Sequence Error Interrupt Enable
649 #define PDB_SC_SWTRIG 0x00010000 // Software Trigger
650 #define PDB_SC_DMAEN 0x00008000 // DMA Enable
651 #define PDB_SC_PRESCALER(n) (((n) & 7) << 12) // Prescaler Divider Select
652 #define PDB_SC_TRGSEL(n) (((n) & 15) << 8) // Trigger Input Source Select
653 #define PDB_SC_PDBEN 0x00000080 // PDB Enable
654 #define PDB_SC_PDBIF 0x00000040 // PDB Interrupt Flag
655 #define PDB_SC_PDBIE 0x00000020 // PDB Interrupt Enable.
656 #define PDB_SC_MULT(n) (((n) & 3) << 2) // Multiplication Factor
657 #define PDB_SC_CONT 0x00000002 // Continuous Mode Enable
658 #define PDB_SC_LDOK 0x00000001 // Load OK
659 #define PDB0_MOD *(volatile uint32_t *)0x40036004 // Modulus Register
660 #define PDB0_CNT *(volatile uint32_t *)0x40036008 // Counter Register
661 #define PDB0_IDLY *(volatile uint32_t *)0x4003600C // Interrupt Delay Register
662 #define PDB0_CH0C1 *(volatile uint32_t *)0x40036010 // Channel n Control Register 1
663 #define PDB0_CH0S *(volatile uint32_t *)0x40036014 // Channel n Status Register
664 #define PDB0_CH0DLY0 *(volatile uint32_t *)0x40036018 // Channel n Delay 0 Register
665 #define PDB0_CH0DLY1 *(volatile uint32_t *)0x4003601C // Channel n Delay 1 Register
666 #define PDB0_POEN *(volatile uint32_t *)0x40036190 // Pulse-Out n Enable Register
667 #define PDB0_PO0DLY *(volatile uint32_t *)0x40036194 // Pulse-Out n Delay Register
668 #define PDB0_PO1DLY *(volatile uint32_t *)0x40036198 // Pulse-Out n Delay Register
670 // Chapter 35: FlexTimer Module (FTM)
671 #define FTM0_SC *(volatile uint32_t *)0x40038000 // Status And Control
672 #define FTM_SC_TOF 0x80 // Timer Overflow Flag
673 #define FTM_SC_TOIE 0x40 // Timer Overflow Interrupt Enable
674 #define FTM_SC_CPWMS 0x20 // Center-Aligned PWM Select
675 #define FTM_SC_CLKS(n) (((n) & 3) << 3) // Clock Source Selection
676 #define FTM_SC_PS(n) (((n) & 7) << 0) // Prescale Factor Selection
677 #define FTM0_CNT *(volatile uint32_t *)0x40038004 // Counter
678 #define FTM0_MOD *(volatile uint32_t *)0x40038008 // Modulo
679 #define FTM0_C0SC *(volatile uint32_t *)0x4003800C // Channel 0 Status And Control
680 #define FTM0_C0V *(volatile uint32_t *)0x40038010 // Channel 0 Value
681 #define FTM0_C1SC *(volatile uint32_t *)0x40038014 // Channel 1 Status And Control
682 #define FTM0_C1V *(volatile uint32_t *)0x40038018 // Channel 1 Value
683 #define FTM0_C2SC *(volatile uint32_t *)0x4003801C // Channel 2 Status And Control
684 #define FTM0_C2V *(volatile uint32_t *)0x40038020 // Channel 2 Value
685 #define FTM0_C3SC *(volatile uint32_t *)0x40038024 // Channel 3 Status And Control
686 #define FTM0_C3V *(volatile uint32_t *)0x40038028 // Channel 3 Value
687 #define FTM0_C4SC *(volatile uint32_t *)0x4003802C // Channel 4 Status And Control
688 #define FTM0_C4V *(volatile uint32_t *)0x40038030 // Channel 4 Value
689 #define FTM0_C5SC *(volatile uint32_t *)0x40038034 // Channel 5 Status And Control
690 #define FTM0_C5V *(volatile uint32_t *)0x40038038 // Channel 5 Value
691 #define FTM0_C6SC *(volatile uint32_t *)0x4003803C // Channel 6 Status And Control
692 #define FTM0_C6V *(volatile uint32_t *)0x40038040 // Channel 6 Value
693 #define FTM0_C7SC *(volatile uint32_t *)0x40038044 // Channel 7 Status And Control
694 #define FTM0_C7V *(volatile uint32_t *)0x40038048 // Channel 7 Value
695 #define FTM0_CNTIN *(volatile uint32_t *)0x4003804C // Counter Initial Value
696 #define FTM0_STATUS *(volatile uint32_t *)0x40038050 // Capture And Compare Status
697 #define FTM0_MODE *(volatile uint32_t *)0x40038054 // Features Mode Selection
698 #define FTM_MODE_FAULTIE 0x80 // Fault Interrupt Enable
699 #define FTM_MODE_FAULTM(n) (((n) & 3) << 5) // Fault Control Mode
700 #define FTM_MODE_CAPTEST 0x10 // Capture Test Mode Enable
701 #define FTM_MODE_PWMSYNC 0x08 // PWM Synchronization Mode
702 #define FTM_MODE_WPDIS 0x04 // Write Protection Disable
703 #define FTM_MODE_INIT 0x02 // Initialize The Channels Output
704 #define FTM_MODE_FTMEN 0x01 // FTM Enable
705 #define FTM0_SYNC *(volatile uint32_t *)0x40038058 // Synchronization
706 #define FTM_SYNC_SWSYNC 0x80 //
707 #define FTM_SYNC_TRIG2 0x40 //
708 #define FTM_SYNC_TRIG1 0x20 //
709 #define FTM_SYNC_TRIG0 0x10 //
710 #define FTM_SYNC_SYNCHOM 0x08 //
711 #define FTM_SYNC_REINIT 0x04 //
712 #define FTM_SYNC_CNTMAX 0x02 //
713 #define FTM_SYNC_CNTMIN 0x01 //
714 #define FTM0_OUTINIT *(volatile uint32_t *)0x4003805C // Initial State For Channels Output
715 #define FTM0_OUTMASK *(volatile uint32_t *)0x40038060 // Output Mask
716 #define FTM0_COMBINE *(volatile uint32_t *)0x40038064 // Function For Linked Channels
717 #define FTM0_DEADTIME *(volatile uint32_t *)0x40038068 // Deadtime Insertion Control
718 #define FTM0_EXTTRIG *(volatile uint32_t *)0x4003806C // FTM External Trigger
719 #define FTM0_POL *(volatile uint32_t *)0x40038070 // Channels Polarity
720 #define FTM0_FMS *(volatile uint32_t *)0x40038074 // Fault Mode Status
721 #define FTM0_FILTER *(volatile uint32_t *)0x40038078 // Input Capture Filter Control
722 #define FTM0_FLTCTRL *(volatile uint32_t *)0x4003807C // Fault Control
723 #define FTM0_QDCTRL *(volatile uint32_t *)0x40038080 // Quadrature Decoder Control And Status
724 #define FTM0_CONF *(volatile uint32_t *)0x40038084 // Configuration
725 #define FTM0_FLTPOL *(volatile uint32_t *)0x40038088 // FTM Fault Input Polarity
726 #define FTM0_SYNCONF *(volatile uint32_t *)0x4003808C // Synchronization Configuration
727 #define FTM0_INVCTRL *(volatile uint32_t *)0x40038090 // FTM Inverting Control
728 #define FTM0_SWOCTRL *(volatile uint32_t *)0x40038094 // FTM Software Output Control
729 #define FTM0_PWMLOAD *(volatile uint32_t *)0x40038098 // FTM PWM Load
730 #define FTM1_SC *(volatile uint32_t *)0x40039000 // Status And Control
731 #define FTM1_CNT *(volatile uint32_t *)0x40039004 // Counter
732 #define FTM1_MOD *(volatile uint32_t *)0x40039008 // Modulo
733 #define FTM1_C0SC *(volatile uint32_t *)0x4003900C // Channel 0 Status And Control
734 #define FTM1_C0V *(volatile uint32_t *)0x40039010 // Channel 0 Value
735 #define FTM1_C1SC *(volatile uint32_t *)0x40039014 // Channel 1 Status And Control
736 #define FTM1_C1V *(volatile uint32_t *)0x40039018 // Channel 1 Value
737 #define FTM1_CNTIN *(volatile uint32_t *)0x4003904C // Counter Initial Value
738 #define FTM1_STATUS *(volatile uint32_t *)0x40039050 // Capture And Compare Status
739 #define FTM1_MODE *(volatile uint32_t *)0x40039054 // Features Mode Selection
740 #define FTM1_SYNC *(volatile uint32_t *)0x40039058 // Synchronization
741 #define FTM1_OUTINIT *(volatile uint32_t *)0x4003905C // Initial State For Channels Output
742 #define FTM1_OUTMASK *(volatile uint32_t *)0x40039060 // Output Mask
743 #define FTM1_COMBINE *(volatile uint32_t *)0x40039064 // Function For Linked Channels
744 #define FTM1_DEADTIME *(volatile uint32_t *)0x40039068 // Deadtime Insertion Control
745 #define FTM1_EXTTRIG *(volatile uint32_t *)0x4003906C // FTM External Trigger
746 #define FTM1_POL *(volatile uint32_t *)0x40039070 // Channels Polarity
747 #define FTM1_FMS *(volatile uint32_t *)0x40039074 // Fault Mode Status
748 #define FTM1_FILTER *(volatile uint32_t *)0x40039078 // Input Capture Filter Control
749 #define FTM1_FLTCTRL *(volatile uint32_t *)0x4003907C // Fault Control
750 #define FTM1_QDCTRL *(volatile uint32_t *)0x40039080 // Quadrature Decoder Control And Status
751 #define FTM1_CONF *(volatile uint32_t *)0x40039084 // Configuration
752 #define FTM1_FLTPOL *(volatile uint32_t *)0x40039088 // FTM Fault Input Polarity
753 #define FTM1_SYNCONF *(volatile uint32_t *)0x4003908C // Synchronization Configuration
754 #define FTM1_INVCTRL *(volatile uint32_t *)0x40039090 // FTM Inverting Control
755 #define FTM1_SWOCTRL *(volatile uint32_t *)0x40039094 // FTM Software Output Control
756 #define FTM1_PWMLOAD *(volatile uint32_t *)0x40039098 // FTM PWM Load
758 // Chapter 36: Periodic Interrupt Timer (PIT)
759 #define PIT_MCR *(volatile uint32_t *)0x40037000 // PIT Module Control Register
760 #define PIT_LDVAL0 *(volatile uint32_t *)0x40037100 // Timer Load Value Register
761 #define PIT_CVAL0 *(volatile uint32_t *)0x40037104 // Current Timer Value Register
762 #define PIT_TCTRL0 *(volatile uint32_t *)0x40037108 // Timer Control Register
763 #define PIT_TFLG0 *(volatile uint32_t *)0x4003710C // Timer Flag Register
764 #define PIT_LDVAL1 *(volatile uint32_t *)0x40037110 // Timer Load Value Register
765 #define PIT_CVAL1 *(volatile uint32_t *)0x40037114 // Current Timer Value Register
766 #define PIT_TCTRL1 *(volatile uint32_t *)0x40037118 // Timer Control Register
767 #define PIT_TFLG1 *(volatile uint32_t *)0x4003711C // Timer Flag Register
768 #define PIT_LDVAL2 *(volatile uint32_t *)0x40037120 // Timer Load Value Register
769 #define PIT_CVAL2 *(volatile uint32_t *)0x40037124 // Current Timer Value Register
770 #define PIT_TCTRL2 *(volatile uint32_t *)0x40037128 // Timer Control Register
771 #define PIT_TFLG2 *(volatile uint32_t *)0x4003712C // Timer Flag Register
772 #define PIT_LDVAL3 *(volatile uint32_t *)0x40037130 // Timer Load Value Register
773 #define PIT_CVAL3 *(volatile uint32_t *)0x40037134 // Current Timer Value Register
774 #define PIT_TCTRL3 *(volatile uint32_t *)0x40037138 // Timer Control Register
775 #define PIT_TFLG3 *(volatile uint32_t *)0x4003713C // Timer Flag Register
777 // Chapter 37: Low-Power Timer (LPTMR)
778 #define LPTMR0_CSR *(volatile uint32_t *)0x40040000 // Low Power Timer Control Status Register
779 #define LPTMR0_PSR *(volatile uint32_t *)0x40040004 // Low Power Timer Prescale Register
780 #define LPTMR0_CMR *(volatile uint32_t *)0x40040008 // Low Power Timer Compare Register
781 #define LPTMR0_CNR *(volatile uint32_t *)0x4004000C // Low Power Timer Counter Register
783 // Chapter 38: Carrier Modulator Transmitter (CMT)
784 #define CMT_CGH1 *(volatile uint8_t *)0x40062000 // CMT Carrier Generator High Data Register 1
785 #define CMT_CGL1 *(volatile uint8_t *)0x40062001 // CMT Carrier Generator Low Data Register 1
786 #define CMT_CGH2 *(volatile uint8_t *)0x40062002 // CMT Carrier Generator High Data Register 2
787 #define CMT_CGL2 *(volatile uint8_t *)0x40062003 // CMT Carrier Generator Low Data Register 2
788 #define CMT_OC *(volatile uint8_t *)0x40062004 // CMT Output Control Register
789 #define CMT_MSC *(volatile uint8_t *)0x40062005 // CMT Modulator Status and Control Register
790 #define CMT_CMD1 *(volatile uint8_t *)0x40062006 // CMT Modulator Data Register Mark High
791 #define CMT_CMD2 *(volatile uint8_t *)0x40062007 // CMT Modulator Data Register Mark Low
792 #define CMT_CMD3 *(volatile uint8_t *)0x40062008 // CMT Modulator Data Register Space High
793 #define CMT_CMD4 *(volatile uint8_t *)0x40062009 // CMT Modulator Data Register Space Low
794 #define CMT_PPS *(volatile uint8_t *)0x4006200A // CMT Primary Prescaler Register
795 #define CMT_DMA *(volatile uint8_t *)0x4006200B // CMT Direct Memory Access Register
797 // Chapter 39: Real Time Clock (RTC)
798 #define RTC_TSR *(volatile uint32_t *)0x4003D000 // RTC Time Seconds Register
799 #define RTC_TPR *(volatile uint32_t *)0x4003D004 // RTC Time Prescaler Register
800 #define RTC_TAR *(volatile uint32_t *)0x4003D008 // RTC Time Alarm Register
801 #define RTC_TCR *(volatile uint32_t *)0x4003D00C // RTC Time Compensation Register
802 #define RTC_TCR_CIC(n) (((n) & 255) << 24) // Compensation Interval Counter
803 #define RTC_TCR_TCV(n) (((n) & 255) << 16) // Time Compensation Value
804 #define RTC_TCR_CIR(n) (((n) & 255) << 8) // Compensation Interval Register
805 #define RTC_TCR_TCR(n) (((n) & 255) << 0) // Time Compensation Register
806 #define RTC_CR *(volatile uint32_t *)0x4003D010 // RTC Control Register
807 #define RTC_CR_SC2P (uint32_t)0x00002000 //
808 #define RTC_CR_SC4P (uint32_t)0x00001000 //
809 #define RTC_CR_SC8P (uint32_t)0x00000800 //
810 #define RTC_CR_SC16P (uint32_t)0x00000400 //
811 #define RTC_CR_CLKO (uint32_t)0x00000200 //
812 #define RTC_CR_OSCE (uint32_t)0x00000100 //
813 #define RTC_CR_UM (uint32_t)0x00000008 //
814 #define RTC_CR_SUP (uint32_t)0x00000004 //
815 #define RTC_CR_WPE (uint32_t)0x00000002 //
816 #define RTC_CR_SWR (uint32_t)0x00000001 //
817 #define RTC_SR *(volatile uint32_t *)0x4003D014 // RTC Status Register
818 #define RTC_SR_TCE (uint32_t)0x00000010 //
819 #define RTC_SR_TAF (uint32_t)0x00000004 //
820 #define RTC_SR_TOF (uint32_t)0x00000002 //
821 #define RTC_SR_TIF (uint32_t)0x00000001 //
822 #define RTC_LR *(volatile uint32_t *)0x4003D018 // RTC Lock Register
823 #define RTC_IER *(volatile uint32_t *)0x4003D01C // RTC Interrupt Enable Register
824 #define RTC_WAR *(volatile uint32_t *)0x4003D800 // RTC Write Access Register
825 #define RTC_RAR *(volatile uint32_t *)0x4003D804 // RTC Read Access Register
827 // Chapter 40: Universal Serial Bus OTG Controller (USBOTG)
828 #define USB0_PERID *(const uint8_t *)0x40072000 // Peripheral ID register
829 #define USB0_IDCOMP *(const uint8_t *)0x40072004 // Peripheral ID Complement register
830 #define USB0_REV *(const uint8_t *)0x40072008 // Peripheral Revision register
831 #define USB0_ADDINFO *(volatile uint8_t *)0x4007200C // Peripheral Additional Info register
832 #define USB0_OTGISTAT *(volatile uint8_t *)0x40072010 // OTG Interrupt Status register
833 #define USB_OTGISTAT_IDCHG (uint8_t)0x80 //
834 #define USB_OTGISTAT_ONEMSEC (uint8_t)0x40 //
835 #define USB_OTGISTAT_LINE_STATE_CHG (uint8_t)0x20 //
836 #define USB_OTGISTAT_SESSVLDCHG (uint8_t)0x08 //
837 #define USB_OTGISTAT_B_SESS_CHG (uint8_t)0x04 //
838 #define USB_OTGISTAT_AVBUSCHG (uint8_t)0x01 //
839 #define USB0_OTGICR *(volatile uint8_t *)0x40072014 // OTG Interrupt Control Register
840 #define USB_OTGICR_IDEN (uint8_t)0x80 //
841 #define USB_OTGICR_ONEMSECEN (uint8_t)0x40 //
842 #define USB_OTGICR_LINESTATEEN (uint8_t)0x20 //
843 #define USB_OTGICR_SESSVLDEN (uint8_t)0x08 //
844 #define USB_OTGICR_BSESSEN (uint8_t)0x04 //
845 #define USB_OTGICR_AVBUSEN (uint8_t)0x01 //
846 #define USB0_OTGSTAT *(volatile uint8_t *)0x40072018 // OTG Status register
847 #define USB_OTGSTAT_ID (uint8_t)0x80 //
848 #define USB_OTGSTAT_ONEMSECEN (uint8_t)0x40 //
849 #define USB_OTGSTAT_LINESTATESTABLE (uint8_t)0x20 //
850 #define USB_OTGSTAT_SESS_VLD (uint8_t)0x08 //
851 #define USB_OTGSTAT_BSESSEND (uint8_t)0x04 //
852 #define USB_OTGSTAT_AVBUSVLD (uint8_t)0x01 //
853 #define USB0_OTGCTL *(volatile uint8_t *)0x4007201C // OTG Control Register
854 #define USB_OTGCTL_DPHIGH (uint8_t)0x80 //
855 #define USB_OTGCTL_DPLOW (uint8_t)0x20 //
856 #define USB_OTGCTL_DMLOW (uint8_t)0x10 //
857 #define USB_OTGCTL_OTGEN (uint8_t)0x04 //
858 #define USB0_ISTAT *(volatile uint8_t *)0x40072080 // Interrupt Status Register
859 #define USB_ISTAT_STALL (uint8_t)0x80 //
860 #define USB_ISTAT_ATTACH (uint8_t)0x40 //
861 #define USB_ISTAT_RESUME (uint8_t)0x20 //
862 #define USB_ISTAT_SLEEP (uint8_t)0x10 //
863 #define USB_ISTAT_TOKDNE (uint8_t)0x08 //
864 #define USB_ISTAT_SOFTOK (uint8_t)0x04 //
865 #define USB_ISTAT_ERROR (uint8_t)0x02 //
866 #define USB_ISTAT_USBRST (uint8_t)0x01 //
867 #define USB0_INTEN *(volatile uint8_t *)0x40072084 // Interrupt Enable Register
868 #define USB_INTEN_STALLEN (uint8_t)0x80 //
869 #define USB_INTEN_ATTACHEN (uint8_t)0x40 //
870 #define USB_INTEN_RESUMEEN (uint8_t)0x20 //
871 #define USB_INTEN_SLEEPEN (uint8_t)0x10 //
872 #define USB_INTEN_TOKDNEEN (uint8_t)0x08 //
873 #define USB_INTEN_SOFTOKEN (uint8_t)0x04 //
874 #define USB_INTEN_ERROREN (uint8_t)0x02 //
875 #define USB_INTEN_USBRSTEN (uint8_t)0x01 //
876 #define USB0_ERRSTAT *(volatile uint8_t *)0x40072088 // Error Interrupt Status Register
877 #define USB_ERRSTAT_BTSERR (uint8_t)0x80 //
878 #define USB_ERRSTAT_DMAERR (uint8_t)0x20 //
879 #define USB_ERRSTAT_BTOERR (uint8_t)0x10 //
880 #define USB_ERRSTAT_DFN8 (uint8_t)0x08 //
881 #define USB_ERRSTAT_CRC16 (uint8_t)0x04 //
882 #define USB_ERRSTAT_CRC5EOF (uint8_t)0x02 //
883 #define USB_ERRSTAT_PIDERR (uint8_t)0x01 //
884 #define USB0_ERREN *(volatile uint8_t *)0x4007208C // Error Interrupt Enable Register
885 #define USB_ERREN_BTSERREN (uint8_t)0x80 //
886 #define USB_ERREN_DMAERREN (uint8_t)0x20 //
887 #define USB_ERREN_BTOERREN (uint8_t)0x10 //
888 #define USB_ERREN_DFN8EN (uint8_t)0x08 //
889 #define USB_ERREN_CRC16EN (uint8_t)0x04 //
890 #define USB_ERREN_CRC5EOFEN (uint8_t)0x02 //
891 #define USB_ERREN_PIDERREN (uint8_t)0x01 //
892 #define USB0_STAT *(volatile uint8_t *)0x40072090 // Status Register
893 #define USB_STAT_TX (uint8_t)0x08 //
894 #define USB_STAT_ODD (uint8_t)0x04 //
895 #define USB_STAT_ENDP(n) (uint8_t)((n) >> 4) //
896 #define USB0_CTL *(volatile uint8_t *)0x40072094 // Control Register
897 #define USB_CTL_JSTATE (uint8_t)0x80 //
898 #define USB_CTL_SE0 (uint8_t)0x40 //
899 #define USB_CTL_TXSUSPENDTOKENBUSY (uint8_t)0x20 //
900 #define USB_CTL_RESET (uint8_t)0x10 //
901 #define USB_CTL_HOSTMODEEN (uint8_t)0x08 //
902 #define USB_CTL_RESUME (uint8_t)0x04 //
903 #define USB_CTL_ODDRST (uint8_t)0x02 //
904 #define USB_CTL_USBENSOFEN (uint8_t)0x01 //
905 #define USB0_ADDR *(volatile uint8_t *)0x40072098 // Address Register
906 #define USB0_BDTPAGE1 *(volatile uint8_t *)0x4007209C // BDT Page Register 1
907 #define USB0_FRMNUML *(volatile uint8_t *)0x400720A0 // Frame Number Register Low
908 #define USB0_FRMNUMH *(volatile uint8_t *)0x400720A4 // Frame Number Register High
909 #define USB0_TOKEN *(volatile uint8_t *)0x400720A8 // Token Register
910 #define USB0_SOFTHLD *(volatile uint8_t *)0x400720AC // SOF Threshold Register
911 #define USB0_BDTPAGE2 *(volatile uint8_t *)0x400720B0 // BDT Page Register 2
912 #define USB0_BDTPAGE3 *(volatile uint8_t *)0x400720B4 // BDT Page Register 3
913 #define USB0_ENDPT0 *(volatile uint8_t *)0x400720C0 // Endpoint Control Register
914 #define USB_ENDPT_HOSTWOHUB (uint8_t)0x80 // host only, enable low speed
915 #define USB_ENDPT_RETRYDIS (uint8_t)0x40 // host only, set to disable NAK retry
916 #define USB_ENDPT_EPCTLDIS (uint8_t)0x10 // 0=control, 1=bulk, interrupt, isync
917 #define USB_ENDPT_EPRXEN (uint8_t)0x08 // enables the endpoint for RX transfers.
918 #define USB_ENDPT_EPTXEN (uint8_t)0x04 // enables the endpoint for TX transfers.
919 #define USB_ENDPT_EPSTALL (uint8_t)0x02 // set to stall endpoint
920 #define USB_ENDPT_EPHSHK (uint8_t)0x01 // enable handshaking during a transaction, generally set unless Isochronous
921 #define USB0_ENDPT1 *(volatile uint8_t *)0x400720C4 // Endpoint Control Register
922 #define USB0_ENDPT2 *(volatile uint8_t *)0x400720C8 // Endpoint Control Register
923 #define USB0_ENDPT3 *(volatile uint8_t *)0x400720CC // Endpoint Control Register
924 #define USB0_ENDPT4 *(volatile uint8_t *)0x400720D0 // Endpoint Control Register
925 #define USB0_ENDPT5 *(volatile uint8_t *)0x400720D4 // Endpoint Control Register
926 #define USB0_ENDPT6 *(volatile uint8_t *)0x400720D8 // Endpoint Control Register
927 #define USB0_ENDPT7 *(volatile uint8_t *)0x400720DC // Endpoint Control Register
928 #define USB0_ENDPT8 *(volatile uint8_t *)0x400720E0 // Endpoint Control Register
929 #define USB0_ENDPT9 *(volatile uint8_t *)0x400720E4 // Endpoint Control Register
930 #define USB0_ENDPT10 *(volatile uint8_t *)0x400720E8 // Endpoint Control Register
931 #define USB0_ENDPT11 *(volatile uint8_t *)0x400720EC // Endpoint Control Register
932 #define USB0_ENDPT12 *(volatile uint8_t *)0x400720F0 // Endpoint Control Register
933 #define USB0_ENDPT13 *(volatile uint8_t *)0x400720F4 // Endpoint Control Register
934 #define USB0_ENDPT14 *(volatile uint8_t *)0x400720F8 // Endpoint Control Register
935 #define USB0_ENDPT15 *(volatile uint8_t *)0x400720FC // Endpoint Control Register
936 #define USB0_USBCTRL *(volatile uint8_t *)0x40072100 // USB Control Register
937 #define USB_USBCTRL_SUSP (uint8_t)0x80 // Places the USB transceiver into the suspend state.
938 #define USB_USBCTRL_PDE (uint8_t)0x40 // Enables the weak pulldowns on the USB transceiver.
939 #define USB0_OBSERVE *(volatile uint8_t *)0x40072104 // USB OTG Observe Register
940 #define USB_OBSERVE_DPPU (uint8_t)0x80 //
941 #define USB_OBSERVE_DPPD (uint8_t)0x40 //
942 #define USB_OBSERVE_DMPD (uint8_t)0x10 //
943 #define USB0_CONTROL *(volatile uint8_t *)0x40072108 // USB OTG Control Register
944 #define USB_CONTROL_DPPULLUPNONOTG (uint8_t)0x10 // Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode.
945 #define USB0_USBTRC0 *(volatile uint8_t *)0x4007210C // USB Transceiver Control Register 0
946 #define USB_USBTRC_USBRESET (uint8_t)0x80 //
947 #define USB_USBTRC_USBRESMEN (uint8_t)0x20 //
948 #define USB_USBTRC_SYNC_DET (uint8_t)0x02 //
949 #define USB_USBTRC_USB_RESUME_INT (uint8_t)0x01 //
950 #define USB0_USBFRMADJUST *(volatile uint8_t *)0x40072114 // Frame Adjust Register
952 // Chapter 41: USB Device Charger Detection Module (USBDCD)
953 #define USBDCD_CONTROL *(volatile uint32_t *)0x40035000 // Control register
954 #define USBDCD_CLOCK *(volatile uint32_t *)0x40035004 // Clock register
955 #define USBDCD_STATUS *(volatile uint32_t *)0x40035008 // Status register
956 #define USBDCD_TIMER0 *(volatile uint32_t *)0x40035010 // TIMER0 register
957 #define USBDCD_TIMER1 *(volatile uint32_t *)0x40035014 // TIMER1 register
958 #define USBDCD_TIMER2 *(volatile uint32_t *)0x40035018 // TIMER2 register
960 // Chapter 43: SPI (DSPI)
961 #define SPI0_MCR *(volatile uint32_t *)0x4002C000 // DSPI Module Configuration Register
962 #define SPI_MCR_MSTR (uint32_t)0x80000000 // Master/Slave Mode Select
963 #define SPI_MCR_CONT_SCKE (uint32_t)0x40000000 //
964 #define SPI_MCR_DCONF(n) (((n) & 3) << 28) //
965 #define SPI_MCR_FRZ (uint32_t)0x08000000 //
966 #define SPI_MCR_MTFE (uint32_t)0x04000000 //
967 #define SPI_MCR_ROOE (uint32_t)0x01000000 //
968 #define SPI_MCR_PCSIS(n) (((n) & 0x1F) << 16) //
969 #define SPI_MCR_DOZE (uint32_t)0x00008000 //
970 #define SPI_MCR_MDIS (uint32_t)0x00004000 //
971 #define SPI_MCR_DIS_TXF (uint32_t)0x00002000 //
972 #define SPI_MCR_DIS_RXF (uint32_t)0x00001000 //
973 #define SPI_MCR_CLR_TXF (uint32_t)0x00000800 //
974 #define SPI_MCR_CLR_RXF (uint32_t)0x00000400 //
975 #define SPI_MCR_SMPL_PT(n) (((n) & 3) << 8) //
976 #define SPI_MCR_HALT (uint32_t)0x00000001 //
977 #define SPI0_TCR *(volatile uint32_t *)0x4002C008 // DSPI Transfer Count Register
978 #define SPI0_CTAR0 *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Master Mode
979 #define SPI_CTAR_DBR (uint32_t)0x80000000 // Double Baud Rate
980 #define SPI_CTAR_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1)
981 #define SPI_CTAR_CPOL (uint32_t)0x04000000 // Clock Polarity
982 #define SPI_CTAR_CPHA (uint32_t)0x02000000 // Clock Phase
983 #define SPI_CTAR_LSBFE (uint32_t)0x01000000 // LSB First
984 #define SPI_CTAR_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler
985 #define SPI_CTAR_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler
986 #define SPI_CTAR_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler
987 #define SPI_CTAR_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler
988 #define SPI_CTAR_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler
989 #define SPI_CTAR_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler
990 #define SPI_CTAR_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler
991 #define SPI_CTAR_BR(n) (((n) & 15) << 0) // Baud Rate Scaler
992 #define SPI0_CTAR0_SLAVE *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Slave Mode
993 #define SPI0_CTAR1 *(volatile uint32_t *)0x4002C010 // DSPI Clock and Transfer Attributes Register, In Master Mode
994 #define SPI0_SR *(volatile uint32_t *)0x4002C02C // DSPI Status Register
995 #define SPI_SR_TCF (uint32_t)0x80000000 // Transfer Complete Flag
996 #define SPI_SR_TXRXS (uint32_t)0x40000000 // TX and RX Status
997 #define SPI_SR_EOQF (uint32_t)0x10000000 // End of Queue Flag
998 #define SPI_SR_TFUF (uint32_t)0x08000000 // Transmit FIFO Underflow Flag
999 #define SPI_SR_TFFF (uint32_t)0x02000000 // Transmit FIFO Fill Flag
1000 #define SPI_SR_RFOF (uint32_t)0x00080000 // Receive FIFO Overflow Flag
1001 #define SPI_SR_RFDF (uint32_t)0x00020000 // Receive FIFO Drain Flag
1002 #define SPI0_RSER *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register
1003 #define SPI0_PUSHR *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Master Mode
1004 #define SPI0_PUSHR_CONT (uint32_t)0x80000000 //
1005 #define SPI0_PUSHR_CTAS(n) (((n) & 7) << 28) //
1006 #define SPI0_PUSHR_EOQ (uint32_t)0x08000000 //
1007 #define SPI0_PUSHR_CTCNT (uint32_t)0x04000000 //
1008 #define SPI0_PUSHR_PCS(n) (((n) & 31) << 16) //
1009 #define SPI0_PUSHR_SLAVE *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Slave Mode
1010 #define SPI0_POPR *(volatile uint32_t *)0x4002C038 // DSPI POP RX FIFO Register
1011 #define SPI0_TXFR0 *(volatile uint32_t *)0x4002C03C // DSPI Transmit FIFO Registers
1012 #define SPI0_TXFR1 *(volatile uint32_t *)0x4002C040 // DSPI Transmit FIFO Registers
1013 #define SPI0_TXFR2 *(volatile uint32_t *)0x4002C044 // DSPI Transmit FIFO Registers
1014 #define SPI0_TXFR3 *(volatile uint32_t *)0x4002C048 // DSPI Transmit FIFO Registers
1015 #define SPI0_RXFR0 *(volatile uint32_t *)0x4002C07C // DSPI Receive FIFO Registers
1016 #define SPI0_RXFR1 *(volatile uint32_t *)0x4002C080 // DSPI Receive FIFO Registers
1017 #define SPI0_RXFR2 *(volatile uint32_t *)0x4002C084 // DSPI Receive FIFO Registers
1018 #define SPI0_RXFR3 *(volatile uint32_t *)0x4002C088 // DSPI Receive FIFO Registers
1020 // Chapter 44: Inter-Integrated Circuit (I2C)
1021 #define I2C0_A1 *(volatile uint8_t *)0x40066000 // I2C Address Register 1
1022 #define I2C0_F *(volatile uint8_t *)0x40066001 // I2C Frequency Divider register
1023 #define I2C0_C1 *(volatile uint8_t *)0x40066002 // I2C Control Register 1
1024 #define I2C_C1_IICEN (uint8_t)0x80 // I2C Enable
1025 #define I2C_C1_IICIE (uint8_t)0x40 // I2C Interrupt Enable
1026 #define I2C_C1_MST (uint8_t)0x20 // Master Mode Select
1027 #define I2C_C1_TX (uint8_t)0x10 // Transmit Mode Select
1028 #define I2C_C1_TXAK (uint8_t)0x08 // Transmit Acknowledge Enable
1029 #define I2C_C1_RSTA (uint8_t)0x04 // Repeat START
1030 #define I2C_C1_WUEN (uint8_t)0x02 // Wakeup Enable
1031 #define I2C_C1_DMAEN (uint8_t)0x01 // DMA Enable
1032 #define I2C0_S *(volatile uint8_t *)0x40066003 // I2C Status register
1033 #define I2C_S_TCF (uint8_t)0x80 // Transfer Complete Flag
1034 #define I2C_S_IAAS (uint8_t)0x40 // Addressed As A Slave
1035 #define I2C_S_BUSY (uint8_t)0x20 // Bus Busy
1036 #define I2C_S_ARBL (uint8_t)0x10 // Arbitration Lost
1037 #define I2C_S_RAM (uint8_t)0x08 // Range Address Match
1038 #define I2C_S_SRW (uint8_t)0x04 // Slave Read/Write
1039 #define I2C_S_IICIF (uint8_t)0x02 // Interrupt Flag
1040 #define I2C_S_RXAK (uint8_t)0x01 // Receive Acknowledge
1041 #define I2C0_D *(volatile uint8_t *)0x40066004 // I2C Data I/O register
1042 #define I2C0_C2 *(volatile uint8_t *)0x40066005 // I2C Control Register 2
1043 #define I2C_C2_GCAEN (uint8_t)0x80 // General Call Address Enable
1044 #define I2C_C2_ADEXT (uint8_t)0x40 // Address Extension
1045 #define I2C_C2_HDRS (uint8_t)0x20 // High Drive Select
1046 #define I2C_C2_SBRC (uint8_t)0x10 // Slave Baud Rate Control
1047 #define I2C_C2_RMEN (uint8_t)0x08 // Range Address Matching Enable
1048 #define I2C_C2_AD(n) ((n) & 7) // Slave Address, upper 3 bits
1049 #define I2C0_FLT *(volatile uint8_t *)0x40066006 // I2C Programmable Input Glitch Filter register
1050 #define I2C0_RA *(volatile uint8_t *)0x40066007 // I2C Range Address register
1051 #define I2C0_SMB *(volatile uint8_t *)0x40066008 // I2C SMBus Control and Status register
1052 #define I2C0_A2 *(volatile uint8_t *)0x40066009 // I2C Address Register 2
1053 #define I2C0_SLTH *(volatile uint8_t *)0x4006600A // I2C SCL Low Timeout Register High
1054 #define I2C0_SLTL *(volatile uint8_t *)0x4006600B // I2C SCL Low Timeout Register Low
1056 // Chapter 45: Universal Asynchronous Receiver/Transmitter (UART)
1057 #define UART0_BDH *(volatile uint8_t *)0x4006A000 // UART Baud Rate Registers: High
1058 #define UART0_BDL *(volatile uint8_t *)0x4006A001 // UART Baud Rate Registers: Low
1059 #define UART0_C1 *(volatile uint8_t *)0x4006A002 // UART Control Register 1
1060 #define UART_C1_LOOPS (uint8_t)0x80 // When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input
1061 #define UART_C1_UARTSWAI (uint8_t)0x40 // UART Stops in Wait Mode
1062 #define UART_C1_RSRC (uint8_t)0x20 // When LOOPS is set, the RSRC field determines the source for the receiver shift register input
1063 #define UART_C1_M (uint8_t)0x10 // 9-bit or 8-bit Mode Select
1064 #define UART_C1_WAKE (uint8_t)0x08 // Determines which condition wakes the UART
1065 #define UART_C1_ILT (uint8_t)0x04 // Idle Line Type Select
1066 #define UART_C1_PE (uint8_t)0x02 // Parity Enable
1067 #define UART_C1_PT (uint8_t)0x01 // Parity Type, 0=even, 1=odd
1068 #define UART0_C2 *(volatile uint8_t *)0x4006A003 // UART Control Register 2
1069 #define UART_C2_TIE (uint8_t)0x80 // Transmitter Interrupt or DMA Transfer Enable.
1070 #define UART_C2_TCIE (uint8_t)0x40 // Transmission Complete Interrupt Enable
1071 #define UART_C2_RIE (uint8_t)0x20 // Receiver Full Interrupt or DMA Transfer Enable
1072 #define UART_C2_ILIE (uint8_t)0x10 // Idle Line Interrupt Enable
1073 #define UART_C2_TE (uint8_t)0x08 // Transmitter Enable
1074 #define UART_C2_RE (uint8_t)0x04 // Receiver Enable
1075 #define UART_C2_RWU (uint8_t)0x02 // Receiver Wakeup Control
1076 #define UART_C2_SBK (uint8_t)0x01 // Send Break
1077 #define UART0_S1 *(volatile uint8_t *)0x4006A004 // UART Status Register 1
1078 #define UART_S1_TDRE (uint8_t)0x80 // Transmit Data Register Empty Flag
1079 #define UART_S1_TC (uint8_t)0x40 // Transmit Complete Flag
1080 #define UART_S1_RDRF (uint8_t)0x20 // Receive Data Register Full Flag
1081 #define UART_S1_IDLE (uint8_t)0x10 // Idle Line Flag
1082 #define UART_S1_OR (uint8_t)0x08 // Receiver Overrun Flag
1083 #define UART_S1_NF (uint8_t)0x04 // Noise Flag
1084 #define UART_S1_FE (uint8_t)0x02 // Framing Error Flag
1085 #define UART_S1_PF (uint8_t)0x01 // Parity Error Flag
1086 #define UART0_S2 *(volatile uint8_t *)0x4006A005 // UART Status Register 2
1087 #define UART0_C3 *(volatile uint8_t *)0x4006A006 // UART Control Register 3
1088 #define UART0_D *(volatile uint8_t *)0x4006A007 // UART Data Register
1089 #define UART0_MA1 *(volatile uint8_t *)0x4006A008 // UART Match Address Registers 1
1090 #define UART0_MA2 *(volatile uint8_t *)0x4006A009 // UART Match Address Registers 2
1091 #define UART0_C4 *(volatile uint8_t *)0x4006A00A // UART Control Register 4
1092 #define UART0_C5 *(volatile uint8_t *)0x4006A00B // UART Control Register 5
1093 #define UART0_ED *(volatile uint8_t *)0x4006A00C // UART Extended Data Register
1094 #define UART0_MODEM *(volatile uint8_t *)0x4006A00D // UART Modem Register
1095 #define UART0_IR *(volatile uint8_t *)0x4006A00E // UART Infrared Register
1096 #define UART0_PFIFO *(volatile uint8_t *)0x4006A010 // UART FIFO Parameters
1097 #define UART_PFIFO_TXFE (uint8_t)0x80
1098 #define UART_PFIFO_RXFE (uint8_t)0x08
1099 #define UART0_CFIFO *(volatile uint8_t *)0x4006A011 // UART FIFO Control Register
1100 #define UART_CFIFO_TXFLUSH (uint8_t)0x80 //
1101 #define UART_CFIFO_RXFLUSH (uint8_t)0x40 //
1102 #define UART_CFIFO_RXOFE (uint8_t)0x04 //
1103 #define UART_CFIFO_TXOFE (uint8_t)0x02 //
1104 #define UART_CFIFO_RXUFE (uint8_t)0x01 //
1105 #define UART0_SFIFO *(volatile uint8_t *)0x4006A012 // UART FIFO Status Register
1106 #define UART_SFIFO_TXEMPT (uint8_t)0x80
1107 #define UART_SFIFO_RXEMPT (uint8_t)0x40
1108 #define UART_SFIFO_RXOF (uint8_t)0x04
1109 #define UART_SFIFO_TXOF (uint8_t)0x02
1110 #define UART_SFIFO_RXUF (uint8_t)0x01
1111 #define UART0_TWFIFO *(volatile uint8_t *)0x4006A013 // UART FIFO Transmit Watermark
1112 #define UART0_TCFIFO *(volatile uint8_t *)0x4006A014 // UART FIFO Transmit Count
1113 #define UART0_RWFIFO *(volatile uint8_t *)0x4006A015 // UART FIFO Receive Watermark
1114 #define UART0_RCFIFO *(volatile uint8_t *)0x4006A016 // UART FIFO Receive Count
1115 #define UART0_C7816 *(volatile uint8_t *)0x4006A018 // UART 7816 Control Register
1116 #define UART0_IE7816 *(volatile uint8_t *)0x4006A019 // UART 7816 Interrupt Enable Register
1117 #define UART0_IS7816 *(volatile uint8_t *)0x4006A01A // UART 7816 Interrupt Status Register
1118 #define UART0_WP7816T0 *(volatile uint8_t *)0x4006A01B // UART 7816 Wait Parameter Register
1119 #define UART0_WP7816T1 *(volatile uint8_t *)0x4006A01B // UART 7816 Wait Parameter Register
1120 #define UART0_WN7816 *(volatile uint8_t *)0x4006A01C // UART 7816 Wait N Register
1121 #define UART0_WF7816 *(volatile uint8_t *)0x4006A01D // UART 7816 Wait FD Register
1122 #define UART0_ET7816 *(volatile uint8_t *)0x4006A01E // UART 7816 Error Threshold Register
1123 #define UART0_TL7816 *(volatile uint8_t *)0x4006A01F // UART 7816 Transmit Length Register
1124 #define UART0_C6 *(volatile uint8_t *)0x4006A021 // UART CEA709.1-B Control Register 6
1125 #define UART0_PCTH *(volatile uint8_t *)0x4006A022 // UART CEA709.1-B Packet Cycle Time Counter High
1126 #define UART0_PCTL *(volatile uint8_t *)0x4006A023 // UART CEA709.1-B Packet Cycle Time Counter Low
1127 #define UART0_B1T *(volatile uint8_t *)0x4006A024 // UART CEA709.1-B Beta1 Timer
1128 #define UART0_SDTH *(volatile uint8_t *)0x4006A025 // UART CEA709.1-B Secondary Delay Timer High
1129 #define UART0_SDTL *(volatile uint8_t *)0x4006A026 // UART CEA709.1-B Secondary Delay Timer Low
1130 #define UART0_PRE *(volatile uint8_t *)0x4006A027 // UART CEA709.1-B Preamble
1131 #define UART0_TPL *(volatile uint8_t *)0x4006A028 // UART CEA709.1-B Transmit Packet Length
1132 #define UART0_IE *(volatile uint8_t *)0x4006A029 // UART CEA709.1-B Interrupt Enable Register
1133 #define UART0_WB *(volatile uint8_t *)0x4006A02A // UART CEA709.1-B WBASE
1134 #define UART0_S3 *(volatile uint8_t *)0x4006A02B // UART CEA709.1-B Status Register
1135 #define UART0_S4 *(volatile uint8_t *)0x4006A02C // UART CEA709.1-B Status Register
1136 #define UART0_RPL *(volatile uint8_t *)0x4006A02D // UART CEA709.1-B Received Packet Length
1137 #define UART0_RPREL *(volatile uint8_t *)0x4006A02E // UART CEA709.1-B Received Preamble Length
1138 #define UART0_CPW *(volatile uint8_t *)0x4006A02F // UART CEA709.1-B Collision Pulse Width
1139 #define UART0_RIDT *(volatile uint8_t *)0x4006A030 // UART CEA709.1-B Receive Indeterminate Time
1140 #define UART0_TIDT *(volatile uint8_t *)0x4006A031 // UART CEA709.1-B Transmit Indeterminate Time
1141 #define UART1_BDH *(volatile uint8_t *)0x4006B000 // UART Baud Rate Registers: High
1142 #define UART1_BDL *(volatile uint8_t *)0x4006B001 // UART Baud Rate Registers: Low
1143 #define UART1_C1 *(volatile uint8_t *)0x4006B002 // UART Control Register 1
1144 #define UART1_C2 *(volatile uint8_t *)0x4006B003 // UART Control Register 2
1145 #define UART1_S1 *(volatile uint8_t *)0x4006B004 // UART Status Register 1
1146 #define UART1_S2 *(volatile uint8_t *)0x4006B005 // UART Status Register 2
1147 #define UART1_C3 *(volatile uint8_t *)0x4006B006 // UART Control Register 3
1148 #define UART1_D *(volatile uint8_t *)0x4006B007 // UART Data Register
1149 #define UART1_MA1 *(volatile uint8_t *)0x4006B008 // UART Match Address Registers 1
1150 #define UART1_MA2 *(volatile uint8_t *)0x4006B009 // UART Match Address Registers 2
1151 #define UART1_C4 *(volatile uint8_t *)0x4006B00A // UART Control Register 4
1152 #define UART1_C5 *(volatile uint8_t *)0x4006B00B // UART Control Register 5
1153 #define UART1_ED *(volatile uint8_t *)0x4006B00C // UART Extended Data Register
1154 #define UART1_MODEM *(volatile uint8_t *)0x4006B00D // UART Modem Register
1155 #define UART1_IR *(volatile uint8_t *)0x4006B00E // UART Infrared Register
1156 #define UART1_PFIFO *(volatile uint8_t *)0x4006B010 // UART FIFO Parameters
1157 #define UART1_CFIFO *(volatile uint8_t *)0x4006B011 // UART FIFO Control Register
1158 #define UART1_SFIFO *(volatile uint8_t *)0x4006B012 // UART FIFO Status Register
1159 #define UART1_TWFIFO *(volatile uint8_t *)0x4006B013 // UART FIFO Transmit Watermark
1160 #define UART1_TCFIFO *(volatile uint8_t *)0x4006B014 // UART FIFO Transmit Count
1161 #define UART1_RWFIFO *(volatile uint8_t *)0x4006B015 // UART FIFO Receive Watermark
1162 #define UART1_RCFIFO *(volatile uint8_t *)0x4006B016 // UART FIFO Receive Count
1163 #define UART1_C7816 *(volatile uint8_t *)0x4006B018 // UART 7816 Control Register
1164 #define UART1_IE7816 *(volatile uint8_t *)0x4006B019 // UART 7816 Interrupt Enable Register
1165 #define UART1_IS7816 *(volatile uint8_t *)0x4006B01A // UART 7816 Interrupt Status Register
1166 #define UART1_WP7816T0 *(volatile uint8_t *)0x4006B01B // UART 7816 Wait Parameter Register
1167 #define UART1_WP7816T1 *(volatile uint8_t *)0x4006B01B // UART 7816 Wait Parameter Register
1168 #define UART1_WN7816 *(volatile uint8_t *)0x4006B01C // UART 7816 Wait N Register
1169 #define UART1_WF7816 *(volatile uint8_t *)0x4006B01D // UART 7816 Wait FD Register
1170 #define UART1_ET7816 *(volatile uint8_t *)0x4006B01E // UART 7816 Error Threshold Register
1171 #define UART1_TL7816 *(volatile uint8_t *)0x4006B01F // UART 7816 Transmit Length Register
1172 #define UART1_C6 *(volatile uint8_t *)0x4006B021 // UART CEA709.1-B Control Register 6
1173 #define UART1_PCTH *(volatile uint8_t *)0x4006B022 // UART CEA709.1-B Packet Cycle Time Counter High
1174 #define UART1_PCTL *(volatile uint8_t *)0x4006B023 // UART CEA709.1-B Packet Cycle Time Counter Low
1175 #define UART1_B1T *(volatile uint8_t *)0x4006B024 // UART CEA709.1-B Beta1 Timer
1176 #define UART1_SDTH *(volatile uint8_t *)0x4006B025 // UART CEA709.1-B Secondary Delay Timer High
1177 #define UART1_SDTL *(volatile uint8_t *)0x4006B026 // UART CEA709.1-B Secondary Delay Timer Low
1178 #define UART1_PRE *(volatile uint8_t *)0x4006B027 // UART CEA709.1-B Preamble
1179 #define UART1_TPL *(volatile uint8_t *)0x4006B028 // UART CEA709.1-B Transmit Packet Length
1180 #define UART1_IE *(volatile uint8_t *)0x4006B029 // UART CEA709.1-B Interrupt Enable Register
1181 #define UART1_WB *(volatile uint8_t *)0x4006B02A // UART CEA709.1-B WBASE
1182 #define UART1_S3 *(volatile uint8_t *)0x4006B02B // UART CEA709.1-B Status Register
1183 #define UART1_S4 *(volatile uint8_t *)0x4006B02C // UART CEA709.1-B Status Register
1184 #define UART1_RPL *(volatile uint8_t *)0x4006B02D // UART CEA709.1-B Received Packet Length
1185 #define UART1_RPREL *(volatile uint8_t *)0x4006B02E // UART CEA709.1-B Received Preamble Length
1186 #define UART1_CPW *(volatile uint8_t *)0x4006B02F // UART CEA709.1-B Collision Pulse Width
1187 #define UART1_RIDT *(volatile uint8_t *)0x4006B030 // UART CEA709.1-B Receive Indeterminate Time
1188 #define UART1_TIDT *(volatile uint8_t *)0x4006B031 // UART CEA709.1-B Transmit Indeterminate Time
1189 #define UART2_BDH *(volatile uint8_t *)0x4006C000 // UART Baud Rate Registers: High
1190 #define UART2_BDL *(volatile uint8_t *)0x4006C001 // UART Baud Rate Registers: Low
1191 #define UART2_C1 *(volatile uint8_t *)0x4006C002 // UART Control Register 1
1192 #define UART2_C2 *(volatile uint8_t *)0x4006C003 // UART Control Register 2
1193 #define UART2_S1 *(volatile uint8_t *)0x4006C004 // UART Status Register 1
1194 #define UART2_S2 *(volatile uint8_t *)0x4006C005 // UART Status Register 2
1195 #define UART2_C3 *(volatile uint8_t *)0x4006C006 // UART Control Register 3
1196 #define UART2_D *(volatile uint8_t *)0x4006C007 // UART Data Register
1197 #define UART2_MA1 *(volatile uint8_t *)0x4006C008 // UART Match Address Registers 1
1198 #define UART2_MA2 *(volatile uint8_t *)0x4006C009 // UART Match Address Registers 2
1199 #define UART2_C4 *(volatile uint8_t *)0x4006C00A // UART Control Register 4
1200 #define UART2_C5 *(volatile uint8_t *)0x4006C00B // UART Control Register 5
1201 #define UART2_ED *(volatile uint8_t *)0x4006C00C // UART Extended Data Register
1202 #define UART2_MODEM *(volatile uint8_t *)0x4006C00D // UART Modem Register
1203 #define UART2_IR *(volatile uint8_t *)0x4006C00E // UART Infrared Register
1204 #define UART2_PFIFO *(volatile uint8_t *)0x4006C010 // UART FIFO Parameters
1205 #define UART2_CFIFO *(volatile uint8_t *)0x4006C011 // UART FIFO Control Register
1206 #define UART2_SFIFO *(volatile uint8_t *)0x4006C012 // UART FIFO Status Register
1207 #define UART2_TWFIFO *(volatile uint8_t *)0x4006C013 // UART FIFO Transmit Watermark
1208 #define UART2_TCFIFO *(volatile uint8_t *)0x4006C014 // UART FIFO Transmit Count
1209 #define UART2_RWFIFO *(volatile uint8_t *)0x4006C015 // UART FIFO Receive Watermark
1210 #define UART2_RCFIFO *(volatile uint8_t *)0x4006C016 // UART FIFO Receive Count
1211 #define UART2_C7816 *(volatile uint8_t *)0x4006C018 // UART 7816 Control Register
1212 #define UART2_IE7816 *(volatile uint8_t *)0x4006C019 // UART 7816 Interrupt Enable Register
1213 #define UART2_IS7816 *(volatile uint8_t *)0x4006C01A // UART 7816 Interrupt Status Register
1214 #define UART2_WP7816T0 *(volatile uint8_t *)0x4006C01B // UART 7816 Wait Parameter Register
1215 #define UART2_WP7816T1 *(volatile uint8_t *)0x4006C01B // UART 7816 Wait Parameter Register
1216 #define UART2_WN7816 *(volatile uint8_t *)0x4006C01C // UART 7816 Wait N Register
1217 #define UART2_WF7816 *(volatile uint8_t *)0x4006C01D // UART 7816 Wait FD Register
1218 #define UART2_ET7816 *(volatile uint8_t *)0x4006C01E // UART 7816 Error Threshold Register
1219 #define UART2_TL7816 *(volatile uint8_t *)0x4006C01F // UART 7816 Transmit Length Register
1220 #define UART2_C6 *(volatile uint8_t *)0x4006C021 // UART CEA709.1-B Control Register 6
1221 #define UART2_PCTH *(volatile uint8_t *)0x4006C022 // UART CEA709.1-B Packet Cycle Time Counter High
1222 #define UART2_PCTL *(volatile uint8_t *)0x4006C023 // UART CEA709.1-B Packet Cycle Time Counter Low
1223 #define UART2_B1T *(volatile uint8_t *)0x4006C024 // UART CEA709.1-B Beta1 Timer
1224 #define UART2_SDTH *(volatile uint8_t *)0x4006C025 // UART CEA709.1-B Secondary Delay Timer High
1225 #define UART2_SDTL *(volatile uint8_t *)0x4006C026 // UART CEA709.1-B Secondary Delay Timer Low
1226 #define UART2_PRE *(volatile uint8_t *)0x4006C027 // UART CEA709.1-B Preamble
1227 #define UART2_TPL *(volatile uint8_t *)0x4006C028 // UART CEA709.1-B Transmit Packet Length
1228 #define UART2_IE *(volatile uint8_t *)0x4006C029 // UART CEA709.1-B Interrupt Enable Register
1229 #define UART2_WB *(volatile uint8_t *)0x4006C02A // UART CEA709.1-B WBASE
1230 #define UART2_S3 *(volatile uint8_t *)0x4006C02B // UART CEA709.1-B Status Register
1231 #define UART2_S4 *(volatile uint8_t *)0x4006C02C // UART CEA709.1-B Status Register
1232 #define UART2_RPL *(volatile uint8_t *)0x4006C02D // UART CEA709.1-B Received Packet Length
1233 #define UART2_RPREL *(volatile uint8_t *)0x4006C02E // UART CEA709.1-B Received Preamble Length
1234 #define UART2_CPW *(volatile uint8_t *)0x4006C02F // UART CEA709.1-B Collision Pulse Width
1235 #define UART2_RIDT *(volatile uint8_t *)0x4006C030 // UART CEA709.1-B Receive Indeterminate Time
1236 #define UART2_TIDT *(volatile uint8_t *)0x4006C031 // UART CEA709.1-B Transmit Indeterminate Time
1238 // Chapter 46: Synchronous Audio Interface (SAI)
1239 #define I2S0_TCSR *(volatile uint32_t *)0x4002F000 // SAI Transmit Control Register
1240 #define I2S0_TCR1 *(volatile uint32_t *)0x4002F004 // SAI Transmit Configuration 1 Register
1241 #define I2S0_TCR2 *(volatile uint32_t *)0x4002F008 // SAI Transmit Configuration 2 Register
1242 #define I2S0_TCR3 *(volatile uint32_t *)0x4002F00C // SAI Transmit Configuration 3 Register
1243 #define I2S0_TCR4 *(volatile uint32_t *)0x4002F010 // SAI Transmit Configuration 4 Register
1244 #define I2S0_TCR5 *(volatile uint32_t *)0x4002F014 // SAI Transmit Configuration 5 Register
1245 #define I2S0_TDR0 *(volatile uint32_t *)0x4002F020 // SAI Transmit Data Register
1246 #define I2S0_TFR0 *(volatile uint32_t *)0x4002F040 // SAI Transmit FIFO Register
1247 #define I2S0_TMR *(volatile uint32_t *)0x4002F060 // SAI Transmit Mask Register
1248 #define I2S0_RCSR *(volatile uint32_t *)0x4002F080 // SAI Receive Control Register
1249 #define I2S0_RCR1 *(volatile uint32_t *)0x4002F084 // SAI Receive Configuration 1 Register
1250 #define I2S0_RCR2 *(volatile uint32_t *)0x4002F088 // SAI Receive Configuration 2 Register
1251 #define I2S0_RCR3 *(volatile uint32_t *)0x4002F08C // SAI Receive Configuration 3 Register
1252 #define I2S0_RCR4 *(volatile uint32_t *)0x4002F090 // SAI Receive Configuration 4 Register
1253 #define I2S0_RCR5 *(volatile uint32_t *)0x4002F094 // SAI Receive Configuration 5 Register
1254 #define I2S0_RDR0 *(volatile uint32_t *)0x4002F0A0 // SAI Receive Data Register
1255 #define I2S0_RFR0 *(volatile uint32_t *)0x4002F0C0 // SAI Receive FIFO Register
1256 #define I2S0_RMR *(volatile uint32_t *)0x4002F0E0 // SAI Receive Mask Register
1257 #define I2S0_MCR *(volatile uint32_t *)0x4002F100 // SAI MCLK Control Register
1258 #define I2S0_MDR *(volatile uint32_t *)0x4002F104 // SAI MCLK Divide Register
1260 // Chapter 47: General-Purpose Input/Output (GPIO)
1261 #define GPIOA_PDOR *(volatile uint32_t *)0x400FF000 // Port Data Output Register
1262 #define GPIOA_PSOR *(volatile uint32_t *)0x400FF004 // Port Set Output Register
1263 #define GPIOA_PCOR *(volatile uint32_t *)0x400FF008 // Port Clear Output Register
1264 #define GPIOA_PTOR *(volatile uint32_t *)0x400FF00C // Port Toggle Output Register
1265 #define GPIOA_PDIR *(volatile uint32_t *)0x400FF010 // Port Data Input Register
1266 #define GPIOA_PDDR *(volatile uint32_t *)0x400FF014 // Port Data Direction Register
1267 #define GPIOB_PDOR *(volatile uint32_t *)0x400FF040 // Port Data Output Register
1268 #define GPIOB_PSOR *(volatile uint32_t *)0x400FF044 // Port Set Output Register
1269 #define GPIOB_PCOR *(volatile uint32_t *)0x400FF048 // Port Clear Output Register
1270 #define GPIOB_PTOR *(volatile uint32_t *)0x400FF04C // Port Toggle Output Register
1271 #define GPIOB_PDIR *(volatile uint32_t *)0x400FF050 // Port Data Input Register
1272 #define GPIOB_PDDR *(volatile uint32_t *)0x400FF054 // Port Data Direction Register
1273 #define GPIOC_PDOR *(volatile uint32_t *)0x400FF080 // Port Data Output Register
1274 #define GPIOC_PSOR *(volatile uint32_t *)0x400FF084 // Port Set Output Register
1275 #define GPIOC_PCOR *(volatile uint32_t *)0x400FF088 // Port Clear Output Register
1276 #define GPIOC_PTOR *(volatile uint32_t *)0x400FF08C // Port Toggle Output Register
1277 #define GPIOC_PDIR *(volatile uint32_t *)0x400FF090 // Port Data Input Register
1278 #define GPIOC_PDDR *(volatile uint32_t *)0x400FF094 // Port Data Direction Register
1279 #define GPIOD_PDOR *(volatile uint32_t *)0x400FF0C0 // Port Data Output Register
1280 #define GPIOD_PSOR *(volatile uint32_t *)0x400FF0C4 // Port Set Output Register
1281 #define GPIOD_PCOR *(volatile uint32_t *)0x400FF0C8 // Port Clear Output Register
1282 #define GPIOD_PTOR *(volatile uint32_t *)0x400FF0CC // Port Toggle Output Register
1283 #define GPIOD_PDIR *(volatile uint32_t *)0x400FF0D0 // Port Data Input Register
1284 #define GPIOD_PDDR *(volatile uint32_t *)0x400FF0D4 // Port Data Direction Register
1285 #define GPIOE_PDOR *(volatile uint32_t *)0x400FF100 // Port Data Output Register
1286 #define GPIOE_PSOR *(volatile uint32_t *)0x400FF104 // Port Set Output Register
1287 #define GPIOE_PCOR *(volatile uint32_t *)0x400FF108 // Port Clear Output Register
1288 #define GPIOE_PTOR *(volatile uint32_t *)0x400FF10C // Port Toggle Output Register
1289 #define GPIOE_PDIR *(volatile uint32_t *)0x400FF110 // Port Data Input Register
1290 #define GPIOE_PDDR *(volatile uint32_t *)0x400FF114 // Port Data Direction Register
1292 // Chapter 48: Touch sense input (TSI)
1293 #define TSI0_GENCS *(volatile uint32_t *)0x40045000 // General Control and Status Register
1294 #define TSI_GENCS_LPCLKS (uint32_t)0x10000000 //
1295 #define TSI_GENCS_LPSCNITV(n) (((n) & 15) << 24) //
1296 #define TSI_GENCS_NSCN(n) (((n) & 31) << 19) //
1297 #define TSI_GENCS_PS(n) (((n) & 7) << 16) //
1298 #define TSI_GENCS_EOSF (uint32_t)0x00008000 //
1299 #define TSI_GENCS_OUTRGF (uint32_t)0x00004000 //
1300 #define TSI_GENCS_EXTERF (uint32_t)0x00002000 //
1301 #define TSI_GENCS_OVRF (uint32_t)0x00001000 //
1302 #define TSI_GENCS_SCNIP (uint32_t)0x00000200 //
1303 #define TSI_GENCS_SWTS (uint32_t)0x00000100 //
1304 #define TSI_GENCS_TSIEN (uint32_t)0x00000080 //
1305 #define TSI_GENCS_TSIIE (uint32_t)0x00000040 //
1306 #define TSI_GENCS_ERIE (uint32_t)0x00000020 //
1307 #define TSI_GENCS_ESOR (uint32_t)0x00000010 //
1308 #define TSI_GENCS_STM (uint32_t)0x00000002 //
1309 #define TSI_GENCS_STPE (uint32_t)0x00000001 //
1310 #define TSI0_SCANC *(volatile uint32_t *)0x40045004 // SCAN Control Register
1311 #define TSI_SCANC_REFCHRG(n) (((n) & 15) << 24) //
1312 #define TSI_SCANC_EXTCHRG(n) (((n) & 7) << 16) //
1313 #define TSI_SCANC_SMOD(n) (((n) & 255) << 8) //
1314 #define TSI_SCANC_AMCLKS(n) (((n) & 3) << 3) //
1315 #define TSI_SCANC_AMPSC(n) (((n) & 7) << 0) //
1316 #define TSI0_PEN *(volatile uint32_t *)0x40045008 // Pin Enable Register
1317 #define TSI0_WUCNTR *(volatile uint32_t *)0x4004500C // Wake-Up Channel Counter Register
1318 #define TSI0_CNTR1 *(volatile uint32_t *)0x40045100 // Counter Register
1319 #define TSI0_CNTR3 *(volatile uint32_t *)0x40045104 // Counter Register
1320 #define TSI0_CNTR5 *(volatile uint32_t *)0x40045108 // Counter Register
1321 #define TSI0_CNTR7 *(volatile uint32_t *)0x4004510C // Counter Register
1322 #define TSI0_CNTR9 *(volatile uint32_t *)0x40045110 // Counter Register
1323 #define TSI0_CNTR11 *(volatile uint32_t *)0x40045114 // Counter Register
1324 #define TSI0_CNTR13 *(volatile uint32_t *)0x40045118 // Counter Register
1325 #define TSI0_CNTR15 *(volatile uint32_t *)0x4004511C // Counter Register
1326 #define TSI0_THRESHOLD *(volatile uint32_t *)0x40045120 // Low Power Channel Threshold Register
1328 // Nested Vectored Interrupt Controller, Table 3-4 & ARMv7 ref, appendix B3.4 (page 750)
1329 #define NVIC_ENABLE_IRQ(n) (*((volatile uint32_t *)0xE000E100 + (n >> 5)) = (1 << (n & 31)))
1330 #define NVIC_DISABLE_IRQ(n) (*((volatile uint32_t *)0xE000E180 + (n >> 5)) = (1 << (n & 31)))
1331 #define NVIC_SET_PENDING(n) (*((volatile uint32_t *)0xE000E200 + (n >> 5)) = (1 << (n & 31)))
1332 #define NVIC_CLEAR_PENDING(n) (*((volatile uint32_t *)0xE000E280 + (n >> 5)) = (1 << (n & 31)))
1334 #define NVIC_ISER0 *(volatile uint32_t *)0xE000E100
1335 #define NVIC_ISER1 *(volatile uint32_t *)0xE000E104
1336 #define NVIC_ICER0 *(volatile uint32_t *)0xE000E180
1337 #define NVIC_ICER1 *(volatile uint32_t *)0xE000E184
1339 //#define NVIC_SET_PRIORITY(n, p)
1340 #define IRQ_DMA_CH0 0
1341 #define IRQ_DMA_CH1 1
1342 #define IRQ_DMA_CH2 2
1343 #define IRQ_DMA_CH3 3
1344 #define IRQ_DMA_ERROR 4
1345 #define IRQ_FTFL_COMPLETE 6
1346 #define IRQ_FTFL_COLLISION 7
1347 #define IRQ_LOW_VOLTAGE 8
1352 #define IRQ_I2S0_TX 13
1353 #define IRQ_I2S0_RX 14
1354 #define IRQ_UART0_LON 15
1355 #define IRQ_UART0_STATUS 16
1356 #define IRQ_UART0_ERROR 17
1357 #define IRQ_UART1_STATUS 18
1358 #define IRQ_UART1_ERROR 19
1359 #define IRQ_UART2_STATUS 20
1360 #define IRQ_UART2_ERROR 21
1367 #define IRQ_RTC_ALARM 28
1368 #define IRQ_RTC_SECOND 29
1369 #define IRQ_PIT_CH0 30
1370 #define IRQ_PIT_CH1 31
1371 #define IRQ_PIT_CH2 32
1372 #define IRQ_PIT_CH3 33
1374 #define IRQ_USBOTG 35
1375 #define IRQ_USBDCD 36
1378 #define IRQ_LPTMR 39
1379 #define IRQ_PORTA 40
1380 #define IRQ_PORTB 41
1381 #define IRQ_PORTC 42
1382 #define IRQ_PORTD 43
1383 #define IRQ_PORTE 44
1384 #define IRQ_SOFTWARE 45
1387 #define __disable_irq() asm volatile("CPSID i");
1388 #define __enable_irq() asm volatile("CPSIE i");
1391 // System Control Space (SCS), ARMv7 ref manual, B3.2, page 708
1392 #define SCB_CPUID *(const uint32_t *)0xE000ED00 // CPUID Base Register
1393 #define SCB_ICSR *(volatile uint32_t *)0xE000ED04 // Interrupt Control and State
1394 #define SCB_ICSR_PENDSTSET (uint32_t)0x04000000
1395 #define SCB_VTOR *(volatile uint32_t *)0xE000ED08 // Vector Table Offset
1396 #define SCB_AIRCR *(volatile uint32_t *)0xE000ED0C // Application Interrupt and Reset Control
1397 #define SCB_SCR *(volatile uint32_t *)0xE000ED10 // System Control Register
1398 #define SCB_CCR *(volatile uint32_t *)0xE000ED14 // Configuration and Control
1399 #define SCB_SHPR1 *(volatile uint32_t *)0xE000ED18 // System Handler Priority Register 1
1400 #define SCB_SHPR2 *(volatile uint32_t *)0xE000ED1C // System Handler Priority Register 2
1401 #define SCB_SHPR3 *(volatile uint32_t *)0xE000ED20 // System Handler Priority Register 3
1402 #define SCB_SHCSR *(volatile uint32_t *)0xE000ED24 // System Handler Control and State
1403 #define SCB_CFSR *(volatile uint32_t *)0xE000ED28 // Configurable Fault Status Register
1404 #define SCB_HFSR *(volatile uint32_t *)0xE000ED2C // HardFault Status
1405 #define SCB_DFSR *(volatile uint32_t *)0xE000ED30 // Debug Fault Status
1406 #define SCB_MMFAR *(volatile uint32_t *)0xE000ED34 // MemManage Fault Address
1408 #define SYST_CSR *(volatile uint32_t *)0xE000E010 // SysTick Control and Status
1409 #define SYST_CSR_COUNTFLAG (uint32_t)0x00010000
1410 #define SYST_CSR_CLKSOURCE (uint32_t)0x00000004
1411 #define SYST_CSR_TICKINT (uint32_t)0x00000002
1412 #define SYST_CSR_ENABLE (uint32_t)0x00000001
1413 #define SYST_RVR *(volatile uint32_t *)0xE000E014 // SysTick Reload Value Register
1414 #define SYST_CVR *(volatile uint32_t *)0xE000E018 // SysTick Current Value Register
1415 #define SYST_CALIB *(const uint32_t *)0xE000E01C // SysTick Calibration Value
1418 #define ARM_DEMCR *(volatile uint32_t *)0xE000EDFC // Debug Exception and Monitor Control
1419 #define ARM_DEMCR_TRCENA (1 << 24) // Enable debugging & monitoring blocks
1420 #define ARM_DWT_CTRL *(volatile uint32_t *)0xE0001000 // DWT control register
1421 #define ARM_DWT_CTRL_CYCCNTENA (1 << 0) // Enable cycle count
1422 #define ARM_DWT_CYCCNT *(volatile uint32_t *)0xE0001004 // Cycle count register
1425 extern void nmi_isr(void);
1426 extern void hard_fault_isr(void);
1427 extern void memmanage_fault_isr(void);
1428 extern void bus_fault_isr(void);
1429 extern void usage_fault_isr(void);
1430 extern void svcall_isr(void);
1431 extern void debugmonitor_isr(void);
1432 extern void pendablesrvreq_isr(void);
1433 extern void systick_isr(void);
1434 extern void dma_ch0_isr(void);
1435 extern void dma_ch1_isr(void);
1436 extern void dma_ch2_isr(void);
1437 extern void dma_ch3_isr(void);
1438 extern void dma_error_isr(void);
1439 extern void flash_cmd_isr(void);
1440 extern void flash_error_isr(void);
1441 extern void low_voltage_isr(void);
1442 extern void wakeup_isr(void);
1443 extern void watchdog_isr(void);
1444 extern void i2c0_isr(void);
1445 extern void spi0_isr(void);
1446 extern void i2s0_tx_isr(void);
1447 extern void i2s0_rx_isr(void);
1448 extern void uart0_lon_isr(void);
1449 extern void uart0_status_isr(void);
1450 extern void uart0_error_isr(void);
1451 extern void uart1_status_isr(void);
1452 extern void uart1_error_isr(void);
1453 extern void uart2_status_isr(void);
1454 extern void uart2_error_isr(void);
1455 extern void adc0_isr(void);
1456 extern void cmp0_isr(void);
1457 extern void cmp1_isr(void);
1458 extern void ftm0_isr(void);
1459 extern void ftm1_isr(void);
1460 extern void cmt_isr(void);
1461 extern void rtc_alarm_isr(void);
1462 extern void rtc_seconds_isr(void);
1463 extern void pit0_isr(void);
1464 extern void pit1_isr(void);
1465 extern void pit2_isr(void);
1466 extern void pit3_isr(void);
1467 extern void pdb_isr(void);
1468 extern void usb_isr(void);
1469 extern void usb_charge_isr(void);
1470 extern void tsi0_isr(void);
1471 extern void mcg_isr(void);
1472 extern void lptmr_isr(void);
1473 extern void porta_isr(void);
1474 extern void portb_isr(void);
1475 extern void portc_isr(void);
1476 extern void portd_isr(void);
1477 extern void porte_isr(void);
1478 extern void software_isr(void);
projects / kiibohd-controller.git / blob