]> git.donarmstrong.com Git - kiibohd-controller.git/commitdiff
Adding initial Teensy 3 support, compiles, but not fully functional yet.
authorJacob Alexander <triplehaata@gmail.com>
Sun, 27 Jan 2013 06:47:52 +0000 (01:47 -0500)
committerJacob Alexander <triplehaata@gmail.com>
Sun, 27 Jan 2013 06:47:52 +0000 (01:47 -0500)
- CDC Output seems to be working
- USB Keyboard output has not been tested, but is "ready"
- UART and Timers have not been tested, or fully utilized
- Issues using Timer 0
- Initial template for MBC-55X Scan module (only module currently compatible with the arm build)
- Updated the interface to the AVR usb module for symmetry with the ARM usb module
- Much gutting was done to the Teensy 3 usb keyboard module, though not in an ideal state yet

29 files changed:
CMakeLists.txt
Debug/print/print.h
Lib/Interrupts.h [new file with mode: 0644]
Lib/aliased_bitband.h [new file with mode: 0644]
Lib/delay.c [new file with mode: 0644]
Lib/delay.h [new file with mode: 0644]
Lib/mk20dx128.c [new file with mode: 0644]
Lib/mk20dx128.h [new file with mode: 0644]
Lib/mk20dx128.ld [new file with mode: 0644]
Lib/pin_map.teensy3 [new file with mode: 0644]
Scan/MBC-55X/scan_loop.c [new file with mode: 0644]
Scan/MBC-55X/scan_loop.h [new file with mode: 0644]
Scan/MBC-55X/setup.cmake [new file with mode: 0644]
USB/pjrc/arm/usb_desc.c [new file with mode: 0644]
USB/pjrc/arm/usb_desc.h [new file with mode: 0644]
USB/pjrc/arm/usb_dev.c [new file with mode: 0644]
USB/pjrc/arm/usb_dev.h [new file with mode: 0644]
USB/pjrc/arm/usb_keyboard.c [new file with mode: 0644]
USB/pjrc/arm/usb_keyboard.h [new file with mode: 0644]
USB/pjrc/arm/usb_mem.c [new file with mode: 0644]
USB/pjrc/arm/usb_mem.h [new file with mode: 0644]
USB/pjrc/arm/usb_serial.c [new file with mode: 0644]
USB/pjrc/arm/usb_serial.h [new file with mode: 0644]
USB/pjrc/avr/usb_keyboard_debug.c
USB/pjrc/usb_com.c
USB/pjrc/usb_com.h
arm.cmake
main.c
setup.cmake

index e1f2e4ba7b1e1e7f5f2fec3f75f26d8b50c6910a..6777092e6090f55fc158007990e3c6b613154cb7 100644 (file)
@@ -27,8 +27,8 @@ include( AddFileDependencies )
 #| "avr"       # Teensy++ 1.0
 #| "avr"       # Teensy++ 2.0
 #| "arm"       # Teensy   3.0
-#set( COMPILER_FAMILY "arm" )
-set( COMPILER_FAMILY "avr" )
+set( COMPILER_FAMILY "arm" )
+#set( COMPILER_FAMILY "avr" )
 
 message( STATUS "Compiler Family:" )
 message( "${COMPILER_FAMILY}" )
index b67f9200d2ab21b13ef364cad6f8c4ed0fe9bfac..fcfffd9970c8975bd3d4d87a91d595efcccd4312 100644 (file)
  */
 
 // Function Aliases
+#if defined(_at90usb162_) || defined(_atmega32u4_) || defined(_at90usb646_) || defined(_at90usb1286_) // AVR
 #define dPrint(c)         usb_debug_putchar(c)
+#elif defined(_mk20dx128_) // ARM
+#define dPrint(c)         usb_debug_putstr (c)
+#endif
 #define dPrintStr(c)      usb_debug_putstr (c)
 #define dPrintStrs(...)   usb_debug_putstrs(__VA_ARGS__, "\0\0\0")      // Convenience Variadic Macro
 #define dPrintStrNL(c)    dPrintStrs       (c, NL)                      // Appends New Line Macro
diff --git a/Lib/Interrupts.h b/Lib/Interrupts.h
new file mode 100644 (file)
index 0000000..943fdb9
--- /dev/null
@@ -0,0 +1,63 @@
+/* Copyright (C) 2013 by Jacob Alexander
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+// This include file unifies some of the nomenclature between the AVR and ARM compilers
+
+
+// ----- Includes -----
+
+#ifndef __INTERRUPTS_H
+#define __INTERRUPTS_H
+
+// ARM
+#if defined(_mk20dx128_)
+
+#include <Lib/mk20dx128.h>
+
+// AVR
+#elif defined(_at90usb162_) || defined(_atmega32u4_) || defined(_at90usb646_) || defined(_at90usb1286_)
+
+#include <avr/interrupt.h>
+
+#endif
+
+
+
+// ----- Defines -----
+
+// ARM
+#if defined(_mk20dx128_)
+
+// Map the Interrupt Enable/Disable to the AVR names
+#define cli() __disable_irq()
+#define sei() __enable_irq()
+
+
+// AVR
+#elif defined(_at90usb162_) || defined(_atmega32u4_) || defined(_at90usb646_) || defined(_at90usb1286_)
+
+
+#endif
+
+
+#endif
+
diff --git a/Lib/aliased_bitband.h b/Lib/aliased_bitband.h
new file mode 100644 (file)
index 0000000..44e8859
--- /dev/null
@@ -0,0 +1,37 @@
+
+#ifndef __aliased_bitband_h
+#define __aliased_bitband_h
+
+
+// Aliased Regions for single bit (0th) register access
+
+// Chapter 4: Memory Map (Table 4-1)
+
+
+
+// TODO
+// - Not all tested, and not all sections added
+
+
+
+// 0x2200 0000 - 0x23FF FFFF - Aliased to SRAM_U bitband
+// TODO
+
+
+
+// 0x4200 0000 - 0x43FF FFFF - Aliased to AIPS and GPIO bitband
+#define GPIO_BITBAND_ADDR(reg, bit) (((uint32_t)&(reg) - 0x40000000) * 32 + (bit) * 4 + 0x42000000)
+#define GPIO_BITBAND_PTR(reg, bit) ((uint32_t *)GPIO_BITBAND_ADDR((reg), (bit)))
+
+// XXX - Only MODREG is tested to work...
+#define GPIO_BITBAND_OUTREG(reg, bit) *((uint32_t *)GPIO_BITBAND_ADDR((reg), (bit)) +   0)
+#define GPIO_BITBAND_SETREG(reg, bit) *((uint32_t *)GPIO_BITBAND_ADDR((reg), (bit)) +  32)
+#define GPIO_BITBAND_CLRREG(reg, bit) *((uint32_t *)GPIO_BITBAND_ADDR((reg), (bit)) +  64)
+#define GPIO_BITBAND_TOGREG(reg, bit) *((uint32_t *)GPIO_BITBAND_ADDR((reg), (bit)) +  96)
+#define GPIO_BITBAND_INPREG(reg, bit) *((uint32_t *)GPIO_BITBAND_ADDR((reg), (bit)) + 128)
+#define GPIO_BITBAND_MODREG(reg, bit) *((uint32_t *)GPIO_BITBAND_ADDR((reg), (bit)) + 160)
+
+
+
+#endif
+
diff --git a/Lib/delay.c b/Lib/delay.c
new file mode 100644 (file)
index 0000000..9e19b9b
--- /dev/null
@@ -0,0 +1,37 @@
+
+#include "delay.h"
+#include "mk20dx128.h"
+
+// the systick interrupt is supposed to increment this at 1 kHz rate
+volatile uint32_t systick_millis_count = 0;
+
+void yield(void) {};
+
+uint32_t micros(void)
+{
+       uint32_t count, current, istatus;
+
+       __disable_irq();
+       current = SYST_CVR;
+       count = systick_millis_count;
+       istatus = SCB_ICSR; // bit 26 indicates if systick exception pending
+       __enable_irq();
+       if ((istatus & SCB_ICSR_PENDSTSET) && current > ((F_CPU / 1000) - 50)) count++;
+       current = ((F_CPU / 1000) - 1) - current;
+       return count * 1000 + current / (F_CPU / 1000000);
+}
+
+void delay(uint32_t ms)
+{
+       uint32_t start = micros();
+
+       while (1) {
+               if ((micros() - start) >= 1000) {
+                       ms--;
+                       if (ms == 0) break;
+                       start += 1000;
+               }
+               yield();
+       }
+}
+
diff --git a/Lib/delay.h b/Lib/delay.h
new file mode 100644 (file)
index 0000000..58746ef
--- /dev/null
@@ -0,0 +1,48 @@
+
+#ifndef __DELAY_H
+#define __DELAY_H
+
+#include <stdint.h>
+
+// Convenience Macros, for delay compatibility with AVR-GCC
+#define _delay_ms(val) delay( val )
+#define _delay_us(val) delayMicroseconds( val )
+
+
+// the systick interrupt is supposed to increment this at 1 kHz rate
+extern volatile uint32_t systick_millis_count;
+
+static inline uint32_t millis(void) __attribute__((always_inline, unused));
+static inline uint32_t millis(void)
+{
+       return systick_millis_count; // single aligned 32 bit is atomic;
+}
+
+
+static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused));
+static inline void delayMicroseconds(uint32_t usec)
+{
+#if F_CPU == 96000000
+       uint32_t n = usec << 5;
+#elif F_CPU == 48000000
+       uint32_t n = usec << 4;
+#elif F_CPU == 24000000
+       uint32_t n = usec << 3;
+#endif
+       asm volatile(
+               "L_%=_delayMicroseconds:"               "\n\t"
+               "subs   %0, #1"                         "\n\t"
+               "bne    L_%=_delayMicroseconds"         "\n"
+               : "+r" (n) :
+       );
+}
+
+
+void yield(void) __attribute__ ((weak));
+
+uint32_t micros(void);
+
+void delay(uint32_t ms);
+
+#endif
+
diff --git a/Lib/mk20dx128.c b/Lib/mk20dx128.c
new file mode 100644 (file)
index 0000000..57a542a
--- /dev/null
@@ -0,0 +1,328 @@
+#include "mk20dx128.h"
+
+
+extern unsigned long _stext;
+extern unsigned long _etext;
+extern unsigned long _sdata;
+extern unsigned long _edata;
+extern unsigned long _sbss;
+extern unsigned long _ebss;
+extern unsigned long _estack;
+//extern void __init_array_start(void);
+//extern void __init_array_end(void);
+extern int main (void);
+void ResetHandler(void);
+void _init_Teensyduino_internal_(void);
+void __libc_init_array(void);
+
+
+void fault_isr(void)
+{
+        while (1); // die
+}
+
+void unused_isr(void)
+{
+        while (1); // die
+}
+
+extern volatile uint32_t systick_millis_count;
+void systick_default_isr(void)
+{
+       systick_millis_count++;
+}
+
+void nmi_isr(void)             __attribute__ ((weak, alias("unused_isr")));
+void hard_fault_isr(void)      __attribute__ ((weak, alias("unused_isr")));
+void memmanage_fault_isr(void) __attribute__ ((weak, alias("unused_isr")));
+void bus_fault_isr(void)       __attribute__ ((weak, alias("unused_isr")));
+void usage_fault_isr(void)     __attribute__ ((weak, alias("unused_isr")));
+void svcall_isr(void)          __attribute__ ((weak, alias("unused_isr")));
+void debugmonitor_isr(void)    __attribute__ ((weak, alias("unused_isr")));
+void pendablesrvreq_isr(void)  __attribute__ ((weak, alias("unused_isr")));
+void systick_isr(void)         __attribute__ ((weak, alias("systick_default_isr")));
+
+void dma_ch0_isr(void)         __attribute__ ((weak, alias("unused_isr")));
+void dma_ch1_isr(void)         __attribute__ ((weak, alias("unused_isr")));
+void dma_ch2_isr(void)         __attribute__ ((weak, alias("unused_isr")));
+void dma_ch3_isr(void)         __attribute__ ((weak, alias("unused_isr")));
+void dma_error_isr(void)       __attribute__ ((weak, alias("unused_isr")));
+void flash_cmd_isr(void)       __attribute__ ((weak, alias("unused_isr")));
+void flash_error_isr(void)     __attribute__ ((weak, alias("unused_isr")));
+void low_voltage_isr(void)     __attribute__ ((weak, alias("unused_isr")));
+void wakeup_isr(void)          __attribute__ ((weak, alias("unused_isr")));
+void watchdog_isr(void)                __attribute__ ((weak, alias("unused_isr")));
+void i2c0_isr(void)            __attribute__ ((weak, alias("unused_isr")));
+void spi0_isr(void)            __attribute__ ((weak, alias("unused_isr")));
+void i2s0_tx_isr(void)         __attribute__ ((weak, alias("unused_isr")));
+void i2s0_rx_isr(void)         __attribute__ ((weak, alias("unused_isr")));
+void uart0_lon_isr(void)       __attribute__ ((weak, alias("unused_isr")));
+void uart0_status_isr(void)    __attribute__ ((weak, alias("unused_isr")));
+void uart0_error_isr(void)     __attribute__ ((weak, alias("unused_isr")));
+void uart1_status_isr(void)    __attribute__ ((weak, alias("unused_isr")));
+void uart1_error_isr(void)     __attribute__ ((weak, alias("unused_isr")));
+void uart2_status_isr(void)    __attribute__ ((weak, alias("unused_isr")));
+void uart2_error_isr(void)     __attribute__ ((weak, alias("unused_isr")));
+void adc0_isr(void)            __attribute__ ((weak, alias("unused_isr")));
+void cmp0_isr(void)            __attribute__ ((weak, alias("unused_isr")));
+void cmp1_isr(void)            __attribute__ ((weak, alias("unused_isr")));
+void ftm0_isr(void)            __attribute__ ((weak, alias("unused_isr")));
+void ftm1_isr(void)            __attribute__ ((weak, alias("unused_isr")));
+void cmt_isr(void)             __attribute__ ((weak, alias("unused_isr")));
+void rtc_alarm_isr(void)       __attribute__ ((weak, alias("unused_isr")));
+void rtc_seconds_isr(void)     __attribute__ ((weak, alias("unused_isr")));
+void pit0_isr(void)            __attribute__ ((weak, alias("unused_isr")));
+void pit1_isr(void)            __attribute__ ((weak, alias("unused_isr")));
+void pit2_isr(void)            __attribute__ ((weak, alias("unused_isr")));
+void pit3_isr(void)            __attribute__ ((weak, alias("unused_isr")));
+void pdb_isr(void)             __attribute__ ((weak, alias("unused_isr")));
+void usb_isr(void)             __attribute__ ((weak, alias("unused_isr")));
+void usb_charge_isr(void)      __attribute__ ((weak, alias("unused_isr")));
+void tsi0_isr(void)            __attribute__ ((weak, alias("unused_isr")));
+void mcg_isr(void)             __attribute__ ((weak, alias("unused_isr")));
+void lptmr_isr(void)           __attribute__ ((weak, alias("unused_isr")));
+void porta_isr(void)           __attribute__ ((weak, alias("unused_isr")));
+void portb_isr(void)           __attribute__ ((weak, alias("unused_isr")));
+void portc_isr(void)           __attribute__ ((weak, alias("unused_isr")));
+void portd_isr(void)           __attribute__ ((weak, alias("unused_isr")));
+void porte_isr(void)           __attribute__ ((weak, alias("unused_isr")));
+void software_isr(void)                __attribute__ ((weak, alias("unused_isr")));
+
+
+// TODO: create AVR-stype ISR() macro, with default linkage to undefined handler
+//
+__attribute__ ((section(".vectors"), used))
+void (* const gVectors[])(void) =
+{
+        (void (*)(void))((unsigned long)&_estack),     //  0 ARM: Initial Stack Pointer
+        ResetHandler,                                  //  1 ARM: Initial Program Counter
+       nmi_isr,                                        //  2 ARM: Non-maskable Interrupt (NMI)
+       hard_fault_isr,                                 //  3 ARM: Hard Fault
+       memmanage_fault_isr,                            //  4 ARM: MemManage Fault
+       bus_fault_isr,                                  //  5 ARM: Bus Fault
+       usage_fault_isr,                                //  6 ARM: Usage Fault
+       fault_isr,                                      //  7 --
+       fault_isr,                                      //  8 --
+       fault_isr,                                      //  9 --
+       fault_isr,                                      // 10 --
+       svcall_isr,                                     // 11 ARM: Supervisor call (SVCall)
+       debugmonitor_isr,                               // 12 ARM: Debug Monitor
+       fault_isr,                                      // 13 --
+       pendablesrvreq_isr,                             // 14 ARM: Pendable req serv(PendableSrvReq)
+       systick_isr,                                    // 15 ARM: System tick timer (SysTick)
+       dma_ch0_isr,                                    // 16 DMA channel 0 transfer complete
+       dma_ch1_isr,                                    // 17 DMA channel 1 transfer complete
+       dma_ch2_isr,                                    // 18 DMA channel 2 transfer complete
+       dma_ch3_isr,                                    // 19 DMA channel 3 transfer complete
+       dma_error_isr,                                  // 20 DMA error interrupt channel
+       unused_isr,                                     // 21 DMA --
+       flash_cmd_isr,                                  // 22 Flash Memory Command complete
+       flash_error_isr,                                // 23 Flash Read collision
+       low_voltage_isr,                                // 24 Low-voltage detect/warning
+       wakeup_isr,                                     // 25 Low Leakage Wakeup
+       watchdog_isr,                                   // 26 Both EWM and WDOG interrupt
+       i2c0_isr,                                       // 27 I2C0
+       spi0_isr,                                       // 28 SPI0
+       i2s0_tx_isr,                                    // 29 I2S0 Transmit
+       i2s0_rx_isr,                                    // 30 I2S0 Receive
+       uart0_lon_isr,                                  // 31 UART0 CEA709.1-B (LON) status
+       uart0_status_isr,                               // 32 UART0 status
+       uart0_error_isr,                                // 33 UART0 error
+       uart1_status_isr,                               // 34 UART1 status
+       uart1_error_isr,                                // 35 UART1 error
+       uart2_status_isr,                               // 36 UART2 status
+       uart2_error_isr,                                // 37 UART2 error
+       adc0_isr,                                       // 38 ADC0
+       cmp0_isr,                                       // 39 CMP0
+       cmp1_isr,                                       // 40 CMP1
+       ftm0_isr,                                       // 41 FTM0
+       ftm1_isr,                                       // 42 FTM1
+       cmt_isr,                                        // 43 CMT
+       rtc_alarm_isr,                                  // 44 RTC Alarm interrupt
+       rtc_seconds_isr,                                // 45 RTC Seconds interrupt
+       pit0_isr,                                       // 46 PIT Channel 0
+       pit1_isr,                                       // 47 PIT Channel 1
+       pit2_isr,                                       // 48 PIT Channel 2
+       pit3_isr,                                       // 49 PIT Channel 3
+       pdb_isr,                                        // 50 PDB Programmable Delay Block
+       usb_isr,                                        // 51 USB OTG
+       usb_charge_isr,                                 // 52 USB Charger Detect
+       tsi0_isr,                                       // 53 TSI0
+       mcg_isr,                                        // 54 MCG
+       lptmr_isr,                                      // 55 Low Power Timer
+       porta_isr,                                      // 56 Pin detect (Port A)
+       portb_isr,                                      // 57 Pin detect (Port B)
+       portc_isr,                                      // 58 Pin detect (Port C)
+       portd_isr,                                      // 59 Pin detect (Port D)
+       porte_isr,                                      // 60 Pin detect (Port E)
+       software_isr,                                   // 61 Software interrupt
+};
+
+//void usb_isr(void)
+//{
+//}
+
+__attribute__ ((section(".flashconfig"), used))
+const uint8_t flashconfigbytes[16] = {
+       0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+       0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF
+};
+
+
+// Automatically initialize the RTC.  When the build defines the compile
+// time, and the user has added a crystal, the RTC will automatically
+// begin at the time of the first upload.
+#ifndef TIME_T
+#define TIME_T 1349049600 // default 1 Oct 2012
+#endif
+extern void rtc_set(unsigned long t);
+
+
+
+void startup_unused_hook(void) {}
+void startup_early_hook(void)          __attribute__ ((weak, alias("startup_unused_hook")));
+void startup_late_hook(void)           __attribute__ ((weak, alias("startup_unused_hook")));
+
+
+__attribute__ ((section(".startup")))
+void ResetHandler(void)
+{
+        uint32_t *src = &_etext;
+        uint32_t *dest = &_sdata;
+
+       WDOG_UNLOCK = WDOG_UNLOCK_SEQ1;
+       WDOG_UNLOCK = WDOG_UNLOCK_SEQ2;
+       WDOG_STCTRLH = WDOG_STCTRLH_ALLOWUPDATE;
+       startup_early_hook();
+
+       // enable clocks to always-used peripherals
+       SIM_SCGC5 = 0x00043F82;         // clocks active to all GPIO
+       SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;
+       // if the RTC oscillator isn't enabled, get it started early
+       if (!(RTC_CR & RTC_CR_OSCE)) {
+               RTC_SR = 0;
+               RTC_CR = RTC_CR_SC16P | RTC_CR_SC4P | RTC_CR_OSCE;
+       }
+
+       // TODO: do this while the PLL is waiting to lock....
+        while (dest < &_edata) *dest++ = *src++;
+        dest = &_sbss;
+        while (dest < &_ebss) *dest++ = 0;
+       SCB_VTOR = 0;   // use vector table in flash
+
+        // start in FEI mode
+        // enable capacitors for crystal
+        OSC0_CR = OSC_SC8P | OSC_SC2P;
+        // enable osc, 8-32 MHz range, low power mode
+        MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS;
+        // switch to crystal as clock source, FLL input = 16 MHz / 512
+        MCG_C1 =  MCG_C1_CLKS(2) | MCG_C1_FRDIV(4);
+        // wait for crystal oscillator to begin
+        while ((MCG_S & MCG_S_OSCINIT0) == 0) ;
+        // wait for FLL to use oscillator
+        while ((MCG_S & MCG_S_IREFST) != 0) ;
+        // wait for MCGOUT to use oscillator
+        while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) ;
+        // now we're in FBE mode
+        // config PLL input for 16 MHz Crystal / 4 = 4 MHz
+        MCG_C5 = MCG_C5_PRDIV0(3);
+        // config PLL for 96 MHz output
+        MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+        // wait for PLL to start using xtal as its input
+        while (!(MCG_S & MCG_S_PLLST)) ;
+        // wait for PLL to lock
+        while (!(MCG_S & MCG_S_LOCK0)) ;
+        // now we're in PBE mode
+#if F_CPU == 96000000
+        // config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash
+        SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |  SIM_CLKDIV1_OUTDIV4(3);
+#elif F_CPU == 48000000
+        // config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash
+        SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) |  SIM_CLKDIV1_OUTDIV4(3);
+#elif F_CPU == 24000000
+        // config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash
+        SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) |  SIM_CLKDIV1_OUTDIV4(3);
+#else
+#error "Error, F_CPU must be 96000000, 48000000, or 24000000"
+#endif
+        // switch to PLL as clock source, FLL input = 16 MHz / 512
+        MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4);
+        // wait for PLL clock to be used
+        while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) ;
+        // now we're in PEE mode
+        // configure USB for 48 MHz clock
+        SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // USB = 96 MHz PLL / 2
+        // USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0
+        SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6);
+
+        // initialize the SysTick counter
+        SYST_RVR = (F_CPU / 1000) - 1;
+        SYST_CSR = SYST_CSR_CLKSOURCE | SYST_CSR_TICKINT | SYST_CSR_ENABLE;
+
+       //init_pins();
+       __enable_irq();
+
+       //_init_Teensyduino_internal_(); XXX HaaTa - Why is this here? Perhaps fixed in a new version of the API?
+       //if (RTC_SR & RTC_SR_TIF) rtc_set(TIME_T); XXX HaaTa - We don't care about the rtc
+
+       __libc_init_array();
+
+/*
+       for (ptr = &__init_array_start; ptr < &__init_array_end; ptr++) {
+               (*ptr)();
+       }
+*/
+       startup_late_hook();
+        main();
+        while (1) ;
+}
+
+// TODO: is this needed for c++ and where does it come from?
+/*
+void _init(void)
+{
+}
+*/
+
+
+void * _sbrk(int incr)
+{
+        static char *heap_end = (char *)&_ebss;
+       char *prev = heap_end;
+
+       heap_end += incr;
+       return prev;
+}
+
+int _read(int file, char *ptr, int len)
+{
+       return 0;
+}
+
+int _write(int file, char *ptr, int len)
+{
+       return 0;
+}
+
+int _close(int fd)
+{
+       return -1;
+}
+
+int _lseek(int fd, long long offset, int whence)
+{
+       return -1;
+}
+
+void _exit(int status)
+{
+       while (1);
+}
+
+void __cxa_pure_virtual()
+{
+       while (1);
+}
+
+
+
diff --git a/Lib/mk20dx128.h b/Lib/mk20dx128.h
new file mode 100644 (file)
index 0000000..74efbb9
--- /dev/null
@@ -0,0 +1,1486 @@
+#ifndef _mk20dx128_h_
+#define _mk20dx128_h_
+
+//#define F_CPU 96000000
+//#define F_CPU 48000000
+//#define F_CPU 24000000
+//#define F_BUS 48000000
+//#define F_BUS 24000000
+//#define F_MEM 24000000
+
+#if (F_CPU == 96000000)
+ #define F_BUS 48000000
+ #define F_MEM 24000000
+#elif (F_CPU == 48000000)
+ #define F_BUS 48000000
+ #define F_MEM 24000000
+#elif (F_CPU == 24000000)
+ #define F_BUS 24000000
+ #define F_MEM 24000000
+#endif
+
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// chapter 11: Port control and interrupts (PORT)
+#define PORTA_PCR0              *(volatile uint32_t *)0x40049000 // Pin Control Register n
+#define PORT_PCR_ISF                   (uint32_t)0x01000000            // Interrupt Status Flag
+#define PORT_PCR_IRQC(n)               (uint32_t)(((n) & 15) << 16)    // Interrupt Configuration
+#define PORT_PCR_IRQC_MASK             (uint32_t)0x000F0000
+#define PORT_PCR_LK                    (uint32_t)0x00008000            // Lock Register
+#define PORT_PCR_MUX(n)                        (uint32_t)(((n) & 7) << 8)      // Pin Mux Control
+#define PORT_PCR_MUX_MASK              (uint32_t)0x00000700
+#define PORT_PCR_DSE                   (uint32_t)0x00000040            // Drive Strength Enable
+#define PORT_PCR_ODE                   (uint32_t)0x00000020            // Open Drain Enable
+#define PORT_PCR_PFE                   (uint32_t)0x00000010            // Passive Filter Enable
+#define PORT_PCR_SRE                   (uint32_t)0x00000004            // Slew Rate Enable
+#define PORT_PCR_PE                    (uint32_t)0x00000002            // Pull Enable
+#define PORT_PCR_PS                    (uint32_t)0x00000001            // Pull Select
+#define PORTA_PCR1              *(volatile uint32_t *)0x40049004 // Pin Control Register n
+#define PORTA_PCR2              *(volatile uint32_t *)0x40049008 // Pin Control Register n
+#define PORTA_PCR3              *(volatile uint32_t *)0x4004900C // Pin Control Register n
+#define PORTA_PCR4              *(volatile uint32_t *)0x40049010 // Pin Control Register n
+#define PORTA_PCR5              *(volatile uint32_t *)0x40049014 // Pin Control Register n
+#define PORTA_PCR6              *(volatile uint32_t *)0x40049018 // Pin Control Register n
+#define PORTA_PCR7              *(volatile uint32_t *)0x4004901C // Pin Control Register n
+#define PORTA_PCR8              *(volatile uint32_t *)0x40049020 // Pin Control Register n
+#define PORTA_PCR9              *(volatile uint32_t *)0x40049024 // Pin Control Register n
+#define PORTA_PCR10             *(volatile uint32_t *)0x40049028 // Pin Control Register n
+#define PORTA_PCR11             *(volatile uint32_t *)0x4004902C // Pin Control Register n
+#define PORTA_PCR12             *(volatile uint32_t *)0x40049030 // Pin Control Register n
+#define PORTA_PCR13             *(volatile uint32_t *)0x40049034 // Pin Control Register n
+#define PORTA_PCR14             *(volatile uint32_t *)0x40049038 // Pin Control Register n
+#define PORTA_PCR15             *(volatile uint32_t *)0x4004903C // Pin Control Register n
+#define PORTA_PCR16             *(volatile uint32_t *)0x40049040 // Pin Control Register n
+#define PORTA_PCR17             *(volatile uint32_t *)0x40049044 // Pin Control Register n
+#define PORTA_PCR18             *(volatile uint32_t *)0x40049048 // Pin Control Register n
+#define PORTA_PCR19             *(volatile uint32_t *)0x4004904C // Pin Control Register n
+#define PORTA_PCR20             *(volatile uint32_t *)0x40049050 // Pin Control Register n
+#define PORTA_PCR21             *(volatile uint32_t *)0x40049054 // Pin Control Register n
+#define PORTA_PCR22             *(volatile uint32_t *)0x40049058 // Pin Control Register n
+#define PORTA_PCR23             *(volatile uint32_t *)0x4004905C // Pin Control Register n
+#define PORTA_PCR24             *(volatile uint32_t *)0x40049060 // Pin Control Register n
+#define PORTA_PCR25             *(volatile uint32_t *)0x40049064 // Pin Control Register n
+#define PORTA_PCR26             *(volatile uint32_t *)0x40049068 // Pin Control Register n
+#define PORTA_PCR27             *(volatile uint32_t *)0x4004906C // Pin Control Register n
+#define PORTA_PCR28             *(volatile uint32_t *)0x40049070 // Pin Control Register n
+#define PORTA_PCR29             *(volatile uint32_t *)0x40049074 // Pin Control Register n
+#define PORTA_PCR30             *(volatile uint32_t *)0x40049078 // Pin Control Register n
+#define PORTA_PCR31             *(volatile uint32_t *)0x4004907C // Pin Control Register n
+#define PORTA_GPCLR             *(volatile uint32_t *)0x40049080 // Global Pin Control Low Register
+#define PORTA_GPCHR             *(volatile uint32_t *)0x40049084 // Global Pin Control High Register
+#define PORTA_ISFR              *(volatile uint32_t *)0x400490A0 // Interrupt Status Flag Register
+#define PORTB_PCR0              *(volatile uint32_t *)0x4004A000 // Pin Control Register n
+#define PORTB_PCR1              *(volatile uint32_t *)0x4004A004 // Pin Control Register n
+#define PORTB_PCR2              *(volatile uint32_t *)0x4004A008 // Pin Control Register n
+#define PORTB_PCR3              *(volatile uint32_t *)0x4004A00C // Pin Control Register n
+#define PORTB_PCR4              *(volatile uint32_t *)0x4004A010 // Pin Control Register n
+#define PORTB_PCR5              *(volatile uint32_t *)0x4004A014 // Pin Control Register n
+#define PORTB_PCR6              *(volatile uint32_t *)0x4004A018 // Pin Control Register n
+#define PORTB_PCR7              *(volatile uint32_t *)0x4004A01C // Pin Control Register n
+#define PORTB_PCR8              *(volatile uint32_t *)0x4004A020 // Pin Control Register n
+#define PORTB_PCR9              *(volatile uint32_t *)0x4004A024 // Pin Control Register n
+#define PORTB_PCR10             *(volatile uint32_t *)0x4004A028 // Pin Control Register n
+#define PORTB_PCR11             *(volatile uint32_t *)0x4004A02C // Pin Control Register n
+#define PORTB_PCR12             *(volatile uint32_t *)0x4004A030 // Pin Control Register n
+#define PORTB_PCR13             *(volatile uint32_t *)0x4004A034 // Pin Control Register n
+#define PORTB_PCR14             *(volatile uint32_t *)0x4004A038 // Pin Control Register n
+#define PORTB_PCR15             *(volatile uint32_t *)0x4004A03C // Pin Control Register n
+#define PORTB_PCR16             *(volatile uint32_t *)0x4004A040 // Pin Control Register n
+#define PORTB_PCR17             *(volatile uint32_t *)0x4004A044 // Pin Control Register n
+#define PORTB_PCR18             *(volatile uint32_t *)0x4004A048 // Pin Control Register n
+#define PORTB_PCR19             *(volatile uint32_t *)0x4004A04C // Pin Control Register n
+#define PORTB_PCR20             *(volatile uint32_t *)0x4004A050 // Pin Control Register n
+#define PORTB_PCR21             *(volatile uint32_t *)0x4004A054 // Pin Control Register n
+#define PORTB_PCR22             *(volatile uint32_t *)0x4004A058 // Pin Control Register n
+#define PORTB_PCR23             *(volatile uint32_t *)0x4004A05C // Pin Control Register n
+#define PORTB_PCR24             *(volatile uint32_t *)0x4004A060 // Pin Control Register n
+#define PORTB_PCR25             *(volatile uint32_t *)0x4004A064 // Pin Control Register n
+#define PORTB_PCR26             *(volatile uint32_t *)0x4004A068 // Pin Control Register n
+#define PORTB_PCR27             *(volatile uint32_t *)0x4004A06C // Pin Control Register n
+#define PORTB_PCR28             *(volatile uint32_t *)0x4004A070 // Pin Control Register n
+#define PORTB_PCR29             *(volatile uint32_t *)0x4004A074 // Pin Control Register n
+#define PORTB_PCR30             *(volatile uint32_t *)0x4004A078 // Pin Control Register n
+#define PORTB_PCR31             *(volatile uint32_t *)0x4004A07C // Pin Control Register n
+#define PORTB_GPCLR             *(volatile uint32_t *)0x4004A080 // Global Pin Control Low Register
+#define PORTB_GPCHR             *(volatile uint32_t *)0x4004A084 // Global Pin Control High Register
+#define PORTB_ISFR              *(volatile uint32_t *)0x4004A0A0 // Interrupt Status Flag Register
+#define PORTC_PCR0              *(volatile uint32_t *)0x4004B000 // Pin Control Register n
+#define PORTC_PCR1              *(volatile uint32_t *)0x4004B004 // Pin Control Register n
+#define PORTC_PCR2              *(volatile uint32_t *)0x4004B008 // Pin Control Register n
+#define PORTC_PCR3              *(volatile uint32_t *)0x4004B00C // Pin Control Register n
+#define PORTC_PCR4              *(volatile uint32_t *)0x4004B010 // Pin Control Register n
+#define PORTC_PCR5              *(volatile uint32_t *)0x4004B014 // Pin Control Register n
+#define PORTC_PCR6              *(volatile uint32_t *)0x4004B018 // Pin Control Register n
+#define PORTC_PCR7              *(volatile uint32_t *)0x4004B01C // Pin Control Register n
+#define PORTC_PCR8              *(volatile uint32_t *)0x4004B020 // Pin Control Register n
+#define PORTC_PCR9              *(volatile uint32_t *)0x4004B024 // Pin Control Register n
+#define PORTC_PCR10             *(volatile uint32_t *)0x4004B028 // Pin Control Register n
+#define PORTC_PCR11             *(volatile uint32_t *)0x4004B02C // Pin Control Register n
+#define PORTC_PCR12             *(volatile uint32_t *)0x4004B030 // Pin Control Register n
+#define PORTC_PCR13             *(volatile uint32_t *)0x4004B034 // Pin Control Register n
+#define PORTC_PCR14             *(volatile uint32_t *)0x4004B038 // Pin Control Register n
+#define PORTC_PCR15             *(volatile uint32_t *)0x4004B03C // Pin Control Register n
+#define PORTC_PCR16             *(volatile uint32_t *)0x4004B040 // Pin Control Register n
+#define PORTC_PCR17             *(volatile uint32_t *)0x4004B044 // Pin Control Register n
+#define PORTC_PCR18             *(volatile uint32_t *)0x4004B048 // Pin Control Register n
+#define PORTC_PCR19             *(volatile uint32_t *)0x4004B04C // Pin Control Register n
+#define PORTC_PCR20             *(volatile uint32_t *)0x4004B050 // Pin Control Register n
+#define PORTC_PCR21             *(volatile uint32_t *)0x4004B054 // Pin Control Register n
+#define PORTC_PCR22             *(volatile uint32_t *)0x4004B058 // Pin Control Register n
+#define PORTC_PCR23             *(volatile uint32_t *)0x4004B05C // Pin Control Register n
+#define PORTC_PCR24             *(volatile uint32_t *)0x4004B060 // Pin Control Register n
+#define PORTC_PCR25             *(volatile uint32_t *)0x4004B064 // Pin Control Register n
+#define PORTC_PCR26             *(volatile uint32_t *)0x4004B068 // Pin Control Register n
+#define PORTC_PCR27             *(volatile uint32_t *)0x4004B06C // Pin Control Register n
+#define PORTC_PCR28             *(volatile uint32_t *)0x4004B070 // Pin Control Register n
+#define PORTC_PCR29             *(volatile uint32_t *)0x4004B074 // Pin Control Register n
+#define PORTC_PCR30             *(volatile uint32_t *)0x4004B078 // Pin Control Register n
+#define PORTC_PCR31             *(volatile uint32_t *)0x4004B07C // Pin Control Register n
+#define PORTC_GPCLR             *(volatile uint32_t *)0x4004B080 // Global Pin Control Low Register
+#define PORTC_GPCHR             *(volatile uint32_t *)0x4004B084 // Global Pin Control High Register
+#define PORTC_ISFR              *(volatile uint32_t *)0x4004B0A0 // Interrupt Status Flag Register
+#define PORTD_PCR0              *(volatile uint32_t *)0x4004C000 // Pin Control Register n
+#define PORTD_PCR1              *(volatile uint32_t *)0x4004C004 // Pin Control Register n
+#define PORTD_PCR2              *(volatile uint32_t *)0x4004C008 // Pin Control Register n
+#define PORTD_PCR3              *(volatile uint32_t *)0x4004C00C // Pin Control Register n
+#define PORTD_PCR4              *(volatile uint32_t *)0x4004C010 // Pin Control Register n
+#define PORTD_PCR5              *(volatile uint32_t *)0x4004C014 // Pin Control Register n
+#define PORTD_PCR6              *(volatile uint32_t *)0x4004C018 // Pin Control Register n
+#define PORTD_PCR7              *(volatile uint32_t *)0x4004C01C // Pin Control Register n
+#define PORTD_PCR8              *(volatile uint32_t *)0x4004C020 // Pin Control Register n
+#define PORTD_PCR9              *(volatile uint32_t *)0x4004C024 // Pin Control Register n
+#define PORTD_PCR10             *(volatile uint32_t *)0x4004C028 // Pin Control Register n
+#define PORTD_PCR11             *(volatile uint32_t *)0x4004C02C // Pin Control Register n
+#define PORTD_PCR12             *(volatile uint32_t *)0x4004C030 // Pin Control Register n
+#define PORTD_PCR13             *(volatile uint32_t *)0x4004C034 // Pin Control Register n
+#define PORTD_PCR14             *(volatile uint32_t *)0x4004C038 // Pin Control Register n
+#define PORTD_PCR15             *(volatile uint32_t *)0x4004C03C // Pin Control Register n
+#define PORTD_PCR16             *(volatile uint32_t *)0x4004C040 // Pin Control Register n
+#define PORTD_PCR17             *(volatile uint32_t *)0x4004C044 // Pin Control Register n
+#define PORTD_PCR18             *(volatile uint32_t *)0x4004C048 // Pin Control Register n
+#define PORTD_PCR19             *(volatile uint32_t *)0x4004C04C // Pin Control Register n
+#define PORTD_PCR20             *(volatile uint32_t *)0x4004C050 // Pin Control Register n
+#define PORTD_PCR21             *(volatile uint32_t *)0x4004C054 // Pin Control Register n
+#define PORTD_PCR22             *(volatile uint32_t *)0x4004C058 // Pin Control Register n
+#define PORTD_PCR23             *(volatile uint32_t *)0x4004C05C // Pin Control Register n
+#define PORTD_PCR24             *(volatile uint32_t *)0x4004C060 // Pin Control Register n
+#define PORTD_PCR25             *(volatile uint32_t *)0x4004C064 // Pin Control Register n
+#define PORTD_PCR26             *(volatile uint32_t *)0x4004C068 // Pin Control Register n
+#define PORTD_PCR27             *(volatile uint32_t *)0x4004C06C // Pin Control Register n
+#define PORTD_PCR28             *(volatile uint32_t *)0x4004C070 // Pin Control Register n
+#define PORTD_PCR29             *(volatile uint32_t *)0x4004C074 // Pin Control Register n
+#define PORTD_PCR30             *(volatile uint32_t *)0x4004C078 // Pin Control Register n
+#define PORTD_PCR31             *(volatile uint32_t *)0x4004C07C // Pin Control Register n
+#define PORTD_GPCLR             *(volatile uint32_t *)0x4004C080 // Global Pin Control Low Register
+#define PORTD_GPCHR             *(volatile uint32_t *)0x4004C084 // Global Pin Control High Register
+#define PORTD_ISFR              *(volatile uint32_t *)0x4004C0A0 // Interrupt Status Flag Register
+#define PORTE_PCR0              *(volatile uint32_t *)0x4004D000 // Pin Control Register n
+#define PORTE_PCR1              *(volatile uint32_t *)0x4004D004 // Pin Control Register n
+#define PORTE_PCR2              *(volatile uint32_t *)0x4004D008 // Pin Control Register n
+#define PORTE_PCR3              *(volatile uint32_t *)0x4004D00C // Pin Control Register n
+#define PORTE_PCR4              *(volatile uint32_t *)0x4004D010 // Pin Control Register n
+#define PORTE_PCR5              *(volatile uint32_t *)0x4004D014 // Pin Control Register n
+#define PORTE_PCR6              *(volatile uint32_t *)0x4004D018 // Pin Control Register n
+#define PORTE_PCR7              *(volatile uint32_t *)0x4004D01C // Pin Control Register n
+#define PORTE_PCR8              *(volatile uint32_t *)0x4004D020 // Pin Control Register n
+#define PORTE_PCR9              *(volatile uint32_t *)0x4004D024 // Pin Control Register n
+#define PORTE_PCR10             *(volatile uint32_t *)0x4004D028 // Pin Control Register n
+#define PORTE_PCR11             *(volatile uint32_t *)0x4004D02C // Pin Control Register n
+#define PORTE_PCR12             *(volatile uint32_t *)0x4004D030 // Pin Control Register n
+#define PORTE_PCR13             *(volatile uint32_t *)0x4004D034 // Pin Control Register n
+#define PORTE_PCR14             *(volatile uint32_t *)0x4004D038 // Pin Control Register n
+#define PORTE_PCR15             *(volatile uint32_t *)0x4004D03C // Pin Control Register n
+#define PORTE_PCR16             *(volatile uint32_t *)0x4004D040 // Pin Control Register n
+#define PORTE_PCR17             *(volatile uint32_t *)0x4004D044 // Pin Control Register n
+#define PORTE_PCR18             *(volatile uint32_t *)0x4004D048 // Pin Control Register n
+#define PORTE_PCR19             *(volatile uint32_t *)0x4004D04C // Pin Control Register n
+#define PORTE_PCR20             *(volatile uint32_t *)0x4004D050 // Pin Control Register n
+#define PORTE_PCR21             *(volatile uint32_t *)0x4004D054 // Pin Control Register n
+#define PORTE_PCR22             *(volatile uint32_t *)0x4004D058 // Pin Control Register n
+#define PORTE_PCR23             *(volatile uint32_t *)0x4004D05C // Pin Control Register n
+#define PORTE_PCR24             *(volatile uint32_t *)0x4004D060 // Pin Control Register n
+#define PORTE_PCR25             *(volatile uint32_t *)0x4004D064 // Pin Control Register n
+#define PORTE_PCR26             *(volatile uint32_t *)0x4004D068 // Pin Control Register n
+#define PORTE_PCR27             *(volatile uint32_t *)0x4004D06C // Pin Control Register n
+#define PORTE_PCR28             *(volatile uint32_t *)0x4004D070 // Pin Control Register n
+#define PORTE_PCR29             *(volatile uint32_t *)0x4004D074 // Pin Control Register n
+#define PORTE_PCR30             *(volatile uint32_t *)0x4004D078 // Pin Control Register n
+#define PORTE_PCR31             *(volatile uint32_t *)0x4004D07C // Pin Control Register n
+#define PORTE_GPCLR             *(volatile uint32_t *)0x4004D080 // Global Pin Control Low Register
+#define PORTE_GPCHR             *(volatile uint32_t *)0x4004D084 // Global Pin Control High Register
+#define PORTE_ISFR              *(volatile uint32_t *)0x4004D0A0 // Interrupt Status Flag Register
+
+// Chapter 12: System Integration Module (SIM)
+#define SIM_SOPT1               *(volatile uint32_t *)0x40047000 // System Options Register 1
+#define SIM_SOPT1CFG            *(volatile uint32_t *)0x40047004 // SOPT1 Configuration Register
+#define SIM_SOPT2               *(volatile uint32_t *)0x40048004 // System Options Register 2
+#define SIM_SOPT2_USBSRC               (uint32_t)0x00040000            // 0=USB_CLKIN, 1=FFL/PLL 
+#define SIM_SOPT2_PLLFLLSEL            (uint32_t)0x00010000            // 0=FLL, 1=PLL
+#define SIM_SOPT2_TRACECLKSEL          (uint32_t)0x00001000            // 0=MCGOUTCLK, 1=CPU
+#define SIM_SOPT2_PTD7PAD              (uint32_t)0x00000800            // 0=normal, 1=double drive PTD7
+#define SIM_SOPT2_CLKOUTSEL(n)         (uint32_t)(((n) & 7) << 5)      // Selects the clock to output on the CLKOUT pin.
+#define SIM_SOPT2_RTCCLKOUTSEL         (uint32_t)0x00000010            // RTC clock out select
+#define SIM_SOPT4               *(volatile uint32_t *)0x4004800C // System Options Register 4
+#define SIM_SOPT5               *(volatile uint32_t *)0x40048010 // System Options Register 5
+#define SIM_SOPT7               *(volatile uint32_t *)0x40048018 // System Options Register 7
+#define SIM_SDID                *(const    uint32_t *)0x40048024 // System Device Identification Register
+#define SIM_SCGC4               *(volatile uint32_t *)0x40048034 // System Clock Gating Control Register 4
+#define SIM_SCGC4_VREF                 (uint32_t)0x00100000            // VREF Clock Gate Control
+#define SIM_SCGC4_CMP                  (uint32_t)0x00080000            // Comparator Clock Gate Control
+#define SIM_SCGC4_USBOTG               (uint32_t)0x00040000            // USB Clock Gate Control
+#define SIM_SCGC4_UART2                        (uint32_t)0x00001000            // UART2 Clock Gate Control
+#define SIM_SCGC4_UART1                        (uint32_t)0x00000800            // UART1 Clock Gate Control
+#define SIM_SCGC4_UART0                        (uint32_t)0x00000400            // UART0 Clock Gate Control
+#define SIM_SCGC4_I2C0                 (uint32_t)0x00000040            // I2C0 Clock Gate Control
+#define SIM_SCGC4_CMT                  (uint32_t)0x00000004            // CMT Clock Gate Control
+#define SIM_SCGC4_EWM                  (uint32_t)0x00000002            // EWM Clock Gate Control
+#define SIM_SCGC5               *(volatile uint32_t *)0x40048038 // System Clock Gating Control Register 5
+#define SIM_SCGC5_PORTE                        (uint32_t)0x00002000            // Port E Clock Gate Control
+#define SIM_SCGC5_PORTD                        (uint32_t)0x00001000            // Port D Clock Gate Control
+#define SIM_SCGC5_PORTC                        (uint32_t)0x00000800            // Port C Clock Gate Control
+#define SIM_SCGC5_PORTB                        (uint32_t)0x00000400            // Port B Clock Gate Control
+#define SIM_SCGC5_PORTA                        (uint32_t)0x00000200            // Port A Clock Gate Control
+#define SIM_SCGC5_TSI                  (uint32_t)0x00000020            // Touch Sense Input TSI Clock Gate Control
+#define SIM_SCGC5_LPTIMER              (uint32_t)0x00000001            // Low Power Timer Access Control
+#define SIM_SCGC6               *(volatile uint32_t *)0x4004803C // System Clock Gating Control Register 6
+#define SIM_SCGC6_RTC                  (uint32_t)0x20000000            // RTC Access
+#define SIM_SCGC6_ADC0                 (uint32_t)0x08000000            // ADC0 Clock Gate Control
+#define SIM_SCGC6_FTM1                 (uint32_t)0x02000000            // FTM1 Clock Gate Control
+#define SIM_SCGC6_FTM0                 (uint32_t)0x01000000            // FTM0 Clock Gate Control
+#define SIM_SCGC6_PIT                  (uint32_t)0x00800000            // PIT Clock Gate Control
+#define SIM_SCGC6_PDB                  (uint32_t)0x00400000            // PDB Clock Gate Control
+#define SIM_SCGC6_USBDCD               (uint32_t)0x00200000            // USB DCD Clock Gate Control
+#define SIM_SCGC6_CRC                  (uint32_t)0x00040000            // CRC Clock Gate Control
+#define SIM_SCGC6_I2S                  (uint32_t)0x00008000            // I2S Clock Gate Control
+#define SIM_SCGC6_SPI0                 (uint32_t)0x00001000            // SPI0 Clock Gate Control
+#define SIM_SCGC6_DMAMUX               (uint32_t)0x00000002            // DMA Mux Clock Gate Control
+#define SIM_SCGC6_FTFL                 (uint32_t)0x00000001            // Flash Memory Clock Gate Control
+#define SIM_SCGC7               *(volatile uint32_t *)0x40048040 // System Clock Gating Control Register 7
+#define SIM_CLKDIV1             *(volatile uint32_t *)0x40048044 // System Clock Divider Register 1
+#define SIM_CLKDIV1_OUTDIV1(n)         (uint32_t)(((n) & 0x0F) << 28)  // divide value for the core/system clock
+#define SIM_CLKDIV1_OUTDIV2(n)         (uint32_t)(((n) & 0x0F) << 24)  // divide value for the peripheral clock
+#define SIM_CLKDIV1_OUTDIV4(n)         (uint32_t)(((n) & 0x0F) << 16)  // divide value for the flash clock
+#define SIM_CLKDIV2             *(volatile uint32_t *)0x40048048 // System Clock Divider Register 2
+#define SIM_CLKDIV2_USBDIV(n)          (uint32_t)(((n) & 0x07) << 1)
+#define SIM_CLKDIV2_USBFRAC            (uint32_t)0x01
+#define SIM_FCFG1               *(const    uint32_t *)0x4004804C // Flash Configuration Register 1
+#define SIM_FCFG2               *(const    uint32_t *)0x40048050 // Flash Configuration Register 2
+#define SIM_UIDH                *(const    uint32_t *)0x40048054 // Unique Identification Register High
+#define SIM_UIDMH               *(const    uint32_t *)0x40048058 // Unique Identification Register Mid-High
+#define SIM_UIDML               *(const    uint32_t *)0x4004805C // Unique Identification Register Mid Low
+#define SIM_UIDL                *(const    uint32_t *)0x40048060 // Unique Identification Register Low
+
+// Chapter 13: Reset Control Module (RCM)
+#define RCM_SRS0                *(volatile uint8_t  *)0x4007F000 // System Reset Status Register 0
+#define RCM_SRS1                *(volatile uint8_t  *)0x4007F001 // System Reset Status Register 1
+#define RCM_RPFC                *(volatile uint8_t  *)0x4007F004 // Reset Pin Filter Control Register
+#define RCM_RPFW                *(volatile uint8_t  *)0x4007F005 // Reset Pin Filter Width Register
+#define RCM_MR                  *(volatile uint8_t  *)0x4007F007 // Mode Register
+
+// Chapter 14: System Mode Controller
+#define SMC_PMPROT              *(volatile uint8_t  *)0x4007E000 // Power Mode Protection Register
+#define SMC_PMCTRL              *(volatile uint8_t  *)0x4007E001 // Power Mode Control Register
+#define SMC_VLLSCTRL            *(volatile uint8_t  *)0x4007E002 // VLLS Control Register
+#define SMC_PMSTAT              *(volatile uint8_t  *)0x4007E003 // Power Mode Status Register
+
+// Chapter 15: Power Management Controller
+#define PMC_LVDSC1              *(volatile uint8_t  *)0x4007D000 // Low Voltage Detect Status And Control 1 register
+#define PMC_LVDSC2              *(volatile uint8_t  *)0x4007D001 // Low Voltage Detect Status And Control 2 register
+#define PMC_REGSC               *(volatile uint8_t  *)0x4007D002 // Regulator Status And Control register
+
+// Chapter 16: Low-Leakage Wakeup Unit (LLWU)
+#define LLWU_PE1                *(volatile uint8_t  *)0x4007C000 // LLWU Pin Enable 1 register
+#define LLWU_PE2                *(volatile uint8_t  *)0x4007C001 // LLWU Pin Enable 2 register
+#define LLWU_PE3                *(volatile uint8_t  *)0x4007C002 // LLWU Pin Enable 3 register
+#define LLWU_PE4                *(volatile uint8_t  *)0x4007C003 // LLWU Pin Enable 4 register
+#define LLWU_ME                 *(volatile uint8_t  *)0x4007C004 // LLWU Module Enable register
+#define LLWU_F1                 *(volatile uint8_t  *)0x4007C005 // LLWU Flag 1 register
+#define LLWU_F2                 *(volatile uint8_t  *)0x4007C006 // LLWU Flag 2 register
+#define LLWU_F3                 *(volatile uint8_t  *)0x4007C007 // LLWU Flag 3 register
+#define LLWU_FILT1              *(volatile uint8_t  *)0x4007C008 // LLWU Pin Filter 1 register
+#define LLWU_FILT2              *(volatile uint8_t  *)0x4007C009 // LLWU Pin Filter 2 register
+#define LLWU_RST                *(volatile uint8_t  *)0x4007C00A // LLWU Reset Enable register
+
+// Chapter 17: Miscellaneous Control Module (MCM)
+#define MCM_PLASC               *(volatile uint16_t *)0xE0080008 // Crossbar Switch (AXBS) Slave Configuration
+#define MCM_PLAMC               *(volatile uint16_t *)0xE008000A // Crossbar Switch (AXBS) Master Configuration
+#define MCM_PLACR               *(volatile uint32_t *)0xE008000C // Crossbar Switch (AXBS) Control Register
+
+// Chapter 20: Direct Memory Access Multiplexer (DMAMUX)
+#define DMAMUX0_CHCFG0          *(volatile uint8_t  *)0x40021000 // Channel Configuration register
+#define DMAMUX0_CHCFG1          *(volatile uint8_t  *)0x40021001 // Channel Configuration register
+#define DMAMUX0_CHCFG2          *(volatile uint8_t  *)0x40021002 // Channel Configuration register
+#define DMAMUX0_CHCFG3          *(volatile uint8_t  *)0x40021003 // Channel Configuration register
+#define DMAMUX0_CHCFG4          *(volatile uint8_t  *)0x40021004 // Channel Configuration register
+#define DMAMUX0_CHCFG5          *(volatile uint8_t  *)0x40021005 // Channel Configuration register
+#define DMAMUX0_CHCFG6          *(volatile uint8_t  *)0x40021006 // Channel Configuration register
+#define DMAMUX0_CHCFG7          *(volatile uint8_t  *)0x40021007 // Channel Configuration register
+#define DMAMUX0_CHCFG8          *(volatile uint8_t  *)0x40021008 // Channel Configuration register
+#define DMAMUX0_CHCFG9          *(volatile uint8_t  *)0x40021009 // Channel Configuration register
+#define DMAMUX0_CHCFG10         *(volatile uint8_t  *)0x4002100A // Channel Configuration register
+#define DMAMUX0_CHCFG11         *(volatile uint8_t  *)0x4002100B // Channel Configuration register
+#define DMAMUX0_CHCFG12         *(volatile uint8_t  *)0x4002100C // Channel Configuration register
+#define DMAMUX0_CHCFG13         *(volatile uint8_t  *)0x4002100D // Channel Configuration register
+#define DMAMUX0_CHCFG14         *(volatile uint8_t  *)0x4002100E // Channel Configuration register
+#define DMAMUX0_CHCFG15         *(volatile uint8_t  *)0x4002100F // Channel Configuration register
+
+// Chapter 21: Direct Memory Access Controller (eDMA)
+#define DMA_CR                  *(volatile uint32_t *)0x40008000 // Control Register
+#define DMA_ES                  *(volatile uint32_t *)0x40008004 // Error Status Register
+#define DMA_ERQ                 *(volatile uint32_t *)0x4000800C // Enable Request Register
+#define DMA_EEI                 *(volatile uint32_t *)0x40008014 // Enable Error Interrupt Register
+#define DMA_CEEI                *(volatile uint8_t  *)0x40008018 // Clear Enable Error Interrupt Register
+#define DMA_SEEI                *(volatile uint8_t  *)0x40008019 // Set Enable Error Interrupt Register
+#define DMA_CERQ                *(volatile uint8_t  *)0x4000801A // Clear Enable Request Register
+#define DMA_SERQ                *(volatile uint8_t  *)0x4000801B // Set Enable Request Register
+#define DMA_CDNE                *(volatile uint8_t  *)0x4000801C // Clear DONE Status Bit Register
+#define DMA_SSRT                *(volatile uint8_t  *)0x4000801D // Set START Bit Register
+#define DMA_CERR                *(volatile uint8_t  *)0x4000801E // Clear Error Register
+#define DMA_CINT                *(volatile uint8_t  *)0x4000801F // Clear Interrupt Request Register
+#define DMA_INT                 *(volatile uint32_t *)0x40008024 // Interrupt Request Register
+#define DMA_ERR                 *(volatile uint32_t *)0x4000802C // Error Register
+#define DMA_HRS                 *(volatile uint32_t *)0x40008034 // Hardware Request Status Register
+#define DMA_DCHPRI3             *(volatile uint8_t  *)0x40008100 // Channel n Priority Register
+#define DMA_DCHPRI2             *(volatile uint8_t  *)0x40008101 // Channel n Priority Register
+#define DMA_DCHPRI1             *(volatile uint8_t  *)0x40008102 // Channel n Priority Register
+#define DMA_DCHPRI0             *(volatile uint8_t  *)0x40008103 // Channel n Priority Register
+
+#define DMA_TCD0_SADDR          *(volatile uint32_t *)0x40009000 // TCD Source Address
+#define DMA_TCD0_SOFF           *(volatile uint16_t *)0x40009004 // TCD Signed Source Address Offset
+#define DMA_TCD0_ATTR           *(volatile uint16_t *)0x40009006 // TCD Transfer Attributes
+#define DMA_TCD0_NBYTES_MLNO    *(volatile uint32_t *)0x40009008 // TCD Minor Byte Count (Minor Loop Disabled)
+#define DMA_TCD0_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+#define DMA_TCD0_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+#define DMA_TCD0_SLAST          *(volatile uint32_t *)0x4000900C // TCD Last Source Address Adjustment
+#define DMA_TCD0_DADDR          *(volatile uint32_t *)0x40009010 // TCD Destination Address
+
+#define DMA_TCD0_DOFF           0x40009014 // TCD Signed Destination Address Offset
+#define DMA_TCD0_DLASTSGA       0x40009018 // TCD Last Destination Address Adjustment/Scatter Gather Address
+#define DMA_TCD0_CSR            0x4000901C // TCD Control and Status
+#define DMA_TCD0_BITER_ELINKYES 0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
+#define DMA_TCD0_BITER_ELINKNO  0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
+#define DMA_TCD1_SADDR          0x40009020 // TCD Source Address
+#define DMA_TCD1_SOFF           0x40009024 // TCD Signed Source Address Offset
+#define DMA_TCD1_ATTR           0x40009026 // TCD Transfer Attributes
+#define DMA_TCD1_NBYTES_MLNO    0x40009028 // TCD Minor Byte Count, Minor Loop Disabled
+#define DMA_TCD1_NBYTES_MLOFFNO 0x40009028 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
+#define DMA_TCD1_NBYTES_MLOFFYES 0x40009028 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
+#define DMA_TCD1_SLAST          0x4000902C // TCD Last Source Address Adjustment
+#define DMA_TCD1_DADDR          0x40009030 // TCD Destination Address
+#define DMA_TCD1_DOFF           0x40009034 // TCD Signed Destination Address Offset
+#define DMA_TCD1_CITER_ELINKYES 0x40009036 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
+#define DMA_TCD1_CITER_ELINKNO  0x40009036 // ??
+#define DMA_TCD1_DLASTSGA       0x40009038 // TCD Last Destination Address Adjustment/Scatter Gather Address
+#define DMA_TCD1_CSR            0x4000903C // TCD Control and Status
+#define DMA_TCD1_BITER_ELINKYES 0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled
+#define DMA_TCD1_BITER_ELINKNO  0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
+#define DMA_TCD2_SADDR          0x40009040 // TCD Source Address
+#define DMA_TCD2_SOFF           0x40009044 // TCD Signed Source Address Offset
+#define DMA_TCD2_ATTR           0x40009046 // TCD Transfer Attributes
+#define DMA_TCD2_NBYTES_MLNO    0x40009048 // TCD Minor Byte Count, Minor Loop Disabled
+#define DMA_TCD2_NBYTES_MLOFFNO 0x40009048 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
+#define DMA_TCD2_NBYTES_MLOFFYES 0x40009048 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
+#define DMA_TCD2_SLAST          0x4000904C // TCD Last Source Address Adjustment
+#define DMA_TCD2_DADDR          0x40009050 // TCD Destination Address
+#define DMA_TCD2_DOFF           0x40009054 // TCD Signed Destination Address Offset
+#define DMA_TCD2_CITER_ELINKYES 0x40009056 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
+#define DMA_TCD2_CITER_ELINKNO  0x40009056 // ??
+#define DMA_TCD2_DLASTSGA       0x40009058 // TCD Last Destination Address Adjustment/Scatter Gather Address
+#define DMA_TCD2_CSR            0x4000905C // TCD Control and Status
+#define DMA_TCD2_BITER_ELINKYES 0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
+#define DMA_TCD2_BITER_ELINKNO  0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
+#define DMA_TCD3_SADDR          0x40009060 // TCD Source Address
+#define DMA_TCD3_SOFF           0x40009064 // TCD Signed Source Address Offset
+#define DMA_TCD3_ATTR           0x40009066 // TCD Transfer Attributes
+#define DMA_TCD3_NBYTES_MLOFFNO 0x40009068 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
+#define DMA_TCD3_NBYTES_MLOFFYES 0x40009068 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
+#define DMA_TCD3_SLAST          0x4000906C // TCD Last Source Address Adjustment
+#define DMA_TCD3_DADDR          0x40009070 // TCD Destination Address
+#define DMA_TCD3_DOFF           0x40009074 // TCD Signed Destination Address Offset
+#define DMA_TCD3_CITER_ELINKYES 0x40009076 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
+#define DMA_TCD3_CITER_ELINKNO  0x40009076 // ??
+#define DMA_TCD3_DLASTSGA       0x40009078 // TCD Last Destination Address Adjustment/Scatter Gather Address
+#define DMA_TCD3_CSR            0x4000907C // TCD Control and Status
+#define DMA_TCD3_BITER_ELINKYES 0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled
+#define DMA_TCD3_BITER_ELINKNO  0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled
+#define DMA_TCD4_BITER_ELINKYES 0x4000909E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled
+
+// Chapter 22: External Watchdog Monitor (EWM)
+#define EWM_CTRL                *(volatile uint8_t  *)0x40061000 // Control Register
+#define EWM_SERV                *(volatile uint8_t  *)0x40061001 // Service Register
+#define EWM_CMPL                *(volatile uint8_t  *)0x40061002 // Compare Low Register
+#define EWM_CMPH                *(volatile uint8_t  *)0x40061003 // Compare High Register
+
+// Chapter 23: Watchdog Timer (WDOG)
+#define WDOG_STCTRLH            *(volatile uint16_t *)0x40052000 // Watchdog Status and Control Register High
+#define WDOG_STCTRLH_DISTESTWDOG       (uint16_t)0x4000                // Allows the WDOG's functional test mode to be disabled permanently.
+#define WDOG_STCTRLH_BYTESEL(n)                (uint16_t)(((n) & 3) << 12)     // selects the byte to be tested when the watchdog is in the byte test mode.
+#define WDOG_STCTRLH_TESTSEL           (uint16_t)0x0800
+#define WDOG_STCTRLH_TESTWDOG          (uint16_t)0x0400
+#define WDOG_STCTRLH_WAITEN            (uint16_t)0x0080
+#define WDOG_STCTRLH_STOPEN            (uint16_t)0x0040
+#define WDOG_STCTRLH_DBGEN             (uint16_t)0x0020
+#define WDOG_STCTRLH_ALLOWUPDATE       (uint16_t)0x0010
+#define WDOG_STCTRLH_WINEN             (uint16_t)0x0008
+#define WDOG_STCTRLH_IRQRSTEN          (uint16_t)0x0004
+#define WDOG_STCTRLH_CLKSRC            (uint16_t)0x0002
+#define WDOG_STCTRLH_WDOGEN            (uint16_t)0x0001
+#define WDOG_STCTRLL            *(volatile uint16_t *)0x40052002 // Watchdog Status and Control Register Low
+#define WDOG_TOVALH             *(volatile uint16_t *)0x40052004 // Watchdog Time-out Value Register High
+#define WDOG_TOVALL             *(volatile uint16_t *)0x40052006 // Watchdog Time-out Value Register Low
+#define WDOG_WINH               *(volatile uint16_t *)0x40052008 // Watchdog Window Register High
+#define WDOG_WINL               *(volatile uint16_t *)0x4005200A // Watchdog Window Register Low
+#define WDOG_REFRESH            *(volatile uint16_t *)0x4005200C // Watchdog Refresh register
+#define WDOG_UNLOCK             *(volatile uint16_t *)0x4005200E // Watchdog Unlock register
+#define WDOG_UNLOCK_SEQ1               (uint16_t)0xC520
+#define WDOG_UNLOCK_SEQ2               (uint16_t)0xD928
+#define WDOG_TMROUTH            *(volatile uint16_t *)0x40052010 // Watchdog Timer Output Register High
+#define WDOG_TMROUTL            *(volatile uint16_t *)0x40052012 // Watchdog Timer Output Register Low
+#define WDOG_RSTCNT             *(volatile uint16_t *)0x40052014 // Watchdog Reset Count register
+#define WDOG_PRESC              *(volatile uint16_t *)0x40052016 // Watchdog Prescaler register
+
+// Chapter 24: Multipurpose Clock Generator (MCG)
+#define MCG_C1                  *(volatile uint8_t  *)0x40064000 // MCG Control 1 Register
+#define MCG_C1_IREFSTEN                        (uint8_t)0x01                   // Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.
+#define MCG_C1_IRCLKEN                 (uint8_t)0x02                   // Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK.
+#define MCG_C1_IREFS                   (uint8_t)0x04                   // Internal Reference Select, Selects the reference clock source for the FLL.
+#define MCG_C1_FRDIV(n)                        (uint8_t)(((n) & 0x07) << 3)    // FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL
+#define MCG_C1_CLKS(n)                 (uint8_t)(((n) & 0x03) << 6)    // Clock Source Select, Selects the clock source for MCGOUTCLK
+#define MCG_C2                  *(volatile uint8_t  *)0x40064001 // MCG Control 2 Register
+#define MCG_C2_IRCS                    (uint8_t)0x01                   // Internal Reference Clock Select, Selects between the fast or slow internal reference clock source.
+#define MCG_C2_LP                      (uint8_t)0x02                   // Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes.
+#define MCG_C2_EREFS                   (uint8_t)0x04                   // External Reference Select, Selects the source for the external reference clock. 
+#define MCG_C2_HGO0                    (uint8_t)0x08                   // High Gain Oscillator Select, Controls the crystal oscillator mode of operation
+#define MCG_C2_RANGE0(n)               (uint8_t)(((n) & 0x03) << 4)    // Frequency Range Select, Selects the frequency range for the crystal oscillator
+#define MCG_C2_LOCRE0                  (uint8_t)0x80                   // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0 
+#define MCG_C3                  *(volatile uint8_t  *)0x40064002 // MCG Control 3 Register
+#define MCG_C3_SCTRIM(n)               (uint8_t)(n)                    // Slow Internal Reference Clock Trim Setting
+#define MCG_C4                  *(volatile uint8_t  *)0x40064003 // MCG Control 4 Register
+#define MCG_C4_SCFTRIM                 (uint8_t)0x01                   // Slow Internal Reference Clock Fine Trim
+#define MCG_C4_FCTRIM(n)               (uint8_t)(((n) & 0x0F) << 1)    // Fast Internal Reference Clock Trim Setting
+#define MCG_C4_DRST_DRS(n)             (uint8_t)(((n) & 0x03) << 5)    // DCO Range Select
+#define MCG_C4_DMX32                   (uint8_t)0x80                   // DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed
+#define MCG_C5                  *(volatile uint8_t  *)0x40064004 // MCG Control 5 Register
+#define MCG_C5_PRDIV0(n)               (uint8_t)((n) & 0x1F)           // PLL External Reference Divider
+#define MCG_C5_PLLSTEN0                        (uint8_t)0x20                   // PLL Stop Enable
+#define MCG_C5_PLLCLKEN0               (uint8_t)0x40                   // PLL Clock Enable
+#define MCG_C6                  *(volatile uint8_t  *)0x40064005 // MCG Control 6 Register
+#define MCG_C6_VDIV0(n)                        (uint8_t)((n) & 0x1F)           // VCO 0 Divider
+#define MCG_C6_CME0                    (uint8_t)0x20                   // Clock Monitor Enable
+#define MCG_C6_PLLS                    (uint8_t)0x40                   // PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. 
+#define MCG_C6_LOLIE0                  (uint8_t)0x80                   // Loss of Lock Interrrupt Enable
+#define MCG_S                   *(volatile uint8_t  *)0x40064006 // MCG Status Register
+#define MCG_S_IRCST                    (uint8_t)0x01                   // Internal Reference Clock Status
+#define MCG_S_OSCINIT0                 (uint8_t)0x02                   // OSC Initialization,  resets to 0, is set to 1 after the initialization cycles of the crystal oscillator
+#define MCG_S_CLKST(n)                 (uint8_t)(((n) & 0x03) << 2)    // Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL
+#define MCG_S_CLKST_MASK               (uint8_t)0x0C
+#define MCG_S_IREFST                   (uint8_t)0x10                   // Internal Reference Status
+#define MCG_S_PLLST                    (uint8_t)0x20                   // PLL Select Status
+#define MCG_S_LOCK0                    (uint8_t)0x40                   // Lock Status, 0=PLL Unlocked, 1=PLL Locked
+#define MCG_S_LOLS0                    (uint8_t)0x80                   // Loss of Lock Status
+#define MCG_SC                  *(volatile uint8_t  *)0x40064008 // MCG Status and Control Register
+#define MCG_SC_LOCS0                   (uint8_t)0x01                   // OSC0 Loss of Clock Status
+#define MCG_SC_FCRDIV(n)               (uint8_t)(((n) & 0x07) << 1)    // Fast Clock Internal Reference Divider
+#define MCG_SC_FLTPRSRV                        (uint8_t)0x10                   // FLL Filter Preserve Enable
+#define MCG_SC_ATMF                    (uint8_t)0x20                   // Automatic Trim Machine Fail Flag
+#define MCG_SC_ATMS                    (uint8_t)0x40                   // Automatic Trim Machine Select
+#define MCG_SC_ATME                    (uint8_t)0x80                   // Automatic Trim Machine Enable
+#define MCG_ATCVH               *(volatile uint8_t  *)0x4006400A // MCG Auto Trim Compare Value High Register
+#define MCG_ATCVL               *(volatile uint8_t  *)0x4006400B // MCG Auto Trim Compare Value Low Register
+#define MCG_C7                  *(volatile uint8_t  *)0x4006400C // MCG Control 7 Register
+#define MCG_C8                  *(volatile uint8_t  *)0x4006400D // MCG Control 8 Register
+
+// Chapter 25: Oscillator (OSC)
+#define OSC0_CR                 *(volatile uint8_t  *)0x40065000 // OSC Control Register
+#define OSC_SC16P                      (uint8_t)0x01                   // Oscillator 16 pF Capacitor Load Configure
+#define OSC_SC8P                       (uint8_t)0x02                   // Oscillator 8 pF Capacitor Load Configure
+#define OSC_SC4P                       (uint8_t)0x04                   // Oscillator 4 pF Capacitor Load Configure
+#define OSC_SC2P                       (uint8_t)0x08                   // Oscillator 2 pF Capacitor Load Configure
+#define OSC_EREFSTEN                   (uint8_t)0x20                   // External Reference Stop Enable, Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode.
+#define OSC_ERCLKEN                    (uint8_t)0x80                   // External Reference Enable, Enables external reference clock (OSCERCLK).
+
+// Chapter 27: Flash Memory Controller (FMC)
+#define FMC_PFAPR              *(volatile uint32_t *)0x4001F000        // Flash Access Protection
+#define FMC_PFB0CR             *(volatile uint32_t *)0x4001F004        // Flash Control
+#define FMC_TAGVDW0S0          *(volatile uint32_t *)0x4001F100        // Cache Tag Storage
+#define FMC_TAGVDW0S1          *(volatile uint32_t *)0x4001F104        // Cache Tag Storage
+#define FMC_TAGVDW1S0          *(volatile uint32_t *)0x4001F108        // Cache Tag Storage
+#define FMC_TAGVDW1S1          *(volatile uint32_t *)0x4001F10C        // Cache Tag Storage
+#define FMC_TAGVDW2S0          *(volatile uint32_t *)0x4001F110        // Cache Tag Storage
+#define FMC_TAGVDW2S1          *(volatile uint32_t *)0x4001F114        // Cache Tag Storage
+#define FMC_TAGVDW3S0          *(volatile uint32_t *)0x4001F118        // Cache Tag Storage
+#define FMC_TAGVDW3S1          *(volatile uint32_t *)0x4001F11C        // Cache Tag Storage
+#define FMC_DATAW0S0           *(volatile uint32_t *)0x4001F200        // Cache Data Storage
+#define FMC_DATAW0S1           *(volatile uint32_t *)0x4001F204        // Cache Data Storage
+#define FMC_DATAW1S0           *(volatile uint32_t *)0x4001F208        // Cache Data Storage
+#define FMC_DATAW1S1           *(volatile uint32_t *)0x4001F20C        // Cache Data Storage
+#define FMC_DATAW2S0           *(volatile uint32_t *)0x4001F210        // Cache Data Storage
+#define FMC_DATAW2S1           *(volatile uint32_t *)0x4001F214        // Cache Data Storage
+#define FMC_DATAW3S0           *(volatile uint32_t *)0x4001F218        // Cache Data Storage
+#define FMC_DATAW3S1           *(volatile uint32_t *)0x4001F21C        // Cache Data Storage
+
+// Chapter 28: Flash Memory Module (FTFL)
+#define FTFL_FSTAT             *(volatile uint8_t  *)0x40020000      // Flash Status Register
+#define FTFL_FSTAT_CCIF                        (uint8_t)0x80                   // Command Complete Interrupt Flag
+#define FTFL_FSTAT_RDCOLERR            (uint8_t)0x40                   // Flash Read Collision Error Flag
+#define FTFL_FSTAT_ACCERR              (uint8_t)0x20                   // Flash Access Error Flag
+#define FTFL_FSTAT_FPVIOL              (uint8_t)0x10                   // Flash Protection Violation Flag
+#define FTFL_FSTAT_MGSTAT0             (uint8_t)0x01                   // Memory Controller Command Completion Status Flag
+#define FTFL_FCNFG             *(volatile uint8_t  *)0x40020001      // Flash Configuration Register
+#define FTFL_FCNFG_CCIE                        (uint8_t)0x80                   // Command Complete Interrupt Enable
+#define FTFL_FCNFG_RDCOLLIE            (uint8_t)0x40                   // Read Collision Error Interrupt Enable
+#define FTFL_FCNFG_ERSAREQ             (uint8_t)0x20                   // Erase All Request
+#define FTFL_FCNFG_ERSSUSP             (uint8_t)0x10                   // Erase Suspend
+#define FTFL_FCNFG_PFLSH               (uint8_t)0x04                   // Flash memory configuration
+#define FTFL_FCNFG_RAMRDY              (uint8_t)0x02                   // RAM Ready
+#define FTFL_FCNFG_EEERDY              (uint8_t)0x01                   // EEPROM Ready
+#define FTFL_FSEC               *(const    uint8_t  *)0x40020002      // Flash Security Register
+#define FTFL_FOPT               *(const    uint8_t  *)0x40020003      // Flash Option Register
+#define FTFL_FCCOB3             *(volatile uint8_t  *)0x40020004      // Flash Common Command Object Registers
+#define FTFL_FCCOB2             *(volatile uint8_t  *)0x40020005
+#define FTFL_FCCOB1             *(volatile uint8_t  *)0x40020006
+#define FTFL_FCCOB0             *(volatile uint8_t  *)0x40020007
+#define FTFL_FCCOB7             *(volatile uint8_t  *)0x40020008
+#define FTFL_FCCOB6             *(volatile uint8_t  *)0x40020009
+#define FTFL_FCCOB5             *(volatile uint8_t  *)0x4002000A
+#define FTFL_FCCOB4             *(volatile uint8_t  *)0x4002000B
+#define FTFL_FCCOBB             *(volatile uint8_t  *)0x4002000C
+#define FTFL_FCCOBA             *(volatile uint8_t  *)0x4002000D
+#define FTFL_FCCOB9             *(volatile uint8_t  *)0x4002000E
+#define FTFL_FCCOB8             *(volatile uint8_t  *)0x4002000F
+#define FTFL_FPROT3             *(volatile uint8_t  *)0x40020010      // Program Flash Protection Registers
+#define FTFL_FPROT2             *(volatile uint8_t  *)0x40020011      // Program Flash Protection Registers
+#define FTFL_FPROT1             *(volatile uint8_t  *)0x40020012      // Program Flash Protection Registers
+#define FTFL_FPROT0             *(volatile uint8_t  *)0x40020013      // Program Flash Protection Registers
+#define FTFL_FEPROT             *(volatile uint8_t  *)0x40020016      // EEPROM Protection Register
+#define FTFL_FDPROT             *(volatile uint8_t  *)0x40020017      // Data Flash Protection Register
+
+// Chapter 30: Cyclic Redundancy Check (CRC)
+#define CRC_CRC                 *(volatile uint32_t *)0x40032000 // CRC Data register
+#define CRC_GPOLY               *(volatile uint32_t *)0x40032004 // CRC Polynomial register
+#define CRC_CTRL                *(volatile uint32_t *)0x40032008 // CRC Control register
+
+// Chapter 31: Analog-to-Digital Converter (ADC)
+#define ADC0_SC1A               *(volatile uint32_t *)0x4003B000 // ADC status and control registers 1
+#define ADC0_SC1B               *(volatile uint32_t *)0x4003B004 // ADC status and control registers 1
+#define ADC_SC1_COCO                   (uint32_t)0x80                  // Conversion complete flag
+#define ADC_SC1_AIEN                   (uint32_t)0x40                  // Interrupt enable
+#define ADC_SC1_DIFF                   (uint32_t)0x20                  // Differential mode enable
+#define ADC_SC1_ADCH(n)                        (uint32_t)((n) & 0x1F)          // Input channel select
+#define ADC0_CFG1               *(volatile uint32_t *)0x4003B008 // ADC configuration register 1
+#define ADC_CFG1_ADLPC                 (uint32_t)0x80                  // Low-power configuration
+#define ADC_CFG1_ADIV(n)               (uint32_t)(((n) & 3) << 5)      // Clock divide select, 0=direct, 1=div2, 2=div4, 3=div8
+#define ADC_CFG1_ADLSMP                        (uint32_t)0x10                  // Sample time configuration, 0=Short, 1=Long
+#define ADC_CFG1_MODE(n)               (uint32_t)(((n) & 3) << 2)      // Conversion mode, 0=8 bit, 1=12 bit, 2=10 bit, 3=16 bit
+#define ADC_CFG1_ADICLK(n)             (uint32_t)(((n) & 3) << 0)      // Input clock, 0=bus, 1=bus/2, 2=OSCERCLK, 3=async
+#define ADC0_CFG2               *(volatile uint32_t *)0x4003B00C // Configuration register 2
+#define ADC_CFG2_MUXSEL                        (uint32_t)0x10                  // 0=a channels, 1=b channels
+#define ADC_CFG2_ADACKEN               (uint32_t)0x08                  // async clock enable
+#define ADC_CFG2_ADHSC                 (uint32_t)0x04                  // High speed configuration
+#define ADC_CFG2_ADLSTS(n)             (uint32_t)(((n) & 3) << 0)      // Sample time, 0=24 cycles, 1=12 cycles, 2=6 cycles, 3=2 cycles
+#define ADC0_RA                 *(volatile uint32_t *)0x4003B010 // ADC data result register
+#define ADC0_RB                 *(volatile uint32_t *)0x4003B014 // ADC data result register
+#define ADC0_CV1                *(volatile uint32_t *)0x4003B018 // Compare value registers
+#define ADC0_CV2                *(volatile uint32_t *)0x4003B01C // Compare value registers
+#define ADC0_SC2                *(volatile uint32_t *)0x4003B020 // Status and control register 2
+#define ADC_SC2_ADACT                  (uint32_t)0x80                  // Conversion active
+#define ADC_SC2_ADTRG                  (uint32_t)0x40                  // Conversion trigger select, 0=software, 1=hardware
+#define ADC_SC2_ACFE                   (uint32_t)0x20                  // Compare function enable
+#define ADC_SC2_ACFGT                  (uint32_t)0x10                  // Compare function greater than enable
+#define ADC_SC2_ACREN                  (uint32_t)0x08                  // Compare function range enable
+#define ADC_SC2_DMAEN                  (uint32_t)0x04                  // DMA enable
+#define ADC_SC2_REFSEL(n)              (uint32_t)(((n) & 3) << 0)      // Voltage reference, 0=vcc/external, 1=1.2 volts
+#define ADC0_SC3                *(volatile uint32_t *)0x4003B024 // Status and control register 3
+#define ADC_SC3_CAL                    (uint32_t)0x80                  // Calibration, 1=begin, stays set while cal in progress
+#define ADC_SC3_CALF                   (uint32_t)0x40                  // Calibration failed flag
+#define ADC_SC3_ADCO                   (uint32_t)0x08                  // Continuous conversion enable
+#define ADC_SC3_AVGE                   (uint32_t)0x04                  // Hardware average enable
+#define ADC_SC3_AVGS(n)                        (uint32_t)(((n) & 3) << 0)      // avg select, 0=4 samples, 1=8 samples, 2=16 samples, 3=32 samples
+#define ADC0_OFS                *(volatile uint32_t *)0x4003B028 // ADC offset correction register
+#define ADC0_PG                 *(volatile uint32_t *)0x4003B02C // ADC plus-side gain register
+#define ADC0_MG                 *(volatile uint32_t *)0x4003B030 // ADC minus-side gain register
+#define ADC0_CLPD               *(volatile uint32_t *)0x4003B034 // ADC plus-side general calibration value register
+#define ADC0_CLPS               *(volatile uint32_t *)0x4003B038 // ADC plus-side general calibration value register
+#define ADC0_CLP4               *(volatile uint32_t *)0x4003B03C // ADC plus-side general calibration value register
+#define ADC0_CLP3               *(volatile uint32_t *)0x4003B040 // ADC plus-side general calibration value register
+#define ADC0_CLP2               *(volatile uint32_t *)0x4003B044 // ADC plus-side general calibration value register
+#define ADC0_CLP1               *(volatile uint32_t *)0x4003B048 // ADC plus-side general calibration value register
+#define ADC0_CLP0               *(volatile uint32_t *)0x4003B04C // ADC plus-side general calibration value register
+#define ADC0_CLMD               *(volatile uint32_t *)0x4003B054 // ADC minus-side general calibration value register
+#define ADC0_CLMS               *(volatile uint32_t *)0x4003B058 // ADC minus-side general calibration value register
+#define ADC0_CLM4               *(volatile uint32_t *)0x4003B05C // ADC minus-side general calibration value register
+#define ADC0_CLM3               *(volatile uint32_t *)0x4003B060 // ADC minus-side general calibration value register
+#define ADC0_CLM2               *(volatile uint32_t *)0x4003B064 // ADC minus-side general calibration value register
+#define ADC0_CLM1               *(volatile uint32_t *)0x4003B068 // ADC minus-side general calibration value register
+#define ADC0_CLM0               *(volatile uint32_t *)0x4003B06C // ADC minus-side general calibration value register
+//#define MCG_C2_RANGE0(n)             (uint8_t)(((n) & 0x03) << 4)    // Frequency Range Select, Selects the frequency range for the crystal oscillator
+//#define MCG_C2_LOCRE0                        (uint8_t)0x80                   // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0 
+
+// Chapter 32: Comparator (CMP)
+#define CMP0_CR0                *(volatile uint8_t  *)0x40073000 // CMP Control Register 0
+#define CMP0_CR1                *(volatile uint8_t  *)0x40073001 // CMP Control Register 1
+#define CMP0_FPR                *(volatile uint8_t  *)0x40073002 // CMP Filter Period Register
+#define CMP0_SCR                *(volatile uint8_t  *)0x40073003 // CMP Status and Control Register
+#define CMP0_DACCR              *(volatile uint8_t  *)0x40073004 // DAC Control Register
+#define CMP0_MUXCR              *(volatile uint8_t  *)0x40073005 // MUX Control Register
+#define CMP1_CR0                *(volatile uint8_t  *)0x40073008 // CMP Control Register 0
+#define CMP1_CR1                *(volatile uint8_t  *)0x40073009 // CMP Control Register 1
+#define CMP1_FPR                *(volatile uint8_t  *)0x4007300A // CMP Filter Period Register
+#define CMP1_SCR                *(volatile uint8_t  *)0x4007300B // CMP Status and Control Register
+#define CMP1_DACCR              *(volatile uint8_t  *)0x4007300C // DAC Control Register
+#define CMP1_MUXCR              *(volatile uint8_t  *)0x4007300D // MUX Control Register
+
+// Chapter 33: Voltage Reference (VREFV1)
+#define VREF_TRM                *(volatile uint8_t  *)0x40074000 // VREF Trim Register
+#define VREF_SC                 *(volatile uint8_t  *)0x40074001 // VREF Status and Control Register
+
+// Chapter 34: Programmable Delay Block (PDB)
+#define PDB0_SC                 *(volatile uint32_t *)0x40036000 // Status and Control Register
+#define PDB_SC_LDMOD(n)                        (((n) & 3) << 18)       // Load Mode Select
+#define PDB_SC_PDBEIE                  0x00020000              // Sequence Error Interrupt Enable
+#define PDB_SC_SWTRIG                  0x00010000              // Software Trigger
+#define PDB_SC_DMAEN                   0x00008000              // DMA Enable
+#define PDB_SC_PRESCALER(n)            (((n) & 7) << 12)       // Prescaler Divider Select
+#define PDB_SC_TRGSEL(n)               (((n) & 15) << 8)       // Trigger Input Source Select
+#define PDB_SC_PDBEN                   0x00000080              // PDB Enable
+#define PDB_SC_PDBIF                   0x00000040              // PDB Interrupt Flag
+#define PDB_SC_PDBIE                   0x00000020              // PDB Interrupt Enable.
+#define PDB_SC_MULT(n)                 (((n) & 3) << 2)        // Multiplication Factor
+#define PDB_SC_CONT                    0x00000002              // Continuous Mode Enable
+#define PDB_SC_LDOK                    0x00000001              // Load OK
+#define PDB0_MOD                *(volatile uint32_t *)0x40036004 // Modulus Register
+#define PDB0_CNT                *(volatile uint32_t *)0x40036008 // Counter Register
+#define PDB0_IDLY               *(volatile uint32_t *)0x4003600C // Interrupt Delay Register
+#define PDB0_CH0C1              *(volatile uint32_t *)0x40036010 // Channel n Control Register 1
+#define PDB0_CH0S               *(volatile uint32_t *)0x40036014 // Channel n Status Register
+#define PDB0_CH0DLY0            *(volatile uint32_t *)0x40036018 // Channel n Delay 0 Register
+#define PDB0_CH0DLY1            *(volatile uint32_t *)0x4003601C // Channel n Delay 1 Register
+#define PDB0_POEN               *(volatile uint32_t *)0x40036190 // Pulse-Out n Enable Register
+#define PDB0_PO0DLY             *(volatile uint32_t *)0x40036194 // Pulse-Out n Delay Register
+#define PDB0_PO1DLY             *(volatile uint32_t *)0x40036198 // Pulse-Out n Delay Register
+
+// Chapter 35: FlexTimer Module (FTM)
+#define FTM0_SC                 *(volatile uint32_t *)0x40038000 // Status And Control
+#define FTM_SC_TOF                     0x80                            // Timer Overflow Flag
+#define FTM_SC_TOIE                    0x40                            // Timer Overflow Interrupt Enable
+#define FTM_SC_CPWMS                   0x20                            // Center-Aligned PWM Select
+#define FTM_SC_CLKS(n)                 (((n) & 3) << 3)                // Clock Source Selection
+#define FTM_SC_PS(n)                   (((n) & 7) << 0)                // Prescale Factor Selection
+#define FTM0_CNT                *(volatile uint32_t *)0x40038004 // Counter
+#define FTM0_MOD                *(volatile uint32_t *)0x40038008 // Modulo
+#define FTM0_C0SC              *(volatile uint32_t *)0x4003800C // Channel 0 Status And Control
+#define FTM0_C0V               *(volatile uint32_t *)0x40038010 // Channel 0 Value
+#define FTM0_C1SC              *(volatile uint32_t *)0x40038014 // Channel 1 Status And Control
+#define FTM0_C1V               *(volatile uint32_t *)0x40038018 // Channel 1 Value
+#define FTM0_C2SC              *(volatile uint32_t *)0x4003801C // Channel 2 Status And Control
+#define FTM0_C2V               *(volatile uint32_t *)0x40038020 // Channel 2 Value
+#define FTM0_C3SC              *(volatile uint32_t *)0x40038024 // Channel 3 Status And Control
+#define FTM0_C3V               *(volatile uint32_t *)0x40038028 // Channel 3 Value
+#define FTM0_C4SC              *(volatile uint32_t *)0x4003802C // Channel 4 Status And Control
+#define FTM0_C4V               *(volatile uint32_t *)0x40038030 // Channel 4 Value
+#define FTM0_C5SC              *(volatile uint32_t *)0x40038034 // Channel 5 Status And Control
+#define FTM0_C5V               *(volatile uint32_t *)0x40038038 // Channel 5 Value
+#define FTM0_C6SC              *(volatile uint32_t *)0x4003803C // Channel 6 Status And Control
+#define FTM0_C6V               *(volatile uint32_t *)0x40038040 // Channel 6 Value
+#define FTM0_C7SC              *(volatile uint32_t *)0x40038044 // Channel 7 Status And Control
+#define FTM0_C7V               *(volatile uint32_t *)0x40038048 // Channel 7 Value
+#define FTM0_CNTIN              *(volatile uint32_t *)0x4003804C // Counter Initial Value
+#define FTM0_STATUS             *(volatile uint32_t *)0x40038050 // Capture And Compare Status
+#define FTM0_MODE               *(volatile uint32_t *)0x40038054 // Features Mode Selection
+#define FTM_MODE_FAULTIE               0x80                            // Fault Interrupt Enable
+#define FTM_MODE_FAULTM(n)             (((n) & 3) << 5)                // Fault Control Mode
+#define FTM_MODE_CAPTEST               0x10                            // Capture Test Mode Enable
+#define FTM_MODE_PWMSYNC               0x08                            // PWM Synchronization Mode
+#define FTM_MODE_WPDIS                 0x04                            // Write Protection Disable
+#define FTM_MODE_INIT                  0x02                            // Initialize The Channels Output
+#define FTM_MODE_FTMEN                 0x01                            // FTM Enable
+#define FTM0_SYNC               *(volatile uint32_t *)0x40038058 // Synchronization
+#define FTM_SYNC_SWSYNC                        0x80                            // 
+#define FTM_SYNC_TRIG2                 0x40                            // 
+#define FTM_SYNC_TRIG1                 0x20                            // 
+#define FTM_SYNC_TRIG0                 0x10                            // 
+#define FTM_SYNC_SYNCHOM               0x08                            // 
+#define FTM_SYNC_REINIT                        0x04                            // 
+#define FTM_SYNC_CNTMAX                        0x02                            // 
+#define FTM_SYNC_CNTMIN                        0x01                            // 
+#define FTM0_OUTINIT            *(volatile uint32_t *)0x4003805C // Initial State For Channels Output
+#define FTM0_OUTMASK            *(volatile uint32_t *)0x40038060 // Output Mask
+#define FTM0_COMBINE            *(volatile uint32_t *)0x40038064 // Function For Linked Channels
+#define FTM0_DEADTIME           *(volatile uint32_t *)0x40038068 // Deadtime Insertion Control
+#define FTM0_EXTTRIG            *(volatile uint32_t *)0x4003806C // FTM External Trigger
+#define FTM0_POL                *(volatile uint32_t *)0x40038070 // Channels Polarity
+#define FTM0_FMS                *(volatile uint32_t *)0x40038074 // Fault Mode Status
+#define FTM0_FILTER             *(volatile uint32_t *)0x40038078 // Input Capture Filter Control
+#define FTM0_FLTCTRL            *(volatile uint32_t *)0x4003807C // Fault Control
+#define FTM0_QDCTRL             *(volatile uint32_t *)0x40038080 // Quadrature Decoder Control And Status
+#define FTM0_CONF               *(volatile uint32_t *)0x40038084 // Configuration
+#define FTM0_FLTPOL             *(volatile uint32_t *)0x40038088 // FTM Fault Input Polarity
+#define FTM0_SYNCONF            *(volatile uint32_t *)0x4003808C // Synchronization Configuration
+#define FTM0_INVCTRL            *(volatile uint32_t *)0x40038090 // FTM Inverting Control
+#define FTM0_SWOCTRL            *(volatile uint32_t *)0x40038094 // FTM Software Output Control
+#define FTM0_PWMLOAD            *(volatile uint32_t *)0x40038098 // FTM PWM Load
+#define FTM1_SC                 *(volatile uint32_t *)0x40039000 // Status And Control
+#define FTM1_CNT                *(volatile uint32_t *)0x40039004 // Counter
+#define FTM1_MOD                *(volatile uint32_t *)0x40039008 // Modulo
+#define FTM1_C0SC              *(volatile uint32_t *)0x4003900C // Channel 0 Status And Control
+#define FTM1_C0V               *(volatile uint32_t *)0x40039010 // Channel 0 Value
+#define FTM1_C1SC              *(volatile uint32_t *)0x40039014 // Channel 1 Status And Control
+#define FTM1_C1V               *(volatile uint32_t *)0x40039018 // Channel 1 Value
+#define FTM1_CNTIN              *(volatile uint32_t *)0x4003904C // Counter Initial Value
+#define FTM1_STATUS             *(volatile uint32_t *)0x40039050 // Capture And Compare Status
+#define FTM1_MODE               *(volatile uint32_t *)0x40039054 // Features Mode Selection
+#define FTM1_SYNC               *(volatile uint32_t *)0x40039058 // Synchronization
+#define FTM1_OUTINIT            *(volatile uint32_t *)0x4003905C // Initial State For Channels Output
+#define FTM1_OUTMASK            *(volatile uint32_t *)0x40039060 // Output Mask
+#define FTM1_COMBINE            *(volatile uint32_t *)0x40039064 // Function For Linked Channels
+#define FTM1_DEADTIME           *(volatile uint32_t *)0x40039068 // Deadtime Insertion Control
+#define FTM1_EXTTRIG            *(volatile uint32_t *)0x4003906C // FTM External Trigger
+#define FTM1_POL                *(volatile uint32_t *)0x40039070 // Channels Polarity
+#define FTM1_FMS                *(volatile uint32_t *)0x40039074 // Fault Mode Status
+#define FTM1_FILTER             *(volatile uint32_t *)0x40039078 // Input Capture Filter Control
+#define FTM1_FLTCTRL            *(volatile uint32_t *)0x4003907C // Fault Control
+#define FTM1_QDCTRL             *(volatile uint32_t *)0x40039080 // Quadrature Decoder Control And Status
+#define FTM1_CONF               *(volatile uint32_t *)0x40039084 // Configuration
+#define FTM1_FLTPOL             *(volatile uint32_t *)0x40039088 // FTM Fault Input Polarity
+#define FTM1_SYNCONF            *(volatile uint32_t *)0x4003908C // Synchronization Configuration
+#define FTM1_INVCTRL            *(volatile uint32_t *)0x40039090 // FTM Inverting Control
+#define FTM1_SWOCTRL            *(volatile uint32_t *)0x40039094 // FTM Software Output Control
+#define FTM1_PWMLOAD            *(volatile uint32_t *)0x40039098 // FTM PWM Load
+
+// Chapter 36: Periodic Interrupt Timer (PIT)
+#define PIT_MCR                 *(volatile uint32_t *)0x40037000 // PIT Module Control Register
+#define PIT_LDVAL0              *(volatile uint32_t *)0x40037100 // Timer Load Value Register
+#define PIT_CVAL0               *(volatile uint32_t *)0x40037104 // Current Timer Value Register
+#define PIT_TCTRL0              *(volatile uint32_t *)0x40037108 // Timer Control Register
+#define PIT_TFLG0               *(volatile uint32_t *)0x4003710C // Timer Flag Register
+#define PIT_LDVAL1              *(volatile uint32_t *)0x40037110 // Timer Load Value Register
+#define PIT_CVAL1               *(volatile uint32_t *)0x40037114 // Current Timer Value Register
+#define PIT_TCTRL1              *(volatile uint32_t *)0x40037118 // Timer Control Register
+#define PIT_TFLG1               *(volatile uint32_t *)0x4003711C // Timer Flag Register
+#define PIT_LDVAL2              *(volatile uint32_t *)0x40037120 // Timer Load Value Register
+#define PIT_CVAL2               *(volatile uint32_t *)0x40037124 // Current Timer Value Register
+#define PIT_TCTRL2              *(volatile uint32_t *)0x40037128 // Timer Control Register
+#define PIT_TFLG2               *(volatile uint32_t *)0x4003712C // Timer Flag Register
+#define PIT_LDVAL3              *(volatile uint32_t *)0x40037130 // Timer Load Value Register
+#define PIT_CVAL3               *(volatile uint32_t *)0x40037134 // Current Timer Value Register
+#define PIT_TCTRL3              *(volatile uint32_t *)0x40037138 // Timer Control Register
+#define PIT_TFLG3               *(volatile uint32_t *)0x4003713C // Timer Flag Register
+
+// Chapter 37: Low-Power Timer (LPTMR)
+#define LPTMR0_CSR              *(volatile uint32_t *)0x40040000 // Low Power Timer Control Status Register
+#define LPTMR0_PSR              *(volatile uint32_t *)0x40040004 // Low Power Timer Prescale Register
+#define LPTMR0_CMR              *(volatile uint32_t *)0x40040008 // Low Power Timer Compare Register
+#define LPTMR0_CNR              *(volatile uint32_t *)0x4004000C // Low Power Timer Counter Register
+
+// Chapter 38: Carrier Modulator Transmitter (CMT)
+#define CMT_CGH1                *(volatile uint8_t  *)0x40062000 // CMT Carrier Generator High Data Register 1
+#define CMT_CGL1                *(volatile uint8_t  *)0x40062001 // CMT Carrier Generator Low Data Register 1
+#define CMT_CGH2                *(volatile uint8_t  *)0x40062002 // CMT Carrier Generator High Data Register 2
+#define CMT_CGL2                *(volatile uint8_t  *)0x40062003 // CMT Carrier Generator Low Data Register 2
+#define CMT_OC                  *(volatile uint8_t  *)0x40062004 // CMT Output Control Register
+#define CMT_MSC                 *(volatile uint8_t  *)0x40062005 // CMT Modulator Status and Control Register
+#define CMT_CMD1                *(volatile uint8_t  *)0x40062006 // CMT Modulator Data Register Mark High
+#define CMT_CMD2                *(volatile uint8_t  *)0x40062007 // CMT Modulator Data Register Mark Low
+#define CMT_CMD3                *(volatile uint8_t  *)0x40062008 // CMT Modulator Data Register Space High
+#define CMT_CMD4                *(volatile uint8_t  *)0x40062009 // CMT Modulator Data Register Space Low
+#define CMT_PPS                 *(volatile uint8_t  *)0x4006200A // CMT Primary Prescaler Register
+#define CMT_DMA                 *(volatile uint8_t  *)0x4006200B // CMT Direct Memory Access Register
+
+// Chapter 39: Real Time Clock (RTC)
+#define RTC_TSR                 *(volatile uint32_t *)0x4003D000 // RTC Time Seconds Register
+#define RTC_TPR                 *(volatile uint32_t *)0x4003D004 // RTC Time Prescaler Register
+#define RTC_TAR                 *(volatile uint32_t *)0x4003D008 // RTC Time Alarm Register
+#define RTC_TCR                 *(volatile uint32_t *)0x4003D00C // RTC Time Compensation Register
+#define RTC_TCR_CIC(n)                 (((n) & 255) << 24)             // Compensation Interval Counter
+#define RTC_TCR_TCV(n)                 (((n) & 255) << 16)             // Time Compensation Value
+#define RTC_TCR_CIR(n)                 (((n) & 255) << 8)              // Compensation Interval Register
+#define RTC_TCR_TCR(n)                 (((n) & 255) << 0)              // Time Compensation Register
+#define RTC_CR                  *(volatile uint32_t *)0x4003D010 // RTC Control Register
+#define RTC_CR_SC2P                    (uint32_t)0x00002000            // 
+#define RTC_CR_SC4P                    (uint32_t)0x00001000            // 
+#define RTC_CR_SC8P                    (uint32_t)0x00000800            // 
+#define RTC_CR_SC16P                   (uint32_t)0x00000400            // 
+#define RTC_CR_CLKO                    (uint32_t)0x00000200            // 
+#define RTC_CR_OSCE                    (uint32_t)0x00000100            // 
+#define RTC_CR_UM                      (uint32_t)0x00000008            // 
+#define RTC_CR_SUP                     (uint32_t)0x00000004            // 
+#define RTC_CR_WPE                     (uint32_t)0x00000002            // 
+#define RTC_CR_SWR                     (uint32_t)0x00000001            // 
+#define RTC_SR                  *(volatile uint32_t *)0x4003D014 // RTC Status Register
+#define RTC_SR_TCE                     (uint32_t)0x00000010            // 
+#define RTC_SR_TAF                     (uint32_t)0x00000004            // 
+#define RTC_SR_TOF                     (uint32_t)0x00000002            // 
+#define RTC_SR_TIF                     (uint32_t)0x00000001            // 
+#define RTC_LR                  *(volatile uint32_t *)0x4003D018 // RTC Lock Register
+#define RTC_IER                 *(volatile uint32_t *)0x4003D01C // RTC Interrupt Enable Register
+#define RTC_WAR                 *(volatile uint32_t *)0x4003D800 // RTC Write Access Register
+#define RTC_RAR                 *(volatile uint32_t *)0x4003D804 // RTC Read Access Register
+
+// Chapter 40: Universal Serial Bus OTG Controller (USBOTG)
+#define USB0_PERID              *(const    uint8_t  *)0x40072000 // Peripheral ID register
+#define USB0_IDCOMP             *(const    uint8_t  *)0x40072004 // Peripheral ID Complement register
+#define USB0_REV                *(const    uint8_t  *)0x40072008 // Peripheral Revision register
+#define USB0_ADDINFO            *(volatile uint8_t  *)0x4007200C // Peripheral Additional Info register
+#define USB0_OTGISTAT           *(volatile uint8_t  *)0x40072010 // OTG Interrupt Status register
+#define USB_OTGISTAT_IDCHG             (uint8_t)0x80                   //
+#define USB_OTGISTAT_ONEMSEC           (uint8_t)0x40                   //
+#define USB_OTGISTAT_LINE_STATE_CHG    (uint8_t)0x20                   //
+#define USB_OTGISTAT_SESSVLDCHG                (uint8_t)0x08                   //
+#define USB_OTGISTAT_B_SESS_CHG                (uint8_t)0x04                   //
+#define USB_OTGISTAT_AVBUSCHG          (uint8_t)0x01                   //
+#define USB0_OTGICR             *(volatile uint8_t  *)0x40072014 // OTG Interrupt Control Register
+#define USB_OTGICR_IDEN                        (uint8_t)0x80                   // 
+#define USB_OTGICR_ONEMSECEN           (uint8_t)0x40                   // 
+#define USB_OTGICR_LINESTATEEN         (uint8_t)0x20                   // 
+#define USB_OTGICR_SESSVLDEN           (uint8_t)0x08                   // 
+#define USB_OTGICR_BSESSEN             (uint8_t)0x04                   // 
+#define USB_OTGICR_AVBUSEN             (uint8_t)0x01                   // 
+#define USB0_OTGSTAT            *(volatile uint8_t  *)0x40072018 // OTG Status register
+#define USB_OTGSTAT_ID                 (uint8_t)0x80                   // 
+#define USB_OTGSTAT_ONEMSECEN          (uint8_t)0x40                   // 
+#define USB_OTGSTAT_LINESTATESTABLE    (uint8_t)0x20                   // 
+#define USB_OTGSTAT_SESS_VLD           (uint8_t)0x08                   // 
+#define USB_OTGSTAT_BSESSEND           (uint8_t)0x04                   // 
+#define USB_OTGSTAT_AVBUSVLD           (uint8_t)0x01                   // 
+#define USB0_OTGCTL             *(volatile uint8_t  *)0x4007201C // OTG Control Register
+#define USB_OTGCTL_DPHIGH              (uint8_t)0x80                   // 
+#define USB_OTGCTL_DPLOW               (uint8_t)0x20                   // 
+#define USB_OTGCTL_DMLOW               (uint8_t)0x10                   // 
+#define USB_OTGCTL_OTGEN               (uint8_t)0x04                   // 
+#define USB0_ISTAT              *(volatile uint8_t  *)0x40072080 // Interrupt Status Register
+#define USB_ISTAT_STALL                        (uint8_t)0x80                   // 
+#define USB_ISTAT_ATTACH               (uint8_t)0x40                   // 
+#define USB_ISTAT_RESUME               (uint8_t)0x20                   // 
+#define USB_ISTAT_SLEEP                        (uint8_t)0x10                   // 
+#define USB_ISTAT_TOKDNE               (uint8_t)0x08                   // 
+#define USB_ISTAT_SOFTOK               (uint8_t)0x04                   // 
+#define USB_ISTAT_ERROR                        (uint8_t)0x02                   // 
+#define USB_ISTAT_USBRST               (uint8_t)0x01                   // 
+#define USB0_INTEN              *(volatile uint8_t  *)0x40072084 // Interrupt Enable Register
+#define USB_INTEN_STALLEN              (uint8_t)0x80                   // 
+#define USB_INTEN_ATTACHEN             (uint8_t)0x40                   // 
+#define USB_INTEN_RESUMEEN             (uint8_t)0x20                   // 
+#define USB_INTEN_SLEEPEN              (uint8_t)0x10                   // 
+#define USB_INTEN_TOKDNEEN             (uint8_t)0x08                   // 
+#define USB_INTEN_SOFTOKEN             (uint8_t)0x04                   // 
+#define USB_INTEN_ERROREN              (uint8_t)0x02                   // 
+#define USB_INTEN_USBRSTEN             (uint8_t)0x01                   // 
+#define USB0_ERRSTAT            *(volatile uint8_t  *)0x40072088 // Error Interrupt Status Register
+#define USB_ERRSTAT_BTSERR             (uint8_t)0x80                   // 
+#define USB_ERRSTAT_DMAERR             (uint8_t)0x20                   // 
+#define USB_ERRSTAT_BTOERR             (uint8_t)0x10                   // 
+#define USB_ERRSTAT_DFN8               (uint8_t)0x08                   // 
+#define USB_ERRSTAT_CRC16              (uint8_t)0x04                   // 
+#define USB_ERRSTAT_CRC5EOF            (uint8_t)0x02                   // 
+#define USB_ERRSTAT_PIDERR             (uint8_t)0x01                   // 
+#define USB0_ERREN              *(volatile uint8_t  *)0x4007208C // Error Interrupt Enable Register
+#define USB_ERREN_BTSERREN             (uint8_t)0x80                   // 
+#define USB_ERREN_DMAERREN             (uint8_t)0x20                   // 
+#define USB_ERREN_BTOERREN             (uint8_t)0x10                   // 
+#define USB_ERREN_DFN8EN               (uint8_t)0x08                   // 
+#define USB_ERREN_CRC16EN              (uint8_t)0x04                   // 
+#define USB_ERREN_CRC5EOFEN            (uint8_t)0x02                   // 
+#define USB_ERREN_PIDERREN             (uint8_t)0x01                   // 
+#define USB0_STAT               *(volatile uint8_t  *)0x40072090 // Status Register
+#define USB_STAT_TX                    (uint8_t)0x08                   // 
+#define USB_STAT_ODD                   (uint8_t)0x04                   // 
+#define USB_STAT_ENDP(n)               (uint8_t)((n) >> 4)             // 
+#define USB0_CTL                *(volatile uint8_t  *)0x40072094 // Control Register
+#define USB_CTL_JSTATE                 (uint8_t)0x80                   // 
+#define USB_CTL_SE0                    (uint8_t)0x40                   // 
+#define USB_CTL_TXSUSPENDTOKENBUSY     (uint8_t)0x20                   // 
+#define USB_CTL_RESET                  (uint8_t)0x10                   // 
+#define USB_CTL_HOSTMODEEN             (uint8_t)0x08                   // 
+#define USB_CTL_RESUME                 (uint8_t)0x04                   // 
+#define USB_CTL_ODDRST                 (uint8_t)0x02                   // 
+#define USB_CTL_USBENSOFEN             (uint8_t)0x01                   // 
+#define USB0_ADDR               *(volatile uint8_t  *)0x40072098 // Address Register
+#define USB0_BDTPAGE1           *(volatile uint8_t  *)0x4007209C // BDT Page Register 1
+#define USB0_FRMNUML            *(volatile uint8_t  *)0x400720A0 // Frame Number Register Low
+#define USB0_FRMNUMH            *(volatile uint8_t  *)0x400720A4 // Frame Number Register High
+#define USB0_TOKEN              *(volatile uint8_t  *)0x400720A8 // Token Register
+#define USB0_SOFTHLD            *(volatile uint8_t  *)0x400720AC // SOF Threshold Register
+#define USB0_BDTPAGE2           *(volatile uint8_t  *)0x400720B0 // BDT Page Register 2
+#define USB0_BDTPAGE3           *(volatile uint8_t  *)0x400720B4 // BDT Page Register 3
+#define USB0_ENDPT0             *(volatile uint8_t  *)0x400720C0 // Endpoint Control Register
+#define USB_ENDPT_HOSTWOHUB            (uint8_t)0x80                   // host only, enable low speed
+#define USB_ENDPT_RETRYDIS             (uint8_t)0x40                   // host only, set to disable NAK retry
+#define USB_ENDPT_EPCTLDIS             (uint8_t)0x10                   // 0=control, 1=bulk, interrupt, isync
+#define USB_ENDPT_EPRXEN               (uint8_t)0x08                   // enables the endpoint for RX transfers.
+#define USB_ENDPT_EPTXEN               (uint8_t)0x04                   // enables the endpoint for TX transfers.
+#define USB_ENDPT_EPSTALL              (uint8_t)0x02                   // set to stall endpoint
+#define USB_ENDPT_EPHSHK               (uint8_t)0x01                   // enable handshaking during a transaction, generally set unless Isochronous
+#define USB0_ENDPT1             *(volatile uint8_t  *)0x400720C4 // Endpoint Control Register
+#define USB0_ENDPT2             *(volatile uint8_t  *)0x400720C8 // Endpoint Control Register
+#define USB0_ENDPT3             *(volatile uint8_t  *)0x400720CC // Endpoint Control Register
+#define USB0_ENDPT4             *(volatile uint8_t  *)0x400720D0 // Endpoint Control Register
+#define USB0_ENDPT5             *(volatile uint8_t  *)0x400720D4 // Endpoint Control Register
+#define USB0_ENDPT6             *(volatile uint8_t  *)0x400720D8 // Endpoint Control Register
+#define USB0_ENDPT7             *(volatile uint8_t  *)0x400720DC // Endpoint Control Register
+#define USB0_ENDPT8             *(volatile uint8_t  *)0x400720E0 // Endpoint Control Register
+#define USB0_ENDPT9             *(volatile uint8_t  *)0x400720E4 // Endpoint Control Register
+#define USB0_ENDPT10            *(volatile uint8_t  *)0x400720E8 // Endpoint Control Register
+#define USB0_ENDPT11            *(volatile uint8_t  *)0x400720EC // Endpoint Control Register
+#define USB0_ENDPT12            *(volatile uint8_t  *)0x400720F0 // Endpoint Control Register
+#define USB0_ENDPT13            *(volatile uint8_t  *)0x400720F4 // Endpoint Control Register
+#define USB0_ENDPT14            *(volatile uint8_t  *)0x400720F8 // Endpoint Control Register
+#define USB0_ENDPT15            *(volatile uint8_t  *)0x400720FC // Endpoint Control Register
+#define USB0_USBCTRL            *(volatile uint8_t  *)0x40072100 // USB Control Register
+#define USB_USBCTRL_SUSP               (uint8_t)0x80                   // Places the USB transceiver into the suspend state.
+#define USB_USBCTRL_PDE                        (uint8_t)0x40                   // Enables the weak pulldowns on the USB transceiver.
+#define USB0_OBSERVE            *(volatile uint8_t  *)0x40072104 // USB OTG Observe Register
+#define USB_OBSERVE_DPPU               (uint8_t)0x80                   // 
+#define USB_OBSERVE_DPPD               (uint8_t)0x40                   // 
+#define USB_OBSERVE_DMPD               (uint8_t)0x10                   // 
+#define USB0_CONTROL            *(volatile uint8_t  *)0x40072108 // USB OTG Control Register
+#define USB_CONTROL_DPPULLUPNONOTG     (uint8_t)0x10                   //  Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode.
+#define USB0_USBTRC0            *(volatile uint8_t  *)0x4007210C // USB Transceiver Control Register 0
+#define USB_USBTRC_USBRESET            (uint8_t)0x80                   //
+#define USB_USBTRC_USBRESMEN           (uint8_t)0x20                   //
+#define USB_USBTRC_SYNC_DET            (uint8_t)0x02                   //
+#define USB_USBTRC_USB_RESUME_INT      (uint8_t)0x01                   //
+#define USB0_USBFRMADJUST       *(volatile uint8_t  *)0x40072114 // Frame Adjust Register
+
+// Chapter 41: USB Device Charger Detection Module (USBDCD)
+#define USBDCD_CONTROL          *(volatile uint32_t *)0x40035000 // Control register
+#define USBDCD_CLOCK            *(volatile uint32_t *)0x40035004 // Clock register
+#define USBDCD_STATUS           *(volatile uint32_t *)0x40035008 // Status register
+#define USBDCD_TIMER0           *(volatile uint32_t *)0x40035010 // TIMER0 register
+#define USBDCD_TIMER1           *(volatile uint32_t *)0x40035014 // TIMER1 register
+#define USBDCD_TIMER2           *(volatile uint32_t *)0x40035018 // TIMER2 register
+
+// Chapter 43: SPI (DSPI)
+#define SPI0_MCR                *(volatile uint32_t *)0x4002C000 // DSPI Module Configuration Register
+#define SPI_MCR_MSTR                   (uint32_t)0x80000000            // Master/Slave Mode Select
+#define SPI_MCR_CONT_SCKE              (uint32_t)0x40000000            // 
+#define SPI_MCR_DCONF(n)               (((n) & 3) << 28)               // 
+#define SPI_MCR_FRZ                    (uint32_t)0x08000000            // 
+#define SPI_MCR_MTFE                   (uint32_t)0x04000000            // 
+#define SPI_MCR_ROOE                   (uint32_t)0x01000000            // 
+#define SPI_MCR_PCSIS(n)               (((n) & 0x1F) << 16)            //
+#define SPI_MCR_DOZE                   (uint32_t)0x00008000            // 
+#define SPI_MCR_MDIS                   (uint32_t)0x00004000            // 
+#define SPI_MCR_DIS_TXF                        (uint32_t)0x00002000            // 
+#define SPI_MCR_DIS_RXF                        (uint32_t)0x00001000            // 
+#define SPI_MCR_CLR_TXF                        (uint32_t)0x00000800            // 
+#define SPI_MCR_CLR_RXF                        (uint32_t)0x00000400            // 
+#define SPI_MCR_SMPL_PT(n)             (((n) & 3) << 8)                //
+#define SPI_MCR_HALT                   (uint32_t)0x00000001            // 
+#define SPI0_TCR                *(volatile uint32_t *)0x4002C008 // DSPI Transfer Count Register
+#define SPI0_CTAR0              *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Master Mode
+#define SPI_CTAR_DBR                   (uint32_t)0x80000000            // Double Baud Rate
+#define SPI_CTAR_FMSZ(n)               (((n) & 15) << 27)              // Frame Size (+1)
+#define SPI_CTAR_CPOL                  (uint32_t)0x04000000            // Clock Polarity
+#define SPI_CTAR_CPHA                  (uint32_t)0x02000000            // Clock Phase
+#define SPI_CTAR_LSBFE                 (uint32_t)0x01000000            // LSB First
+#define SPI_CTAR_PCSSCK(n)             (((n) & 3) << 22)               // PCS to SCK Delay Prescaler
+#define SPI_CTAR_PASC(n)               (((n) & 3) << 20)               // After SCK Delay Prescaler
+#define SPI_CTAR_PDT(n)                        (((n) & 3) << 18)               // Delay after Transfer Prescaler
+#define SPI_CTAR_PBR(n)                        (((n) & 3) << 16)               // Baud Rate Prescaler
+#define SPI_CTAR_CSSCK(n)              (((n) & 15) << 12)              // PCS to SCK Delay Scaler
+#define SPI_CTAR_ASC(n)                        (((n) & 15) << 8)               // After SCK Delay Scaler
+#define SPI_CTAR_DT(n)                 (((n) & 15) << 4)               // Delay After Transfer Scaler
+#define SPI_CTAR_BR(n)                 (((n) & 15) << 0)               // Baud Rate Scaler
+#define SPI0_CTAR0_SLAVE        *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Slave Mode
+#define SPI0_CTAR1              *(volatile uint32_t *)0x4002C010 // DSPI Clock and Transfer Attributes Register, In Master Mode
+#define SPI0_SR                 *(volatile uint32_t *)0x4002C02C // DSPI Status Register
+#define SPI_SR_TCF                     (uint32_t)0x80000000            // Transfer Complete Flag
+#define SPI_SR_TXRXS                   (uint32_t)0x40000000            // TX and RX Status
+#define SPI_SR_EOQF                    (uint32_t)0x10000000            // End of Queue Flag
+#define SPI_SR_TFUF                    (uint32_t)0x08000000            // Transmit FIFO Underflow Flag
+#define SPI_SR_TFFF                    (uint32_t)0x02000000            // Transmit FIFO Fill Flag
+#define SPI_SR_RFOF                    (uint32_t)0x00080000            // Receive FIFO Overflow Flag
+#define SPI_SR_RFDF                    (uint32_t)0x00020000            // Receive FIFO Drain Flag
+#define SPI0_RSER               *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register
+#define SPI0_PUSHR              *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Master Mode
+#define SPI0_PUSHR_CONT                        (uint32_t)0x80000000            // 
+#define SPI0_PUSHR_CTAS(n)             (((n) & 7) << 28)               // 
+#define SPI0_PUSHR_EOQ                 (uint32_t)0x08000000            // 
+#define SPI0_PUSHR_CTCNT               (uint32_t)0x04000000            // 
+#define SPI0_PUSHR_PCS(n)              (((n) & 31) << 16)              //
+#define SPI0_PUSHR_SLAVE        *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Slave Mode
+#define SPI0_POPR               *(volatile uint32_t *)0x4002C038 // DSPI POP RX FIFO Register
+#define SPI0_TXFR0              *(volatile uint32_t *)0x4002C03C // DSPI Transmit FIFO Registers
+#define SPI0_TXFR1              *(volatile uint32_t *)0x4002C040 // DSPI Transmit FIFO Registers
+#define SPI0_TXFR2              *(volatile uint32_t *)0x4002C044 // DSPI Transmit FIFO Registers
+#define SPI0_TXFR3              *(volatile uint32_t *)0x4002C048 // DSPI Transmit FIFO Registers
+#define SPI0_RXFR0              *(volatile uint32_t *)0x4002C07C // DSPI Receive FIFO Registers
+#define SPI0_RXFR1              *(volatile uint32_t *)0x4002C080 // DSPI Receive FIFO Registers
+#define SPI0_RXFR2              *(volatile uint32_t *)0x4002C084 // DSPI Receive FIFO Registers
+#define SPI0_RXFR3              *(volatile uint32_t *)0x4002C088 // DSPI Receive FIFO Registers
+
+// Chapter 44: Inter-Integrated Circuit (I2C)
+#define I2C0_A1                 *(volatile uint8_t  *)0x40066000 // I2C Address Register 1
+#define I2C0_F                  *(volatile uint8_t  *)0x40066001 // I2C Frequency Divider register
+#define I2C0_C1                 *(volatile uint8_t  *)0x40066002 // I2C Control Register 1
+#define I2C_C1_IICEN                   (uint8_t)0x80                   // I2C Enable
+#define I2C_C1_IICIE                   (uint8_t)0x40                   // I2C Interrupt Enable
+#define I2C_C1_MST                     (uint8_t)0x20                   // Master Mode Select
+#define I2C_C1_TX                      (uint8_t)0x10                   // Transmit Mode Select
+#define I2C_C1_TXAK                    (uint8_t)0x08                   // Transmit Acknowledge Enable
+#define I2C_C1_RSTA                    (uint8_t)0x04                   // Repeat START
+#define I2C_C1_WUEN                    (uint8_t)0x02                   // Wakeup Enable
+#define I2C_C1_DMAEN                   (uint8_t)0x01                   // DMA Enable
+#define I2C0_S                  *(volatile uint8_t  *)0x40066003 // I2C Status register
+#define I2C_S_TCF                      (uint8_t)0x80                   // Transfer Complete Flag
+#define I2C_S_IAAS                     (uint8_t)0x40                   // Addressed As A Slave
+#define I2C_S_BUSY                     (uint8_t)0x20                   // Bus Busy
+#define I2C_S_ARBL                     (uint8_t)0x10                   // Arbitration Lost
+#define I2C_S_RAM                      (uint8_t)0x08                   // Range Address Match
+#define I2C_S_SRW                      (uint8_t)0x04                   // Slave Read/Write
+#define I2C_S_IICIF                    (uint8_t)0x02                   // Interrupt Flag
+#define I2C_S_RXAK                     (uint8_t)0x01                   // Receive Acknowledge
+#define I2C0_D                  *(volatile uint8_t  *)0x40066004 // I2C Data I/O register
+#define I2C0_C2                 *(volatile uint8_t  *)0x40066005 // I2C Control Register 2
+#define I2C_C2_GCAEN                   (uint8_t)0x80                   // General Call Address Enable
+#define I2C_C2_ADEXT                   (uint8_t)0x40                   // Address Extension
+#define I2C_C2_HDRS                    (uint8_t)0x20                   // High Drive Select
+#define I2C_C2_SBRC                    (uint8_t)0x10                   // Slave Baud Rate Control
+#define I2C_C2_RMEN                    (uint8_t)0x08                   // Range Address Matching Enable
+#define I2C_C2_AD(n)                   ((n) & 7)                       // Slave Address, upper 3 bits
+#define I2C0_FLT                *(volatile uint8_t  *)0x40066006 // I2C Programmable Input Glitch Filter register
+#define I2C0_RA                 *(volatile uint8_t  *)0x40066007 // I2C Range Address register
+#define I2C0_SMB                *(volatile uint8_t  *)0x40066008 // I2C SMBus Control and Status register
+#define I2C0_A2                 *(volatile uint8_t  *)0x40066009 // I2C Address Register 2
+#define I2C0_SLTH               *(volatile uint8_t  *)0x4006600A // I2C SCL Low Timeout Register High
+#define I2C0_SLTL               *(volatile uint8_t  *)0x4006600B // I2C SCL Low Timeout Register Low
+
+// Chapter 45: Universal Asynchronous Receiver/Transmitter (UART)
+#define UART0_BDH               *(volatile uint8_t  *)0x4006A000 // UART Baud Rate Registers: High
+#define UART0_BDL               *(volatile uint8_t  *)0x4006A001 // UART Baud Rate Registers: Low
+#define UART0_C1                *(volatile uint8_t  *)0x4006A002 // UART Control Register 1
+#define UART_C1_LOOPS                  (uint8_t)0x80                   // When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input
+#define UART_C1_UARTSWAI               (uint8_t)0x40                   // UART Stops in Wait Mode
+#define UART_C1_RSRC                   (uint8_t)0x20                   // When LOOPS is set, the RSRC field determines the source for the receiver shift register input
+#define UART_C1_M                      (uint8_t)0x10                   // 9-bit or 8-bit Mode Select
+#define UART_C1_WAKE                   (uint8_t)0x08                   // Determines which condition wakes the UART
+#define UART_C1_ILT                    (uint8_t)0x04                   // Idle Line Type Select
+#define UART_C1_PE                     (uint8_t)0x02                   // Parity Enable
+#define UART_C1_PT                     (uint8_t)0x01                   // Parity Type, 0=even, 1=odd
+#define UART0_C2                *(volatile uint8_t  *)0x4006A003 // UART Control Register 2
+#define UART_C2_TIE                    (uint8_t)0x80                   // Transmitter Interrupt or DMA Transfer Enable.
+#define UART_C2_TCIE                   (uint8_t)0x40                   // Transmission Complete Interrupt Enable
+#define UART_C2_RIE                    (uint8_t)0x20                   // Receiver Full Interrupt or DMA Transfer Enable
+#define UART_C2_ILIE                   (uint8_t)0x10                   // Idle Line Interrupt Enable
+#define UART_C2_TE                     (uint8_t)0x08                   // Transmitter Enable
+#define UART_C2_RE                     (uint8_t)0x04                   // Receiver Enable
+#define UART_C2_RWU                    (uint8_t)0x02                   // Receiver Wakeup Control
+#define UART_C2_SBK                    (uint8_t)0x01                   // Send Break
+#define UART0_S1                *(volatile uint8_t  *)0x4006A004 // UART Status Register 1
+#define UART_S1_TDRE                   (uint8_t)0x80                   // Transmit Data Register Empty Flag
+#define UART_S1_TC                     (uint8_t)0x40                   // Transmit Complete Flag
+#define UART_S1_RDRF                   (uint8_t)0x20                   // Receive Data Register Full Flag
+#define UART_S1_IDLE                   (uint8_t)0x10                   // Idle Line Flag
+#define UART_S1_OR                     (uint8_t)0x08                   // Receiver Overrun Flag
+#define UART_S1_NF                     (uint8_t)0x04                   // Noise Flag
+#define UART_S1_FE                     (uint8_t)0x02                   // Framing Error Flag
+#define UART_S1_PF                     (uint8_t)0x01                   // Parity Error Flag
+#define UART0_S2                *(volatile uint8_t  *)0x4006A005 // UART Status Register 2
+#define UART0_C3                *(volatile uint8_t  *)0x4006A006 // UART Control Register 3
+#define UART0_D                 *(volatile uint8_t  *)0x4006A007 // UART Data Register
+#define UART0_MA1               *(volatile uint8_t  *)0x4006A008 // UART Match Address Registers 1
+#define UART0_MA2               *(volatile uint8_t  *)0x4006A009 // UART Match Address Registers 2
+#define UART0_C4                *(volatile uint8_t  *)0x4006A00A // UART Control Register 4
+#define UART0_C5                *(volatile uint8_t  *)0x4006A00B // UART Control Register 5
+#define UART0_ED                *(volatile uint8_t  *)0x4006A00C // UART Extended Data Register
+#define UART0_MODEM             *(volatile uint8_t  *)0x4006A00D // UART Modem Register
+#define UART0_IR                *(volatile uint8_t  *)0x4006A00E // UART Infrared Register
+#define UART0_PFIFO             *(volatile uint8_t  *)0x4006A010 // UART FIFO Parameters
+#define UART_PFIFO_TXFE                        (uint8_t)0x80
+#define UART_PFIFO_RXFE                        (uint8_t)0x08
+#define UART0_CFIFO             *(volatile uint8_t  *)0x4006A011 // UART FIFO Control Register
+#define UART_CFIFO_TXFLUSH             (uint8_t)0x80                   // 
+#define UART_CFIFO_RXFLUSH             (uint8_t)0x40                   // 
+#define UART_CFIFO_RXOFE               (uint8_t)0x04                   // 
+#define UART_CFIFO_TXOFE               (uint8_t)0x02                   // 
+#define UART_CFIFO_RXUFE               (uint8_t)0x01                   // 
+#define UART0_SFIFO             *(volatile uint8_t  *)0x4006A012 // UART FIFO Status Register
+#define UART_SFIFO_TXEMPT              (uint8_t)0x80
+#define UART_SFIFO_RXEMPT              (uint8_t)0x40
+#define UART_SFIFO_RXOF                        (uint8_t)0x04
+#define UART_SFIFO_TXOF                        (uint8_t)0x02
+#define UART_SFIFO_RXUF                        (uint8_t)0x01
+#define UART0_TWFIFO            *(volatile uint8_t  *)0x4006A013 // UART FIFO Transmit Watermark
+#define UART0_TCFIFO            *(volatile uint8_t  *)0x4006A014 // UART FIFO Transmit Count
+#define UART0_RWFIFO            *(volatile uint8_t  *)0x4006A015 // UART FIFO Receive Watermark
+#define UART0_RCFIFO            *(volatile uint8_t  *)0x4006A016 // UART FIFO Receive Count
+#define UART0_C7816             *(volatile uint8_t  *)0x4006A018 // UART 7816 Control Register
+#define UART0_IE7816            *(volatile uint8_t  *)0x4006A019 // UART 7816 Interrupt Enable Register
+#define UART0_IS7816            *(volatile uint8_t  *)0x4006A01A // UART 7816 Interrupt Status Register
+#define UART0_WP7816T0          *(volatile uint8_t  *)0x4006A01B // UART 7816 Wait Parameter Register
+#define UART0_WP7816T1          *(volatile uint8_t  *)0x4006A01B // UART 7816 Wait Parameter Register
+#define UART0_WN7816            *(volatile uint8_t  *)0x4006A01C // UART 7816 Wait N Register
+#define UART0_WF7816            *(volatile uint8_t  *)0x4006A01D // UART 7816 Wait FD Register
+#define UART0_ET7816            *(volatile uint8_t  *)0x4006A01E // UART 7816 Error Threshold Register
+#define UART0_TL7816            *(volatile uint8_t  *)0x4006A01F // UART 7816 Transmit Length Register
+#define UART0_C6                *(volatile uint8_t  *)0x4006A021 // UART CEA709.1-B Control Register 6
+#define UART0_PCTH              *(volatile uint8_t  *)0x4006A022 // UART CEA709.1-B Packet Cycle Time Counter High
+#define UART0_PCTL              *(volatile uint8_t  *)0x4006A023 // UART CEA709.1-B Packet Cycle Time Counter Low
+#define UART0_B1T               *(volatile uint8_t  *)0x4006A024 // UART CEA709.1-B Beta1 Timer
+#define UART0_SDTH              *(volatile uint8_t  *)0x4006A025 // UART CEA709.1-B Secondary Delay Timer High
+#define UART0_SDTL              *(volatile uint8_t  *)0x4006A026 // UART CEA709.1-B Secondary Delay Timer Low
+#define UART0_PRE               *(volatile uint8_t  *)0x4006A027 // UART CEA709.1-B Preamble
+#define UART0_TPL               *(volatile uint8_t  *)0x4006A028 // UART CEA709.1-B Transmit Packet Length
+#define UART0_IE                *(volatile uint8_t  *)0x4006A029 // UART CEA709.1-B Interrupt Enable Register
+#define UART0_WB                *(volatile uint8_t  *)0x4006A02A // UART CEA709.1-B WBASE
+#define UART0_S3                *(volatile uint8_t  *)0x4006A02B // UART CEA709.1-B Status Register
+#define UART0_S4                *(volatile uint8_t  *)0x4006A02C // UART CEA709.1-B Status Register
+#define UART0_RPL               *(volatile uint8_t  *)0x4006A02D // UART CEA709.1-B Received Packet Length
+#define UART0_RPREL             *(volatile uint8_t  *)0x4006A02E // UART CEA709.1-B Received Preamble Length
+#define UART0_CPW               *(volatile uint8_t  *)0x4006A02F // UART CEA709.1-B Collision Pulse Width
+#define UART0_RIDT              *(volatile uint8_t  *)0x4006A030 // UART CEA709.1-B Receive Indeterminate Time
+#define UART0_TIDT              *(volatile uint8_t  *)0x4006A031 // UART CEA709.1-B Transmit Indeterminate Time
+#define UART1_BDH               *(volatile uint8_t  *)0x4006B000 // UART Baud Rate Registers: High
+#define UART1_BDL               *(volatile uint8_t  *)0x4006B001 // UART Baud Rate Registers: Low
+#define UART1_C1                *(volatile uint8_t  *)0x4006B002 // UART Control Register 1
+#define UART1_C2                *(volatile uint8_t  *)0x4006B003 // UART Control Register 2
+#define UART1_S1                *(volatile uint8_t  *)0x4006B004 // UART Status Register 1
+#define UART1_S2                *(volatile uint8_t  *)0x4006B005 // UART Status Register 2
+#define UART1_C3                *(volatile uint8_t  *)0x4006B006 // UART Control Register 3
+#define UART1_D                 *(volatile uint8_t  *)0x4006B007 // UART Data Register
+#define UART1_MA1               *(volatile uint8_t  *)0x4006B008 // UART Match Address Registers 1
+#define UART1_MA2               *(volatile uint8_t  *)0x4006B009 // UART Match Address Registers 2
+#define UART1_C4                *(volatile uint8_t  *)0x4006B00A // UART Control Register 4
+#define UART1_C5                *(volatile uint8_t  *)0x4006B00B // UART Control Register 5
+#define UART1_ED                *(volatile uint8_t  *)0x4006B00C // UART Extended Data Register
+#define UART1_MODEM             *(volatile uint8_t  *)0x4006B00D // UART Modem Register
+#define UART1_IR                *(volatile uint8_t  *)0x4006B00E // UART Infrared Register
+#define UART1_PFIFO             *(volatile uint8_t  *)0x4006B010 // UART FIFO Parameters
+#define UART1_CFIFO             *(volatile uint8_t  *)0x4006B011 // UART FIFO Control Register
+#define UART1_SFIFO             *(volatile uint8_t  *)0x4006B012 // UART FIFO Status Register
+#define UART1_TWFIFO            *(volatile uint8_t  *)0x4006B013 // UART FIFO Transmit Watermark
+#define UART1_TCFIFO            *(volatile uint8_t  *)0x4006B014 // UART FIFO Transmit Count
+#define UART1_RWFIFO            *(volatile uint8_t  *)0x4006B015 // UART FIFO Receive Watermark
+#define UART1_RCFIFO            *(volatile uint8_t  *)0x4006B016 // UART FIFO Receive Count
+#define UART1_C7816             *(volatile uint8_t  *)0x4006B018 // UART 7816 Control Register
+#define UART1_IE7816            *(volatile uint8_t  *)0x4006B019 // UART 7816 Interrupt Enable Register
+#define UART1_IS7816            *(volatile uint8_t  *)0x4006B01A // UART 7816 Interrupt Status Register
+#define UART1_WP7816T0          *(volatile uint8_t  *)0x4006B01B // UART 7816 Wait Parameter Register
+#define UART1_WP7816T1          *(volatile uint8_t  *)0x4006B01B // UART 7816 Wait Parameter Register
+#define UART1_WN7816            *(volatile uint8_t  *)0x4006B01C // UART 7816 Wait N Register
+#define UART1_WF7816            *(volatile uint8_t  *)0x4006B01D // UART 7816 Wait FD Register
+#define UART1_ET7816            *(volatile uint8_t  *)0x4006B01E // UART 7816 Error Threshold Register
+#define UART1_TL7816            *(volatile uint8_t  *)0x4006B01F // UART 7816 Transmit Length Register
+#define UART1_C6                *(volatile uint8_t  *)0x4006B021 // UART CEA709.1-B Control Register 6
+#define UART1_PCTH              *(volatile uint8_t  *)0x4006B022 // UART CEA709.1-B Packet Cycle Time Counter High
+#define UART1_PCTL              *(volatile uint8_t  *)0x4006B023 // UART CEA709.1-B Packet Cycle Time Counter Low
+#define UART1_B1T               *(volatile uint8_t  *)0x4006B024 // UART CEA709.1-B Beta1 Timer
+#define UART1_SDTH              *(volatile uint8_t  *)0x4006B025 // UART CEA709.1-B Secondary Delay Timer High
+#define UART1_SDTL              *(volatile uint8_t  *)0x4006B026 // UART CEA709.1-B Secondary Delay Timer Low
+#define UART1_PRE               *(volatile uint8_t  *)0x4006B027 // UART CEA709.1-B Preamble
+#define UART1_TPL               *(volatile uint8_t  *)0x4006B028 // UART CEA709.1-B Transmit Packet Length
+#define UART1_IE                *(volatile uint8_t  *)0x4006B029 // UART CEA709.1-B Interrupt Enable Register
+#define UART1_WB                *(volatile uint8_t  *)0x4006B02A // UART CEA709.1-B WBASE
+#define UART1_S3                *(volatile uint8_t  *)0x4006B02B // UART CEA709.1-B Status Register
+#define UART1_S4                *(volatile uint8_t  *)0x4006B02C // UART CEA709.1-B Status Register
+#define UART1_RPL               *(volatile uint8_t  *)0x4006B02D // UART CEA709.1-B Received Packet Length
+#define UART1_RPREL             *(volatile uint8_t  *)0x4006B02E // UART CEA709.1-B Received Preamble Length
+#define UART1_CPW               *(volatile uint8_t  *)0x4006B02F // UART CEA709.1-B Collision Pulse Width
+#define UART1_RIDT              *(volatile uint8_t  *)0x4006B030 // UART CEA709.1-B Receive Indeterminate Time
+#define UART1_TIDT              *(volatile uint8_t  *)0x4006B031 // UART CEA709.1-B Transmit Indeterminate Time
+#define UART2_BDH               *(volatile uint8_t  *)0x4006C000 // UART Baud Rate Registers: High
+#define UART2_BDL               *(volatile uint8_t  *)0x4006C001 // UART Baud Rate Registers: Low
+#define UART2_C1                *(volatile uint8_t  *)0x4006C002 // UART Control Register 1
+#define UART2_C2                *(volatile uint8_t  *)0x4006C003 // UART Control Register 2
+#define UART2_S1                *(volatile uint8_t  *)0x4006C004 // UART Status Register 1
+#define UART2_S2                *(volatile uint8_t  *)0x4006C005 // UART Status Register 2
+#define UART2_C3                *(volatile uint8_t  *)0x4006C006 // UART Control Register 3
+#define UART2_D                 *(volatile uint8_t  *)0x4006C007 // UART Data Register
+#define UART2_MA1               *(volatile uint8_t  *)0x4006C008 // UART Match Address Registers 1
+#define UART2_MA2               *(volatile uint8_t  *)0x4006C009 // UART Match Address Registers 2
+#define UART2_C4                *(volatile uint8_t  *)0x4006C00A // UART Control Register 4
+#define UART2_C5                *(volatile uint8_t  *)0x4006C00B // UART Control Register 5
+#define UART2_ED                *(volatile uint8_t  *)0x4006C00C // UART Extended Data Register
+#define UART2_MODEM             *(volatile uint8_t  *)0x4006C00D // UART Modem Register
+#define UART2_IR                *(volatile uint8_t  *)0x4006C00E // UART Infrared Register
+#define UART2_PFIFO             *(volatile uint8_t  *)0x4006C010 // UART FIFO Parameters
+#define UART2_CFIFO             *(volatile uint8_t  *)0x4006C011 // UART FIFO Control Register
+#define UART2_SFIFO             *(volatile uint8_t  *)0x4006C012 // UART FIFO Status Register
+#define UART2_TWFIFO            *(volatile uint8_t  *)0x4006C013 // UART FIFO Transmit Watermark
+#define UART2_TCFIFO            *(volatile uint8_t  *)0x4006C014 // UART FIFO Transmit Count
+#define UART2_RWFIFO            *(volatile uint8_t  *)0x4006C015 // UART FIFO Receive Watermark
+#define UART2_RCFIFO            *(volatile uint8_t  *)0x4006C016 // UART FIFO Receive Count
+#define UART2_C7816             *(volatile uint8_t  *)0x4006C018 // UART 7816 Control Register
+#define UART2_IE7816            *(volatile uint8_t  *)0x4006C019 // UART 7816 Interrupt Enable Register
+#define UART2_IS7816            *(volatile uint8_t  *)0x4006C01A // UART 7816 Interrupt Status Register
+#define UART2_WP7816T0          *(volatile uint8_t  *)0x4006C01B // UART 7816 Wait Parameter Register
+#define UART2_WP7816T1          *(volatile uint8_t  *)0x4006C01B // UART 7816 Wait Parameter Register
+#define UART2_WN7816            *(volatile uint8_t  *)0x4006C01C // UART 7816 Wait N Register
+#define UART2_WF7816            *(volatile uint8_t  *)0x4006C01D // UART 7816 Wait FD Register
+#define UART2_ET7816            *(volatile uint8_t  *)0x4006C01E // UART 7816 Error Threshold Register
+#define UART2_TL7816            *(volatile uint8_t  *)0x4006C01F // UART 7816 Transmit Length Register
+#define UART2_C6                *(volatile uint8_t  *)0x4006C021 // UART CEA709.1-B Control Register 6
+#define UART2_PCTH              *(volatile uint8_t  *)0x4006C022 // UART CEA709.1-B Packet Cycle Time Counter High
+#define UART2_PCTL              *(volatile uint8_t  *)0x4006C023 // UART CEA709.1-B Packet Cycle Time Counter Low
+#define UART2_B1T               *(volatile uint8_t  *)0x4006C024 // UART CEA709.1-B Beta1 Timer
+#define UART2_SDTH              *(volatile uint8_t  *)0x4006C025 // UART CEA709.1-B Secondary Delay Timer High
+#define UART2_SDTL              *(volatile uint8_t  *)0x4006C026 // UART CEA709.1-B Secondary Delay Timer Low
+#define UART2_PRE               *(volatile uint8_t  *)0x4006C027 // UART CEA709.1-B Preamble
+#define UART2_TPL               *(volatile uint8_t  *)0x4006C028 // UART CEA709.1-B Transmit Packet Length
+#define UART2_IE                *(volatile uint8_t  *)0x4006C029 // UART CEA709.1-B Interrupt Enable Register
+#define UART2_WB                *(volatile uint8_t  *)0x4006C02A // UART CEA709.1-B WBASE
+#define UART2_S3                *(volatile uint8_t  *)0x4006C02B // UART CEA709.1-B Status Register
+#define UART2_S4                *(volatile uint8_t  *)0x4006C02C // UART CEA709.1-B Status Register
+#define UART2_RPL               *(volatile uint8_t  *)0x4006C02D // UART CEA709.1-B Received Packet Length
+#define UART2_RPREL             *(volatile uint8_t  *)0x4006C02E // UART CEA709.1-B Received Preamble Length
+#define UART2_CPW               *(volatile uint8_t  *)0x4006C02F // UART CEA709.1-B Collision Pulse Width
+#define UART2_RIDT              *(volatile uint8_t  *)0x4006C030 // UART CEA709.1-B Receive Indeterminate Time
+#define UART2_TIDT              *(volatile uint8_t  *)0x4006C031 // UART CEA709.1-B Transmit Indeterminate Time
+
+// Chapter 46: Synchronous Audio Interface (SAI)
+#define I2S0_TCSR               *(volatile uint32_t *)0x4002F000 // SAI Transmit Control Register
+#define I2S0_TCR1               *(volatile uint32_t *)0x4002F004 // SAI Transmit Configuration 1 Register
+#define I2S0_TCR2               *(volatile uint32_t *)0x4002F008 // SAI Transmit Configuration 2 Register
+#define I2S0_TCR3               *(volatile uint32_t *)0x4002F00C // SAI Transmit Configuration 3 Register
+#define I2S0_TCR4               *(volatile uint32_t *)0x4002F010 // SAI Transmit Configuration 4 Register
+#define I2S0_TCR5               *(volatile uint32_t *)0x4002F014 // SAI Transmit Configuration 5 Register
+#define I2S0_TDR0               *(volatile uint32_t *)0x4002F020 // SAI Transmit Data Register
+#define I2S0_TFR0               *(volatile uint32_t *)0x4002F040 // SAI Transmit FIFO Register
+#define I2S0_TMR                *(volatile uint32_t *)0x4002F060 // SAI Transmit Mask Register
+#define I2S0_RCSR               *(volatile uint32_t *)0x4002F080 // SAI Receive Control Register
+#define I2S0_RCR1               *(volatile uint32_t *)0x4002F084 // SAI Receive Configuration 1 Register
+#define I2S0_RCR2               *(volatile uint32_t *)0x4002F088 // SAI Receive Configuration 2 Register
+#define I2S0_RCR3               *(volatile uint32_t *)0x4002F08C // SAI Receive Configuration 3 Register
+#define I2S0_RCR4               *(volatile uint32_t *)0x4002F090 // SAI Receive Configuration 4 Register
+#define I2S0_RCR5               *(volatile uint32_t *)0x4002F094 // SAI Receive Configuration 5 Register
+#define I2S0_RDR0               *(volatile uint32_t *)0x4002F0A0 // SAI Receive Data Register
+#define I2S0_RFR0               *(volatile uint32_t *)0x4002F0C0 // SAI Receive FIFO Register
+#define I2S0_RMR                *(volatile uint32_t *)0x4002F0E0 // SAI Receive Mask Register
+#define I2S0_MCR                *(volatile uint32_t *)0x4002F100 // SAI MCLK Control Register
+#define I2S0_MDR                *(volatile uint32_t *)0x4002F104 // SAI MCLK Divide Register
+
+// Chapter 47: General-Purpose Input/Output (GPIO)
+#define GPIOA_PDOR              *(volatile uint32_t *)0x400FF000 // Port Data Output Register
+#define GPIOA_PSOR              *(volatile uint32_t *)0x400FF004 // Port Set Output Register
+#define GPIOA_PCOR              *(volatile uint32_t *)0x400FF008 // Port Clear Output Register
+#define GPIOA_PTOR              *(volatile uint32_t *)0x400FF00C // Port Toggle Output Register
+#define GPIOA_PDIR              *(volatile uint32_t *)0x400FF010 // Port Data Input Register
+#define GPIOA_PDDR              *(volatile uint32_t *)0x400FF014 // Port Data Direction Register
+#define GPIOB_PDOR              *(volatile uint32_t *)0x400FF040 // Port Data Output Register
+#define GPIOB_PSOR              *(volatile uint32_t *)0x400FF044 // Port Set Output Register
+#define GPIOB_PCOR              *(volatile uint32_t *)0x400FF048 // Port Clear Output Register
+#define GPIOB_PTOR              *(volatile uint32_t *)0x400FF04C // Port Toggle Output Register
+#define GPIOB_PDIR              *(volatile uint32_t *)0x400FF050 // Port Data Input Register
+#define GPIOB_PDDR              *(volatile uint32_t *)0x400FF054 // Port Data Direction Register
+#define GPIOC_PDOR              *(volatile uint32_t *)0x400FF080 // Port Data Output Register
+#define GPIOC_PSOR              *(volatile uint32_t *)0x400FF084 // Port Set Output Register
+#define GPIOC_PCOR              *(volatile uint32_t *)0x400FF088 // Port Clear Output Register
+#define GPIOC_PTOR              *(volatile uint32_t *)0x400FF08C // Port Toggle Output Register
+#define GPIOC_PDIR              *(volatile uint32_t *)0x400FF090 // Port Data Input Register
+#define GPIOC_PDDR              *(volatile uint32_t *)0x400FF094 // Port Data Direction Register
+#define GPIOD_PDOR              *(volatile uint32_t *)0x400FF0C0 // Port Data Output Register
+#define GPIOD_PSOR              *(volatile uint32_t *)0x400FF0C4 // Port Set Output Register
+#define GPIOD_PCOR              *(volatile uint32_t *)0x400FF0C8 // Port Clear Output Register
+#define GPIOD_PTOR              *(volatile uint32_t *)0x400FF0CC // Port Toggle Output Register
+#define GPIOD_PDIR              *(volatile uint32_t *)0x400FF0D0 // Port Data Input Register
+#define GPIOD_PDDR              *(volatile uint32_t *)0x400FF0D4 // Port Data Direction Register
+#define GPIOE_PDOR              *(volatile uint32_t *)0x400FF100 // Port Data Output Register
+#define GPIOE_PSOR              *(volatile uint32_t *)0x400FF104 // Port Set Output Register
+#define GPIOE_PCOR              *(volatile uint32_t *)0x400FF108 // Port Clear Output Register
+#define GPIOE_PTOR              *(volatile uint32_t *)0x400FF10C // Port Toggle Output Register
+#define GPIOE_PDIR              *(volatile uint32_t *)0x400FF110 // Port Data Input Register
+#define GPIOE_PDDR              *(volatile uint32_t *)0x400FF114 // Port Data Direction Register
+
+// Chapter 48: Touch sense input (TSI)
+#define TSI0_GENCS              *(volatile uint32_t *)0x40045000 // General Control and Status Register
+#define TSI_GENCS_LPCLKS               (uint32_t)0x10000000            // 
+#define TSI_GENCS_LPSCNITV(n)          (((n) & 15) << 24)              // 
+#define TSI_GENCS_NSCN(n)              (((n) & 31) << 19)              // 
+#define TSI_GENCS_PS(n)                        (((n) & 7) << 16)               // 
+#define TSI_GENCS_EOSF                 (uint32_t)0x00008000            // 
+#define TSI_GENCS_OUTRGF               (uint32_t)0x00004000            // 
+#define TSI_GENCS_EXTERF               (uint32_t)0x00002000            // 
+#define TSI_GENCS_OVRF                 (uint32_t)0x00001000            // 
+#define TSI_GENCS_SCNIP                        (uint32_t)0x00000200            // 
+#define TSI_GENCS_SWTS                 (uint32_t)0x00000100            // 
+#define TSI_GENCS_TSIEN                        (uint32_t)0x00000080            // 
+#define TSI_GENCS_TSIIE                        (uint32_t)0x00000040            // 
+#define TSI_GENCS_ERIE                 (uint32_t)0x00000020            // 
+#define TSI_GENCS_ESOR                 (uint32_t)0x00000010            // 
+#define TSI_GENCS_STM                  (uint32_t)0x00000002            // 
+#define TSI_GENCS_STPE                 (uint32_t)0x00000001            // 
+#define TSI0_SCANC              *(volatile uint32_t *)0x40045004 // SCAN Control Register
+#define TSI_SCANC_REFCHRG(n)           (((n) & 15) << 24)              // 
+#define TSI_SCANC_EXTCHRG(n)           (((n) & 7) << 16)               // 
+#define TSI_SCANC_SMOD(n)              (((n) & 255) << 8)              // 
+#define TSI_SCANC_AMCLKS(n)            (((n) & 3) << 3)                // 
+#define TSI_SCANC_AMPSC(n)             (((n) & 7) << 0)                // 
+#define TSI0_PEN                *(volatile uint32_t *)0x40045008 // Pin Enable Register
+#define TSI0_WUCNTR             *(volatile uint32_t *)0x4004500C // Wake-Up Channel Counter Register
+#define TSI0_CNTR1              *(volatile uint32_t *)0x40045100 // Counter Register
+#define TSI0_CNTR3              *(volatile uint32_t *)0x40045104 // Counter Register
+#define TSI0_CNTR5              *(volatile uint32_t *)0x40045108 // Counter Register
+#define TSI0_CNTR7              *(volatile uint32_t *)0x4004510C // Counter Register
+#define TSI0_CNTR9              *(volatile uint32_t *)0x40045110 // Counter Register
+#define TSI0_CNTR11             *(volatile uint32_t *)0x40045114 // Counter Register
+#define TSI0_CNTR13             *(volatile uint32_t *)0x40045118 // Counter Register
+#define TSI0_CNTR15             *(volatile uint32_t *)0x4004511C // Counter Register
+#define TSI0_THRESHOLD          *(volatile uint32_t *)0x40045120 // Low Power Channel Threshold Register
+
+// Nested Vectored Interrupt Controller, Table 3-4 & ARMv7 ref, appendix B3.4 (page 750)
+#define NVIC_ENABLE_IRQ(n)     (*((volatile uint32_t *)0xE000E100 + (n >> 5)) = (1 << (n & 31)))
+#define NVIC_DISABLE_IRQ(n)    (*((volatile uint32_t *)0xE000E180 + (n >> 5)) = (1 << (n & 31)))
+#define NVIC_SET_PENDING(n)    (*((volatile uint32_t *)0xE000E200 + (n >> 5)) = (1 << (n & 31)))
+#define NVIC_CLEAR_PENDING(n)  (*((volatile uint32_t *)0xE000E280 + (n >> 5)) = (1 << (n & 31)))
+
+#define NVIC_ISER0             *(volatile uint32_t *)0xE000E100
+#define NVIC_ISER1             *(volatile uint32_t *)0xE000E104
+#define NVIC_ICER0             *(volatile uint32_t *)0xE000E180
+#define NVIC_ICER1             *(volatile uint32_t *)0xE000E184
+
+//#define NVIC_SET_PRIORITY(n, p)      
+#define IRQ_DMA_CH0            0
+#define IRQ_DMA_CH1            1
+#define IRQ_DMA_CH2            2
+#define IRQ_DMA_CH3            3
+#define IRQ_DMA_ERROR          4
+#define IRQ_FTFL_COMPLETE      6
+#define IRQ_FTFL_COLLISION     7
+#define IRQ_LOW_VOLTAGE                8
+#define IRQ_LLWU               9
+#define IRQ_WDOG               10
+#define IRQ_I2C0               11
+#define IRQ_SPI0               12
+#define IRQ_I2S0_TX            13
+#define IRQ_I2S0_RX            14
+#define IRQ_UART0_LON          15
+#define IRQ_UART0_STATUS       16
+#define IRQ_UART0_ERROR                17
+#define IRQ_UART1_STATUS       18
+#define IRQ_UART1_ERROR                19
+#define IRQ_UART2_STATUS       20
+#define IRQ_UART2_ERROR                21
+#define IRQ_ADC0               22
+#define IRQ_CMP0               23
+#define IRQ_CMP1               24
+#define IRQ_FTM0               25
+#define IRQ_FTM1               26
+#define IRQ_CMT                        27
+#define IRQ_RTC_ALARM          28
+#define IRQ_RTC_SECOND         29
+#define IRQ_PIT_CH0            30
+#define IRQ_PIT_CH1            31
+#define IRQ_PIT_CH2            32
+#define IRQ_PIT_CH3            33
+#define IRQ_PDB                        34
+#define IRQ_USBOTG             35
+#define IRQ_USBDCD             36
+#define IRQ_TSI                        37
+#define IRQ_MCG                        38
+#define IRQ_LPTMR              39
+#define IRQ_PORTA              40
+#define IRQ_PORTB              41
+#define IRQ_PORTC              42
+#define IRQ_PORTD              43
+#define IRQ_PORTE              44
+#define IRQ_SOFTWARE           45
+
+
+#define __disable_irq() asm volatile("CPSID i");
+#define __enable_irq()  asm volatile("CPSIE i");
+
+
+// System Control Space (SCS), ARMv7 ref manual, B3.2, page 708
+#define SCB_CPUID              *(const    uint32_t *)0xE000ED00 // CPUID Base Register
+#define SCB_ICSR               *(volatile uint32_t *)0xE000ED04 // Interrupt Control and State
+#define SCB_ICSR_PENDSTSET             (uint32_t)0x04000000
+#define SCB_VTOR               *(volatile uint32_t *)0xE000ED08 // Vector Table Offset
+#define SCB_AIRCR              *(volatile uint32_t *)0xE000ED0C // Application Interrupt and Reset Control
+#define SCB_SCR                        *(volatile uint32_t *)0xE000ED10 // System Control Register
+#define SCB_CCR                        *(volatile uint32_t *)0xE000ED14 // Configuration and Control
+#define SCB_SHPR1              *(volatile uint32_t *)0xE000ED18 // System Handler Priority Register 1
+#define SCB_SHPR2              *(volatile uint32_t *)0xE000ED1C // System Handler Priority Register 2
+#define SCB_SHPR3              *(volatile uint32_t *)0xE000ED20 // System Handler Priority Register 3
+#define SCB_SHCSR              *(volatile uint32_t *)0xE000ED24 // System Handler Control and State
+#define SCB_CFSR               *(volatile uint32_t *)0xE000ED28 // Configurable Fault Status Register
+#define SCB_HFSR               *(volatile uint32_t *)0xE000ED2C // HardFault Status
+#define SCB_DFSR               *(volatile uint32_t *)0xE000ED30 // Debug Fault Status
+#define SCB_MMFAR              *(volatile uint32_t *)0xE000ED34 // MemManage Fault Address
+
+#define SYST_CSR               *(volatile uint32_t *)0xE000E010 // SysTick Control and Status
+#define SYST_CSR_COUNTFLAG             (uint32_t)0x00010000
+#define SYST_CSR_CLKSOURCE             (uint32_t)0x00000004
+#define SYST_CSR_TICKINT               (uint32_t)0x00000002
+#define SYST_CSR_ENABLE                        (uint32_t)0x00000001
+#define SYST_RVR               *(volatile uint32_t *)0xE000E014 // SysTick Reload Value Register
+#define SYST_CVR               *(volatile uint32_t *)0xE000E018 // SysTick Current Value Register
+#define SYST_CALIB             *(const    uint32_t *)0xE000E01C // SysTick Calibration Value
+
+
+#define ARM_DEMCR               *(volatile uint32_t *)0xE000EDFC // Debug Exception and Monitor Control
+#define ARM_DEMCR_TRCENA               (1 << 24)        // Enable debugging & monitoring blocks
+#define ARM_DWT_CTRL            *(volatile uint32_t *)0xE0001000 // DWT control register
+#define ARM_DWT_CTRL_CYCCNTENA          (1 << 0)                // Enable cycle count
+#define ARM_DWT_CYCCNT          *(volatile uint32_t *)0xE0001004 // Cycle count register
+
+
+extern void nmi_isr(void);
+extern void hard_fault_isr(void);
+extern void memmanage_fault_isr(void);
+extern void bus_fault_isr(void);
+extern void usage_fault_isr(void);
+extern void svcall_isr(void);
+extern void debugmonitor_isr(void);
+extern void pendablesrvreq_isr(void);
+extern void systick_isr(void);
+extern void dma_ch0_isr(void);
+extern void dma_ch1_isr(void);
+extern void dma_ch2_isr(void);
+extern void dma_ch3_isr(void);
+extern void dma_error_isr(void);
+extern void flash_cmd_isr(void);
+extern void flash_error_isr(void);
+extern void low_voltage_isr(void);
+extern void wakeup_isr(void);
+extern void watchdog_isr(void);
+extern void i2c0_isr(void);
+extern void spi0_isr(void);
+extern void i2s0_tx_isr(void);
+extern void i2s0_rx_isr(void);
+extern void uart0_lon_isr(void);
+extern void uart0_status_isr(void);
+extern void uart0_error_isr(void);
+extern void uart1_status_isr(void);
+extern void uart1_error_isr(void);
+extern void uart2_status_isr(void);
+extern void uart2_error_isr(void);
+extern void adc0_isr(void);
+extern void cmp0_isr(void);
+extern void cmp1_isr(void);
+extern void ftm0_isr(void);
+extern void ftm1_isr(void);
+extern void cmt_isr(void);
+extern void rtc_alarm_isr(void);
+extern void rtc_seconds_isr(void);
+extern void pit0_isr(void);
+extern void pit1_isr(void);
+extern void pit2_isr(void);
+extern void pit3_isr(void);
+extern void pdb_isr(void);
+extern void usb_isr(void);
+extern void usb_charge_isr(void);
+extern void tsi0_isr(void);
+extern void mcg_isr(void);
+extern void lptmr_isr(void);
+extern void porta_isr(void);
+extern void portb_isr(void);
+extern void portc_isr(void);
+extern void portd_isr(void);
+extern void porte_isr(void);
+extern void software_isr(void);
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/Lib/mk20dx128.ld b/Lib/mk20dx128.ld
new file mode 100644 (file)
index 0000000..e3af354
--- /dev/null
@@ -0,0 +1,73 @@
+MEMORY
+{
+       FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
+       RAM  (rwx) : ORIGIN = 0x1FFFE000, LENGTH = 16K
+}
+
+
+SECTIONS
+{
+       .text : {
+               . = 0;
+               KEEP(*(.vectors))
+               *(.startup*)
+               /* TODO: does linker detect startup overflow onto flashconfig? */
+               . = 0x400;
+               KEEP(*(.flashconfig*))
+               *(.text*)
+               *(.rodata*)
+               . = ALIGN(4);
+               KEEP(*(.init))
+               . = ALIGN(4);
+               __preinit_array_start = .;
+               KEEP (*(.preinit_array))
+               __preinit_array_end = .;
+               __init_array_start = .;
+               KEEP (*(SORT(.init_array.*)))
+               KEEP (*(.init_array))
+               __init_array_end = .;
+       } > FLASH = 0xFF
+
+       .ARM.exidx : {
+               __exidx_start = .;
+               *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+               __exidx_end = .;
+       } > FLASH
+       _etext = .;
+
+       .usbdescriptortable (NOLOAD) : {
+               /* . = ORIGIN(RAM); */
+               . = ALIGN(512);
+               *(.usbdescriptortable*)
+       } > RAM
+
+       .usbbuffers (NOLOAD) : {
+               . = ALIGN(4);
+               *(.usbbuffers*)
+       } > RAM
+
+       .data : AT (_etext) {
+               . = ALIGN(4);
+               _sdata = .; 
+               *(.data*)
+               . = ALIGN(4);
+               _edata = .; 
+       } > RAM
+
+       .noinit (NOLOAD) : {
+               *(.noinit*)
+       } > RAM
+
+       .bss : {
+               . = ALIGN(4);
+               _sbss = .; 
+               *(.bss*)
+               *(COMMON)
+               . = ALIGN(4);
+               _ebss = .;   
+       } > RAM
+
+       _estack = ORIGIN(RAM) + LENGTH(RAM);
+}
+
+
diff --git a/Lib/pin_map.teensy3 b/Lib/pin_map.teensy3
new file mode 100644 (file)
index 0000000..922eeb4
--- /dev/null
@@ -0,0 +1,46 @@
+// Pin                         Arduino
+//  0  B16                     RXD
+//  1  B17                     TXD
+//  2  D0                      
+//  3  A12     FTM1_CH0        
+//  4  A13     FTM1_CH1        
+//  5  D7      FTM0_CH7        OC0B/T1
+//  6  D4      FTM0_CH4        OC0A
+//  7  D2                      
+//  8  D3                      ICP1
+//  9  C3      FTM0_CH2        OC1A
+// 10  C4      FTM0_CH3        SS/OC1B
+// 11  C6                      MOSI/OC2A
+// 12  C7                      MISO
+// 13  C5                      SCK     
+// 14  D1                      
+// 15  C0                      
+// 16  B0      (FTM1_CH0)      
+// 17  B1      (FTM1_CH1)      
+// 18  B3                      SDA
+// 19  B2                      SCL
+// 20  D5      FTM0_CH5        
+// 21  D6      FTM0_CH6        
+// 22  C1      FTM0_CH0        
+// 23  C2      FTM0_CH1        
+// 24  A5      (FTM0_CH2)      
+// 25  B19
+// 26  E1
+// 27  C9
+// 28  C8
+// 29  C10
+// 30  C11
+// 31  E0
+// 32  B18
+// 33  A4      (FTM0_CH1)
+// (34)        analog only
+// (35)        analog only
+// (36)        analog only
+// (37)        analog only
+
+// not available to user:
+//     A0      FTM0_CH5        SWD Clock
+//     A1      FTM0_CH6        USB ID
+//     A2      FTM0_CH7        SWD Trace
+//     A3      FTM0_CH0        SWD Data
+
diff --git a/Scan/MBC-55X/scan_loop.c b/Scan/MBC-55X/scan_loop.c
new file mode 100644 (file)
index 0000000..be23572
--- /dev/null
@@ -0,0 +1,236 @@
+/* Copyright (C) 2013 by Jacob Alexander
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+// ----- Includes -----
+
+// Compiler Includes
+#include <Lib/ScanLib.h>
+
+// Project Includes
+#include <led.h>
+#include <print.h>
+
+// Local Includes
+#include "scan_loop.h"
+
+
+
+// ----- Defines -----
+
+
+// ----- Macros -----
+
+// Make sure we haven't overflowed the buffer
+#define bufferAdd(byte) \
+               if ( KeyIndex_BufferUsed < KEYBOARD_BUFFER ) \
+                       KeyIndex_Buffer[KeyIndex_BufferUsed++] = byte
+
+
+
+// ----- Variables -----
+
+// Buffer used to inform the macro processing module which keys have been detected as pressed
+volatile uint8_t KeyIndex_Buffer[KEYBOARD_BUFFER];
+volatile uint8_t KeyIndex_BufferUsed;
+
+
+
+// ----- Function Declarations -----
+
+void processKeyValue( uint8_t valueType );
+void  removeKeyValue( uint8_t keyValue );
+
+
+
+// ----- Interrupt Functions -----
+
+// UART Receive Buffer Full Interrupt
+#if defined(_at90usb162_) || defined(_atmega32u4_) || defined(_at90usb646_) || defined(_at90usb1286_) // AVR
+ISR(USART1_RX_vect)
+#elif defined(_mk20dx128_) // ARM
+void uart0_status_isr(void)
+#endif
+{
+       cli(); // Disable Interrupts
+
+       // Read part of the scan code (3 8bit chunks) from USART
+#if defined(_at90usb162_) || defined(_atmega32u4_) || defined(_at90usb646_) || defined(_at90usb1286_) // AVR
+       uint8_t tmp = UDR1;
+#elif defined(_mk20dx128_) // ARM
+       // TODO
+       uint8_t tmp = 0;
+#endif
+
+       // Debug
+       char tmpStr[6];
+       hexToStr( tmp, tmpStr );
+       dPrintStrs( tmpStr, " " ); // Debug
+
+       // TODO
+
+       sei(); // Re-enable Interrupts
+}
+
+
+
+// ----- Functions -----
+
+// Setup
+inline void scan_setup()
+#if defined(_at90usb162_) || defined(_atmega32u4_) || defined(_at90usb646_) || defined(_at90usb1286_) // AVR
+{
+       // Setup the the USART interface for keyboard data input
+
+       // TODO
+       // Setup baud rate
+       // 16 MHz / ( 16 * Baud ) = UBRR
+       // Baud: 4817 -> 16 MHz / ( 16 * 4817 ) = 207.5981
+       // Thus baud setting = 208
+       uint16_t baud = 208; // Max setting of 4095
+       UBRR1H = (uint8_t)(baud >> 8);
+       UBRR1L = (uint8_t)baud;
+
+       // Enable the receiver, transmitter, and RX Complete Interrupt
+       UCSR1B = 0x98;
+
+       // Set frame format: 8 data, 1 stop bit, odd parity
+       // Asynchrounous USART mode
+       UCSR1C = 0x36;
+
+       // Reset the keyboard before scanning, we might be in a wierd state
+       scan_resetKeyboard();
+}
+#elif defined(_mk20dx128_) // ARM
+{
+       // Setup the the UART interface for keyboard data input
+
+       // Setup baud rate
+       // TODO
+
+       // Reset the keyboard before scanning, we might be in a wierd state
+       scan_resetKeyboard();
+}
+#endif
+
+
+// Main Detection Loop
+inline uint8_t scan_loop()
+{
+       return 0;
+}
+
+void processKeyValue( uint8_t keyValue )
+{
+       // TODO Process ASCII
+
+       // Make sure the key isn't already in the buffer
+       for ( uint8_t c = 0; c < KeyIndex_BufferUsed + 1; c++ )
+       {
+               // Key isn't in the buffer yet
+               if ( c == KeyIndex_BufferUsed )
+               {
+                       bufferAdd( keyValue );
+                       break;
+               }
+
+               // Key already in the buffer
+               if ( KeyIndex_Buffer[c] == keyValue )
+                       break;
+       }
+}
+
+void removeKeyValue( uint8_t keyValue )
+{
+       // Check for the released key, and shift the other keys lower on the buffer
+       uint8_t c;
+       for ( c = 0; c < KeyIndex_BufferUsed; c++ )
+       {
+               // Key to release found
+               if ( KeyIndex_Buffer[c] == keyValue )
+               {
+                       // Shift keys from c position
+                       for ( uint8_t k = c; k < KeyIndex_BufferUsed - 1; k++ )
+                               KeyIndex_Buffer[k] = KeyIndex_Buffer[k + 1];
+
+                       // Decrement Buffer
+                       KeyIndex_BufferUsed--;
+
+                       break;
+               }
+       }
+
+       // Error case (no key to release)
+       if ( c == KeyIndex_BufferUsed + 1 )
+       {
+               errorLED( 1 );
+               char tmpStr[6];
+               hexToStr( keyValue, tmpStr );
+               erro_dPrint( "Could not find key to release: ", tmpStr );
+       }
+}
+
+// Send data 
+uint8_t scan_sendData( uint8_t dataPayload )
+{
+       // Debug
+       char tmpStr[6];
+       hexToStr( dataPayload, tmpStr );
+       info_dPrint( "Sending - ", tmpStr );
+
+#if defined(_at90usb162_) || defined(_atmega32u4_) || defined(_at90usb646_) || defined(_at90usb1286_) // AVR
+       UDR1 = dataPayload;
+#elif defined(_mk20dx128_) // ARM
+       // TODO
+#endif
+
+       return 0;
+}
+
+// Signal KeyIndex_Buffer that it has been properly read
+void scan_finishedWithBuffer( uint8_t sentKeys )
+{
+}
+
+// Signal that the keys have been properly sent over USB
+void scan_finishedWithUSBBuffer( uint8_t sentKeys )
+{
+}
+
+// Reset/Hold keyboard
+// NOTE: Does nothing with the FACOM6684
+void scan_lockKeyboard( void )
+{
+}
+
+// NOTE: Does nothing with the FACOM6684
+void scan_unlockKeyboard( void )
+{
+}
+
+// Reset Keyboard
+void scan_resetKeyboard( void )
+{
+       // Not a calculated valued...
+       _delay_ms( 50 );
+
+       KeyIndex_BufferUsed = 0;
+}
+
diff --git a/Scan/MBC-55X/scan_loop.h b/Scan/MBC-55X/scan_loop.h
new file mode 100644 (file)
index 0000000..c46a2a7
--- /dev/null
@@ -0,0 +1,67 @@
+/* Copyright (C) 2013 by Jacob Alexander
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef __SCAN_LOOP_H
+#define __SCAN_LOOP_H
+
+// ----- Includes -----
+
+// Compiler Includes
+#include <stdint.h>
+
+// Local Includes
+
+
+
+// ----- Defines -----
+
+#define KEYBOARD_KEYS 0x7F // 127 - Size of the array space for the keyboard(max index)
+#define KEYBOARD_BUFFER 24 // Max number of key signals to buffer
+
+
+
+// ----- Variables -----
+
+extern volatile     uint8_t KeyIndex_Buffer[KEYBOARD_BUFFER];
+extern volatile     uint8_t KeyIndex_BufferUsed;
+extern volatile     uint8_t KeyIndex_Add_InputSignal;
+
+
+
+// ----- Functions -----
+
+// Functions used by main.c
+void scan_setup( void );
+uint8_t scan_loop( void );
+
+
+// Functions available to macro.c
+uint8_t scan_sendData( uint8_t dataPayload );
+
+void scan_finishedWithBuffer( uint8_t sentKeys );
+void scan_finishedWithUSBBuffer( uint8_t sentKeys );
+void scan_lockKeyboard( void );
+void scan_unlockKeyboard( void );
+void scan_resetKeyboard( void );
+
+
+#endif // __SCAN_LOOP_H
+
diff --git a/Scan/MBC-55X/setup.cmake b/Scan/MBC-55X/setup.cmake
new file mode 100644 (file)
index 0000000..c10e47e
--- /dev/null
@@ -0,0 +1,48 @@
+###| CMake Kiibohd Controller Scan Module |###
+#
+# Written by Jacob Alexander in 2013 for the Kiibohd Controller
+#
+# Released into the Public Domain
+#
+# For the Sanyo MBC-55X Series of keyboards
+#
+###
+
+
+###
+# Module C files
+#
+
+set( SCAN_SRCS
+       scan_loop.c
+)
+
+
+###
+# Module H files
+#
+set( SCAN_HDRS
+       scan_loop.h
+)
+
+
+###
+# File Dependency Setup
+#
+ADD_FILE_DEPENDENCIES( scan_loop.c ${SCAN_HDRS} )
+#add_file_dependencies( scan_loop.c ${SCAN_HDRS} )
+#add_file_dependencies( macro.c keymap.h facom6684.h )
+
+
+###
+# Module Specific Options
+#
+add_definitions( -I${HEAD_DIR}/Keymap )
+
+#| Keymap Settings
+add_definitions(
+       -DMODIFIER_MASK=facom6684_ModifierMask
+       #-DKEYINDEX_MASK=facom6684_ColemakMap
+       -DKEYINDEX_MASK=facom6684_DefaultMap
+)
+
diff --git a/USB/pjrc/arm/usb_desc.c b/USB/pjrc/arm/usb_desc.c
new file mode 100644 (file)
index 0000000..99c94bd
--- /dev/null
@@ -0,0 +1,556 @@
+#include "usb_desc.h"
+
+
+// USB Descriptors are binary data which the USB host reads to
+// automatically detect a USB device's capabilities.  The format
+// and meaning of every field is documented in numerous USB
+// standards.  When working with USB descriptors, despite the
+// complexity of the standards and poor writing quality in many
+// of those documents, remember descriptors are nothing more
+// than constant binary data that tells the USB host what the
+// device can do.  Computers will load drivers based on this data.
+// Those drivers then communicate on the endpoints specified by
+// the descriptors.
+
+// To configure a new combination of interfaces or make minor
+// changes to existing configuration (eg, change the name or ID
+// numbers), usually you would edit "usb_desc.h".  This file
+// is meant to be configured by the header, so generally it is
+// only edited to add completely new USB interfaces or features.
+
+
+
+// **************************************************************
+//   USB Device
+// **************************************************************
+
+#define LSB(n) ((n) & 255)
+#define MSB(n) (((n) >> 8) & 255)
+
+// USB Device Descriptor.  The USB host reads this first, to learn
+// what type of device is connected.
+static uint8_t device_descriptor[] = {
+        18,                                     // bLength
+        1,                                      // bDescriptorType
+        0x00, 0x02,                             // bcdUSB
+#ifdef DEVICE_CLASS
+        DEVICE_CLASS,                           // bDeviceClass
+#else
+       0,
+#endif
+#ifdef DEVICE_SUBCLASS
+        DEVICE_SUBCLASS,                        // bDeviceSubClass
+#else
+       0,
+#endif
+#ifdef DEVICE_PROTOCOL
+        DEVICE_PROTOCOL,                        // bDeviceProtocol
+#else
+       0,
+#endif
+        EP0_SIZE,                               // bMaxPacketSize0
+        LSB(VENDOR_ID), MSB(VENDOR_ID),         // idVendor
+        LSB(PRODUCT_ID), MSB(PRODUCT_ID),       // idProduct
+        0x00, 0x01,                             // bcdDevice
+        1,                                      // iManufacturer
+        2,                                      // iProduct
+        3,                                      // iSerialNumber
+        1                                       // bNumConfigurations
+};
+
+// These descriptors must NOT be "const", because the USB DMA
+// has trouble accessing flash memory with enough bandwidth
+// while the processor is executing from flash.
+
+
+
+// **************************************************************
+//   HID Report Descriptors
+// **************************************************************
+
+// Each HID interface needs a special report descriptor that tells
+// the meaning and format of the data.
+
+#ifdef KEYBOARD_INTERFACE
+// Keyboard Protocol 1, HID 1.11 spec, Appendix B, page 59-60
+static uint8_t keyboard_report_desc[] = {
+        0x05, 0x01,             //  Usage Page (Generic Desktop),
+        0x09, 0x06,             //  Usage (Keyboard),
+        0xA1, 0x01,             //  Collection (Application),
+        0x75, 0x01,             //  Report Size (1),
+        0x95, 0x08,             //  Report Count (8),
+        0x05, 0x07,             //  Usage Page (Key Codes),
+        0x19, 0xE0,             //  Usage Minimum (224),
+        0x29, 0xE7,             //  Usage Maximum (231),
+        0x15, 0x00,             //  Logical Minimum (0),
+        0x25, 0x01,             //  Logical Maximum (1),
+        0x81, 0x02,             //  Input (Data, Variable, Absolute), ;Modifier byte
+        0x95, 0x08,             //  Report Count (8),
+        0x75, 0x01,             //  Report Size (1),
+        0x15, 0x00,             //  Logical Minimum (0),
+        0x25, 0x01,             //  Logical Maximum (1),
+        0x05, 0x0C,             //  Usage Page (Consumer),
+        0x09, 0xE9,             //  Usage (Volume Increment),
+        0x09, 0xEA,             //  Usage (Volume Decrement),
+        0x09, 0xE2,             //  Usage (Mute),
+        0x09, 0xCD,             //  Usage (Play/Pause),
+        0x09, 0xB5,             //  Usage (Scan Next Track),
+        0x09, 0xB6,             //  Usage (Scan Previous Track),
+        0x09, 0xB7,             //  Usage (Stop),
+        0x09, 0xB8,             //  Usage (Eject),
+        0x81, 0x02,             //  Input (Data, Variable, Absolute), ;Media keys
+        0x95, 0x05,             //  Report Count (5),
+        0x75, 0x01,             //  Report Size (1),
+        0x05, 0x08,             //  Usage Page (LEDs),
+        0x19, 0x01,             //  Usage Minimum (1),
+        0x29, 0x05,             //  Usage Maximum (5),
+        0x91, 0x02,             //  Output (Data, Variable, Absolute), ;LED report
+        0x95, 0x01,             //  Report Count (1),
+        0x75, 0x03,             //  Report Size (3),
+        0x91, 0x03,             //  Output (Constant),                 ;LED report padding
+        0x95, 0x06,             //  Report Count (6),
+        0x75, 0x08,             //  Report Size (8),
+        0x15, 0x00,             //  Logical Minimum (0),
+        0x25, 0x7F,             //  Logical Maximum(104),
+        0x05, 0x07,             //  Usage Page (Key Codes),
+        0x19, 0x00,             //  Usage Minimum (0),
+        0x29, 0x7F,             //  Usage Maximum (104),
+        0x81, 0x00,             //  Input (Data, Array),                ;Normal keys
+        0xc0                    // End Collection
+};
+#endif
+
+#ifdef MOUSE_INTERFACE
+// Mouse Protocol 1, HID 1.11 spec, Appendix B, page 59-60, with wheel extension
+static uint8_t mouse_report_desc[] = {
+        0x05, 0x01,                     // Usage Page (Generic Desktop)
+        0x09, 0x02,                     // Usage (Mouse)
+        0xA1, 0x01,                     // Collection (Application)
+        0x05, 0x09,                     //   Usage Page (Button)
+        0x19, 0x01,                     //   Usage Minimum (Button #1)
+        0x29, 0x03,                     //   Usage Maximum (Button #3)
+        0x15, 0x00,                     //   Logical Minimum (0)
+        0x25, 0x01,                     //   Logical Maximum (1)
+        0x95, 0x03,                     //   Report Count (3)
+        0x75, 0x01,                     //   Report Size (1)
+        0x81, 0x02,                     //   Input (Data, Variable, Absolute)
+        0x95, 0x01,                     //   Report Count (1)
+        0x75, 0x05,                     //   Report Size (5)
+        0x81, 0x03,                     //   Input (Constant)
+        0x05, 0x01,                     //   Usage Page (Generic Desktop)
+        0x09, 0x30,                     //   Usage (X)
+        0x09, 0x31,                     //   Usage (Y)
+        0x15, 0x81,                     //   Logical Minimum (-127)
+        0x25, 0x7F,                     //   Logical Maximum (127)
+        0x75, 0x08,                     //   Report Size (8),
+        0x95, 0x02,                     //   Report Count (2),
+        0x81, 0x06,                     //   Input (Data, Variable, Relative)
+        0x09, 0x38,                     //   Usage (Wheel)
+        0x95, 0x01,                     //   Report Count (1),
+        0x81, 0x06,                     //   Input (Data, Variable, Relative)
+        0xC0                            // End Collection
+};
+#endif
+
+#ifdef JOYSTICK_INTERFACE
+static uint8_t joystick_report_desc[] = {
+        0x05, 0x01,                     // Usage Page (Generic Desktop)
+        0x09, 0x04,                     // Usage (Joystick)
+        0xA1, 0x01,                     // Collection (Application)
+        0x15, 0x00,                     // Logical Minimum (0)
+        0x25, 0x01,                     // Logical Maximum (1)
+        0x75, 0x01,                     // Report Size (1)
+        0x95, 0x20,                     // Report Count (32)
+        0x05, 0x09,                     // Usage Page (Button)
+        0x19, 0x01,                     // Usage Minimum (Button #1)
+        0x29, 0x20,                     // Usage Maximum (Button #32)
+        0x81, 0x02,                     // Input (variable,absolute)
+        0x15, 0x00,                     // Logical Minimum (0)
+        0x25, 0x07,                     // Logical Maximum (7)
+        0x35, 0x00,                     // Physical Minimum (0)
+        0x46, 0x3B, 0x01,               // Physical Maximum (315)
+        0x75, 0x04,                     // Report Size (4)
+        0x95, 0x01,                     // Report Count (1)
+        0x65, 0x14,                     // Unit (20)
+        0x05, 0x01,                     // Usage Page (Generic Desktop)
+        0x09, 0x39,                     // Usage (Hat switch)
+        0x81, 0x42,                     // Input (variable,absolute,null_state)
+        0x05, 0x01,                     // Usage Page (Generic Desktop)
+        0x09, 0x01,                     // Usage (Pointer)
+        0xA1, 0x00,                     // Collection ()
+        0x15, 0x00,                     //   Logical Minimum (0)
+        0x26, 0xFF, 0x03,               //   Logical Maximum (1023)
+        0x75, 0x0A,                     //   Report Size (10)
+        0x95, 0x04,                     //   Report Count (4)
+        0x09, 0x30,                     //   Usage (X)
+        0x09, 0x31,                     //   Usage (Y)
+        0x09, 0x32,                     //   Usage (Z)
+        0x09, 0x35,                     //   Usage (Rz)
+        0x81, 0x02,                     //   Input (variable,absolute)
+        0xC0,                           // End Collection
+        0x15, 0x00,                     // Logical Minimum (0)
+        0x26, 0xFF, 0x03,               // Logical Maximum (1023)
+        0x75, 0x0A,                     // Report Size (10)
+        0x95, 0x02,                     // Report Count (2)
+        0x09, 0x36,                     // Usage (Slider)
+        0x09, 0x36,                     // Usage (Slider)
+        0x81, 0x02,                     // Input (variable,absolute)
+        0xC0                            // End Collection
+};
+#endif
+
+
+
+// **************************************************************
+//   USB Configuration
+// **************************************************************
+
+// USB Configuration Descriptor.  This huge descriptor tells all
+// of the devices capbilities.
+static uint8_t config_descriptor[CONFIG_DESC_SIZE] = {
+        // configuration descriptor, USB spec 9.6.3, page 264-266, Table 9-10
+        9,                                      // bLength;
+        2,                                      // bDescriptorType;
+        LSB(CONFIG_DESC_SIZE),                 // wTotalLength
+        MSB(CONFIG_DESC_SIZE),
+        NUM_INTERFACE,                          // bNumInterfaces
+        1,                                      // bConfigurationValue
+        0,                                      // iConfiguration
+        0xC0,                                   // bmAttributes
+        50,                                     // bMaxPower
+
+#ifdef CDC_IAD_DESCRIPTOR
+        // interface association descriptor, USB ECN, Table 9-Z
+        8,                                      // bLength
+        11,                                     // bDescriptorType
+        CDC_STATUS_INTERFACE,                   // bFirstInterface
+        2,                                      // bInterfaceCount
+        0x02,                                   // bFunctionClass
+        0x02,                                   // bFunctionSubClass
+        0x01,                                   // bFunctionProtocol
+        4,                                      // iFunction
+#endif
+
+#ifdef CDC_DATA_INTERFACE
+        // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12
+        9,                                      // bLength
+        4,                                      // bDescriptorType
+        CDC_STATUS_INTERFACE,                  // bInterfaceNumber
+        0,                                      // bAlternateSetting
+        1,                                      // bNumEndpoints
+        0x02,                                   // bInterfaceClass
+        0x02,                                   // bInterfaceSubClass
+        0x01,                                   // bInterfaceProtocol
+        0,                                      // iInterface
+        // CDC Header Functional Descriptor, CDC Spec 5.2.3.1, Table 26
+        5,                                      // bFunctionLength
+        0x24,                                   // bDescriptorType
+        0x00,                                   // bDescriptorSubtype
+        0x10, 0x01,                             // bcdCDC
+        // Call Management Functional Descriptor, CDC Spec 5.2.3.2, Table 27
+        5,                                      // bFunctionLength
+        0x24,                                   // bDescriptorType
+        0x01,                                   // bDescriptorSubtype
+        0x01,                                   // bmCapabilities
+        1,                                      // bDataInterface
+        // Abstract Control Management Functional Descriptor, CDC Spec 5.2.3.3, Table 28
+        4,                                      // bFunctionLength
+        0x24,                                   // bDescriptorType
+        0x02,                                   // bDescriptorSubtype
+        0x06,                                   // bmCapabilities
+        // Union Functional Descriptor, CDC Spec 5.2.3.8, Table 33
+        5,                                      // bFunctionLength
+        0x24,                                   // bDescriptorType
+        0x06,                                   // bDescriptorSubtype
+        CDC_STATUS_INTERFACE,                   // bMasterInterface
+        CDC_DATA_INTERFACE,                     // bSlaveInterface0
+        // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+        7,                                      // bLength
+        5,                                      // bDescriptorType
+        CDC_ACM_ENDPOINT | 0x80,                // bEndpointAddress
+        0x03,                                   // bmAttributes (0x03=intr)
+        CDC_ACM_SIZE, 0,                        // wMaxPacketSize
+        64,                                     // bInterval
+        // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12
+        9,                                      // bLength
+        4,                                      // bDescriptorType
+        CDC_DATA_INTERFACE,                     // bInterfaceNumber
+        0,                                      // bAlternateSetting
+        2,                                      // bNumEndpoints
+        0x0A,                                   // bInterfaceClass
+        0x00,                                   // bInterfaceSubClass
+        0x00,                                   // bInterfaceProtocol
+        0,                                      // iInterface
+        // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+        7,                                      // bLength
+        5,                                      // bDescriptorType
+        CDC_RX_ENDPOINT,                        // bEndpointAddress
+        0x02,                                   // bmAttributes (0x02=bulk)
+        CDC_RX_SIZE, 0,                         // wMaxPacketSize
+        0,                                      // bInterval
+        // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+        7,                                      // bLength
+        5,                                      // bDescriptorType
+        CDC_TX_ENDPOINT | 0x80,                 // bEndpointAddress
+        0x02,                                   // bmAttributes (0x02=bulk)
+        CDC_TX_SIZE, 0,                         // wMaxPacketSize
+        0,                                      // bInterval
+#endif // CDC_DATA_INTERFACE
+
+#ifdef KEYBOARD_INTERFACE
+        // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12
+        9,                                      // bLength
+        4,                                      // bDescriptorType
+        KEYBOARD_INTERFACE,                     // bInterfaceNumber
+        0,                                      // bAlternateSetting
+        1,                                      // bNumEndpoints
+        0x03,                                   // bInterfaceClass (0x03 = HID)
+        0x01,                                   // bInterfaceSubClass (0x01 = Boot)
+        0x01,                                   // bInterfaceProtocol (0x01 = Keyboard)
+        0,                                      // iInterface
+        // HID interface descriptor, HID 1.11 spec, section 6.2.1
+        9,                                      // bLength
+        0x21,                                   // bDescriptorType
+        0x11, 0x01,                             // bcdHID
+        0,                                      // bCountryCode
+        1,                                      // bNumDescriptors
+        0x22,                                   // bDescriptorType
+        LSB(sizeof(keyboard_report_desc)),      // wDescriptorLength
+        MSB(sizeof(keyboard_report_desc)),
+        // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+        7,                                      // bLength
+        5,                                      // bDescriptorType
+        KEYBOARD_ENDPOINT | 0x80,               // bEndpointAddress
+        0x03,                                   // bmAttributes (0x03=intr)
+        KEYBOARD_SIZE, 0,                       // wMaxPacketSize
+        KEYBOARD_INTERVAL,                      // bInterval
+#endif // KEYBOARD_INTERFACE
+
+#ifdef MOUSE_INTERFACE
+        // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12
+        9,                                      // bLength
+        4,                                      // bDescriptorType
+        MOUSE_INTERFACE,                        // bInterfaceNumber
+        0,                                      // bAlternateSetting
+        1,                                      // bNumEndpoints
+        0x03,                                   // bInterfaceClass (0x03 = HID)
+        0x01,                                   // bInterfaceSubClass (0x01 = Boot)
+        0x02,                                   // bInterfaceProtocol (0x02 = Mouse)
+        0,                                      // iInterface
+        // HID interface descriptor, HID 1.11 spec, section 6.2.1
+        9,                                      // bLength
+        0x21,                                   // bDescriptorType
+        0x11, 0x01,                             // bcdHID
+        0,                                      // bCountryCode
+        1,                                      // bNumDescriptors
+        0x22,                                   // bDescriptorType
+        LSB(sizeof(mouse_report_desc)),         // wDescriptorLength
+        MSB(sizeof(mouse_report_desc)),
+        // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+        7,                                      // bLength
+        5,                                      // bDescriptorType
+        MOUSE_ENDPOINT | 0x80,                  // bEndpointAddress
+        0x03,                                   // bmAttributes (0x03=intr)
+        MOUSE_SIZE, 0,                          // wMaxPacketSize
+        MOUSE_INTERVAL,                         // bInterval
+#endif // MOUSE_INTERFACE
+
+#ifdef JOYSTICK_INTERFACE
+        // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12
+        9,                                      // bLength
+        4,                                      // bDescriptorType
+        JOYSTICK_INTERFACE,                     // bInterfaceNumber
+        0,                                      // bAlternateSetting
+        1,                                      // bNumEndpoints
+        0x03,                                   // bInterfaceClass (0x03 = HID)
+        0x00,                                   // bInterfaceSubClass
+        0x00,                                   // bInterfaceProtocol
+        0,                                      // iInterface
+        // HID interface descriptor, HID 1.11 spec, section 6.2.1
+        9,                                      // bLength
+        0x21,                                   // bDescriptorType
+        0x11, 0x01,                             // bcdHID
+        0,                                      // bCountryCode
+        1,                                      // bNumDescriptors
+        0x22,                                   // bDescriptorType
+        LSB(sizeof(joystick_report_desc)),      // wDescriptorLength
+        MSB(sizeof(joystick_report_desc)),
+        // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+        7,                                      // bLength
+        5,                                      // bDescriptorType
+        JOYSTICK_ENDPOINT | 0x80,               // bEndpointAddress
+        0x03,                                   // bmAttributes (0x03=intr)
+        JOYSTICK_SIZE, 0,                       // wMaxPacketSize
+        JOYSTICK_INTERVAL,                      // bInterval
+#endif
+};
+
+
+
+// **************************************************************
+//   String Descriptors
+// **************************************************************
+
+// The descriptors above can provide human readable strings,
+// referenced by index numbers.  These descriptors are the
+// actual string data
+
+struct usb_string_descriptor_struct {
+        uint8_t bLength;
+        uint8_t bDescriptorType;
+        uint16_t wString[];
+};
+
+static struct usb_string_descriptor_struct string0 = {
+        4,
+        3,
+        {0x0409}
+};
+
+static struct usb_string_descriptor_struct string1 = {
+        2 + MANUFACTURER_NAME_LEN * 2,
+        3,
+        MANUFACTURER_NAME
+};
+static struct usb_string_descriptor_struct string2 = {
+       2 + PRODUCT_NAME_LEN * 2,
+        3,
+        PRODUCT_NAME
+};
+static struct usb_string_descriptor_struct string3 = {
+        12,
+        3,
+        {'1','2','3','4','5'}
+};
+
+
+// **************************************************************
+//   Descriptors List
+// **************************************************************
+
+// This table provides access to all the descriptor data above.
+
+const usb_descriptor_list_t usb_descriptor_list[] = {
+       //wValue, wIndex, address,          length
+       {0x0100, 0x0000, device_descriptor, sizeof(device_descriptor)},
+       {0x0200, 0x0000, config_descriptor, sizeof(config_descriptor)},
+#ifdef KEYBOARD_INTERFACE
+        {0x2200, KEYBOARD_INTERFACE, keyboard_report_desc, sizeof(keyboard_report_desc)},
+        {0x2100, KEYBOARD_INTERFACE, config_descriptor+KEYBOARD_DESC_OFFSET, 9},
+#endif
+#ifdef MOUSE_INTERFACE
+        {0x2200, MOUSE_INTERFACE, mouse_report_desc, sizeof(mouse_report_desc)},
+        {0x2100, MOUSE_INTERFACE, config_descriptor+MOUSE_DESC_OFFSET, 9},
+#endif
+#ifdef JOYSTICK_INTERFACE
+        {0x2200, JOYSTICK_INTERFACE, joystick_report_desc, sizeof(joystick_report_desc)},
+        {0x2100, JOYSTICK_INTERFACE, config_descriptor+JOYSTICK_DESC_OFFSET, 9},
+#endif
+        {0x0300, 0x0000, (const uint8_t *)&string0, 4},
+        {0x0301, 0x0409, (const uint8_t *)&string1, 2 + MANUFACTURER_NAME_LEN * 2},
+        {0x0302, 0x0409, (const uint8_t *)&string2, 2 + PRODUCT_NAME_LEN * 2},
+        {0x0303, 0x0409, (const uint8_t *)&string3, 12},
+       {0, 0, NULL, 0}
+};
+
+
+// **************************************************************
+//   Endpoint Configuration
+// **************************************************************
+
+#if 0
+// 0x00 = not used
+// 0x19 = Recieve only
+// 0x15 = Transmit only
+// 0x1D = Transmit & Recieve
+// 
+const uint8_t usb_endpoint_config_table[NUM_ENDPOINTS] = 
+{
+       0x00, 0x15, 0x19, 0x15, 0x00, 0x00, 0x00, 0x00, 
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+};
+#endif
+
+
+const uint8_t usb_endpoint_config_table[NUM_ENDPOINTS] = 
+{
+#if (defined(ENDPOINT1_CONFIG) && NUM_ENDPOINTS >= 1)
+       ENDPOINT1_CONFIG,
+#elif (NUM_ENDPOINTS >= 1)
+       ENDPOINT_UNUSED,
+#endif
+#if (defined(ENDPOINT2_CONFIG) && NUM_ENDPOINTS >= 2)
+       ENDPOINT2_CONFIG,
+#elif (NUM_ENDPOINTS >= 2)
+       ENDPOINT_UNUSED,
+#endif
+#if (defined(ENDPOINT3_CONFIG) && NUM_ENDPOINTS >= 3)
+       ENDPOINT3_CONFIG,
+#elif (NUM_ENDPOINTS >= 3)
+       ENDPOINT_UNUSED,
+#endif
+#if (defined(ENDPOINT4_CONFIG) && NUM_ENDPOINTS >= 4)
+       ENDPOINT4_CONFIG,
+#elif (NUM_ENDPOINTS >= 4)
+       ENDPOINT_UNUSED,
+#endif
+#if (defined(ENDPOINT5_CONFIG) && NUM_ENDPOINTS >= 5)
+       ENDPOINT5_CONFIG,
+#elif (NUM_ENDPOINTS >= 5)
+       ENDPOINT_UNUSED,
+#endif
+#if (defined(ENDPOINT6_CONFIG) && NUM_ENDPOINTS >= 6)
+       ENDPOINT6_CONFIG,
+#elif (NUM_ENDPOINTS >= 6)
+       ENDPOINT_UNUSED,
+#endif
+#if (defined(ENDPOINT7_CONFIG) && NUM_ENDPOINTS >= 7)
+       ENDPOINT7_CONFIG,
+#elif (NUM_ENDPOINTS >= 7)
+       ENDPOINT_UNUSED,
+#endif
+#if (defined(ENDPOINT8_CONFIG) && NUM_ENDPOINTS >= 8)
+       ENDPOINT8_CONFIG,
+#elif (NUM_ENDPOINTS >= 8)
+       ENDPOINT_UNUSED,
+#endif
+#if (defined(ENDPOINT9_CONFIG) && NUM_ENDPOINTS >= 9)
+       ENDPOINT9_CONFIG,
+#elif (NUM_ENDPOINTS >= 9)
+       ENDPOINT_UNUSED,
+#endif
+#if (defined(ENDPOINT10_CONFIG) && NUM_ENDPOINTS >= 10)
+       ENDPOINT10_CONFIG,
+#elif (NUM_ENDPOINTS >= 10)
+       ENDPOINT_UNUSED,
+#endif
+#if (defined(ENDPOINT11_CONFIG) && NUM_ENDPOINTS >= 11)
+       ENDPOINT11_CONFIG,
+#elif (NUM_ENDPOINTS >= 11)
+       ENDPOINT_UNUSED,
+#endif
+#if (defined(ENDPOINT12_CONFIG) && NUM_ENDPOINTS >= 12)
+       ENDPOINT12_CONFIG,
+#elif (NUM_ENDPOINTS >= 12)
+       ENDPOINT_UNUSED,
+#endif
+#if (defined(ENDPOINT13_CONFIG) && NUM_ENDPOINTS >= 13)
+       ENDPOINT13_CONFIG,
+#elif (NUM_ENDPOINTS >= 13)
+       ENDPOINT_UNUSED,
+#endif
+#if (defined(ENDPOINT14_CONFIG) && NUM_ENDPOINTS >= 14)
+       ENDPOINT14_CONFIG,
+#elif (NUM_ENDPOINTS >= 14)
+       ENDPOINT_UNUSED,
+#endif
+#if (defined(ENDPOINT15_CONFIG) && NUM_ENDPOINTS >= 15)
+       ENDPOINT15_CONFIG,
+#elif (NUM_ENDPOINTS >= 15)
+       ENDPOINT_UNUSED,
+#endif
+};
+
+
+
+
diff --git a/USB/pjrc/arm/usb_desc.h b/USB/pjrc/arm/usb_desc.h
new file mode 100644 (file)
index 0000000..a45ea76
--- /dev/null
@@ -0,0 +1,80 @@
+#ifndef _usb_desc_h_
+#define _usb_desc_h_
+
+// This header is NOT meant to be included when compiling
+// user sketches in Arduino.  The low-level functions
+// provided by usb_dev.c are meant to be called only by
+// code which provides higher-level interfaces to the user.
+
+#include <stdint.h>
+#include <stddef.h>
+#include "usb_com.h"
+
+#define ENDPOINT_UNUSED                        0x00
+#define ENDPOINT_TRANSIMIT_ONLY                0x15
+#define ENDPOINT_RECEIVE_ONLY          0x19
+#define ENDPOINT_TRANSMIT_AND_RECEIVE  0x1D
+
+// Some operating systems, especially Windows, may cache USB device
+// info.  Changes to the device name may not update on the same
+// computer unless the vendor or product ID numbers change, or the
+// "bcdDevice" revision code is increased.
+
+#define DEVICE_CLASS           0xEF
+#define DEVICE_SUBCLASS        0x02
+#define DEVICE_PROTOCOL        0x01
+#define MANUFACTURER_NAME      {'T','e','e','n','s','y','d','u','i','n','o'}
+#define MANUFACTURER_NAME_LEN  11
+#define PRODUCT_NAME           {'S','e','r','i','a','l','/','K','e','y','b','o','a','r','d','/','M','o','u','s','e','/','J','o','y','s','t','i','c','k'}
+#define PRODUCT_NAME_LEN       30
+#define EP0_SIZE               64
+#define NUM_ENDPOINTS          15
+#define NUM_INTERFACE          5
+#define CDC_IAD_DESCRIPTOR     1
+#define CDC_STATUS_INTERFACE   0
+#define CDC_DATA_INTERFACE     1       // Serial
+#define CDC_ACM_ENDPOINT       2
+#define CDC_RX_ENDPOINT       3
+#define CDC_TX_ENDPOINT       4
+#define CDC_ACM_SIZE          16
+#define CDC_RX_SIZE           64
+#define CDC_TX_SIZE           64
+#define KEYBOARD_INTERFACE    2        // Keyboard
+#define KEYBOARD_ENDPOINT     1
+#define KEYBOARD_SIZE         8
+#define KEYBOARD_INTERVAL     1
+#define MOUSE_INTERFACE       3        // Mouse
+#define MOUSE_ENDPOINT        5
+#define MOUSE_SIZE            8
+#define MOUSE_INTERVAL        2
+#define JOYSTICK_INTERFACE    4        // Joystick
+#define JOYSTICK_ENDPOINT     6
+#define JOYSTICK_SIZE         16
+#define JOYSTICK_INTERVAL     1
+#define KEYBOARD_DESC_OFFSET   (9+8 + 9+5+5+4+5+7+9+7+7 + 9)
+#define MOUSE_DESC_OFFSET      (9+8 + 9+5+5+4+5+7+9+7+7 + 9+9+7 + 9)
+#define JOYSTICK_DESC_OFFSET   (9+8 + 9+5+5+4+5+7+9+7+7 + 9+9+7 + 9+9+7 + 9)
+#define CONFIG_DESC_SIZE       (9+8 + 9+5+5+4+5+7+9+7+7 + 9+9+7 + 9+9+7 + 9+9+7)
+#define ENDPOINT1_CONFIG       ENDPOINT_TRANSIMIT_ONLY
+#define ENDPOINT2_CONFIG       ENDPOINT_TRANSIMIT_ONLY
+#define ENDPOINT3_CONFIG       ENDPOINT_RECEIVE_ONLY
+#define ENDPOINT4_CONFIG       ENDPOINT_TRANSIMIT_ONLY
+#define ENDPOINT5_CONFIG       ENDPOINT_TRANSIMIT_ONLY
+#define ENDPOINT6_CONFIG       ENDPOINT_TRANSIMIT_ONLY
+
+
+
+// NUM_ENDPOINTS = number of non-zero endpoints (0 to 15)
+extern const uint8_t usb_endpoint_config_table[NUM_ENDPOINTS];
+
+typedef struct {
+       uint16_t        wValue;
+       uint16_t        wIndex;
+       const uint8_t   *addr;
+       uint16_t        length;
+} usb_descriptor_list_t;
+
+extern const usb_descriptor_list_t usb_descriptor_list[];
+
+
+#endif
diff --git a/USB/pjrc/arm/usb_dev.c b/USB/pjrc/arm/usb_dev.c
new file mode 100644 (file)
index 0000000..7974636
--- /dev/null
@@ -0,0 +1,867 @@
+#include <Lib/USBLib.h>
+#include "usb_dev.h"
+#include "usb_mem.h"
+
+// buffer descriptor table
+
+typedef struct {
+       uint32_t desc;
+       void * addr;
+} bdt_t;
+
+__attribute__ ((section(".usbdescriptortable"), used))
+static bdt_t table[64];
+
+#define BDT_OWN                0x80
+#define BDT_DATA1      0x40
+#define BDT_DATA0      0x00
+#define BDT_DTS                0x08
+#define BDT_STALL      0x04
+#define BDT_PID(n)     (((n) >> 2) & 15)
+
+#define BDT_DESC(count, data)  (BDT_OWN | BDT_DTS \
+                               | ((data) ? BDT_DATA1 : BDT_DATA0) \
+                               | ((count) << 16))
+
+#define TX   1
+#define RX   0
+#define ODD  1
+#define EVEN 0
+#define DATA0 0
+#define DATA1 1
+#define index(endpoint, tx, odd) (((endpoint) << 2) | ((tx) << 1) | (odd))
+#define stat2bufferdescriptor(stat) (table + ((stat) >> 2))
+
+
+static union {
+ struct {
+  union {
+   struct {
+       uint8_t bmRequestType;
+       uint8_t bRequest;
+   };
+       uint16_t wRequestAndType;
+  };
+       uint16_t wValue;
+       uint16_t wIndex;
+       uint16_t wLength;
+ };
+ struct {
+       uint32_t word1;
+       uint32_t word2;
+ };
+} setup;
+
+
+#define GET_STATUS             0
+#define CLEAR_FEATURE          1
+#define SET_FEATURE            3
+#define SET_ADDRESS            5
+#define GET_DESCRIPTOR         6
+#define SET_DESCRIPTOR         7
+#define GET_CONFIGURATION      8
+#define SET_CONFIGURATION      9
+#define GET_INTERFACE          10
+#define SET_INTERFACE          11
+#define SYNCH_FRAME            12
+
+// SETUP always uses a DATA0 PID for the data field of the SETUP transaction.
+// transactions in the data phase start with DATA1 and toggle (figure 8-12, USB1.1)
+// Status stage uses a DATA1 PID.
+
+static uint8_t ep0_rx0_buf[EP0_SIZE] __attribute__ ((aligned (4)));
+static uint8_t ep0_rx1_buf[EP0_SIZE] __attribute__ ((aligned (4)));
+static const uint8_t *ep0_tx_ptr = NULL;
+static uint16_t ep0_tx_len;
+static uint8_t ep0_tx_bdt_bank = 0;
+static uint8_t ep0_tx_data_toggle = 0;
+uint8_t usb_rx_memory_needed = 0;
+
+volatile uint8_t usb_configuration = 0;
+volatile uint8_t usb_reboot_timer = 0;
+
+
+static void endpoint0_stall(void)
+{
+       USB0_ENDPT0 = USB_ENDPT_EPSTALL | USB_ENDPT_EPRXEN | USB_ENDPT_EPTXEN | USB_ENDPT_EPHSHK;
+}
+
+
+static void endpoint0_transmit(const void *data, uint32_t len)
+{
+#if 0
+       serial_print("tx0:");
+       serial_phex32((uint32_t)data);
+       serial_print(",");
+       serial_phex16(len);
+       serial_print(ep0_tx_bdt_bank ? ", odd" : ", even");
+       serial_print(ep0_tx_data_toggle ? ", d1\n" : ", d0\n");
+#endif
+       table[index(0, TX, ep0_tx_bdt_bank)].addr = (void *)data;
+       table[index(0, TX, ep0_tx_bdt_bank)].desc = BDT_DESC(len, ep0_tx_data_toggle);
+       ep0_tx_data_toggle ^= 1;
+       ep0_tx_bdt_bank ^= 1;
+}
+
+static uint8_t reply_buffer[8];
+
+static void usbdev_setup(void)
+{
+       const uint8_t *data = NULL;
+       uint32_t datalen = 0;
+       const usb_descriptor_list_t *list;
+       uint32_t size;
+       volatile uint8_t *reg;
+       uint8_t epconf;
+       const uint8_t *cfg;
+       int i;
+
+       switch (setup.wRequestAndType) {
+         case 0x0500: // SET_ADDRESS
+               break;
+         case 0x0900: // SET_CONFIGURATION
+               //serial_print("configure\n");
+               usb_configuration = setup.wValue;
+               reg = &USB0_ENDPT1;
+               cfg = usb_endpoint_config_table;
+               // clear all BDT entries, free any allocated memory...
+               for (i=4; i <= NUM_ENDPOINTS*4; i++) {
+                       if (table[i].desc & BDT_OWN) {
+                               usb_free((usb_packet_t *)((uint8_t *)(table[i].addr) - 8));
+                               table[i].desc = 0;
+                       }
+               }
+               usb_rx_memory_needed = 0;
+               for (i=1; i <= NUM_ENDPOINTS; i++) {
+                       epconf = *cfg++;
+                       *reg = epconf;
+                       reg += 4;
+                       if (epconf & USB_ENDPT_EPRXEN) {
+                               usb_packet_t *p;
+                               p = usb_malloc();
+                               if (p) {
+                                       table[index(i, RX, EVEN)].addr = p->buf;
+                                       table[index(i, RX, EVEN)].desc = BDT_DESC(64, 0);
+                               } else {
+                                       table[index(i, RX, EVEN)].desc = 0;
+                                       usb_rx_memory_needed++;
+                               }
+                               p = usb_malloc();
+                               if (p) {
+                                       table[index(i, RX, ODD)].addr = p->buf;
+                                       table[index(i, RX, ODD)].desc = BDT_DESC(64, 1);
+                               } else {
+                                       table[index(i, RX, ODD)].desc = 0;
+                                       usb_rx_memory_needed++;
+                               }
+                       }
+                       table[index(i, TX, EVEN)].desc = 0;
+                       table[index(i, TX, ODD)].desc = 0;
+               }
+               break;
+         case 0x0880: // GET_CONFIGURATION
+               reply_buffer[0] = usb_configuration;
+               datalen = 1;
+               data = reply_buffer;
+               break;
+         case 0x0080: // GET_STATUS (device)
+               reply_buffer[0] = 0;
+               reply_buffer[1] = 0;
+               datalen = 2;
+               data = reply_buffer;
+               break;
+         case 0x0082: // GET_STATUS (endpoint)
+               if (setup.wIndex > NUM_ENDPOINTS) {
+                       // TODO: do we need to handle IN vs OUT here?
+                       endpoint0_stall();
+                       return;
+               }
+               reply_buffer[0] = 0;
+               reply_buffer[1] = 0;
+               if (*(uint8_t *)(&USB0_ENDPT0 + setup.wIndex * 4) & 0x02) reply_buffer[0] = 1;
+               data = reply_buffer;
+               datalen = 2;
+               break;
+         case 0x0102: // CLEAR_FEATURE (endpoint)
+               i = setup.wIndex & 0x7F;
+               if (i > NUM_ENDPOINTS || setup.wValue != 0) {
+                       // TODO: do we need to handle IN vs OUT here?
+                       endpoint0_stall();
+                       return;
+               }
+               (*(uint8_t *)(&USB0_ENDPT0 + setup.wIndex * 4)) &= ~0x02;
+               // TODO: do we need to clear the data toggle here?
+               break;
+         case 0x0302: // SET_FEATURE (endpoint)
+               i = setup.wIndex & 0x7F;
+               if (i > NUM_ENDPOINTS || setup.wValue != 0) {
+                       // TODO: do we need to handle IN vs OUT here?
+                       endpoint0_stall();
+                       return;
+               }
+               (*(uint8_t *)(&USB0_ENDPT0 + setup.wIndex * 4)) |= 0x02;
+               // TODO: do we need to clear the data toggle here?
+               break;
+         case 0x0680: // GET_DESCRIPTOR
+         case 0x0681:
+               //serial_print("desc:");
+               //serial_phex16(setup.wValue);
+               //serial_print("\n");
+               for (list = usb_descriptor_list; 1; list++) {
+                       if (list->addr == NULL) break;
+                       //if (setup.wValue == list->wValue && 
+                       //(setup.wIndex == list->wIndex) || ((setup.wValue >> 8) == 3)) {
+                       if (setup.wValue == list->wValue && setup.wIndex == list->wIndex) {
+                               data = list->addr;
+                               datalen = list->length;
+#if 0
+                               serial_print("Desc found, ");
+                               serial_phex32((uint32_t)data);
+                               serial_print(",");
+                               serial_phex16(datalen);
+                               serial_print(",");
+                               serial_phex(data[0]);
+                               serial_phex(data[1]);
+                               serial_phex(data[2]);
+                               serial_phex(data[3]);
+                               serial_phex(data[4]);
+                               serial_phex(data[5]);
+                               serial_print("\n");
+#endif
+                               goto send;
+                       }
+               }
+               //serial_print("desc: not found\n");
+               endpoint0_stall();
+               return;
+#if defined(CDC_STATUS_INTERFACE)
+         case 0x2221: // CDC_SET_CONTROL_LINE_STATE
+               usb_cdc_line_rtsdtr = setup.wValue;
+               //serial_print("set control line state\n");
+               break;
+         case 0x2021: // CDC_SET_LINE_CODING
+               //serial_print("set coding, waiting...\n");
+               return;
+#endif
+
+// TODO: this does not work... why?
+#if defined(SEREMU_INTERFACE) || defined(KEYBOARD_INTERFACE)
+         case 0x0921: // HID SET_REPORT
+               //serial_print(":)\n");
+               return;
+         case 0x0A21: // HID SET_IDLE
+               break;
+         // case 0xC940:
+#endif
+         default:
+               endpoint0_stall();
+               return;
+       }
+       send:
+       //serial_print("setup send ");
+       //serial_phex32(data);
+       //serial_print(",");
+       //serial_phex16(datalen);
+       //serial_print("\n");
+
+       if (datalen > setup.wLength) datalen = setup.wLength;
+       size = datalen;
+       if (size > EP0_SIZE) size = EP0_SIZE;
+       endpoint0_transmit(data, size);
+       data += size;
+       datalen -= size;
+       if (datalen == 0 && size < EP0_SIZE) return;
+
+       size = datalen;
+       if (size > EP0_SIZE) size = EP0_SIZE;
+       endpoint0_transmit(data, size);
+       data += size;
+       datalen -= size;
+       if (datalen == 0 && size < EP0_SIZE) return;
+
+       ep0_tx_ptr = data;
+       ep0_tx_len = datalen;
+}
+
+
+
+//A bulk endpoint's toggle sequence is initialized to DATA0 when the endpoint
+//experiences any configuration event (configuration events are explained in
+//Sections 9.1.1.5 and 9.4.5).
+
+//Configuring a device or changing an alternate setting causes all of the status
+//and configuration values associated with endpoints in the affected interfaces
+//to be set to their default values. This includes setting the data toggle of
+//any endpoint using data toggles to the value DATA0.
+
+//For endpoints using data toggle, regardless of whether an endpoint has the
+//Halt feature set, a ClearFeature(ENDPOINT_HALT) request always results in the
+//data toggle being reinitialized to DATA0.
+
+
+
+// #define stat2bufferdescriptor(stat) (table + ((stat) >> 2))
+
+static void usb_control(uint32_t stat)
+{
+       bdt_t *b;
+       uint32_t pid, size;
+       uint8_t *buf;
+       const uint8_t *data;
+
+       b = stat2bufferdescriptor(stat);
+       pid = BDT_PID(b->desc);
+       //count = b->desc >> 16;
+       buf = b->addr;
+       //serial_print("pid:");
+       //serial_phex(pid);
+       //serial_print(", count:");
+       //serial_phex(count);
+       //serial_print("\n");
+
+       switch (pid) {
+       case 0x0D: // Setup received from host
+               //serial_print("PID=Setup\n");
+               //if (count != 8) ; // panic?
+               // grab the 8 byte setup info
+               setup.word1 = *(uint32_t *)(buf);
+               setup.word2 = *(uint32_t *)(buf + 4);
+
+               // give the buffer back
+               b->desc = BDT_DESC(EP0_SIZE, DATA1);
+               //table[index(0, RX, EVEN)].desc = BDT_DESC(EP0_SIZE, 1);
+               //table[index(0, RX, ODD)].desc = BDT_DESC(EP0_SIZE, 1);
+
+               // clear any leftover pending IN transactions
+               ep0_tx_ptr = NULL;
+               if (ep0_tx_data_toggle) {
+               }
+               //if (table[index(0, TX, EVEN)].desc & 0x80) {
+                       //serial_print("leftover tx even\n");
+               //}
+               //if (table[index(0, TX, ODD)].desc & 0x80) {
+                       //serial_print("leftover tx odd\n");
+               //}
+               table[index(0, TX, EVEN)].desc = 0;
+               table[index(0, TX, ODD)].desc = 0;
+               // first IN after Setup is always DATA1
+               ep0_tx_data_toggle = 1;
+
+#if 0
+               serial_print("bmRequestType:");
+               serial_phex(setup.bmRequestType);
+               serial_print(", bRequest:");
+               serial_phex(setup.bRequest);
+               serial_print(", wValue:");
+               serial_phex16(setup.wValue);
+               serial_print(", wIndex:");
+               serial_phex16(setup.wIndex);
+               serial_print(", len:");
+               serial_phex16(setup.wLength);
+               serial_print("\n");
+#endif
+               // actually "do" the setup request
+               usbdev_setup();
+               // unfreeze the USB, now that we're ready
+               USB0_CTL = USB_CTL_USBENSOFEN; // clear TXSUSPENDTOKENBUSY bit
+               break;
+       case 0x01:  // OUT transaction received from host
+       case 0x02:
+               //serial_print("PID=OUT\n");
+#ifdef CDC_STATUS_INTERFACE
+               if (setup.wRequestAndType == 0x2021 /*CDC_SET_LINE_CODING*/) {
+                       int i;
+                       uint8_t *dst = usb_cdc_line_coding;
+                       //serial_print("set line coding ");
+                       for (i=0; i<7; i++) {
+                               //serial_phex(*buf);
+                               *dst++ = *buf++;
+                       }
+                       //serial_phex32(*(uint32_t *)usb_cdc_line_coding);
+                       //serial_print("\n");
+                       // TODO - Fix this warning
+                       if (*(uint32_t *)usb_cdc_line_coding == 134) usb_reboot_timer = 15;
+                       endpoint0_transmit(NULL, 0);
+               }
+#endif
+#ifdef KEYBOARD_INTERFACE
+               if (setup.word1 == 0x02000921 && setup.word2 == ((1<<16)|KEYBOARD_INTERFACE)) {
+                       USBKeys_LEDs = buf[0];
+                       endpoint0_transmit(NULL, 0);
+               }
+#endif
+               // give the buffer back
+               b->desc = BDT_DESC(EP0_SIZE, DATA1);
+               break;
+
+       case 0x09: // IN transaction completed to host
+               //serial_print("PID=IN:");
+               //serial_phex(stat);
+               //serial_print("\n");
+
+               // send remaining data, if any...
+               data = ep0_tx_ptr;
+               if (data) {
+                       size = ep0_tx_len;
+                       if (size > EP0_SIZE) size = EP0_SIZE;
+                       endpoint0_transmit(data, size);
+                       data += size;
+                       ep0_tx_len -= size;
+                       ep0_tx_ptr = (ep0_tx_len > 0 || size == EP0_SIZE) ? data : NULL;
+               }
+
+               if (setup.bRequest == 5 && setup.bmRequestType == 0) {
+                       setup.bRequest = 0;
+                       //serial_print("set address: ");
+                       //serial_phex16(setup.wValue);
+                       //serial_print("\n");
+                       USB0_ADDR = setup.wValue;
+               }
+
+               break;
+       //default:
+               //serial_print("PID=unknown:");
+               //serial_phex(pid);
+               //serial_print("\n");
+       }
+       USB0_CTL = USB_CTL_USBENSOFEN; // clear TXSUSPENDTOKENBUSY bit
+}
+
+
+
+static usb_packet_t *rx_first[NUM_ENDPOINTS];
+static usb_packet_t *rx_last[NUM_ENDPOINTS];
+static usb_packet_t *tx_first[NUM_ENDPOINTS];
+static usb_packet_t *tx_last[NUM_ENDPOINTS];
+
+static uint8_t tx_state[NUM_ENDPOINTS];
+#define TX_STATE_BOTH_FREE_EVEN_FIRST  0
+#define TX_STATE_BOTH_FREE_ODD_FIRST   1
+#define TX_STATE_EVEN_FREE             2
+#define TX_STATE_ODD_FREE              3
+#define TX_STATE_NONE_FREE             4
+
+
+
+usb_packet_t *usb_rx(uint32_t endpoint)
+{
+       usb_packet_t *ret;
+       endpoint--;
+       if (endpoint >= NUM_ENDPOINTS) return NULL;
+       __disable_irq();
+       ret = rx_first[endpoint];
+       if (ret) rx_first[endpoint] = ret->next;
+       __enable_irq();
+       //serial_print("rx, epidx=");
+       //serial_phex(endpoint);
+       //serial_print(", packet=");
+       //serial_phex32(ret);
+       //serial_print("\n");
+       return ret;
+}
+
+static uint32_t usb_queue_byte_count(const usb_packet_t *p)
+{
+       uint32_t count=0;
+
+       __disable_irq();
+       for ( ; p; p = p->next) {
+               count += p->len;
+       }
+       __enable_irq();
+       return count;
+}
+
+uint32_t usb_rx_byte_count(uint32_t endpoint)
+{
+       endpoint--;
+       if (endpoint >= NUM_ENDPOINTS) return 0;
+       return usb_queue_byte_count(rx_first[endpoint]);
+}
+
+uint32_t usb_tx_byte_count(uint32_t endpoint)
+{
+       endpoint--;
+       if (endpoint >= NUM_ENDPOINTS) return 0;
+       return usb_queue_byte_count(tx_first[endpoint]);
+}
+
+uint32_t usb_tx_packet_count(uint32_t endpoint)
+{
+       const usb_packet_t *p;
+       uint32_t count=0;
+
+       endpoint--;
+       if (endpoint >= NUM_ENDPOINTS) return 0;
+       p = tx_first[endpoint];
+       __disable_irq();
+       for ( ; p; p = p->next) count++;
+       __enable_irq();
+       return count;
+}
+
+
+// Called from usb_free, but only when usb_rx_memory_needed > 0, indicating
+// receive endpoints are starving for memory.  The intention is to give
+// endpoints needing receive memory priority over the user's code, which is
+// likely calling usb_malloc to obtain memory for transmitting.  When the
+// user is creating data very quickly, their consumption could starve reception
+// without this prioritization.  The packet buffer (input) is assigned to the
+// first endpoint needing memory.
+//
+void usb_rx_memory(usb_packet_t *packet)
+{
+       unsigned int i;
+       const uint8_t *cfg;
+
+       cfg = usb_endpoint_config_table;
+       //serial_print("rx_mem:");
+       __disable_irq();
+       for (i=1; i <= NUM_ENDPOINTS; i++) {
+               if (*cfg++ & USB_ENDPT_EPRXEN) {
+                       if (table[index(i, RX, EVEN)].desc == 0) {
+                               table[index(i, RX, EVEN)].addr = packet->buf;
+                               table[index(i, RX, EVEN)].desc = BDT_DESC(64, 0);
+                               usb_rx_memory_needed--;
+                               __enable_irq();
+                               //serial_phex(i);
+                               //serial_print(",even\n");
+                               return;
+                       }
+                       if (table[index(i, RX, ODD)].desc == 0) {
+                               table[index(i, RX, ODD)].addr = packet->buf;
+                               table[index(i, RX, ODD)].desc = BDT_DESC(64, 1);
+                               usb_rx_memory_needed--;
+                               __enable_irq();
+                               //serial_phex(i);
+                               //serial_print(",odd\n");
+                               return;
+                       }
+               }
+       }
+       __enable_irq();
+       // we should never reach this point.  If we get here, it means
+       // usb_rx_memory_needed was set greater than zero, but no memory
+       // was actually needed.  
+       usb_rx_memory_needed = 0;
+       usb_free(packet);
+       return;
+}
+
+//#define index(endpoint, tx, odd) (((endpoint) << 2) | ((tx) << 1) | (odd))
+//#define stat2bufferdescriptor(stat) (table + ((stat) >> 2))
+
+void usb_tx(uint32_t endpoint, usb_packet_t *packet)
+{
+       bdt_t *b = &table[index(endpoint, TX, EVEN)];
+       uint8_t next;
+
+       endpoint--;
+       if (endpoint >= NUM_ENDPOINTS) return;
+       __disable_irq();
+       //serial_print("txstate=");
+       //serial_phex(tx_state[endpoint]);
+       //serial_print("\n");
+       switch (tx_state[endpoint]) {
+         case TX_STATE_BOTH_FREE_EVEN_FIRST:
+               next = TX_STATE_ODD_FREE;
+               break;
+         case TX_STATE_BOTH_FREE_ODD_FIRST:
+               b++;
+               next = TX_STATE_EVEN_FREE;
+               break;
+         case TX_STATE_EVEN_FREE:
+               next = TX_STATE_NONE_FREE;
+               break;
+         case TX_STATE_ODD_FREE:
+               b++;
+               next = TX_STATE_NONE_FREE;
+               break;
+         default:
+               if (tx_first[endpoint] == NULL) {
+                       tx_first[endpoint] = packet;
+               } else {
+                       tx_last[endpoint]->next = packet;
+               }
+               tx_last[endpoint] = packet;
+               __enable_irq();
+               return;
+       }
+       tx_state[endpoint] = next;
+       b->addr = packet->buf;
+       b->desc = BDT_DESC(packet->len, ((uint32_t)b & 8) ? DATA1 : DATA0);
+       __enable_irq();
+}
+
+
+
+
+
+
+void _reboot_Teensyduino_(void)
+{
+       // TODO: initialize R0 with a code....
+       asm volatile("bkpt");
+}
+
+
+
+void usb_isr(void)
+{
+       uint8_t status, stat, t;
+
+       //serial_print("isr");
+       //status = USB0_ISTAT;
+       //serial_phex(status);
+       //serial_print("\n");
+       restart:
+       status = USB0_ISTAT;
+
+       if ((status & USB_INTEN_SOFTOKEN /* 04 */ )) {
+               if (usb_configuration) {
+                       t = usb_reboot_timer;
+                       if (t) {
+                               usb_reboot_timer = --t;
+                               if (!t) _reboot_Teensyduino_();
+                       }
+#ifdef CDC_DATA_INTERFACE
+                       t = usb_cdc_transmit_flush_timer;
+                       if (t) {
+                               usb_cdc_transmit_flush_timer = --t;
+                               if (t == 0) usb_serial_flush_callback();
+                       }
+#endif
+               }
+               USB0_ISTAT = USB_INTEN_SOFTOKEN;
+       }
+
+       if ((status & USB_ISTAT_TOKDNE /* 08 */ )) {
+               uint8_t endpoint;
+               stat = USB0_STAT;
+               //serial_print("token: ep=");
+               //serial_phex(stat >> 4);
+               //serial_print(stat & 0x08 ? ",tx" : ",rx");
+               //serial_print(stat & 0x04 ? ",odd\n" : ",even\n");
+               endpoint = stat >> 4;
+               if (endpoint == 0) {
+                       usb_control(stat);
+               } else {
+                       bdt_t *b = stat2bufferdescriptor(stat);
+                       usb_packet_t *packet = (usb_packet_t *)((uint8_t *)(b->addr) - 8);
+#if 0
+                       serial_print("ep:");
+                       serial_phex(endpoint);
+                       serial_print(", pid:");
+                       serial_phex(BDT_PID(b->desc));
+                       serial_print(((uint32_t)b & 8) ? ", odd" : ", even");
+                       serial_print(", count:");
+                       serial_phex(b->desc >> 16);
+                       serial_print("\n");
+#endif
+                       endpoint--;     // endpoint is index to zero-based arrays
+
+                       if (stat & 0x08) { // transmit
+                               usb_free(packet);
+                               packet = tx_first[endpoint];
+                               if (packet) {
+                                       //serial_print("tx packet\n");
+                                       tx_first[endpoint] = packet->next;
+                                       b->addr = packet->buf;
+                                       switch (tx_state[endpoint]) {
+                                         case TX_STATE_BOTH_FREE_EVEN_FIRST:
+                                               tx_state[endpoint] = TX_STATE_ODD_FREE;
+                                               break;
+                                         case TX_STATE_BOTH_FREE_ODD_FIRST:
+                                               tx_state[endpoint] = TX_STATE_EVEN_FREE;
+                                               break;
+                                         case TX_STATE_EVEN_FREE:
+                                         case TX_STATE_ODD_FREE:
+                                         default:
+                                               tx_state[endpoint] = TX_STATE_NONE_FREE;
+                                               break;
+                                       }
+                                       b->desc = BDT_DESC(packet->len, ((uint32_t)b & 8) ? DATA1 : DATA0);
+                               } else {
+                                       //serial_print("tx no packet\n");
+                                       switch (tx_state[endpoint]) {
+                                         case TX_STATE_BOTH_FREE_EVEN_FIRST:
+                                         case TX_STATE_BOTH_FREE_ODD_FIRST:
+                                               break;
+                                         case TX_STATE_EVEN_FREE:
+                                               tx_state[endpoint] = TX_STATE_BOTH_FREE_EVEN_FIRST;
+                                               break;
+                                         case TX_STATE_ODD_FREE:
+                                               tx_state[endpoint] = TX_STATE_BOTH_FREE_ODD_FIRST;
+                                               break;
+                                         default:
+                                               tx_state[endpoint] = ((uint32_t)b & 8) ?
+                                                 TX_STATE_ODD_FREE : TX_STATE_EVEN_FREE;
+                                               break;
+                                       }
+                               }
+                       } else { // receive
+                               packet->len = b->desc >> 16;
+                               packet->index = 0;
+                               packet->next = NULL;
+                               if (rx_first[endpoint] == NULL) {
+                                       //serial_print("rx 1st, epidx=");
+                                       //serial_phex(endpoint);
+                                       //serial_print(", packet=");
+                                       //serial_phex32((uint32_t)packet);
+                                       //serial_print("\n");
+                                       rx_first[endpoint] = packet;
+                               } else {
+                                       //serial_print("rx Nth, epidx=");
+                                       //serial_phex(endpoint);
+                                       //serial_print(", packet=");
+                                       //serial_phex32((uint32_t)packet);
+                                       //serial_print("\n");
+                                       rx_last[endpoint]->next = packet;
+                               }
+                               rx_last[endpoint] = packet;
+                               // TODO: implement a per-endpoint maximum # of allocated packets
+                               // so a flood of incoming data on 1 endpoint doesn't starve
+                               // the others if the user isn't reading it regularly
+                               packet = usb_malloc();
+                               if (packet) {
+                                       b->addr = packet->buf;
+                                       b->desc = BDT_DESC(64, ((uint32_t)b & 8) ? DATA1 : DATA0);
+                               } else {
+                                       //serial_print("starving ");
+                                       //serial_phex(endpoint + 1);
+                                       //serial_print(((uint32_t)b & 8) ? ",odd\n" : ",even\n");
+                                       b->desc = 0;
+                                       usb_rx_memory_needed++;
+                               }
+                       }
+
+
+
+
+               }
+               USB0_ISTAT = USB_ISTAT_TOKDNE;
+               goto restart;
+       }
+
+
+
+       if (status & USB_ISTAT_USBRST /* 01 */ ) {
+               //serial_print("reset\n");
+
+               // initialize BDT toggle bits
+               USB0_CTL = USB_CTL_ODDRST;
+               ep0_tx_bdt_bank = 0;
+
+               // set up buffers to receive Setup and OUT packets
+               table[index(0, RX, EVEN)].desc = BDT_DESC(EP0_SIZE, 0);
+               table[index(0, RX, EVEN)].addr = ep0_rx0_buf;
+               table[index(0, RX, ODD)].desc = BDT_DESC(EP0_SIZE, 0);
+               table[index(0, RX, ODD)].addr = ep0_rx1_buf;
+               table[index(0, TX, EVEN)].desc = 0;
+               table[index(0, TX, ODD)].desc = 0;
+               
+               // activate endpoint 0
+               USB0_ENDPT0 = USB_ENDPT_EPRXEN | USB_ENDPT_EPTXEN | USB_ENDPT_EPHSHK;
+
+               // clear all ending interrupts
+               USB0_ERRSTAT = 0xFF;
+               USB0_ISTAT = 0xFF;
+
+               // set the address to zero during enumeration
+               USB0_ADDR = 0;
+
+               // enable other interrupts
+               USB0_ERREN = 0xFF;
+               USB0_INTEN = USB_INTEN_TOKDNEEN |
+                       USB_INTEN_SOFTOKEN |
+                       USB_INTEN_STALLEN |
+                       USB_INTEN_ERROREN |
+                       USB_INTEN_USBRSTEN |
+                       USB_INTEN_SLEEPEN;
+
+               // is this necessary?
+               USB0_CTL = USB_CTL_USBENSOFEN;
+               return;
+       }
+
+
+       if ((status & USB_ISTAT_STALL /* 80 */ )) {
+               //serial_print("stall:\n");
+               USB0_ENDPT0 = USB_ENDPT_EPRXEN | USB_ENDPT_EPTXEN | USB_ENDPT_EPHSHK;
+               USB0_ISTAT = USB_ISTAT_STALL;
+       }
+       if ((status & USB_ISTAT_ERROR /* 02 */ )) {
+               uint8_t err = USB0_ERRSTAT;
+               USB0_ERRSTAT = err;
+               //serial_print("err:");
+               //serial_phex(err);
+               //serial_print("\n");
+               USB0_ISTAT = USB_ISTAT_ERROR;
+       }
+
+       if ((status & USB_ISTAT_SLEEP /* 10 */ )) {
+               //serial_print("sleep\n");
+               USB0_ISTAT = USB_ISTAT_SLEEP;
+       }
+
+}
+
+
+
+void usb_init(void)
+{
+       int i;
+
+       //serial_begin(BAUD2DIV(115200));
+       //serial_print("usb_init\n");
+
+       for (i=0; i <= NUM_ENDPOINTS*4; i++) {
+               table[i].desc = 0;
+               table[i].addr = 0;
+       }
+
+       // this basically follows the flowchart in the Kinetis
+       // Quick Reference User Guide, Rev. 1, 03/2012, page 141
+
+       // assume 48 MHz clock already running
+       // SIM - enable clock
+       SIM_SCGC4 |= SIM_SCGC4_USBOTG;
+
+       // reset USB module
+       USB0_USBTRC0 = USB_USBTRC_USBRESET;
+       while ((USB0_USBTRC0 & USB_USBTRC_USBRESET) != 0) ; // wait for reset to end
+
+       // set desc table base addr
+       USB0_BDTPAGE1 = ((uint32_t)table) >> 8;
+       USB0_BDTPAGE2 = ((uint32_t)table) >> 16;
+       USB0_BDTPAGE3 = ((uint32_t)table) >> 24;
+
+       // clear all ISR flags
+       USB0_ISTAT = 0xFF;
+       USB0_ERRSTAT = 0xFF;
+       USB0_OTGISTAT = 0xFF;
+
+       USB0_USBTRC0 |= 0x40; // undocumented bit
+
+       // enable USB
+       USB0_CTL = USB_CTL_USBENSOFEN;
+       USB0_USBCTRL = 0;
+
+       // enable reset interrupt
+       USB0_INTEN = USB_INTEN_USBRSTEN;
+
+       // enable interrupt in NVIC...
+       NVIC_ENABLE_IRQ(IRQ_USBOTG);
+
+       // enable d+ pullup
+       USB0_CONTROL = USB_CONTROL_DPPULLUPNONOTG;
+}
+
+// return 0 if the USB is not configured, or the configuration
+// number selected by the HOST
+uint8_t usb_configured(void)
+{
+       return usb_configuration;
+}
+
+
diff --git a/USB/pjrc/arm/usb_dev.h b/USB/pjrc/arm/usb_dev.h
new file mode 100644 (file)
index 0000000..d5448fc
--- /dev/null
@@ -0,0 +1,38 @@
+#ifndef _usb_dev_h_
+#define _usb_dev_h_
+
+// This header is NOT meant to be included when compiling
+// user sketches in Arduino.  The low-level functions
+// provided by usb_dev.c are meant to be called only by
+// code which provides higher-level interfaces to the user.
+
+#include "usb_mem.h"
+#include "usb_desc.h"
+
+void usb_init(void);
+uint8_t usb_configured(void);          // is the USB port configured
+void usb_isr(void);
+usb_packet_t *usb_rx(uint32_t endpoint);
+uint32_t usb_rx_byte_count(uint32_t endpoint);
+uint32_t usb_tx_byte_count(uint32_t endpoint);
+uint32_t usb_tx_packet_count(uint32_t endpoint);
+void usb_tx(uint32_t endpoint, usb_packet_t *packet);
+void usb_tx_isr(uint32_t endpoint, usb_packet_t *packet);
+
+extern volatile uint8_t usb_configuration;
+
+#ifdef CDC_DATA_INTERFACE
+extern uint8_t usb_cdc_line_coding[7];
+extern volatile uint8_t usb_cdc_line_rtsdtr;
+extern volatile uint8_t usb_cdc_transmit_flush_timer;
+extern void usb_serial_flush_callback(void);
+#endif
+
+#ifdef SEREMU_INTERFACE
+extern volatile uint8_t usb_seremu_transmit_flush_timer;
+extern void usb_seremu_flush_callback(void);
+#endif
+
+
+#endif
+
diff --git a/USB/pjrc/arm/usb_keyboard.c b/USB/pjrc/arm/usb_keyboard.c
new file mode 100644 (file)
index 0000000..ffe2293
--- /dev/null
@@ -0,0 +1,52 @@
+#include "usb_dev.h"
+#include "usb_keyboard.h"
+#include <Lib/USBLib.h>
+#include <string.h> // for memcpy()
+
+
+// Maximum number of transmit packets to queue so we don't starve other endpoints for memory
+#define TX_PACKET_LIMIT 4
+
+static uint8_t transmit_previous_timeout=0;
+
+// When the PC isn't listening, how long do we wait before discarding data?
+#define TX_TIMEOUT_MSEC 50
+
+#if F_CPU == 96000000
+  #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 596)
+#elif F_CPU == 48000000
+  #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 428)
+#elif F_CPU == 24000000
+  #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 262)
+#endif
+
+
+// send the contents of keyboard_keys and keyboard_modifier_keys
+uint8_t usb_keyboard_send(void)
+{
+       uint32_t wait_count=0;
+       usb_packet_t *tx_packet;
+
+       while (1) {
+               if (!usb_configuration) {
+                       return -1;
+               }
+               if (usb_tx_packet_count(KEYBOARD_ENDPOINT) < TX_PACKET_LIMIT) {
+                       tx_packet = usb_malloc();
+                       if (tx_packet) break;
+               }
+               if (++wait_count > TX_TIMEOUT || transmit_previous_timeout) {
+                       transmit_previous_timeout = 1;
+                       return -1;
+               }
+               yield();
+       }
+       *(tx_packet->buf) = USBKeys_Modifiers;
+       *(tx_packet->buf + 1) = 0;
+       memcpy(tx_packet->buf + 2, USBKeys_Array, USB_MAX_KEY_SEND);
+       tx_packet->len = 8;
+       usb_tx(KEYBOARD_ENDPOINT, tx_packet);
+
+       return 0;
+}
+
diff --git a/USB/pjrc/arm/usb_keyboard.h b/USB/pjrc/arm/usb_keyboard.h
new file mode 100644 (file)
index 0000000..49aa84d
--- /dev/null
@@ -0,0 +1,10 @@
+#ifndef USBkeyboard_h_
+#define USBkeyboard_h_
+
+#include <inttypes.h>
+#include "usb_com.h"
+
+uint8_t usb_keyboard_send(void);
+
+#endif // USBkeyboard_h_
+
diff --git a/USB/pjrc/arm/usb_mem.c b/USB/pjrc/arm/usb_mem.c
new file mode 100644 (file)
index 0000000..47956f6
--- /dev/null
@@ -0,0 +1,78 @@
+#include <Lib/USBLib.h>
+#include "usb_dev.h"
+#include "usb_mem.h"
+
+#define NUM_BUF 30
+
+__attribute__ ((section(".usbbuffers"), used))
+//static unsigned char usb_buffer_memory[NUM_BUF * sizeof(usb_packet_t)];
+unsigned char usb_buffer_memory[NUM_BUF * sizeof(usb_packet_t)];
+
+static uint32_t usb_buffer_available = 0xFFFFFFFF;
+
+// use bitmask and CLZ instruction to implement fast free list
+// http://www.archivum.info/gnu.gcc.help/2006-08/00148/Re-GCC-Inline-Assembly.html
+// http://gcc.gnu.org/ml/gcc/2012-06/msg00015.html
+// __builtin_clz()
+
+usb_packet_t * usb_malloc(void)
+{
+       unsigned int n, avail;
+       uint8_t *p;
+
+       __disable_irq();
+       avail = usb_buffer_available;
+       n = __builtin_clz(avail); // clz = count leading zeros
+       if (n >= NUM_BUF) {
+               __enable_irq();
+               return NULL;
+       }
+       //serial_print("malloc:");
+       //serial_phex(n);
+       //serial_print("\n");
+
+       usb_buffer_available = avail & ~(0x80000000 >> n);
+       __enable_irq();
+       p = usb_buffer_memory + (n * sizeof(usb_packet_t));
+       //serial_print("malloc:");
+       //serial_phex32((int)p);
+       //serial_print("\n");
+       *(uint32_t *)p = 0;
+       *(uint32_t *)(p + 4) = 0;
+       return (usb_packet_t *)p;
+}
+
+// for the receive endpoints to request memory
+extern uint8_t usb_rx_memory_needed;
+extern void usb_rx_memory(usb_packet_t *packet);
+
+void usb_free(usb_packet_t *p)
+{
+       unsigned int n, mask;
+
+       //serial_print("free:");
+       n = ((uint8_t *)p - usb_buffer_memory) / sizeof(usb_packet_t);
+       if (n >= NUM_BUF) return;
+       //serial_phex(n);
+       //serial_print("\n");
+
+       // if any endpoints are starving for memory to receive
+       // packets, give this memory to them immediately!
+       if (usb_rx_memory_needed && usb_configuration) {
+               //serial_print("give to rx:");
+               //serial_phex32((int)p);
+               //serial_print("\n");
+               usb_rx_memory(p);
+               return;
+       }
+
+       mask = (0x80000000 >> n);
+       __disable_irq();
+       usb_buffer_available |= mask;
+       __enable_irq();
+
+       //serial_print("free:");
+       //serial_phex32((int)p);
+       //serial_print("\n");
+}
+
diff --git a/USB/pjrc/arm/usb_mem.h b/USB/pjrc/arm/usb_mem.h
new file mode 100644 (file)
index 0000000..c3f1f8d
--- /dev/null
@@ -0,0 +1,19 @@
+#ifndef _usb_mem_h_
+#define _usb_mem_h_
+
+#include <stdint.h>
+
+typedef struct usb_packet_struct {
+       uint16_t len;
+       uint16_t index;
+       struct usb_packet_struct *next;
+       uint8_t buf[64];
+} usb_packet_t;
+
+usb_packet_t * usb_malloc(void);
+void usb_free(usb_packet_t *p);
+
+
+
+
+#endif
diff --git a/USB/pjrc/arm/usb_serial.c b/USB/pjrc/arm/usb_serial.c
new file mode 100644 (file)
index 0000000..cbbd6ce
--- /dev/null
@@ -0,0 +1,248 @@
+#include "usb_dev.h"
+#include "usb_serial.h"
+#include <Lib/USBLib.h>
+
+// defined by usb_dev.h -> usb_desc.h
+#if defined(CDC_STATUS_INTERFACE) && defined(CDC_DATA_INTERFACE)
+
+uint8_t usb_cdc_line_coding[7];
+volatile uint8_t usb_cdc_line_rtsdtr=0;
+volatile uint8_t usb_cdc_transmit_flush_timer=0;
+
+static usb_packet_t *rx_packet=NULL;
+static usb_packet_t *tx_packet=NULL;
+static volatile uint8_t tx_noautoflush=0;
+
+#define TRANSMIT_FLUSH_TIMEOUT 5   /* in milliseconds */
+
+static void usb_serial_receive(void)
+{
+       if (!usb_configuration) return;
+       if (rx_packet) return;
+       while (1) {
+               rx_packet = usb_rx(CDC_RX_ENDPOINT);
+               if (rx_packet == NULL) return;
+               if (rx_packet->len > 0) return;
+               usb_free(rx_packet);
+               rx_packet = NULL;
+       }
+}
+
+// get the next character, or -1 if nothing received
+int usb_serial_getchar(void)
+{
+       unsigned int i;
+       int c;
+
+       usb_serial_receive();
+       if (!rx_packet) return -1;
+       i = rx_packet->index;
+       c = rx_packet->buf[i++];
+       if (i >= rx_packet->len) {
+               usb_free(rx_packet);
+               rx_packet = NULL;
+       } else {
+               rx_packet->index = i;
+       }
+       return c;
+}
+
+// peek at the next character, or -1 if nothing received
+int usb_serial_peekchar(void)
+{
+       usb_serial_receive();
+       if (!rx_packet) return -1;
+       return rx_packet->buf[rx_packet->index];
+}
+
+// number of bytes available in the receive buffer
+int usb_serial_available(void)
+{
+       int count=0;
+
+       if (usb_configuration) {
+               count = usb_rx_byte_count(CDC_RX_ENDPOINT);
+       }
+       if (rx_packet) count += rx_packet->len - rx_packet->index;
+       return count;
+}
+
+// discard any buffered input
+void usb_serial_flush_input(void)
+{
+       usb_packet_t *rx;
+
+       if (!usb_configuration) return;
+       if (rx_packet) {
+               usb_free(rx_packet);
+               rx_packet = NULL;
+       }
+       while (1) {
+               rx = usb_rx(CDC_RX_ENDPOINT);
+               if (!rx) break;
+               usb_free(rx);
+       }
+}
+
+// Maximum number of transmit packets to queue so we don't starve other endpoints for memory
+#define TX_PACKET_LIMIT 8
+
+// When the PC isn't listening, how long do we wait before discarding data?  If this is
+// too short, we risk losing data during the stalls that are common with ordinary desktop
+// software.  If it's too long, we stall the user's program when no software is running.
+#define TX_TIMEOUT_MSEC 70
+
+#if F_CPU == 96000000
+  #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 596)
+#elif F_CPU == 48000000
+  #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 428)
+#elif F_CPU == 24000000
+  #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 262)
+#endif
+
+// When we've suffered the transmit timeout, don't wait again until the computer
+// begins accepting data.  If no software is running to receive, we'll just discard
+// data as rapidly as Serial.print() can generate it, until there's something to
+// actually receive it.
+static uint8_t transmit_previous_timeout=0;
+
+
+// transmit a character.  0 returned on success, -1 on error
+int usb_serial_putchar(uint8_t c)
+{
+#if 1
+       return usb_serial_write(&c, 1);
+#endif
+#if 0
+       uint32_t wait_count;
+
+       tx_noautoflush = 1;
+       if (!tx_packet) {
+               wait_count = 0;
+               while (1) {
+                       if (!usb_configuration) {
+                               tx_noautoflush = 0;
+                               return -1;
+                       }
+                       if (usb_tx_packet_count(CDC_TX_ENDPOINT) < TX_PACKET_LIMIT) {
+                               tx_noautoflush = 1;
+                               tx_packet = usb_malloc();
+                               if (tx_packet) break;
+                               tx_noautoflush = 0;
+                       }
+                       if (++wait_count > TX_TIMEOUT || transmit_previous_timeout) {
+                               transmit_previous_timeout = 1;
+                               return -1;
+                       }
+               }
+       }
+       transmit_previous_timeout = 0;
+       tx_packet->buf[tx_packet->index++] = c;
+       if (tx_packet->index < CDC_TX_SIZE) {
+               usb_cdc_transmit_flush_timer = TRANSMIT_FLUSH_TIMEOUT;
+       } else {
+               tx_packet->len = CDC_TX_SIZE;
+               usb_cdc_transmit_flush_timer = 0;
+               usb_tx(CDC_TX_ENDPOINT, tx_packet);
+               tx_packet = NULL;
+       }
+       tx_noautoflush = 0;
+       return 0;
+#endif
+}
+
+
+int usb_serial_write(const void *buffer, uint32_t size)
+{
+#if 1
+       uint32_t len;
+       uint32_t wait_count;
+       const uint8_t *src = (const uint8_t *)buffer;
+       uint8_t *dest;
+
+       tx_noautoflush = 1;
+       while (size > 0) {
+               if (!tx_packet) {
+                       wait_count = 0;
+                       while (1) {
+                               if (!usb_configuration) {
+                                       tx_noautoflush = 0;
+                                       return -1;
+                               }
+                               if (usb_tx_packet_count(CDC_TX_ENDPOINT) < TX_PACKET_LIMIT) {
+                                       tx_noautoflush = 1;
+                                       tx_packet = usb_malloc();
+                                       if (tx_packet) break;
+                                       tx_noautoflush = 0;
+                               }
+                               if (++wait_count > TX_TIMEOUT || transmit_previous_timeout) {
+                                       transmit_previous_timeout = 1;
+                                       return -1;
+                               }
+                               yield();
+                       }
+               }
+               transmit_previous_timeout = 0;
+               len = CDC_TX_SIZE - tx_packet->index;
+               if (len > size) len = size;
+               dest = tx_packet->buf + tx_packet->index;
+               tx_packet->index += len;
+               size -= len;
+               while (len-- > 0) *dest++ = *src++;
+               if (tx_packet->index < CDC_TX_SIZE) {
+                       usb_cdc_transmit_flush_timer = TRANSMIT_FLUSH_TIMEOUT;
+               } else {
+                       tx_packet->len = CDC_TX_SIZE;
+                       usb_cdc_transmit_flush_timer = 0;
+                       usb_tx(CDC_TX_ENDPOINT, tx_packet);
+                       tx_packet = NULL;
+               }
+       }
+       tx_noautoflush = 0;
+       return 0;
+#endif
+#if 0
+       const uint8_t *p = (const uint8_t *)buffer;
+       int r;
+
+       while (size) {
+               r = usb_serial_putchar(*p++);
+               if (r < 0) return -1;
+               size--;
+       }
+       return 0;
+#endif
+}
+
+void usb_serial_flush_output(void)
+{
+       if (!usb_configuration) return;
+       //serial_print("usb_serial_flush_output\n");
+       if (tx_packet && tx_packet->index > 0) {
+               usb_cdc_transmit_flush_timer = 0;
+               tx_packet->len = tx_packet->index;
+               usb_tx(CDC_TX_ENDPOINT, tx_packet);
+               tx_packet = NULL;
+       }
+       // while (usb_tx_byte_count(CDC_TX_ENDPOINT) > 0) ; // wait
+}
+
+void usb_serial_flush_callback(void)
+{
+       if (tx_noautoflush) return;
+       //serial_print("usb_flush_callback \n");
+       tx_packet->len = tx_packet->index;
+       usb_tx(CDC_TX_ENDPOINT, tx_packet);
+       tx_packet = NULL;
+       //serial_print("usb_flush_callback end\n");
+}
+
+
+
+
+
+
+
+
+
+#endif // CDC_STATUS_INTERFACE && CDC_DATA_INTERFACE
diff --git a/USB/pjrc/arm/usb_serial.h b/USB/pjrc/arm/usb_serial.h
new file mode 100644 (file)
index 0000000..4dbfa05
--- /dev/null
@@ -0,0 +1,25 @@
+#ifndef USBserial_h_
+#define USBserial_h_
+
+#include <inttypes.h>
+
+// Compatibility defines from AVR
+#define PROGMEM
+#define PGM_P  const char *
+#define PSTR(str) (str)
+
+
+int usb_serial_getchar(void);
+int usb_serial_peekchar(void);
+int usb_serial_available(void);
+void usb_serial_flush_input(void);
+int usb_serial_putchar(uint8_t c);
+int usb_serial_write(const void *buffer, uint32_t size);
+void usb_serial_flush_output(void);
+extern uint8_t usb_cdc_line_coding[7];
+extern volatile uint8_t usb_cdc_line_rtsdtr;
+extern volatile uint8_t usb_cdc_transmit_flush_timer;
+extern volatile uint8_t usb_configuration;
+
+#endif // USBserial_h_
+
index fd9d573341de64f085cabb884ae3c858937d4061..5e283abdc2099c918a8ed4ec3d7d039a53fdcf4e 100644 (file)
@@ -274,18 +274,6 @@ static volatile uint8_t usb_configuration=0;
 // packet, or send a zero length packet.
 static volatile uint8_t debug_flush_timer=0;
 
-// protocol setting from the host.  We use exactly the same report
-// either way, so this variable only stores the setting since we
-// are required to be able to report which setting is in use.
-static uint8_t keyboard_protocol=1;
-
-// the idle configuration, how often we send the report to the
-// host (ms * 4) even when it hasn't changed
-static uint8_t keyboard_idle_config=125;
-
-// count until idle timeout
-static uint8_t keyboard_idle_count=0;
-
 
 /**************************************************************************
  *
@@ -344,7 +332,7 @@ int8_t usb_keyboard_send(void)
                UEDATX = USBKeys_Array[i];
        }
        UEINTX = 0x3A;
-       keyboard_idle_count = 0;
+       USBKeys_Idle_Count = 0;
        SREG = intr_state;
        return 0;
 }
@@ -461,12 +449,12 @@ ISR(USB_GEN_vect)
                                UEINTX = 0x3A;
                        }
                }
-               if (keyboard_idle_config && (++div4 & 3) == 0) {
+               if (USBKeys_Idle_Config && (++div4 & 3) == 0) {
                        UENUM = KEYBOARD_ENDPOINT;
                        if (UEINTX & (1<<RWAL)) {
-                               keyboard_idle_count++;
-                               if (keyboard_idle_count == keyboard_idle_config) {
-                                       keyboard_idle_count = 0;
+                               USBKeys_Idle_Count++;
+                               if (USBKeys_Idle_Count == USBKeys_Idle_Config) {
+                                       USBKeys_Idle_Count = 0;
                                        UEDATX = USBKeys_Modifiers;
                                        UEDATX = 0;
                                        for (i=0; i<6; i++) {
@@ -651,13 +639,13 @@ ISR(USB_COM_vect)
                                }
                                if (bRequest == HID_GET_IDLE) {
                                        usb_wait_in_ready();
-                                       UEDATX = keyboard_idle_config;
+                                       UEDATX = USBKeys_Idle_Config;
                                        usb_send_in();
                                        return;
                                }
                                if (bRequest == HID_GET_PROTOCOL) {
                                        usb_wait_in_ready();
-                                       UEDATX = keyboard_protocol;
+                                       UEDATX = USBKeys_Protocol;
                                        usb_send_in();
                                        return;
                                }
@@ -671,14 +659,14 @@ ISR(USB_COM_vect)
                                        return;
                                }
                                if (bRequest == HID_SET_IDLE) {
-                                       keyboard_idle_config = (wValue >> 8);
-                                       keyboard_idle_count = 0;
+                                       USBKeys_Idle_Config = (wValue >> 8);
+                                       USBKeys_Idle_Count = 0;
                                        //usb_wait_in_ready();
                                        usb_send_in();
                                        return;
                                }
                                if (bRequest == HID_SET_PROTOCOL) {
-                                       keyboard_protocol = wValue;
+                                       USBKeys_Protocol = wValue;
                                        //usb_wait_in_ready();
                                        usb_send_in();
                                        return;
index 91f18c9abf34f31edf46595ad7afe4099399b6f7..eaac9c95a0d86c53afbcd764169740ead4055a15 100644 (file)
 // 1=num lock, 2=caps lock, 4=scroll lock, 8=compose, 16=kana
 volatile uint8_t USBKeys_LEDs = 0;
 
+// protocol setting from the host.  We use exactly the same report
+// either way, so this variable only stores the setting since we
+// are required to be able to report which setting is in use.
+         uint8_t USBKeys_Protocol = 1;
+
+// the idle configuration, how often we send the report to the
+// host (ms * 4) even when it hasn't changed
+         uint8_t USBKeys_Idle_Config = 125;
+
+// count until idle timeout
+         uint8_t USBKeys_Idle_Count = 0;
+
 
 
 // ----- Functions -----
index f0589b0fdedeaea5a82d4b67be0950bfbbf68baa..73cb5440716ed9d744b63084062a3dbda0ebab69 100644 (file)
@@ -60,8 +60,14 @@ extern                       uint8_t USBKeys_Modifiers;
 extern                       uint8_t USBKeys_Array[USB_MAX_KEY_SEND];
 extern                       uint8_t USBKeys_Sent;
 extern volatile              uint8_t USBKeys_LEDs;
+
                 static const uint8_t USBKeys_MaxSize = USB_MAX_KEY_SEND;
 
+// Misc variables (XXX Some are only properly utilized using AVR)
+extern                       uint8_t USBKeys_Protocol;
+extern                       uint8_t USBKeys_Idle_Config;
+extern                       uint8_t USBKeys_Idle_Count;
+
 
 
 // ----- Functions -----
index 518283b831b85ca241c011760e4a32187be9c807..be722d2ffb64b27213f6201d2393d57e81c8018a 100644 (file)
--- a/arm.cmake
+++ b/arm.cmake
@@ -58,6 +58,9 @@ set( COMPILER_SRCS
        Lib/delay.c
 )
 
+message( STATUS "Compiler Source Files:" )
+message( "${COMPILER_SRCS}" )
+
 
 #| Compiler flag to set the C Standard level.
 #|     c89   = "ANSI" C
diff --git a/main.c b/main.c
index 55870e729f90534c0ae2385b5fd71e973df18c16..0a1de615d1a3ddc06d4307f24d5a87202f032342 100644 (file)
--- a/main.c
+++ b/main.c
@@ -111,7 +111,17 @@ inline void usbTimerSetup(void)
 
 // ARM
 #elif defined(_mk20dx128_)
-       // TODO
+       // 48 MHz clock by default
+
+       // Enable Timers
+       /* TODO Fixme!!
+       PIT_MCR = 0x00;
+
+       // Setup ISR Timer for flagging a kepress send to USB
+       // 1 ms / (1 / 48 MHz) - 1 = 47999 cycles -> 0xBB7F
+       PIT_LDVAL0 = 0x0000BB7F;
+       PIT_TCTRL0 = 0x3; // Enable Timer 0 interrupts, and Enable Timer 0
+       */
 #endif
 }
 
@@ -125,6 +135,7 @@ int main(void)
        // Setup USB Module
        usb_setup();
 
+       print("TEST");
        // Setup ISR Timer for flagging a kepress send to USB
        usbTimerSetup();
 
@@ -143,6 +154,10 @@ int main(void)
                        while ( scan_loop() );
                        sei();
 
+                       // XXX DEBUG
+                       dPrint("AAAAAAA\r\n");
+                       print("AAAAAAB\r\n");
+
                        // Run Macros over Key Indices and convert to USB Keys
                        process_macros();
 
@@ -174,10 +189,12 @@ int main(void)
 
 // ----- Interrupts -----
 
-// AVR - USB Keyboard Data Send Counter Interrupt
-#if defined(_at90usb162_) || defined(_atmega32u4_) || defined(_at90usb646_) || defined(_at90usb1286_)
-
+// USB Keyboard Data Send Counter Interrupt
+#if defined(_at90usb162_) || defined(_atmega32u4_) || defined(_at90usb646_) || defined(_at90usb1286_) // AVR
 ISR( TIMER0_OVF_vect )
+#elif defined(_mk20dx128_) // ARM
+void pit0_isr(void)
+#endif
 {
        sendKeypressCounter++;
        if ( sendKeypressCounter > USB_TRANSFER_DIVIDER ) {
@@ -186,8 +203,3 @@ ISR( TIMER0_OVF_vect )
        }
 }
 
-// ARM - USB Keyboard Data Send Counter Interrupt
-#elif defined(_mk20dx128_)
-       // TODO
-#endif
-
index b56c5814e5317753259b2528007c58106775f180..90ea27a02df73f94a5a0d2f98d9081f9c598cf23 100644 (file)
@@ -20,7 +20,7 @@
 #| Please the {Scan,Macro,USB,Debug}/module.txt for information on the modules and how to create new ones
 
 ##| Deals with acquiring the keypress information and turning it into a key index
-set(  ScanModule  "FACOM6684" )
+set(  ScanModule  "MBC-55X" )
 
 ##| Uses the key index and potentially applies special conditions to it, mapping it to a usb key code
 set( MacroModule  "buffer"  )