1 /* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
16 #include "mbed_assert.h"
20 #include "r_typedefs.h"
22 #include "riic_iodefine.h"
23 #include "RZ_A1_Init.h"
26 volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
29 RIIC[obj->i2c]->RIICn##N
32 #define CR1_RST (1 << 6)
33 #define CR1_ICE (1 << 7)
36 #define CR2_ST (1 << 1)
37 #define CR2_RS (1 << 2)
38 #define CR2_SP (1 << 3)
39 #define CR2_TRS (1 << 5)
40 #define CR2_BBSY (1 << 7)
43 #define MR3_ACKBT (1 << 3)
44 #define MR3_ACKWP (1 << 4)
45 #define MR3_WAIT (1 << 6)
48 #define SER_SAR0E (1 << 0)
51 #define SR1_AAS0 (1 << 0)
54 #define SR2_START (1 << 2)
55 #define SR2_STOP (1 << 3)
56 #define SR2_NACKF (1 << 4)
57 #define SR2_RDRF (1 << 5)
58 #define SR2_TEND (1 << 6)
59 #define SR2_TDRE (1 << 7)
61 #define WAIT_TIMEOUT (4200) /* Loop counter : Time-out is about 1ms. By 4200 loops, measured value is 1009ms. */
63 static const PinMap PinMap_I2C_SDA[] = {
70 static const PinMap PinMap_I2C_SCL[] = {
78 static inline int i2c_status(i2c_t *obj) {
79 return REG(SR2.UINT8[0]);
82 static void i2c_reg_reset(i2c_t *obj) {
84 REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off
85 REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on
86 REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on
88 REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack)
89 REG(SER.UINT8[0]) = 0x00; // no slave addr enabled
92 REG(MR1.UINT8[0]) |= obj->pclk_bit;
93 REG(BRL.UINT8[0]) = obj->width_low;
94 REG(BRH.UINT8[0]) = obj->width_hi;
96 REG(MR2.UINT8[0]) = 0x07;
97 REG(MR3.UINT8[0]) = 0x00;
99 REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT
100 REG(IER.UINT8[0]) = 0x00; // no interrupt
102 REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset
105 static inline int i2c_wait_RDRF(i2c_t *obj) {
108 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
109 while (!(i2c_status(obj) & SR2_RDRF)) {
111 if (timeout >= WAIT_TIMEOUT) {
119 static int i2c_wait_TDRE(i2c_t *obj) {
122 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
123 while (!(i2c_status(obj) & SR2_TDRE)) {
125 if (timeout >= WAIT_TIMEOUT) {
133 static int i2c_wait_TEND(i2c_t *obj) {
136 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
137 while (!(i2c_status(obj) & SR2_TEND)) {
139 if (timeout >= WAIT_TIMEOUT) {
148 static int i2c_wait_START(i2c_t *obj) {
151 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
152 while (!(i2c_status(obj) & SR2_START)) {
154 if (timeout >= WAIT_TIMEOUT) {
162 static int i2c_wait_STOP(i2c_t *obj) {
165 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
166 while (!(i2c_status(obj) & SR2_STOP)) {
168 if (timeout >= WAIT_TIMEOUT) {
176 static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) {
178 REG(SR2.UINT32) &= ~SR2_NACKF;
180 REG(SR2.UINT32) &= ~SR2_STOP;
183 static void i2c_set_MR3_NACK(i2c_t *obj) {
185 REG(MR3.UINT32) |= MR3_ACKWP;
186 REG(MR3.UINT32) |= MR3_ACKBT;
187 REG(MR3.UINT32) &= ~MR3_ACKWP;
190 static void i2c_set_MR3_ACK(i2c_t *obj) {
192 REG(MR3.UINT32) |= MR3_ACKWP;
193 REG(MR3.UINT32) &= ~MR3_ACKBT;
194 REG(MR3.UINT32) &= ~MR3_ACKWP;
197 static inline void i2c_power_enable(i2c_t *obj) {
198 volatile uint8_t dummy;
199 switch ((int)obj->i2c) {
201 CPGSTBCR9 &= ~(0x80);
204 CPGSTBCR9 &= ~(0x40);
207 CPGSTBCR9 &= ~(0x20);
210 CPGSTBCR9 &= ~(0x10);
216 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
217 /* determine the I2C to use */
218 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
219 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
220 obj->i2c = pinmap_merge(i2c_sda, i2c_scl);
221 MBED_ASSERT((int)obj->i2c != NC);
224 i2c_power_enable(obj);
226 /* set default frequency at 100k */
227 i2c_frequency(obj, 100000);
229 pinmap_pinout(sda, PinMap_I2C_SDA);
230 pinmap_pinout(scl, PinMap_I2C_SCL);
232 obj->last_stop_flag = 1;
235 inline int i2c_start(i2c_t *obj) {
238 while (REG(CR2.UINT32) & CR2_BBSY) {
240 if (timeout >= obj->bbsy_wait_cnt) {
244 /* Start Condition */
245 REG(CR2.UINT8[0]) |= CR2_ST;
250 static inline int i2c_restart(i2c_t *obj) {
252 REG(SR2.UINT32) &= ~SR2_START;
253 /* ReStart condition */
254 REG(CR2.UINT32) |= CR2_RS;
259 inline int i2c_stop(i2c_t *obj) {
261 REG(SR2.UINT32) &= ~SR2_STOP;
263 REG(CR2.UINT32) |= CR2_SP;
268 static void i2c_set_err_noslave(i2c_t *obj) {
270 (void)i2c_wait_STOP(obj);
271 i2c_set_SR2_NACKF_STOP(obj);
272 obj->last_stop_flag = 1;
275 static inline int i2c_do_write(i2c_t *obj, int value) {
278 if (!(i2c_status(obj) & SR2_NACKF)) {
279 /* RIICnSR2.NACKF=0 */
280 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
281 while (!(i2c_status(obj) & SR2_TDRE)) {
282 /* RIICnSR2.TDRE=0 */
284 if (timeout >= WAIT_TIMEOUT) {
287 if (i2c_status(obj) & SR2_NACKF) {
288 /* RIICnSR2.NACKF=1 */
293 REG(DRT.UINT32) = value;
301 static inline int i2c_read_address_write(i2c_t *obj, int value) {
304 status = i2c_wait_TDRE(obj);
307 REG(DRT.UINT32) = value;
314 static inline int i2c_do_read(i2c_t *obj, int last) {
316 /* this time is befor last byte read */
317 /* Set MR3 WAIT bit is 1 */;
318 REG(MR3.UINT32) |= MR3_WAIT;
319 } else if (last == 1) {
320 i2c_set_MR3_NACK(obj);
322 i2c_set_MR3_ACK(obj);
325 /* return the data */
326 return (REG(DRR.UINT32) & 0xFF);
329 void i2c_frequency(i2c_t *obj, int hz) {
331 float64_t wait_utime;
332 volatile float64_t bps;
333 volatile float64_t L_time; /* H Width period */
334 volatile float64_t H_time; /* L Width period */
335 uint32_t tmp_L_width;
336 uint32_t tmp_H_width;
341 if (false == RZ_A1_IsClockMode0()) {
342 pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK;
344 pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK;
347 /* Min 10kHz, Max 400kHz */
350 } else if (hz > 400000) {
356 /* Calculation L width time */
357 L_time = (1 / (2 * bps)); /* Harf period of frequency */
360 /* Check I2C mode of Speed */
363 L_time -= 102E-9; /* Falling time of SCL clock. */
364 H_time -= 138E-9; /* Rising time of SCL clock. */
366 if (L_time < 1.3E-6) {
367 /* Wnen L width less than 1.3us */
368 /* Subtract Rise up and down time for SCL from H/L width */
370 H_time = (1 / bps) - L_time - 138E-9 - 102E-9;
374 tmp_L_width = (uint32_t)(L_time * pclk_val * 10);
377 while (tmp_L_width >= 341) {
381 remainder = tmp_L_width % 10;
382 tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */
384 tmp_H_width = (uint32_t)(H_time * pclk_val * 10);
385 tmp_H_width >>= wk_cks;
386 if (remainder == 0) {
387 tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */
389 remainder += tmp_H_width % 10;
390 tmp_H_width = (tmp_H_width / 10) - 3;
391 if (remainder > 10) {
392 tmp_H_width += 1; /* fine adjustment */
395 /* timeout of BBSY bit is minimum low width by frequency */
396 /* so timeout calculates "(low width) * 2" by frequency */
397 wait_utime = (L_time * 2) * 1000000;
398 /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */
399 if (wait_utime <= 0.3) {
400 obj->bbsy_wait_cnt = 1;
402 obj->bbsy_wait_cnt = (int)(wait_utime / 0.3);
407 obj->pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */
408 obj->width_low = (uint8_t)(tmp_L_width | 0x000000E0);
409 obj->width_hi = (uint8_t)(tmp_H_width | 0x000000E0);
415 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
419 volatile uint32_t work_reg = 0;
424 i2c_set_MR3_ACK(obj);
425 /* There is a STOP condition for last processing */
426 if (obj->last_stop_flag != 0) {
427 status = i2c_start(obj);
429 i2c_set_err_noslave(obj);
430 return I2C_ERROR_BUS_BUSY;
433 obj->last_stop_flag = stop;
434 /* Send Slave address */
435 status = i2c_read_address_write(obj, (address | 0x01));
437 i2c_set_err_noslave(obj);
438 return I2C_ERROR_NO_SLAVE;
441 status = i2c_wait_RDRF(obj);
443 if ((status != 0) || (REG(SR2.UINT32) & SR2_NACKF == 1)) {
444 /* Slave sends NACK */
447 value = REG(DRR.UINT32);
448 (void)i2c_wait_STOP(obj);
449 i2c_set_SR2_NACKF_STOP(obj);
450 obj->last_stop_flag = 1;
451 return I2C_ERROR_NO_SLAVE;
453 /* Read in all except last byte */
456 value = REG(DRR.UINT32);
457 for (count = 0; count < (length - 1); count++) {
458 /* wait for it to arrive */
459 status = i2c_wait_RDRF(obj);
461 i2c_set_err_noslave(obj);
462 return I2C_ERROR_NO_SLAVE;
464 /* Recieve the data */
465 if (count == (length - 2)) {
466 value = i2c_do_read(obj, 1);
467 } else if ((length >= 3) && (count == (length - 3))) {
468 value = i2c_do_read(obj, 2);
470 value = i2c_do_read(obj, 0);
472 data[count] = (char)value;
474 } else if (length == 2) {
475 /* Set MR3 WATI bit is 1 */
476 REG(MR3.UINT32) |= MR3_WAIT;
478 value = REG(DRR.UINT32);
479 /* wait for it to arrive */
480 status = i2c_wait_RDRF(obj);
482 i2c_set_err_noslave(obj);
483 return I2C_ERROR_NO_SLAVE;
485 i2c_set_MR3_NACK(obj);
486 data[count] = (char)REG(DRR.UINT32);
490 /* Set MR3 WATI bit is 1 */;
491 REG(MR3.UINT32) |= MR3_WAIT;
492 i2c_set_MR3_NACK(obj);
494 value = REG(DRR.UINT32);
496 /* wait for it to arrive */
497 status = i2c_wait_RDRF(obj);
499 i2c_set_err_noslave(obj);
500 return I2C_ERROR_NO_SLAVE;
503 /* If not repeated start, send stop. */
507 value = REG(DRR.UINT32) & 0xFF;
508 data[count] = (char)value;
509 /* RIICnMR3.WAIT = 0 */
510 REG(MR3.UINT32) &= ~MR3_WAIT;
511 (void)i2c_wait_STOP(obj);
512 i2c_set_SR2_NACKF_STOP(obj);
514 (void)i2c_restart(obj);
516 value = REG(DRR.UINT32) & 0xFF;
517 data[count] = (char)value;
518 /* RIICnMR3.WAIT = 0 */
519 REG(MR3.UINT32) &= ~MR3_WAIT;
520 (void)i2c_wait_START(obj);
522 REG(SR2.UINT32) &= ~SR2_START;
528 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
536 /* There is a STOP condition for last processing */
537 if (obj->last_stop_flag != 0) {
538 status = i2c_start(obj);
540 i2c_set_err_noslave(obj);
541 return I2C_ERROR_BUS_BUSY;
544 obj->last_stop_flag = stop;
545 /* Send Slave address */
546 status = i2c_do_write(obj, address);
548 i2c_set_err_noslave(obj);
549 return I2C_ERROR_NO_SLAVE;
551 /* Send Write data */
552 for (cnt=0; cnt<length; cnt++) {
553 status = i2c_do_write(obj, data[cnt]);
555 i2c_set_err_noslave(obj);
560 status = i2c_wait_TEND(obj);
562 i2c_set_err_noslave(obj);
563 return I2C_ERROR_NO_SLAVE;
565 /* If not repeated start, send stop. */
568 (void)i2c_wait_STOP(obj);
569 i2c_set_SR2_NACKF_STOP(obj);
571 (void)i2c_restart(obj);
572 (void)i2c_wait_START(obj);
574 REG(SR2.UINT32) &= ~SR2_START;
581 void i2c_reset(i2c_t *obj) {
583 (void)i2c_wait_STOP(obj);
584 i2c_set_SR2_NACKF_STOP(obj);
587 int i2c_byte_read(i2c_t *obj, int last) {
590 /* wait for it to arrive */
591 status = i2c_wait_RDRF(obj);
593 i2c_set_err_noslave(obj);
594 return I2C_ERROR_NO_SLAVE;
597 return (i2c_do_read(obj, last));
600 int i2c_byte_write(i2c_t *obj, int data) {
604 status = i2c_do_write(obj, (data & 0xFF));
606 i2c_set_err_noslave(obj);
615 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
616 if (enable_slave != 0) {
617 REG(SER.UINT32) |= SER_SAR0E; // only slave addr 0 is enabled
619 REG(SER.UINT32) &= ~SER_SAR0E; // no slave addr enabled
623 int i2c_slave_receive(i2c_t *obj) {
627 status = REG(SR1.UINT8[0]) & SR1_AAS0;
628 status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4;
632 /* the master is writing to this slave */
636 /* the master is writing to all slave */
640 /* the master has requested a read from this slave */
652 int i2c_slave_read(i2c_t *obj, char *data, int length) {
660 for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) {
661 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
662 while ((i2c_status(obj) & SR2_STOP) || (!(i2c_status(obj) & SR2_RDRF))) {
663 /* RIICnSR2.STOP = 1 or RIICnSR2.RDRF = 0 */
664 if (i2c_status(obj) & SR2_STOP) {
665 /* RIICnSR2.STOP = 1 */
670 if (timeout >= WAIT_TIMEOUT) {
674 if (break_flg == 0) {
677 (void)REG(DRR.UINT32);
679 data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF);
683 if (break_flg == 0) {
684 (void)i2c_wait_STOP(obj);
686 if (i2c_status(obj) & SR2_RDRF) {
690 (void)REG(DRR.UINT32);
692 data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF);
697 REG(SR2.UINT32) &= ~SR2_STOP;
702 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
710 while ((count < length) && (status == 0)) {
711 status = i2c_do_write(obj, data[count]);
716 status = i2c_wait_TEND(obj);
718 i2c_set_err_noslave(obj);
723 (void)REG(DRR.UINT32);
724 (void)i2c_wait_STOP(obj);
725 i2c_set_SR2_NACKF_STOP(obj);
730 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
731 REG(SAR0.UINT32) = address & 0xfffffffe;