tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c

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  32  */
  33
  34 #include "mbed_assert.h"
  35 #include "i2c_api.h"
  36 #include "cmsis.h"
  37 #include "i2cm_regs.h"
  38 #include "clkman_regs.h"
  39 #include "ioman_regs.h"
  40 #include "PeripheralPins.h"
  41
  42 #define I2C_SLAVE_ADDR_READ_BIT     0x0001
  43
  44 #ifndef MXC_I2CM_TX_TIMEOUT
  45 #define MXC_I2CM_TX_TIMEOUT         0x5000
  46 #endif
  47
  48 #ifndef MXC_I2CM_RX_TIMEOUT
  49 #define MXC_I2CM_RX_TIMEOUT         0x5000
  50 #endif
  51
  52 typedef enum {
  53     /** 100KHz */
  54     MXC_E_I2CM_SPEED_100KHZ = 0,
  55     /** 400KHz */
  56     MXC_E_I2CM_SPEED_400KHZ,
  57     /** 1MHz */
  58     MXC_E_I2CM_SPEED_1MHZ
  59 } i2cm_speed_t;
  60
  61 /* Clock divider lookup table */
  62 static const uint32_t clk_div_table[3][8] = {
  63     /* MXC_E_I2CM_SPEED_100KHZ */
  64     {
  65         /* 0:       */ 0, /* not supported */
  66         /* 1: 6MHz  */ (( 3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | ( 7 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
  67         /* 2: 8MHz  */ (( 4 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (10 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 48 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
  68         /* 3: 12MHz */ (( 6 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (17 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 72 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
  69         /* 4: 16MHz */ (( 8 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 96 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
  70         /* 5:       */ 0, /* not supported */
  71         /* 6:       */ 0, /* not supported */
  72         /* 7: 24MHz */ ((12 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (38 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (144 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
  73     },
  74     /* MXC_E_I2CM_SPEED_400KHZ */
  75     {
  76         /* 0:       */ 0, /* not supported */
  77         /* 1:       */ 0, /* not supported */
  78         /* 2:       */ 0, /* not supported */
  79         /* 3: 12MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (1 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (18 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
  80         /* 4: 16MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (2 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
  81         /* 5:       */ 0, /* not supported */
  82         /* 6:       */ 0, /* not supported */
  83         /* 7: 24MHz */ ((3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (5 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
  84     },
  85     /* MXC_E_I2CM_SPEED_1MHZ */
  86     {
  87         /* 0:       */ 0, /* not supported */
  88         /* 1:       */ 0, /* not supported */
  89         /* 2:       */ 0, /* not supported */
  90         /* 3:       */ 0, /* not supported */
  91         /* 4:       */ 0, /* not supported */
  92         /* 5:       */ 0, /* not supported */
  93         /* 6:       */ 0, /* not supported */
  94         /* 7: 24MHz */ ((1 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (0 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (14 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
  95     },
  96 };
  97
  98 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
  99 {
 100     // determine the I2C to use
 101     I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
 102     I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
 103     mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl);
 104     MBED_ASSERT((int)i2c != NC);
 105
 106     obj->i2c = i2c;
 107     obj->txfifo = (uint16_t*)MXC_I2CM_GET_BASE_TX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c));
 108     obj->rxfifo = (uint16_t*)MXC_I2CM_GET_BASE_RX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c));
 109     obj->start_pending = 0;
 110         obj->stop_pending = 0;
 111
 112     // configure the pins
 113     pinmap_pinout(sda, PinMap_I2C_SDA);
 114     pinmap_pinout(scl, PinMap_I2C_SCL);
 115
 116     // enable the clock
 117     MXC_CLKMAN->clk_ctrl_6_i2cm = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
 118
 119     // reset module
 120     i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
 121     i2c->ctrl = 0;
 122
 123     // set default frequency at 100k
 124     i2c_frequency(obj, 100000);
 125
 126     // set timeout to 255 ms and turn on the auto-stop option
 127     i2c->timeout = (0xFF << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS) | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN;
 128
 129     // enable tx_fifo and rx_fifo
 130     i2c->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN);
 131 }
 132
 133 void i2c_frequency(i2c_t *obj, int hz)
 134 {
 135     // compute clock array index
 136     int clki = ((SystemCoreClock + 1500000) / 3000000) - 1;
 137
 138     // get clock divider settings from lookup table
 139     if ((hz < 400000) && (clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki] > 0)) {
 140         obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki];
 141     } else if ((hz < 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki] > 0)) {
 142         obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki];
 143     } else if ((hz >= 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki] > 0)) {
 144         obj->i2c->hs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki];
 145     }
 146 }
 147
 148 static int write_tx_fifo(i2c_t *obj, const uint16_t data)
 149 {
 150     int timeout = MXC_I2CM_TX_TIMEOUT;
 151
 152     while (*obj->txfifo) {
 153         uint32_t intfl = obj->i2c->intfl;
 154         if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
 155             return I2C_ERROR_NO_SLAVE;
 156         }
 157         if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
 158             return I2C_ERROR_BUS_BUSY;
 159         }
 160         timeout--;
 161     }
 162     *obj->txfifo = data;
 163
 164     return 0;
 165 }
 166
 167 static int wait_tx_in_progress(i2c_t *obj)
 168 {
 169     int timeout = MXC_I2CM_TX_TIMEOUT;
 170
 171     while ((obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout);
 172
 173     uint32_t intfl = obj->i2c->intfl;
 174
 175     if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
 176         i2c_reset(obj);
 177         return I2C_ERROR_NO_SLAVE;
 178     }
 179
 180     if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
 181         i2c_reset(obj);
 182         return I2C_ERROR_BUS_BUSY;
 183     }
 184
 185     return 0;
 186 }
 187
 188 int i2c_start(i2c_t *obj)
 189 {
 190     obj->start_pending = 1;
 191     return 0;
 192 }
 193
 194 int i2c_stop(i2c_t *obj)
 195 {
 196     obj->start_pending = 0;
 197     write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP);
 198
 199     return wait_tx_in_progress(obj);
 200 }
 201
 202 void i2c_reset(i2c_t *obj)
 203 {
 204     obj->i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
 205     obj->i2c->intfl = 0x3FF; // clear all interrupts
 206     obj->i2c->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN;
 207     obj->start_pending = 0;
 208 }
 209
 210 int i2c_byte_write(i2c_t *obj, int data)
 211 {
 212     int err;
 213
 214     // clear all interrupts
 215     obj->i2c->intfl = 0x3FF;
 216
 217     if (obj->start_pending) {
 218         obj->start_pending = 0;
 219         data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_START;
 220     } else {
 221         data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_TXDATA_ACK;
 222     }
 223
 224     if ((err = write_tx_fifo(obj, data)) != 0) {
 225         return err;
 226     }
 227
 228     obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
 229
 230     return 0;
 231 }
 232
 233 int i2c_byte_read(i2c_t *obj, int last)
 234 {
 235     uint16_t fifo_value;
 236     int err;
 237
 238     // clear all interrupts
 239     obj->i2c->intfl = 0x3FF;
 240
 241     if (last) {
 242         fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_NACK;
 243     } else {
 244         fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT;
 245     }
 246
 247     if ((err = write_tx_fifo(obj, fifo_value)) != 0) {
 248         return err;
 249     }
 250
 251     obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
 252
 253     int timeout = MXC_I2CM_RX_TIMEOUT;
 254     while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
 255             (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
 256         if ((--timeout < 0) || !(obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
 257             break;
 258         }
 259     }
 260
 261     if (obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) {
 262         obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
 263         return *obj->rxfifo;
 264     }
 265
 266     return -1;
 267 }
 268
 269 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
 270 {
 271     int err, retval = 0;
 272     int i;
 273
 274     if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
 275         return 0;
 276     }
 277
 278     // clear all interrupts
 279     obj->i2c->intfl = 0x3FF;
 280
 281     // write the address to the fifo
 282     if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address))) != 0) { // start + addr (write)
 283         return err;
 284     }
 285     obj->start_pending = 0;
 286
 287     // start the transaction
 288     obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
 289
 290     // load as much of the cmd into the FIFO as possible
 291     for (i = 0; i < length; i++) {
 292         if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != 0) { // cmd (expect ACK)
 293             retval = (retval ? retval : err);
 294             break;
 295         }
 296     }
 297
 298     if (stop) {
 299                 obj->stop_pending = 0;
 300         if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
 301             retval = (retval ? retval : err);
 302         }
 303
 304         if ((err = wait_tx_in_progress(obj)) != 0) {
 305             retval = (retval ? retval : err);
 306         }
 307     } else {
 308         obj->stop_pending = 1;
 309         int timeout = MXC_I2CM_TX_TIMEOUT;
 310         // Wait for TX fifo to be empty
 311         while(!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY) && timeout--) {}
 312     }
 313
 314     if (retval == 0) {
 315         return length;
 316     }
 317
 318     return retval;
 319 }
 320
 321 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
 322 {
 323     int err, retval = 0;
 324     int i = length;
 325     int timeout;
 326
 327     if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
 328         return 0;
 329     }
 330
 331     // clear all interrupts
 332     obj->i2c->intfl = 0x3FF;
 333
 334     // start + addr (read)
 335     if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address | I2C_SLAVE_ADDR_READ_BIT))) != 0) {
 336         goto read_done;
 337     }
 338     obj->start_pending = 0;
 339
 340     while (i > 256) {
 341         if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != 0) {
 342             goto read_done;
 343         }
 344         i -= 256;
 345     }
 346
 347     if (i > 1) {
 348         if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i - 2)))) != 0) {
 349             goto read_done;
 350         }
 351     }
 352
 353     // start the transaction
 354     obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
 355
 356     if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK)) != 0) { // NACK last data byte
 357         goto read_done;
 358     }
 359
 360     if (stop) {
 361         if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
 362             goto read_done;
 363         }
 364     }
 365
 366     timeout = MXC_I2CM_RX_TIMEOUT;
 367     i = 0;
 368     while (i < length) {
 369         while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
 370                 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
 371             if ((--timeout < 0) || !(obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
 372                 retval = -3;
 373                 goto read_done;
 374             }
 375         }
 376
 377         timeout = MXC_I2CM_RX_TIMEOUT;
 378
 379         obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
 380
 381         uint16_t temp = *obj->rxfifo;
 382
 383         if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) {
 384             continue;
 385         }
 386         data[i++] = (uint8_t) temp;
 387     }
 388
 389 read_done:
 390
 391     if (stop) {
 392         obj->stop_pending = 0;
 393         if ((err = wait_tx_in_progress(obj)) != 0) {
 394             retval = (retval ? retval : err);
 395         }
 396     } else {
 397         obj->stop_pending = 1;
 398     }
 399
 400     if (retval == 0) {
 401         return length;
 402     }
 403
 404     return retval;
 405 }