tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbint.c

   1 /*******************************************************************************
   2 * DISCLAIMER
   3 * This software is supplied by Renesas Electronics Corporation and is only
   4 * intended for use with Renesas products. No other uses are authorized. This
   5 * software is owned by Renesas Electronics Corporation and is protected under
   6 * all applicable laws, including copyright laws.
   7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
   8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
   9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
  10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
  11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
  12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
  13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
  14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
  15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
  16 * Renesas reserves the right, without notice, to make changes to this software
  17 * and to discontinue the availability of this software. By using this software,
  18 * you agree to the additional terms and conditions found by accessing the
  19 * following link:
  20 * http://www.renesas.com/disclaimer
  21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
  22 *******************************************************************************/
  23 /*******************************************************************************
  24 * File Name    : usb0_host_usbint.c
  25 * $Rev: 1116 $
  26 * $Date:: 2014-07-09 16:29:19 +0900#$
  27 * Device(s)    : RZ/A1H
  28 * Tool-Chain   :
  29 * OS           : None
  30 * H/W Platform :
  31 * Description  : RZ/A1H R7S72100 USB Sample Program
  32 * Operation    :
  33 * Limitations  :
  34 *******************************************************************************/
  35
  36
  37 /*******************************************************************************
  38 Includes   <System Includes> , "Project Includes"
  39 *******************************************************************************/
  40 #include "usb0_host.h"
  41 #if(1) /* ohci_wrapp */
  42 #include "ohci_wrapp_RZ_A1_local.h"
  43 #endif
  44
  45
  46 /*******************************************************************************
  47 Typedef definitions
  48 *******************************************************************************/
  49
  50
  51 /*******************************************************************************
  52 Macro definitions
  53 *******************************************************************************/
  54
  55
  56 /*******************************************************************************
  57 Imported global variables and functions (from other files)
  58 *******************************************************************************/
  59
  60
  61 /*******************************************************************************
  62 Exported global variables and functions (to be accessed by other files)
  63 *******************************************************************************/
  64 static void usb0_host_interrupt1(void);
  65 static void usb0_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
  66 static void usb0_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
  67 static void usb0_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl);
  68
  69
  70 /*******************************************************************************
  71 Private global variables and functions
  72 *******************************************************************************/
  73
  74
  75 /*******************************************************************************
  76 * Function Name: usb0_host_interrupt
  77 * Description  : Executes USB interrupt.
  78 *              : Register this function in the USB interrupt handler.
  79 *              : Set CFIF0 in the pipe set before the interrupt after executing
  80 *              : this function.
  81 * Arguments    : uint32_t int_sense ; Interrupts detection mode
  82 *              :                    ;  INTC_LEVEL_SENSITIVE : Level sense
  83 *              :                    ;  INTC_EDGE_TRIGGER : Edge trigger
  84 * Return Value : none
  85 *******************************************************************************/
  86 void usb0_host_interrupt (uint32_t int_sense)
  87 {
  88     uint16_t savepipe1;
  89     uint16_t savepipe2;
  90     uint16_t buffer;
  91
  92     savepipe1 = USB200.CFIFOSEL;
  93     savepipe2 = USB200.PIPESEL;
  94     usb0_host_interrupt1();
  95
  96     /* Control transmission changes ISEL within interruption processing. */
  97     /* For this reason, write return of ISEL cannot be performed. */
  98     buffer = USB200.CFIFOSEL;
  99     buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
 100     buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE);
 101     USB200.CFIFOSEL = buffer;
 102     USB200.PIPESEL = savepipe2;
 103 }
 104
 105 /*******************************************************************************
 106 * Function Name: usb0_host_interrupt1
 107 * Description  : Execue the USB interrupt.
 108 * Arguments    : none
 109 * Return Value : none
 110 *******************************************************************************/
 111 void usb0_host_interrupt1 (void)
 112 {
 113     uint16_t intsts0;
 114     uint16_t intsts1;
 115     uint16_t intenb0;
 116     uint16_t intenb1;
 117     uint16_t brdysts;
 118     uint16_t nrdysts;
 119     uint16_t bempsts;
 120     uint16_t brdyenb;
 121     uint16_t nrdyenb;
 122     uint16_t bempenb;
 123     volatile uint16_t dumy_sts;
 124
 125     intsts0 = USB200.INTSTS0;
 126     intsts1 = USB200.INTSTS1;
 127     intenb0 = USB200.INTENB0;
 128     intenb1 = USB200.INTENB1;
 129
 130     if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE))
 131     {
 132             USB200.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG;
 133             RZA_IO_RegWrite_16(&USB200.INTENB1,
 134                                 0,
 135                                 USB_INTENB1_BCHGE_SHIFT,
 136                                 USB_INTENB1_BCHGE);
 137             g_usb0_host_bchg_flag = USB_HOST_YES;
 138     }
 139     else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE))
 140     {
 141         USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSACK;
 142 #if(1) /* ohci_wrapp */
 143         ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
 144 #else
 145         g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
 146         g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
 147 #endif
 148     }
 149     else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE))
 150     {
 151         USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN;
 152 #if(1) /* ohci_wrapp */
 153         g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
 154         ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
 155 #else
 156         g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
 157         g_usb0_host_CmdStage |= USB_HOST_CMD_NORES;
 158 #endif
 159     }
 160     else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH)
 161           && ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE))
 162     {
 163         USB200.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH;
 164         RZA_IO_RegWrite_16(&USB200.INTENB1,
 165                             0,
 166                             USB_INTENB1_DTCHE_SHIFT,
 167                             USB_INTENB1_DTCHE);
 168         g_usb0_host_detach_flag = USB_HOST_YES;
 169
 170         Userdef_USB_usb0_host_detach();
 171
 172         usb0_host_UsbDetach2();
 173     }
 174     else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH)
 175           && ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE))
 176     {
 177         USB200.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH;
 178         RZA_IO_RegWrite_16(&USB200.INTENB1,
 179                             0,
 180                             USB_INTENB1_ATTCHE_SHIFT,
 181                             USB_INTENB1_ATTCHE);
 182         g_usb0_host_attach_flag = USB_HOST_YES;
 183
 184         Userdef_USB_usb0_host_attach();
 185
 186         usb0_host_UsbAttach();
 187     }
 188     else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY)))
 189     {
 190         brdysts = USB200.BRDYSTS;
 191         nrdysts = USB200.NRDYSTS;
 192         bempsts = USB200.BEMPSTS;
 193         brdyenb = USB200.BRDYENB;
 194         nrdyenb = USB200.NRDYENB;
 195         bempenb = USB200.BEMPENB;
 196
 197         if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb))
 198         {
 199             usb0_host_BRDYInterrupt(brdysts, brdyenb);
 200         }
 201         else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb))
 202         {
 203             usb0_host_BEMPInterrupt(bempsts, bempenb);
 204         }
 205         else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb))
 206         {
 207             usb0_host_NRDYInterrupt(nrdysts, nrdyenb);
 208         }
 209         else
 210         {
 211             /* Do Nothing */
 212         }
 213     }
 214     else
 215     {
 216         /* Do Nothing */
 217     }
 218
 219     /* Three dummy read for clearing interrupt requests */
 220     dumy_sts = USB200.INTSTS0;
 221     dumy_sts = USB200.INTSTS1;
 222
 223 }
 224
 225 /*******************************************************************************
 226 * Function Name: usb0_host_BRDYInterrupt
 227 * Description  : Executes USB BRDY interrupt.
 228 * Arguments    : uint16_t Status   ; BRDYSTS Register Value
 229 *              : uint16_t Int_enbl ; BRDYENB Register Value
 230 * Return Value : none
 231 *******************************************************************************/
 232 void usb0_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
 233 {
 234     uint16_t          buffer;
 235     volatile uint16_t dumy_sts;
 236
 237     if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
 238     {
 239         USB200.BRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
 240
 241 #if(1) /* ohci_wrapp */
 242         switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
 243         {
 244             case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
 245                 buffer  = usb0_host_read_buffer_c(USB_HOST_PIPE0);
 246                 usb0_host_disable_brdy_int(USB_HOST_PIPE0);
 247                 g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
 248                 g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
 249                 ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
 250             break;
 251
 252             case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
 253                 buffer  = usb0_host_read_buffer_c(USB_HOST_PIPE0);
 254                 switch (buffer)
 255                 {
 256                     case USB_HOST_READING:                  /* Continue of data read */
 257                     break;
 258
 259                     case USB_HOST_READEND:                  /* End of data read */
 260                     case USB_HOST_READSHRT:                 /* End of data read */
 261                         usb0_host_disable_brdy_int(USB_HOST_PIPE0);
 262                         g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
 263                         g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
 264                         ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
 265                     break;
 266
 267                     case USB_HOST_READOVER:                 /* buffer over */
 268                         USB200.CFIFOCTR = USB_HOST_BITBCLR;
 269                         usb0_host_disable_brdy_int(USB_HOST_PIPE0);
 270                         g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
 271                         g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
 272                         ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
 273                     break;
 274
 275                     case USB_HOST_FIFOERROR:                    /* FIFO access error */
 276                     default:
 277                     break;
 278                 }
 279             break;
 280
 281             default:
 282             break;
 283         }
 284 #else
 285         switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
 286         {
 287             case (USB_HOST_MODE_WRITE   | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
 288             case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
 289                 buffer  = usb0_host_read_buffer_c(USB_HOST_PIPE0);
 290                 usb0_host_disable_brdy_int(USB_HOST_PIPE0);
 291                 g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
 292                 g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
 293             break;
 294
 295             case (USB_HOST_MODE_READ   | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
 296                 buffer  = usb0_host_read_buffer_c(USB_HOST_PIPE0);
 297
 298                 switch (buffer)
 299                 {
 300                     case USB_HOST_READING:                  /* Continue of data read */
 301                     break;
 302
 303                     case USB_HOST_READEND:                  /* End of data read */
 304                     case USB_HOST_READSHRT:                 /* End of data read */
 305                         usb0_host_disable_brdy_int(USB_HOST_PIPE0);
 306                         g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
 307                         g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
 308                     break;
 309
 310                     case USB_HOST_READOVER:                 /* buffer over */
 311                         USB200.CFIFOCTR = USB_HOST_BITBCLR;
 312                         usb0_host_disable_brdy_int(USB_HOST_PIPE0);
 313                         g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
 314                         g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
 315                     break;
 316
 317                     case USB_HOST_FIFOERROR:                    /* FIFO access error */
 318                     default:
 319                     break;
 320                 }
 321             break;
 322
 323             default:
 324             break;
 325         }
 326 #endif
 327     }
 328     else
 329     {
 330         usb0_host_brdy_int(Status, Int_enbl);
 331     }
 332
 333     /* Three dummy reads for clearing interrupt requests */
 334     dumy_sts = USB200.BRDYSTS;
 335 }
 336
 337 /*******************************************************************************
 338 * Function Name: usb0_host_NRDYInterrupt
 339 * Description  : Executes USB NRDY interrupt.
 340 * Arguments    : uint16_t Status        ; NRDYSTS Register Value
 341 *              : uint16_t Int_enbl      ; NRDYENB Register Value
 342 * Return Value : none
 343 *******************************************************************************/
 344 void usb0_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
 345 {
 346     uint16_t          pid;
 347     volatile uint16_t dumy_sts;
 348
 349     if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
 350     {
 351         USB200.NRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
 352         pid = usb0_host_get_pid(USB_HOST_PIPE0);
 353
 354         if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
 355         {
 356             g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
 357             g_usb0_host_CmdStage |= USB_HOST_CMD_STALL;
 358 #if(1) /* ohci_wrapp */
 359             g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;
 360             ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
 361 #endif
 362         }
 363         else if (pid  == USB_HOST_PID_NAK)
 364         {
 365             g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
 366             g_usb0_host_CmdStage |= USB_HOST_CMD_NORES;
 367 #if(1) /* ohci_wrapp */
 368             g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;
 369             ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
 370 #endif
 371         }
 372         else
 373         {
 374             /* Do Nothing */
 375         }
 376     }
 377     else
 378     {
 379         usb0_host_nrdy_int(Status, Int_enbl);
 380     }
 381
 382     /* Three dummy reads for clearing interrupt requests */
 383     dumy_sts = USB200.NRDYSTS;
 384 }
 385
 386 /*******************************************************************************
 387 * Function Name: usb0_host_BEMPInterrupt
 388 * Description  : Executes USB BEMP interrupt.
 389 * Arguments    : uint16_t Status        ; BEMPSTS Register Value
 390 *              : uint16_t Int_enbl      ; BEMPENB Register Value
 391 * Return Value : none
 392 *******************************************************************************/
 393 void usb0_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl)
 394 {
 395     uint16_t          buffer;
 396     uint16_t          pid;
 397     volatile uint16_t dumy_sts;
 398
 399     if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
 400     {
 401         USB200.BEMPSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
 402         pid = usb0_host_get_pid(USB_HOST_PIPE0);
 403
 404         if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
 405         {
 406             g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
 407             g_usb0_host_CmdStage |= USB_HOST_CMD_STALL;
 408 #if(1) /* ohci_wrapp */
 409             g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;      /* exit STALL */
 410             ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
 411 #endif
 412         }
 413         else
 414         {
 415 #if(1) /* ohci_wrapp */
 416             switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
 417             {
 418                 case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
 419                     g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
 420                     g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
 421                     ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
 422                 break;
 423
 424                 case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
 425                     buffer  = usb0_host_write_buffer(USB_HOST_PIPE0);
 426                     switch (buffer)
 427                     {
 428                         case USB_HOST_WRITING:                  /* Continue of data write */
 429                         case USB_HOST_WRITEEND:                 /* End of data write (zero-length) */
 430                         break;
 431
 432                         case USB_HOST_WRITESHRT:                    /* End of data write */
 433                             g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
 434                             g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
 435                             ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
 436                         break;
 437
 438                         case USB_HOST_FIFOERROR:                    /* FIFO access error */
 439                         default:
 440                         break;
 441                     }
 442                 break;
 443
 444                 default:
 445                     /* do nothing */
 446                 break;
 447             }
 448 #else
 449             switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
 450             {
 451                 case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
 452                     g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
 453                     g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
 454                 break;
 455
 456                 case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
 457                     buffer  = usb0_host_write_buffer(USB_HOST_PIPE0);
 458                     switch (buffer)
 459                     {
 460                         case USB_HOST_WRITING:                  /* Continue of data write */
 461                         case USB_HOST_WRITEEND:                 /* End of data write (zero-length) */
 462                         break;
 463
 464                         case USB_HOST_WRITESHRT:                    /* End of data write */
 465                             g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
 466                             g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
 467                         break;
 468
 469                         case USB_HOST_FIFOERROR:                    /* FIFO access error */
 470                         default:
 471                         break;
 472                     }
 473                 break;
 474
 475                 case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
 476                     g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
 477                     g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
 478                 break;
 479
 480                 default:
 481                     /* do nothing */
 482                 break;
 483             }
 484 #endif
 485         }
 486     }
 487     else
 488     {
 489         usb0_host_bemp_int(Status, Int_enbl);
 490     }
 491
 492     /* Three dummy reads for clearing interrupt requests */
 493     dumy_sts = USB200.BEMPSTS;
 494 }
 495
 496 /* End of File */