// Chapter 20: Direct Memory Access Multiplexer (DMAMUX)
- #define DMAMUX0_CHCFG0 *(volatile uint8_t *)0x40021000 // Channel Configuration register
- #define DMAMUX0_CHCFG1 *(volatile uint8_t *)0x40021001 // Channel Configuration register
- #define DMAMUX0_CHCFG2 *(volatile uint8_t *)0x40021002 // Channel Configuration register
- #define DMAMUX0_CHCFG3 *(volatile uint8_t *)0x40021003 // Channel Configuration register
- #define DMAMUX0_CHCFG4 *(volatile uint8_t *)0x40021004 // Channel Configuration register
- #define DMAMUX0_CHCFG5 *(volatile uint8_t *)0x40021005 // Channel Configuration register
- #define DMAMUX0_CHCFG6 *(volatile uint8_t *)0x40021006 // Channel Configuration register
- #define DMAMUX0_CHCFG7 *(volatile uint8_t *)0x40021007 // Channel Configuration register
- #define DMAMUX0_CHCFG8 *(volatile uint8_t *)0x40021008 // Channel Configuration register
- #define DMAMUX0_CHCFG9 *(volatile uint8_t *)0x40021009 // Channel Configuration register
- #define DMAMUX0_CHCFG10 *(volatile uint8_t *)0x4002100A // Channel Configuration register
- #define DMAMUX0_CHCFG11 *(volatile uint8_t *)0x4002100B // Channel Configuration register
- #define DMAMUX0_CHCFG12 *(volatile uint8_t *)0x4002100C // Channel Configuration register
- #define DMAMUX0_CHCFG13 *(volatile uint8_t *)0x4002100D // Channel Configuration register
- #define DMAMUX0_CHCFG14 *(volatile uint8_t *)0x4002100E // Channel Configuration register
- #define DMAMUX0_CHCFG15 *(volatile uint8_t *)0x4002100F // Channel Configuration register
- #define DMAMUX_DISABLE 0
- #define DMAMUX_TRIG 64
- #define DMAMUX_ENABLE 128
- #define DMAMUX_SOURCE_UART0_RX 2
- #define DMAMUX_SOURCE_UART0_TX 3
- #define DMAMUX_SOURCE_UART1_RX 4
- #define DMAMUX_SOURCE_UART1_TX 5
- #define DMAMUX_SOURCE_UART2_RX 6
- #define DMAMUX_SOURCE_UART2_TX 7
- #define DMAMUX_SOURCE_I2S0_RX 14
- #define DMAMUX_SOURCE_I2S0_TX 15
- #define DMAMUX_SOURCE_SPI0_RX 16
- #define DMAMUX_SOURCE_SPI0_TX 17
- #define DMAMUX_SOURCE_I2C0 22
- #define DMAMUX_SOURCE_I2C1 23
- #define DMAMUX_SOURCE_FTM0_CH0 24
- #define DMAMUX_SOURCE_FTM0_CH1 25
- #define DMAMUX_SOURCE_FTM0_CH2 26
- #define DMAMUX_SOURCE_FTM0_CH3 27
- #define DMAMUX_SOURCE_FTM0_CH4 28
- #define DMAMUX_SOURCE_FTM0_CH5 29
- #define DMAMUX_SOURCE_FTM0_CH6 30
- #define DMAMUX_SOURCE_FTM0_CH7 31
- #define DMAMUX_SOURCE_FTM1_CH0 32
- #define DMAMUX_SOURCE_FTM1_CH1 33
- #define DMAMUX_SOURCE_FTM2_CH0 34
- #define DMAMUX_SOURCE_FTM2_CH1 35
- #define DMAMUX_SOURCE_ADC0 40
- #define DMAMUX_SOURCE_ADC1 41
- #define DMAMUX_SOURCE_CMP0 42
- #define DMAMUX_SOURCE_CMP1 43
- #define DMAMUX_SOURCE_CMP2 44
- #define DMAMUX_SOURCE_DAC0 45
- #define DMAMUX_SOURCE_CMT 47
- #define DMAMUX_SOURCE_PDB 48
- #define DMAMUX_SOURCE_PORTA 49
- #define DMAMUX_SOURCE_PORTB 50
- #define DMAMUX_SOURCE_PORTC 51
- #define DMAMUX_SOURCE_PORTD 52
- #define DMAMUX_SOURCE_PORTE 53
- #define DMAMUX_SOURCE_ALWAYS0 54
- #define DMAMUX_SOURCE_ALWAYS1 55
- #define DMAMUX_SOURCE_ALWAYS2 56
- #define DMAMUX_SOURCE_ALWAYS3 57
- #define DMAMUX_SOURCE_ALWAYS4 58
- #define DMAMUX_SOURCE_ALWAYS5 59
- #define DMAMUX_SOURCE_ALWAYS6 60
- #define DMAMUX_SOURCE_ALWAYS7 61
- #define DMAMUX_SOURCE_ALWAYS8 62
- #define DMAMUX_SOURCE_ALWAYS9 63
+ #define DMAMUX0_CHCFG0 *(volatile uint8_t *)0x40021000 // Channel Configuration register
+ #define DMAMUX0_CHCFG1 *(volatile uint8_t *)0x40021001 // Channel Configuration register
+ #define DMAMUX0_CHCFG2 *(volatile uint8_t *)0x40021002 // Channel Configuration register
+ #define DMAMUX0_CHCFG3 *(volatile uint8_t *)0x40021003 // Channel Configuration register
+ #define DMAMUX0_CHCFG4 *(volatile uint8_t *)0x40021004 // Channel Configuration register
+ #define DMAMUX0_CHCFG5 *(volatile uint8_t *)0x40021005 // Channel Configuration register
+ #define DMAMUX0_CHCFG6 *(volatile uint8_t *)0x40021006 // Channel Configuration register
+ #define DMAMUX0_CHCFG7 *(volatile uint8_t *)0x40021007 // Channel Configuration register
+ #define DMAMUX0_CHCFG8 *(volatile uint8_t *)0x40021008 // Channel Configuration register
+ #define DMAMUX0_CHCFG9 *(volatile uint8_t *)0x40021009 // Channel Configuration register
+ #define DMAMUX0_CHCFG10 *(volatile uint8_t *)0x4002100A // Channel Configuration register
+ #define DMAMUX0_CHCFG11 *(volatile uint8_t *)0x4002100B // Channel Configuration register
+ #define DMAMUX0_CHCFG12 *(volatile uint8_t *)0x4002100C // Channel Configuration register
+ #define DMAMUX0_CHCFG13 *(volatile uint8_t *)0x4002100D // Channel Configuration register
+ #define DMAMUX0_CHCFG14 *(volatile uint8_t *)0x4002100E // Channel Configuration register
+ #define DMAMUX0_CHCFG15 *(volatile uint8_t *)0x4002100F // Channel Configuration register
+ #define DMAMUX_DISABLE 0
+ #define DMAMUX_TRIG 64
+ #define DMAMUX_ENABLE 128
+ #define DMAMUX_SOURCE_UART0_RX 2
+ #define DMAMUX_SOURCE_UART0_TX 3
+ #define DMAMUX_SOURCE_UART1_RX 4
+ #define DMAMUX_SOURCE_UART1_TX 5
+ #define DMAMUX_SOURCE_UART2_RX 6
+ #define DMAMUX_SOURCE_UART2_TX 7
+ #define DMAMUX_SOURCE_I2S0_RX 14
+ #define DMAMUX_SOURCE_I2S0_TX 15
+ #define DMAMUX_SOURCE_SPI0_RX 16
+ #define DMAMUX_SOURCE_SPI0_TX 17
+ #define DMAMUX_SOURCE_I2C0 22
+ #define DMAMUX_SOURCE_I2C1 23
+ #define DMAMUX_SOURCE_FTM0_CH0 24
+ #define DMAMUX_SOURCE_FTM0_CH1 25
+ #define DMAMUX_SOURCE_FTM0_CH2 26
+ #define DMAMUX_SOURCE_FTM0_CH3 27
+ #define DMAMUX_SOURCE_FTM0_CH4 28
+ #define DMAMUX_SOURCE_FTM0_CH5 29
+ #define DMAMUX_SOURCE_FTM0_CH6 30
+ #define DMAMUX_SOURCE_FTM0_CH7 31
+ #define DMAMUX_SOURCE_FTM1_CH0 32
+ #define DMAMUX_SOURCE_FTM1_CH1 33
+ #define DMAMUX_SOURCE_FTM2_CH0 34
+ #define DMAMUX_SOURCE_FTM2_CH1 35
+ #define DMAMUX_SOURCE_ADC0 40
+ #define DMAMUX_SOURCE_ADC1 41
+ #define DMAMUX_SOURCE_CMP0 42
+ #define DMAMUX_SOURCE_CMP1 43
+ #define DMAMUX_SOURCE_CMP2 44
+ #define DMAMUX_SOURCE_DAC0 45
+ #define DMAMUX_SOURCE_CMT 47
+ #define DMAMUX_SOURCE_PDB 48
+ #define DMAMUX_SOURCE_PORTA 49
+ #define DMAMUX_SOURCE_PORTB 50
+ #define DMAMUX_SOURCE_PORTC 51
+ #define DMAMUX_SOURCE_PORTD 52
+ #define DMAMUX_SOURCE_PORTE 53
+ #define DMAMUX_SOURCE_ALWAYS0 54
+ #define DMAMUX_SOURCE_ALWAYS1 55
+ #define DMAMUX_SOURCE_ALWAYS2 56
+ #define DMAMUX_SOURCE_ALWAYS3 57
+ #define DMAMUX_SOURCE_ALWAYS4 58
+ #define DMAMUX_SOURCE_ALWAYS5 59
+ #define DMAMUX_SOURCE_ALWAYS6 60
+ #define DMAMUX_SOURCE_ALWAYS7 61
+ #define DMAMUX_SOURCE_ALWAYS8 62
+ #define DMAMUX_SOURCE_ALWAYS9 63
// Chapter 21: Direct Memory Access Controller (eDMA)
- #define DMA_CR *(volatile uint32_t *)0x40008000 // Control Register
- #define DMA_CR_CX ((uint32_t)(1<<17)) // Cancel Transfer
- #define DMA_CR_ECX ((uint32_t)(1<<16)) // Error Cancel Transfer
- #define DMA_CR_EMLM ((uint32_t)0x80) // Enable Minor Loop Mapping
- #define DMA_CR_CLM ((uint32_t)0x40) // Continuous Link Mode
- #define DMA_CR_HALT ((uint32_t)0x20) // Halt DMA Operations
- #define DMA_CR_HOE ((uint32_t)0x10) // Halt On Error
- #define DMA_CR_ERCA ((uint32_t)0x04) // Enable Round Robin Channel Arbitration
- #define DMA_CR_EDBG ((uint32_t)0x02) // Enable Debug
- #define DMA_ES *(volatile uint32_t *)0x40008004 // Error Status Register
- #define DMA_ERQ *(volatile uint32_t *)0x4000800C // Enable Request Register
- #define DMA_ERQ_ERQ0 ((uint32_t)1<<0) // Enable DMA Request 0
- #define DMA_ERQ_ERQ1 ((uint32_t)1<<1) // Enable DMA Request 1
- #define DMA_ERQ_ERQ2 ((uint32_t)1<<2) // Enable DMA Request 2
- #define DMA_ERQ_ERQ3 ((uint32_t)1<<3) // Enable DMA Request 3
- #define DMA_EEI *(volatile uint32_t *)0x40008014 // Enable Error Interrupt Register
- #define DMA_EEI_EEI0 ((uint32_t)1<<0) // Enable Error Interrupt 0
- #define DMA_EEI_EEI1 ((uint32_t)1<<1) // Enable Error Interrupt 1
- #define DMA_EEI_EEI2 ((uint32_t)1<<2) // Enable Error Interrupt 2
- #define DMA_EEI_EEI3 ((uint32_t)1<<3) // Enable Error Interrupt 3
- #define DMA_CEEI *(volatile uint8_t *)0x40008018 // Clear Enable Error Interrupt Register
- #define DMA_CEEI_CEEI(n) ((uint8_t)(n & 3)<<0) // Clear Enable Error Interrupt
- #define DMA_CEEI_CAEE ((uint8_t)1<<6) // Clear All Enable Error Interrupts
- #define DMA_CEEI_NOP ((uint8_t)1<<7) // NOP
- #define DMA_SEEI *(volatile uint8_t *)0x40008019 // Set Enable Error Interrupt Register
- #define DMA_SEEI_SEEI(n) ((uint8_t)(n & 3)<<0) // Set Enable Error Interrupt
- #define DMA_SEEI_SAEE ((uint8_t)1<<6) // Set All Enable Error Interrupts
- #define DMA_SEEI_NOP ((uint8_t)1<<7) // NOP
- #define DMA_CERQ *(volatile uint8_t *)0x4000801A // Clear Enable Request Register
- #define DMA_CERQ_CERQ(n) ((uint8_t)(n & 3)<<0) // Clear Enable Request
- #define DMA_CERQ_CAER ((uint8_t)1<<6) // Clear All Enable Requests
- #define DMA_CERQ_NOP ((uint8_t)1<<7) // NOP
- #define DMA_SERQ *(volatile uint8_t *)0x4000801B // Set Enable Request Register
- #define DMA_SERQ_SERQ(n) ((uint8_t)(n & 3)<<0) // Set Enable Request
- #define DMA_SERQ_SAER ((uint8_t)1<<6) // Set All Enable Requests
- #define DMA_SERQ_NOP ((uint8_t)1<<7) // NOP
- #define DMA_CDNE *(volatile uint8_t *)0x4000801C // Clear DONE Status Bit Register
- #define DMA_CDNE_CDNE(n) ((uint8_t)(n & 3)<<0) // Clear Done Bit
- #define DMA_CDNE_CADN ((uint8_t)1<<6) // Clear All Done Bits
- #define DMA_CDNE_NOP ((uint8_t)1<<7) // NOP
- #define DMA_SSRT *(volatile uint8_t *)0x4000801D // Set START Bit Register
- #define DMA_SSRT_SSRT(n) ((uint8_t)(n & 3)<<0) // Set Start Bit
- #define DMA_SSRT_SAST ((uint8_t)1<<6) // Set All Start Bits
- #define DMA_SSRT_NOP ((uint8_t)1<<7) // NOP
- #define DMA_CERR *(volatile uint8_t *)0x4000801E // Clear Error Register
- #define DMA_CERR_CERR(n) ((uint8_t)(n & 3)<<0) // Clear Error Indicator
- #define DMA_CERR_CAEI ((uint8_t)1<<6) // Clear All Error Indicators
- #define DMA_CERR_NOP ((uint8_t)1<<7) // NOP
- #define DMA_CINT *(volatile uint8_t *)0x4000801F // Clear Interrupt Request Register
- #define DMA_CINT_CINT(n) ((uint8_t)(n & 3)<<0) // Clear Interrupt Request
- #define DMA_CINT_CAIR ((uint8_t)1<<6) // Clear All Interrupt Requests
- #define DMA_CINT_NOP ((uint8_t)1<<7) // NOP
- #define DMA_INT *(volatile uint32_t *)0x40008024 // Interrupt Request Register
- #define DMA_INT_INT0 ((uint32_t)1<<0) // Interrupt Request 0
- #define DMA_INT_INT1 ((uint32_t)1<<1) // Interrupt Request 1
- #define DMA_INT_INT2 ((uint32_t)1<<2) // Interrupt Request 2
- #define DMA_INT_INT3 ((uint32_t)1<<3) // Interrupt Request 3
- #define DMA_ERR *(volatile uint32_t *)0x4000802C // Error Register
- #define DMA_ERR_ERR0 ((uint32_t)1<<0) // Error in Channel 0
- #define DMA_ERR_ERR1 ((uint32_t)1<<1) // Error in Channel 1
- #define DMA_ERR_ERR2 ((uint32_t)1<<2) // Error in Channel 2
- #define DMA_ERR_ERR3 ((uint32_t)1<<3) // Error in Channel 3
- #define DMA_HRS *(volatile uint32_t *)0x40008034 // Hardware Request Status Register
- #define DMA_HRS_HRS0 ((uint32_t)1<<0) // Hardware Request Status Channel 0
- #define DMA_HRS_HRS1 ((uint32_t)1<<1) // Hardware Request Status Channel 1
- #define DMA_HRS_HRS2 ((uint32_t)1<<2) // Hardware Request Status Channel 2
- #define DMA_HRS_HRS3 ((uint32_t)1<<3) // Hardware Request Status Channel 3
- #define DMA_DCHPRI3 *(volatile uint8_t *)0x40008100 // Channel n Priority Register
- #define DMA_DCHPRI2 *(volatile uint8_t *)0x40008101 // Channel n Priority Register
- #define DMA_DCHPRI1 *(volatile uint8_t *)0x40008102 // Channel n Priority Register
- #define DMA_DCHPRI0 *(volatile uint8_t *)0x40008103 // Channel n Priority Register
- #define DMA_DCHPRI_CHPRI(n) ((uint8_t)(n & 3)<<0) // Channel Arbitration Priority
- #define DMA_DCHPRI_DPA ((uint8_t)1<<6) // Disable PreEmpt Ability
- #define DMA_DCHPRI_ECP ((uint8_t)1<<7) // Enable PreEmption
-
-
- #define DMA_TCD_ATTR_SMOD(n) (((n) & 0x1F) << 11)
- #define DMA_TCD_ATTR_SSIZE(n) (((n) & 0x7) << 8)
- #define DMA_TCD_ATTR_DMOD(n) (((n) & 0x1F) << 3)
- #define DMA_TCD_ATTR_DSIZE(n) (((n) & 0x7) << 0)
- #define DMA_TCD_ATTR_SIZE_8BIT 0
- #define DMA_TCD_ATTR_SIZE_16BIT 1
- #define DMA_TCD_ATTR_SIZE_32BIT 2
- #define DMA_TCD_ATTR_SIZE_16BYTE 4
- #define DMA_TCD_ATTR_SIZE_32BYTE 5
- #define DMA_TCD_CSR_BWC(n) (((n) & 0x3) << 14)
- #define DMA_TCD_CSR_MAJORLINKCH(n) (((n) & 0x3) << 8)
- #define DMA_TCD_CSR_DONE 0x0080
- #define DMA_TCD_CSR_ACTIVE 0x0040
- #define DMA_TCD_CSR_MAJORELINK 0x0020
- #define DMA_TCD_CSR_ESG 0x0010
- #define DMA_TCD_CSR_DREQ 0x0008
- #define DMA_TCD_CSR_INTHALF 0x0004
- #define DMA_TCD_CSR_INTMAJOR 0x0002
- #define DMA_TCD_CSR_START 0x0001
- #define DMA_TCD_CITER_MASK ((uint16_t)0x7FFF) // Loop count mask
- #define DMA_TCD_CITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete
- #define DMA_TCD_BITER_MASK ((uint16_t)0x7FFF) // Loop count mask
- #define DMA_TCD_BITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete
- #define DMA_TCD_NBYTES_SMLOE ((uint32_t)1<<31) // Source Minor Loop Offset Enable
- #define DMA_TCD_NBYTES_DMLOE ((uint32_t)1<<30) // Destination Minor Loop Offset Enable
- #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n) ((uint32_t)(n)) // NBytes transfer count when minor loop disabled
- #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(n) ((uint32_t)(n & 0x1F)) // NBytes transfer count when minor loop enabled
- #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n) ((uint32_t)(n & 0xFFFFF)<<10) // Offset
-
- #define DMA_TCD0_SADDR *(volatile const void * volatile *)0x40009000 // TCD Source Address
- #define DMA_TCD0_SOFF *(volatile int16_t *)0x40009004 // TCD Signed Source Address Offset
- #define DMA_TCD0_ATTR *(volatile uint16_t *)0x40009006 // TCD Transfer Attributes
- #define DMA_TCD0_NBYTES_MLNO *(volatile uint32_t *)0x40009008 // TCD Minor Byte Count (Minor Loop Disabled)
+ #define DMA_CR *(volatile uint32_t *)0x40008000 // Control Register
+ #define DMA_CR_CX ((uint32_t)(1<<17)) // Cancel Transfer
+ #define DMA_CR_ECX ((uint32_t)(1<<16)) // Error Cancel Transfer
+ #define DMA_CR_EMLM ((uint32_t)0x80) // Enable Minor Loop Mapping
+ #define DMA_CR_CLM ((uint32_t)0x40) // Continuous Link Mode
+ #define DMA_CR_HALT ((uint32_t)0x20) // Halt DMA Operations
+ #define DMA_CR_HOE ((uint32_t)0x10) // Halt On Error
+ #define DMA_CR_ERCA ((uint32_t)0x04) // Enable Round Robin Channel Arbitration
+ #define DMA_CR_EDBG ((uint32_t)0x02) // Enable Debug
+ #define DMA_ES *(volatile uint32_t *)0x40008004 // Error Status Register
+ #define DMA_ERQ *(volatile uint32_t *)0x4000800C // Enable Request Register
+ #define DMA_ERQ_ERQ0 ((uint32_t)1<<0) // Enable DMA Request 0
+ #define DMA_ERQ_ERQ1 ((uint32_t)1<<1) // Enable DMA Request 1
+ #define DMA_ERQ_ERQ2 ((uint32_t)1<<2) // Enable DMA Request 2
+ #define DMA_ERQ_ERQ3 ((uint32_t)1<<3) // Enable DMA Request 3
+ #define DMA_EEI *(volatile uint32_t *)0x40008014 // Enable Error Interrupt Register
+ #define DMA_EEI_EEI0 ((uint32_t)1<<0) // Enable Error Interrupt 0
+ #define DMA_EEI_EEI1 ((uint32_t)1<<1) // Enable Error Interrupt 1
+ #define DMA_EEI_EEI2 ((uint32_t)1<<2) // Enable Error Interrupt 2
+ #define DMA_EEI_EEI3 ((uint32_t)1<<3) // Enable Error Interrupt 3
+ #define DMA_CEEI *(volatile uint8_t *)0x40008018 // Clear Enable Error Interrupt Register
+ #define DMA_CEEI_CEEI(n) ((uint8_t)(n & 3)<<0) // Clear Enable Error Interrupt
+ #define DMA_CEEI_CAEE ((uint8_t)1<<6) // Clear All Enable Error Interrupts
+ #define DMA_CEEI_NOP ((uint8_t)1<<7) // NOP
+ #define DMA_SEEI *(volatile uint8_t *)0x40008019 // Set Enable Error Interrupt Register
+ #define DMA_SEEI_SEEI(n) ((uint8_t)(n & 3)<<0) // Set Enable Error Interrupt
+ #define DMA_SEEI_SAEE ((uint8_t)1<<6) // Set All Enable Error Interrupts
+ #define DMA_SEEI_NOP ((uint8_t)1<<7) // NOP
+ #define DMA_CERQ *(volatile uint8_t *)0x4000801A // Clear Enable Request Register
+ #define DMA_CERQ_CERQ(n) ((uint8_t)(n & 3)<<0) // Clear Enable Request
+ #define DMA_CERQ_CAER ((uint8_t)1<<6) // Clear All Enable Requests
+ #define DMA_CERQ_NOP ((uint8_t)1<<7) // NOP
+ #define DMA_SERQ *(volatile uint8_t *)0x4000801B // Set Enable Request Register
+ #define DMA_SERQ_SERQ(n) ((uint8_t)(n & 3)<<0) // Set Enable Request
+ #define DMA_SERQ_SAER ((uint8_t)1<<6) // Set All Enable Requests
+ #define DMA_SERQ_NOP ((uint8_t)1<<7) // NOP
+ #define DMA_CDNE *(volatile uint8_t *)0x4000801C // Clear DONE Status Bit Register
+ #define DMA_CDNE_CDNE(n) ((uint8_t)(n & 3)<<0) // Clear Done Bit
+ #define DMA_CDNE_CADN ((uint8_t)1<<6) // Clear All Done Bits
+ #define DMA_CDNE_NOP ((uint8_t)1<<7) // NOP
+ #define DMA_SSRT *(volatile uint8_t *)0x4000801D // Set START Bit Register
+ #define DMA_SSRT_SSRT(n) ((uint8_t)(n & 3)<<0) // Set Start Bit
+ #define DMA_SSRT_SAST ((uint8_t)1<<6) // Set All Start Bits
+ #define DMA_SSRT_NOP ((uint8_t)1<<7) // NOP
+ #define DMA_CERR *(volatile uint8_t *)0x4000801E // Clear Error Register
+ #define DMA_CERR_CERR(n) ((uint8_t)(n & 3)<<0) // Clear Error Indicator
+ #define DMA_CERR_CAEI ((uint8_t)1<<6) // Clear All Error Indicators
+ #define DMA_CERR_NOP ((uint8_t)1<<7) // NOP
+ #define DMA_CINT *(volatile uint8_t *)0x4000801F // Clear Interrupt Request Register
+ #define DMA_CINT_CINT(n) ((uint8_t)(n & 3)<<0) // Clear Interrupt Request
+ #define DMA_CINT_CAIR ((uint8_t)1<<6) // Clear All Interrupt Requests
+ #define DMA_CINT_NOP ((uint8_t)1<<7) // NOP
+ #define DMA_INT *(volatile uint32_t *)0x40008024 // Interrupt Request Register
+ #define DMA_INT_INT0 ((uint32_t)1<<0) // Interrupt Request 0
+ #define DMA_INT_INT1 ((uint32_t)1<<1) // Interrupt Request 1
+ #define DMA_INT_INT2 ((uint32_t)1<<2) // Interrupt Request 2
+ #define DMA_INT_INT3 ((uint32_t)1<<3) // Interrupt Request 3
+ #define DMA_ERR *(volatile uint32_t *)0x4000802C // Error Register
+ #define DMA_ERR_ERR0 ((uint32_t)1<<0) // Error in Channel 0
+ #define DMA_ERR_ERR1 ((uint32_t)1<<1) // Error in Channel 1
+ #define DMA_ERR_ERR2 ((uint32_t)1<<2) // Error in Channel 2
+ #define DMA_ERR_ERR3 ((uint32_t)1<<3) // Error in Channel 3
+ #define DMA_HRS *(volatile uint32_t *)0x40008034 // Hardware Request Status Register
+ #define DMA_HRS_HRS0 ((uint32_t)1<<0) // Hardware Request Status Channel 0
+ #define DMA_HRS_HRS1 ((uint32_t)1<<1) // Hardware Request Status Channel 1
+ #define DMA_HRS_HRS2 ((uint32_t)1<<2) // Hardware Request Status Channel 2
+ #define DMA_HRS_HRS3 ((uint32_t)1<<3) // Hardware Request Status Channel 3
+ #define DMA_DCHPRI3 *(volatile uint8_t *)0x40008100 // Channel n Priority Register
+ #define DMA_DCHPRI2 *(volatile uint8_t *)0x40008101 // Channel n Priority Register
+ #define DMA_DCHPRI1 *(volatile uint8_t *)0x40008102 // Channel n Priority Register
+ #define DMA_DCHPRI0 *(volatile uint8_t *)0x40008103 // Channel n Priority Register
+ #define DMA_DCHPRI_CHPRI(n) ((uint8_t)(n & 3)<<0) // Channel Arbitration Priority
+ #define DMA_DCHPRI_DPA ((uint8_t)1<<6) // Disable PreEmpt Ability
+ #define DMA_DCHPRI_ECP ((uint8_t)1<<7) // Enable PreEmption
+
+
+ #define DMA_TCD_ATTR_SMOD(n) (((n) & 0x1F) << 11)
+ #define DMA_TCD_ATTR_SSIZE(n) (((n) & 0x7) << 8)
+ #define DMA_TCD_ATTR_DMOD(n) (((n) & 0x1F) << 3)
+ #define DMA_TCD_ATTR_DSIZE(n) (((n) & 0x7) << 0)
+ #define DMA_TCD_ATTR_SIZE_8BIT 0
+ #define DMA_TCD_ATTR_SIZE_16BIT 1
+ #define DMA_TCD_ATTR_SIZE_32BIT 2
+ #define DMA_TCD_ATTR_SIZE_16BYTE 4
+ #define DMA_TCD_ATTR_SIZE_32BYTE 5
+ #define DMA_TCD_CSR_BWC(n) (((n) & 0x3) << 14)
+ #define DMA_TCD_CSR_MAJORLINKCH(n) (((n) & 0x3) << 8)
+ #define DMA_TCD_CSR_DONE 0x0080
+ #define DMA_TCD_CSR_ACTIVE 0x0040
+ #define DMA_TCD_CSR_MAJORELINK 0x0020
+ #define DMA_TCD_CSR_ESG 0x0010
+ #define DMA_TCD_CSR_DREQ 0x0008
+ #define DMA_TCD_CSR_INTHALF 0x0004
+ #define DMA_TCD_CSR_INTMAJOR 0x0002
+ #define DMA_TCD_CSR_START 0x0001
+ #define DMA_TCD_CITER_MASK ((uint16_t)0x7FFF) // Loop count mask
+ #define DMA_TCD_CITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete
+ #define DMA_TCD_BITER_MASK ((uint16_t)0x7FFF) // Loop count mask
+ #define DMA_TCD_BITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete
+ #define DMA_TCD_NBYTES_SMLOE ((uint32_t)1<<31) // Source Minor Loop Offset Enable
+ #define DMA_TCD_NBYTES_DMLOE ((uint32_t)1<<30) // Destination Minor Loop Offset Enable
+ #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n) ((uint32_t)(n)) // NBytes transfer count when minor loop disabled
+ #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(n) ((uint32_t)(n & 0x1F)) // NBytes transfer count when minor loop enabled
-#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n) ((uint32_t)(n & 0xFFFFF)<<10) // Offset
++#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n) ((uint32_t)(n & 0xFFFFF)<<10) // Offset
+
+ #define DMA_TCD0_SADDR *(volatile const void * volatile *)0x40009000 // TCD Source Address
+ #define DMA_TCD0_SOFF *(volatile int16_t *)0x40009004 // TCD Signed Source Address Offset
+ #define DMA_TCD0_ATTR *(volatile uint16_t *)0x40009006 // TCD Transfer Attributes
+ #define DMA_TCD0_NBYTES_MLNO *(volatile uint32_t *)0x40009008 // TCD Minor Byte Count (Minor Loop Disabled)
#define DMA_TCD0_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
#define DMA_TCD0_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
- #define DMA_TCD0_SLAST *(volatile int32_t *)0x4000900C // TCD Last Source Address Adjustment
- #define DMA_TCD0_DADDR *(volatile void * volatile *)0x40009010 // TCD Destination Address
- #define DMA_TCD0_DOFF *(volatile int16_t *)0x40009014 // TCD Signed Destination Address Offset
+ #define DMA_TCD0_SLAST *(volatile int32_t *)0x4000900C // TCD Last Source Address Adjustment
+ #define DMA_TCD0_DADDR *(volatile void * volatile *)0x40009010 // TCD Destination Address
+ #define DMA_TCD0_DOFF *(volatile int16_t *)0x40009014 // TCD Signed Destination Address Offset
#define DMA_TCD0_CITER_ELINKYES *(volatile uint16_t *)0x40009016 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
- #define DMA_TCD0_CITER_ELINKNO *(volatile uint16_t *)0x40009016 // ??
- #define DMA_TCD0_DLASTSGA *(volatile int32_t *)0x40009018 // TCD Last Destination Address Adjustment/Scatter Gather Address
- #define DMA_TCD0_CSR *(volatile uint16_t *)0x4000901C // TCD Control and Status
+ #define DMA_TCD0_CITER_ELINKNO *(volatile uint16_t *)0x40009016 // ??
+ #define DMA_TCD0_DLASTSGA *(volatile int32_t *)0x40009018 // TCD Last Destination Address Adjustment/Scatter Gather Address
+ #define DMA_TCD0_CSR *(volatile uint16_t *)0x4000901C // TCD Control and Status
#define DMA_TCD0_BITER_ELINKYES *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
- #define DMA_TCD0_BITER_ELINKNO *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
+ #define DMA_TCD0_BITER_ELINKNO *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
- #define DMA_TCD1_SADDR *(volatile const void * volatile *)0x40009020 // TCD Source Address
- #define DMA_TCD1_SOFF *(volatile int16_t *)0x40009024 // TCD Signed Source Address Offset
- #define DMA_TCD1_ATTR *(volatile uint16_t *)0x40009026 // TCD Transfer Attributes
- #define DMA_TCD1_NBYTES_MLNO *(volatile uint32_t *)0x40009028 // TCD Minor Byte Count, Minor Loop Disabled
+ #define DMA_TCD1_SADDR *(volatile const void * volatile *)0x40009020 // TCD Source Address
+ #define DMA_TCD1_SOFF *(volatile int16_t *)0x40009024 // TCD Signed Source Address Offset
+ #define DMA_TCD1_ATTR *(volatile uint16_t *)0x40009026 // TCD Transfer Attributes
+ #define DMA_TCD1_NBYTES_MLNO *(volatile uint32_t *)0x40009028 // TCD Minor Byte Count, Minor Loop Disabled
#define DMA_TCD1_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
#define DMA_TCD1_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
- #define DMA_TCD1_SLAST *(volatile int32_t *)0x4000902C // TCD Last Source Address Adjustment
- #define DMA_TCD1_DADDR *(volatile void * volatile *)0x40009030 // TCD Destination Address
- #define DMA_TCD1_DOFF *(volatile int16_t *)0x40009034 // TCD Signed Destination Address Offset
+ #define DMA_TCD1_SLAST *(volatile int32_t *)0x4000902C // TCD Last Source Address Adjustment
+ #define DMA_TCD1_DADDR *(volatile void * volatile *)0x40009030 // TCD Destination Address
+ #define DMA_TCD1_DOFF *(volatile int16_t *)0x40009034 // TCD Signed Destination Address Offset
#define DMA_TCD1_CITER_ELINKYES *(volatile uint16_t *)0x40009036 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
- #define DMA_TCD1_CITER_ELINKNO *(volatile uint16_t *)0x40009036 // ??
- #define DMA_TCD1_DLASTSGA *(volatile int32_t *)0x40009038 // TCD Last Destination Address Adjustment/Scatter Gather Address
- #define DMA_TCD1_CSR *(volatile uint16_t *)0x4000903C // TCD Control and Status
+ #define DMA_TCD1_CITER_ELINKNO *(volatile uint16_t *)0x40009036 // ??
+ #define DMA_TCD1_DLASTSGA *(volatile int32_t *)0x40009038 // TCD Last Destination Address Adjustment/Scatter Gather Address
+ #define DMA_TCD1_CSR *(volatile uint16_t *)0x4000903C // TCD Control and Status
#define DMA_TCD1_BITER_ELINKYES *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled
- #define DMA_TCD1_BITER_ELINKNO *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
+ #define DMA_TCD1_BITER_ELINKNO *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
- #define DMA_TCD2_SADDR *(volatile const void * volatile *)0x40009040 // TCD Source Address
- #define DMA_TCD2_SOFF *(volatile int16_t *)0x40009044 // TCD Signed Source Address Offset
- #define DMA_TCD2_ATTR *(volatile uint16_t *)0x40009046 // TCD Transfer Attributes
- #define DMA_TCD2_NBYTES_MLNO *(volatile uint32_t *)0x40009048 // TCD Minor Byte Count, Minor Loop Disabled
+ #define DMA_TCD2_SADDR *(volatile const void * volatile *)0x40009040 // TCD Source Address
+ #define DMA_TCD2_SOFF *(volatile int16_t *)0x40009044 // TCD Signed Source Address Offset
+ #define DMA_TCD2_ATTR *(volatile uint16_t *)0x40009046 // TCD Transfer Attributes
+ #define DMA_TCD2_NBYTES_MLNO *(volatile uint32_t *)0x40009048 // TCD Minor Byte Count, Minor Loop Disabled
#define DMA_TCD2_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
#define DMA_TCD2_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
- #define DMA_TCD2_SLAST *(volatile int32_t *)0x4000904C // TCD Last Source Address Adjustment
- #define DMA_TCD2_DADDR *(volatile void * volatile *)0x40009050 // TCD Destination Address
- #define DMA_TCD2_DOFF *(volatile int16_t *)0x40009054 // TCD Signed Destination Address Offset
+ #define DMA_TCD2_SLAST *(volatile int32_t *)0x4000904C // TCD Last Source Address Adjustment
+ #define DMA_TCD2_DADDR *(volatile void * volatile *)0x40009050 // TCD Destination Address
+ #define DMA_TCD2_DOFF *(volatile int16_t *)0x40009054 // TCD Signed Destination Address Offset
#define DMA_TCD2_CITER_ELINKYES *(volatile uint16_t *)0x40009056 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
- #define DMA_TCD2_CITER_ELINKNO *(volatile uint16_t *)0x40009056 // ??
- #define DMA_TCD2_DLASTSGA *(volatile int32_t *)0x40009058 // TCD Last Destination Address Adjustment/Scatter Gather Address
- #define DMA_TCD2_CSR *(volatile uint16_t *)0x4000905C // TCD Control and Status
+ #define DMA_TCD2_CITER_ELINKNO *(volatile uint16_t *)0x40009056 // ??
+ #define DMA_TCD2_DLASTSGA *(volatile int32_t *)0x40009058 // TCD Last Destination Address Adjustment/Scatter Gather Address
+ #define DMA_TCD2_CSR *(volatile uint16_t *)0x4000905C // TCD Control and Status
#define DMA_TCD2_BITER_ELINKYES *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
- #define DMA_TCD2_BITER_ELINKNO *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
+ #define DMA_TCD2_BITER_ELINKNO *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
- #define DMA_TCD3_SADDR *(volatile const void * volatile *)0x40009060 // TCD Source Address
- #define DMA_TCD3_SOFF *(volatile int16_t *)0x40009064 // TCD Signed Source Address Offset
- #define DMA_TCD3_ATTR *(volatile uint16_t *)0x40009066 // TCD Transfer Attributes
- #define DMA_TCD3_NBYTES_MLNO *(volatile uint32_t *)0x40009068 // TCD Minor Byte Count, Minor Loop Disabled
+ #define DMA_TCD3_SADDR *(volatile const void * volatile *)0x40009060 // TCD Source Address
+ #define DMA_TCD3_SOFF *(volatile int16_t *)0x40009064 // TCD Signed Source Address Offset
+ #define DMA_TCD3_ATTR *(volatile uint16_t *)0x40009066 // TCD Transfer Attributes
+ #define DMA_TCD3_NBYTES_MLNO *(volatile uint32_t *)0x40009068 // TCD Minor Byte Count, Minor Loop Disabled
#define DMA_TCD3_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
#define DMA_TCD3_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
- #define DMA_TCD3_SLAST *(volatile int32_t *)0x4000906C // TCD Last Source Address Adjustment
- #define DMA_TCD3_DADDR *(volatile void * volatile *)0x40009070 // TCD Destination Address
- #define DMA_TCD3_DOFF *(volatile int16_t *)0x40009074 // TCD Signed Destination Address Offset
+ #define DMA_TCD3_SLAST *(volatile int32_t *)0x4000906C // TCD Last Source Address Adjustment
+ #define DMA_TCD3_DADDR *(volatile void * volatile *)0x40009070 // TCD Destination Address
+ #define DMA_TCD3_DOFF *(volatile int16_t *)0x40009074 // TCD Signed Destination Address Offset
#define DMA_TCD3_CITER_ELINKYES *(volatile uint16_t *)0x40009076 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
- #define DMA_TCD3_CITER_ELINKNO *(volatile uint16_t *)0x40009076 // ??
- #define DMA_TCD3_DLASTSGA *(volatile int32_t *)0x40009078 // TCD Last Destination Address Adjustment/Scatter Gather Address
- #define DMA_TCD3_CSR *(volatile uint16_t *)0x4000907C // TCD Control and Status
+ #define DMA_TCD3_CITER_ELINKNO *(volatile uint16_t *)0x40009076 // ??
+ #define DMA_TCD3_DLASTSGA *(volatile int32_t *)0x40009078 // TCD Last Destination Address Adjustment/Scatter Gather Address
+ #define DMA_TCD3_CSR *(volatile uint16_t *)0x4000907C // TCD Control and Status
#define DMA_TCD3_BITER_ELINKYES *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled
- #define DMA_TCD3_BITER_ELINKNO *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled
+ #define DMA_TCD3_BITER_ELINKNO *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled
// Chapter 22: External Watchdog Monitor (EWM)
#define EWM_CTRL *(volatile uint8_t *)0x40061000 // Control Register
// Chapter 24: Multipurpose Clock Generator (MCG)
#define MCG_C1 *(volatile uint8_t *)0x40064000 // MCG Control 1 Register
- #define MCG_C1_IREFSTEN (uint8_t)0x01 // Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.
- #define MCG_C1_IRCLKEN (uint8_t)0x02 // Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK.
- #define MCG_C1_IREFS (uint8_t)0x04 // Internal Reference Select, Selects the reference clock source for the FLL.
- #define MCG_C1_FRDIV(n) (uint8_t)(((n) & 0x07) << 3) // FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL
- #define MCG_C1_CLKS(n) (uint8_t)(((n) & 0x03) << 6) // Clock Source Select, Selects the clock source for MCGOUTCLK
+ #define MCG_C1_IREFSTEN (uint8_t)0x01 // Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.
+ #define MCG_C1_IRCLKEN (uint8_t)0x02 // Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK.
+ #define MCG_C1_IREFS (uint8_t)0x04 // Internal Reference Select, Selects the reference clock source for the FLL.
+ #define MCG_C1_FRDIV(n) (uint8_t)(((n) & 0x07) << 3) // FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL
+ #define MCG_C1_CLKS(n) (uint8_t)(((n) & 0x03) << 6) // Clock Source Select, Selects the clock source for MCGOUTCLK
#define MCG_C2 *(volatile uint8_t *)0x40064001 // MCG Control 2 Register
- #define MCG_C2_IRCS (uint8_t)0x01 // Internal Reference Clock Select, Selects between the fast or slow internal reference clock source.
- #define MCG_C2_LP (uint8_t)0x02 // Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes.
- #define MCG_C2_EREFS (uint8_t)0x04 // External Reference Select, Selects the source for the external reference clock.
- #define MCG_C2_HGO0 (uint8_t)0x08 // High Gain Oscillator Select, Controls the crystal oscillator mode of operation
- #define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator
- #define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
+ #define MCG_C2_IRCS (uint8_t)0x01 // Internal Reference Clock Select, Selects between the fast or slow internal reference clock source.
+ #define MCG_C2_LP (uint8_t)0x02 // Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes.
+ #define MCG_C2_EREFS (uint8_t)0x04 // External Reference Select, Selects the source for the external reference clock.
+ #define MCG_C2_HGO0 (uint8_t)0x08 // High Gain Oscillator Select, Controls the crystal oscillator mode of operation
+ #define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator
-#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
++#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
#define MCG_C3 *(volatile uint8_t *)0x40064002 // MCG Control 3 Register
- #define MCG_C3_SCTRIM(n) (uint8_t)(n) // Slow Internal Reference Clock Trim Setting
+ #define MCG_C3_SCTRIM(n) (uint8_t)(n) // Slow Internal Reference Clock Trim Setting
#define MCG_C4 *(volatile uint8_t *)0x40064003 // MCG Control 4 Register
- #define MCG_C4_SCFTRIM (uint8_t)0x01 // Slow Internal Reference Clock Fine Trim
- #define MCG_C4_FCTRIM(n) (uint8_t)(((n) & 0x0F) << 1) // Fast Internal Reference Clock Trim Setting
- #define MCG_C4_DRST_DRS(n) (uint8_t)(((n) & 0x03) << 5) // DCO Range Select
- #define MCG_C4_DMX32 (uint8_t)0x80 // DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed
+ #define MCG_C4_SCFTRIM (uint8_t)0x01 // Slow Internal Reference Clock Fine Trim
+ #define MCG_C4_FCTRIM(n) (uint8_t)(((n) & 0x0F) << 1) // Fast Internal Reference Clock Trim Setting
+ #define MCG_C4_DRST_DRS(n) (uint8_t)(((n) & 0x03) << 5) // DCO Range Select
+ #define MCG_C4_DMX32 (uint8_t)0x80 // DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed
#define MCG_C5 *(volatile uint8_t *)0x40064004 // MCG Control 5 Register
- #define MCG_C5_PRDIV0(n) (uint8_t)((n) & 0x1F) // PLL External Reference Divider
- #define MCG_C5_PLLSTEN0 (uint8_t)0x20 // PLL Stop Enable
- #define MCG_C5_PLLCLKEN0 (uint8_t)0x40 // PLL Clock Enable
+ #define MCG_C5_PRDIV0(n) (uint8_t)((n) & 0x1F) // PLL External Reference Divider
+ #define MCG_C5_PLLSTEN0 (uint8_t)0x20 // PLL Stop Enable
+ #define MCG_C5_PLLCLKEN0 (uint8_t)0x40 // PLL Clock Enable
#define MCG_C6 *(volatile uint8_t *)0x40064005 // MCG Control 6 Register
- #define MCG_C6_VDIV0(n) (uint8_t)((n) & 0x1F) // VCO 0 Divider
- #define MCG_C6_CME0 (uint8_t)0x20 // Clock Monitor Enable
- #define MCG_C6_PLLS (uint8_t)0x40 // PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00.
- #define MCG_C6_LOLIE0 (uint8_t)0x80 // Loss of Lock Interrrupt Enable
+ #define MCG_C6_VDIV0(n) (uint8_t)((n) & 0x1F) // VCO 0 Divider
+ #define MCG_C6_CME0 (uint8_t)0x20 // Clock Monitor Enable
+ #define MCG_C6_PLLS (uint8_t)0x40 // PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00.
+ #define MCG_C6_LOLIE0 (uint8_t)0x80 // Loss of Lock Interrrupt Enable
#define MCG_S *(volatile uint8_t *)0x40064006 // MCG Status Register
- #define MCG_S_IRCST (uint8_t)0x01 // Internal Reference Clock Status
- #define MCG_S_OSCINIT0 (uint8_t)0x02 // OSC Initialization, resets to 0, is set to 1 after the initialization cycles of the crystal oscillator
- #define MCG_S_CLKST(n) (uint8_t)(((n) & 0x03) << 2) // Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL
- #define MCG_S_CLKST_MASK (uint8_t)0x0C
- #define MCG_S_IREFST (uint8_t)0x10 // Internal Reference Status
- #define MCG_S_PLLST (uint8_t)0x20 // PLL Select Status
- #define MCG_S_LOCK0 (uint8_t)0x40 // Lock Status, 0=PLL Unlocked, 1=PLL Locked
- #define MCG_S_LOLS0 (uint8_t)0x80 // Loss of Lock Status
+ #define MCG_S_IRCST (uint8_t)0x01 // Internal Reference Clock Status
+ #define MCG_S_OSCINIT0 (uint8_t)0x02 // OSC Initialization, resets to 0, is set to 1 after the initialization cycles of the crystal oscillator
+ #define MCG_S_CLKST(n) (uint8_t)(((n) & 0x03) << 2) // Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL
+ #define MCG_S_CLKST_MASK (uint8_t)0x0C
+ #define MCG_S_IREFST (uint8_t)0x10 // Internal Reference Status
+ #define MCG_S_PLLST (uint8_t)0x20 // PLL Select Status
+ #define MCG_S_LOCK0 (uint8_t)0x40 // Lock Status, 0=PLL Unlocked, 1=PLL Locked
+ #define MCG_S_LOLS0 (uint8_t)0x80 // Loss of Lock Status
#define MCG_SC *(volatile uint8_t *)0x40064008 // MCG Status and Control Register
- #define MCG_SC_LOCS0 (uint8_t)0x01 // OSC0 Loss of Clock Status
- #define MCG_SC_FCRDIV(n) (uint8_t)(((n) & 0x07) << 1) // Fast Clock Internal Reference Divider
- #define MCG_SC_FLTPRSRV (uint8_t)0x10 // FLL Filter Preserve Enable
- #define MCG_SC_ATMF (uint8_t)0x20 // Automatic Trim Machine Fail Flag
- #define MCG_SC_ATMS (uint8_t)0x40 // Automatic Trim Machine Select
- #define MCG_SC_ATME (uint8_t)0x80 // Automatic Trim Machine Enable
+ #define MCG_SC_LOCS0 (uint8_t)0x01 // OSC0 Loss of Clock Status
+ #define MCG_SC_FCRDIV(n) (uint8_t)(((n) & 0x07) << 1) // Fast Clock Internal Reference Divider
+ #define MCG_SC_FLTPRSRV (uint8_t)0x10 // FLL Filter Preserve Enable
+ #define MCG_SC_ATMF (uint8_t)0x20 // Automatic Trim Machine Fail Flag
+ #define MCG_SC_ATMS (uint8_t)0x40 // Automatic Trim Machine Select
+ #define MCG_SC_ATME (uint8_t)0x80 // Automatic Trim Machine Enable
#define MCG_ATCVH *(volatile uint8_t *)0x4006400A // MCG Auto Trim Compare Value High Register
#define MCG_ATCVL *(volatile uint8_t *)0x4006400B // MCG Auto Trim Compare Value Low Register
#define MCG_C7 *(volatile uint8_t *)0x4006400C // MCG Control 7 Register
#define ADC0_CV1 *(volatile uint32_t *)0x4003B018 // Compare value registers
#define ADC0_CV2 *(volatile uint32_t *)0x4003B01C // Compare value registers
#define ADC0_SC2 *(volatile uint32_t *)0x4003B020 // Status and control register 2
- #define ADC_SC2_ADACT (uint32_t)0x80 // Conversion active
- #define ADC_SC2_ADTRG (uint32_t)0x40 // Conversion trigger select, 0=software, 1=hardware
- #define ADC_SC2_ACFE (uint32_t)0x20 // Compare function enable
- #define ADC_SC2_ACFGT (uint32_t)0x10 // Compare function greater than enable
- #define ADC_SC2_ACREN (uint32_t)0x08 // Compare function range enable
- #define ADC_SC2_DMAEN (uint32_t)0x04 // DMA enable
- #define ADC_SC2_REFSEL(n) (uint32_t)(((n) & 3) << 0) // Voltage reference, 0=vcc/external, 1=1.2 volts
+ #define ADC_SC2_ADACT (uint32_t)0x80 // Conversion active
+ #define ADC_SC2_ADTRG (uint32_t)0x40 // Conversion trigger select, 0=software, 1=hardware
+ #define ADC_SC2_ACFE (uint32_t)0x20 // Compare function enable
+ #define ADC_SC2_ACFGT (uint32_t)0x10 // Compare function greater than enable
+ #define ADC_SC2_ACREN (uint32_t)0x08 // Compare function range enable
+ #define ADC_SC2_DMAEN (uint32_t)0x04 // DMA enable
+ #define ADC_SC2_REFSEL(n) (uint32_t)(((n) & 3) << 0) // Voltage reference, 0=vcc/external, 1=1.2 volts
#define ADC0_SC3 *(volatile uint32_t *)0x4003B024 // Status and control register 3
- #define ADC_SC3_CAL (uint32_t)0x80 // Calibration, 1=begin, stays set while cal in progress
- #define ADC_SC3_CALF (uint32_t)0x40 // Calibration failed flag
- #define ADC_SC3_ADCO (uint32_t)0x08 // Continuous conversion enable
- #define ADC_SC3_AVGE (uint32_t)0x04 // Hardware average enable
- #define ADC_SC3_AVGS(n) (uint32_t)(((n) & 3) << 0) // avg select, 0=4 samples, 1=8 samples, 2=16 samples, 3=32 samples
- #define ADC0_OFS *(volatile uint32_t *)0x4003B028 // ADC offset correction register
- #define ADC0_PG *(volatile uint32_t *)0x4003B02C // ADC plus-side gain register
- #define ADC0_MG *(volatile uint32_t *)0x4003B030 // ADC minus-side gain register
- #define ADC0_CLPD *(volatile uint32_t *)0x4003B034 // ADC plus-side general calibration value register
- #define ADC0_CLPS *(volatile uint32_t *)0x4003B038 // ADC plus-side general calibration value register
- #define ADC0_CLP4 *(volatile uint32_t *)0x4003B03C // ADC plus-side general calibration value register
- #define ADC0_CLP3 *(volatile uint32_t *)0x4003B040 // ADC plus-side general calibration value register
- #define ADC0_CLP2 *(volatile uint32_t *)0x4003B044 // ADC plus-side general calibration value register
- #define ADC0_CLP1 *(volatile uint32_t *)0x4003B048 // ADC plus-side general calibration value register
- #define ADC0_CLP0 *(volatile uint32_t *)0x4003B04C // ADC plus-side general calibration value register
- #define ADC0_CLMD *(volatile uint32_t *)0x4003B054 // ADC minus-side general calibration value register
- #define ADC0_CLMS *(volatile uint32_t *)0x4003B058 // ADC minus-side general calibration value register
- #define ADC0_CLM4 *(volatile uint32_t *)0x4003B05C // ADC minus-side general calibration value register
- #define ADC0_CLM3 *(volatile uint32_t *)0x4003B060 // ADC minus-side general calibration value register
- #define ADC0_CLM2 *(volatile uint32_t *)0x4003B064 // ADC minus-side general calibration value register
- #define ADC0_CLM1 *(volatile uint32_t *)0x4003B068 // ADC minus-side general calibration value register
- #define ADC0_CLM0 *(volatile uint32_t *)0x4003B06C // ADC minus-side general calibration value register
-
- #define ADC1_SC1A *(volatile uint32_t *)0x400BB000 // ADC status and control registers 1
- #define ADC1_SC1B *(volatile uint32_t *)0x400BB004 // ADC status and control registers 1
- #define ADC1_CFG1 *(volatile uint32_t *)0x400BB008 // ADC configuration register 1
- #define ADC1_CFG2 *(volatile uint32_t *)0x400BB00C // Configuration register 2
- #define ADC1_RA *(volatile uint32_t *)0x400BB010 // ADC data result register
- #define ADC1_RB *(volatile uint32_t *)0x400BB014 // ADC data result register
- #define ADC1_CV1 *(volatile uint32_t *)0x400BB018 // Compare value registers
- #define ADC1_CV2 *(volatile uint32_t *)0x400BB01C // Compare value registers
- #define ADC1_SC2 *(volatile uint32_t *)0x400BB020 // Status and control register 2
- #define ADC1_SC3 *(volatile uint32_t *)0x400BB024 // Status and control register 3
- #define ADC1_OFS *(volatile uint32_t *)0x400BB028 // ADC offset correction register
- #define ADC1_PG *(volatile uint32_t *)0x400BB02C // ADC plus-side gain register
- #define ADC1_MG *(volatile uint32_t *)0x400BB030 // ADC minus-side gain register
- #define ADC1_CLPD *(volatile uint32_t *)0x400BB034 // ADC plus-side general calibration value register
- #define ADC1_CLPS *(volatile uint32_t *)0x400BB038 // ADC plus-side general calibration value register
- #define ADC1_CLP4 *(volatile uint32_t *)0x400BB03C // ADC plus-side general calibration value register
- #define ADC1_CLP3 *(volatile uint32_t *)0x400BB040 // ADC plus-side general calibration value register
- #define ADC1_CLP2 *(volatile uint32_t *)0x400BB044 // ADC plus-side general calibration value register
- #define ADC1_CLP1 *(volatile uint32_t *)0x400BB048 // ADC plus-side general calibration value register
- #define ADC1_CLP0 *(volatile uint32_t *)0x400BB04C // ADC plus-side general calibration value register
- #define ADC1_CLMD *(volatile uint32_t *)0x400BB054 // ADC minus-side general calibration value register
- #define ADC1_CLMS *(volatile uint32_t *)0x400BB058 // ADC minus-side general calibration value register
- #define ADC1_CLM4 *(volatile uint32_t *)0x400BB05C // ADC minus-side general calibration value register
- #define ADC1_CLM3 *(volatile uint32_t *)0x400BB060 // ADC minus-side general calibration value register
- #define ADC1_CLM2 *(volatile uint32_t *)0x400BB064 // ADC minus-side general calibration value register
- #define ADC1_CLM1 *(volatile uint32_t *)0x400BB068 // ADC minus-side general calibration value register
- #define ADC1_CLM0 *(volatile uint32_t *)0x400BB06C // ADC minus-side general calibration value register
-
- #define DAC0_DAT0L *(volatile uint8_t *)0x400CC000 // DAC Data Low Register
- #define DAC0_DATH *(volatile uint8_t *)0x400CC001 // DAC Data High Register
- #define DAC0_DAT1L *(volatile uint8_t *)0x400CC002 // DAC Data Low Register
- #define DAC0_DAT2L *(volatile uint8_t *)0x400CC004 // DAC Data Low Register
- #define DAC0_DAT3L *(volatile uint8_t *)0x400CC006 // DAC Data Low Register
- #define DAC0_DAT4L *(volatile uint8_t *)0x400CC008 // DAC Data Low Register
- #define DAC0_DAT5L *(volatile uint8_t *)0x400CC00A // DAC Data Low Register
- #define DAC0_DAT6L *(volatile uint8_t *)0x400CC00C // DAC Data Low Register
- #define DAC0_DAT7L *(volatile uint8_t *)0x400CC00E // DAC Data Low Register
- #define DAC0_DAT8L *(volatile uint8_t *)0x400CC010 // DAC Data Low Register
- #define DAC0_DAT9L *(volatile uint8_t *)0x400CC012 // DAC Data Low Register
- #define DAC0_DAT10L *(volatile uint8_t *)0x400CC014 // DAC Data Low Register
- #define DAC0_DAT11L *(volatile uint8_t *)0x400CC016 // DAC Data Low Register
- #define DAC0_DAT12L *(volatile uint8_t *)0x400CC018 // DAC Data Low Register
- #define DAC0_DAT13L *(volatile uint8_t *)0x400CC01A // DAC Data Low Register
- #define DAC0_DAT14L *(volatile uint8_t *)0x400CC01C // DAC Data Low Register
- #define DAC0_DAT15L *(volatile uint8_t *)0x400CC01E // DAC Data Low Register
- #define DAC0_SR *(volatile uint8_t *)0x400CC020 // DAC Status Register
- #define DAC0_C0 *(volatile uint8_t *)0x400CC021 // DAC Control Register
- #define DAC_C0_DACEN 0x80 // DAC Enable
- #define DAC_C0_DACRFS 0x40 // DAC Reference Select
- #define DAC_C0_DACTRGSEL 0x20 // DAC Trigger Select
- #define DAC_C0_DACSWTRG 0x10 // DAC Software Trigger
- #define DAC_C0_LPEN 0x08 // DAC Low Power Control
- #define DAC_C0_DACBWIEN 0x04 // DAC Buffer Watermark Interrupt Enable
- #define DAC_C0_DACBTIEN 0x02 // DAC Buffer Read Pointer Top Flag Interrupt Enable
- #define DAC_C0_DACBBIEN 0x01 // DAC Buffer Read Pointer Bottom Flag Interrupt Enable
- #define DAC0_C1 *(volatile uint8_t *)0x400CC022 // DAC Control Register 1
- #define DAC_C1_DMAEN 0x80 // DMA Enable Select
- #define DAC_C1_DACBFWM(n) (((n) & 3) << 3) // DAC Buffer Watermark Select
- #define DAC_C1_DACBFMD(n) (((n) & 3) << 0) // DAC Buffer Work Mode Select
- #define DAC_C1_DACBFEN 0x00 // DAC Buffer Enable
-
- #define DAC0_C2 *(volatile uint8_t *)0x400CC023 // DAC Control Register 2
- #define DAC_C2_DACBFRP(n) (((n) & 15) << 4) // DAC Buffer Read Pointer
- #define DAC_C2_DACBFUP(n) (((n) & 15) << 0) // DAC Buffer Upper Limit
-
-
- //#define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator
- //#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
+ #define ADC_SC3_CAL (uint32_t)0x80 // Calibration, 1=begin, stays set while cal in progress
+ #define ADC_SC3_CALF (uint32_t)0x40 // Calibration failed flag
+ #define ADC_SC3_ADCO (uint32_t)0x08 // Continuous conversion enable
+ #define ADC_SC3_AVGE (uint32_t)0x04 // Hardware average enable
+ #define ADC_SC3_AVGS(n) (uint32_t)(((n) & 3) << 0) // avg select, 0=4 samples, 1=8 samples, 2=16 samples, 3=32 samples
+ #define ADC0_OFS *(volatile uint32_t *)0x4003B028 // ADC offset correction register
+ #define ADC0_PG *(volatile uint32_t *)0x4003B02C // ADC plus-side gain register
+ #define ADC0_MG *(volatile uint32_t *)0x4003B030 // ADC minus-side gain register
+ #define ADC0_CLPD *(volatile uint32_t *)0x4003B034 // ADC plus-side general calibration value register
+ #define ADC0_CLPS *(volatile uint32_t *)0x4003B038 // ADC plus-side general calibration value register
+ #define ADC0_CLP4 *(volatile uint32_t *)0x4003B03C // ADC plus-side general calibration value register
+ #define ADC0_CLP3 *(volatile uint32_t *)0x4003B040 // ADC plus-side general calibration value register
+ #define ADC0_CLP2 *(volatile uint32_t *)0x4003B044 // ADC plus-side general calibration value register
+ #define ADC0_CLP1 *(volatile uint32_t *)0x4003B048 // ADC plus-side general calibration value register
+ #define ADC0_CLP0 *(volatile uint32_t *)0x4003B04C // ADC plus-side general calibration value register
+ #define ADC0_CLMD *(volatile uint32_t *)0x4003B054 // ADC minus-side general calibration value register
+ #define ADC0_CLMS *(volatile uint32_t *)0x4003B058 // ADC minus-side general calibration value register
+ #define ADC0_CLM4 *(volatile uint32_t *)0x4003B05C // ADC minus-side general calibration value register
+ #define ADC0_CLM3 *(volatile uint32_t *)0x4003B060 // ADC minus-side general calibration value register
+ #define ADC0_CLM2 *(volatile uint32_t *)0x4003B064 // ADC minus-side general calibration value register
+ #define ADC0_CLM1 *(volatile uint32_t *)0x4003B068 // ADC minus-side general calibration value register
+ #define ADC0_CLM0 *(volatile uint32_t *)0x4003B06C // ADC minus-side general calibration value register
+
+ #define ADC1_SC1A *(volatile uint32_t *)0x400BB000 // ADC status and control registers 1
+ #define ADC1_SC1B *(volatile uint32_t *)0x400BB004 // ADC status and control registers 1
+ #define ADC1_CFG1 *(volatile uint32_t *)0x400BB008 // ADC configuration register 1
+ #define ADC1_CFG2 *(volatile uint32_t *)0x400BB00C // Configuration register 2
+ #define ADC1_RA *(volatile uint32_t *)0x400BB010 // ADC data result register
+ #define ADC1_RB *(volatile uint32_t *)0x400BB014 // ADC data result register
+ #define ADC1_CV1 *(volatile uint32_t *)0x400BB018 // Compare value registers
+ #define ADC1_CV2 *(volatile uint32_t *)0x400BB01C // Compare value registers
+ #define ADC1_SC2 *(volatile uint32_t *)0x400BB020 // Status and control register 2
+ #define ADC1_SC3 *(volatile uint32_t *)0x400BB024 // Status and control register 3
+ #define ADC1_OFS *(volatile uint32_t *)0x400BB028 // ADC offset correction register
+ #define ADC1_PG *(volatile uint32_t *)0x400BB02C // ADC plus-side gain register
+ #define ADC1_MG *(volatile uint32_t *)0x400BB030 // ADC minus-side gain register
+ #define ADC1_CLPD *(volatile uint32_t *)0x400BB034 // ADC plus-side general calibration value register
+ #define ADC1_CLPS *(volatile uint32_t *)0x400BB038 // ADC plus-side general calibration value register
+ #define ADC1_CLP4 *(volatile uint32_t *)0x400BB03C // ADC plus-side general calibration value register
+ #define ADC1_CLP3 *(volatile uint32_t *)0x400BB040 // ADC plus-side general calibration value register
+ #define ADC1_CLP2 *(volatile uint32_t *)0x400BB044 // ADC plus-side general calibration value register
+ #define ADC1_CLP1 *(volatile uint32_t *)0x400BB048 // ADC plus-side general calibration value register
+ #define ADC1_CLP0 *(volatile uint32_t *)0x400BB04C // ADC plus-side general calibration value register
+ #define ADC1_CLMD *(volatile uint32_t *)0x400BB054 // ADC minus-side general calibration value register
+ #define ADC1_CLMS *(volatile uint32_t *)0x400BB058 // ADC minus-side general calibration value register
+ #define ADC1_CLM4 *(volatile uint32_t *)0x400BB05C // ADC minus-side general calibration value register
+ #define ADC1_CLM3 *(volatile uint32_t *)0x400BB060 // ADC minus-side general calibration value register
+ #define ADC1_CLM2 *(volatile uint32_t *)0x400BB064 // ADC minus-side general calibration value register
+ #define ADC1_CLM1 *(volatile uint32_t *)0x400BB068 // ADC minus-side general calibration value register
+ #define ADC1_CLM0 *(volatile uint32_t *)0x400BB06C // ADC minus-side general calibration value register
+
-#define DAC0_DAT0L *(volatile uint8_t *)0x400CC000 // DAC Data Low Register
-#define DAC0_DATH *(volatile uint8_t *)0x400CC001 // DAC Data High Register
-#define DAC0_DAT1L *(volatile uint8_t *)0x400CC002 // DAC Data Low Register
-#define DAC0_DAT2L *(volatile uint8_t *)0x400CC004 // DAC Data Low Register
-#define DAC0_DAT3L *(volatile uint8_t *)0x400CC006 // DAC Data Low Register
-#define DAC0_DAT4L *(volatile uint8_t *)0x400CC008 // DAC Data Low Register
-#define DAC0_DAT5L *(volatile uint8_t *)0x400CC00A // DAC Data Low Register
-#define DAC0_DAT6L *(volatile uint8_t *)0x400CC00C // DAC Data Low Register
-#define DAC0_DAT7L *(volatile uint8_t *)0x400CC00E // DAC Data Low Register
-#define DAC0_DAT8L *(volatile uint8_t *)0x400CC010 // DAC Data Low Register
-#define DAC0_DAT9L *(volatile uint8_t *)0x400CC012 // DAC Data Low Register
-#define DAC0_DAT10L *(volatile uint8_t *)0x400CC014 // DAC Data Low Register
-#define DAC0_DAT11L *(volatile uint8_t *)0x400CC016 // DAC Data Low Register
-#define DAC0_DAT12L *(volatile uint8_t *)0x400CC018 // DAC Data Low Register
-#define DAC0_DAT13L *(volatile uint8_t *)0x400CC01A // DAC Data Low Register
-#define DAC0_DAT14L *(volatile uint8_t *)0x400CC01C // DAC Data Low Register
-#define DAC0_DAT15L *(volatile uint8_t *)0x400CC01E // DAC Data Low Register
-#define DAC0_SR *(volatile uint8_t *)0x400CC020 // DAC Status Register
-#define DAC0_C0 *(volatile uint8_t *)0x400CC021 // DAC Control Register
++#define DAC0_DAT0L *(volatile uint8_t *)0x400CC000 // DAC Data Low Register
++#define DAC0_DATH *(volatile uint8_t *)0x400CC001 // DAC Data High Register
++#define DAC0_DAT1L *(volatile uint8_t *)0x400CC002 // DAC Data Low Register
++#define DAC0_DAT2L *(volatile uint8_t *)0x400CC004 // DAC Data Low Register
++#define DAC0_DAT3L *(volatile uint8_t *)0x400CC006 // DAC Data Low Register
++#define DAC0_DAT4L *(volatile uint8_t *)0x400CC008 // DAC Data Low Register
++#define DAC0_DAT5L *(volatile uint8_t *)0x400CC00A // DAC Data Low Register
++#define DAC0_DAT6L *(volatile uint8_t *)0x400CC00C // DAC Data Low Register
++#define DAC0_DAT7L *(volatile uint8_t *)0x400CC00E // DAC Data Low Register
++#define DAC0_DAT8L *(volatile uint8_t *)0x400CC010 // DAC Data Low Register
++#define DAC0_DAT9L *(volatile uint8_t *)0x400CC012 // DAC Data Low Register
++#define DAC0_DAT10L *(volatile uint8_t *)0x400CC014 // DAC Data Low Register
++#define DAC0_DAT11L *(volatile uint8_t *)0x400CC016 // DAC Data Low Register
++#define DAC0_DAT12L *(volatile uint8_t *)0x400CC018 // DAC Data Low Register
++#define DAC0_DAT13L *(volatile uint8_t *)0x400CC01A // DAC Data Low Register
++#define DAC0_DAT14L *(volatile uint8_t *)0x400CC01C // DAC Data Low Register
++#define DAC0_DAT15L *(volatile uint8_t *)0x400CC01E // DAC Data Low Register
++#define DAC0_SR *(volatile uint8_t *)0x400CC020 // DAC Status Register
++#define DAC0_C0 *(volatile uint8_t *)0x400CC021 // DAC Control Register
+ #define DAC_C0_DACEN 0x80 // DAC Enable
+ #define DAC_C0_DACRFS 0x40 // DAC Reference Select
+ #define DAC_C0_DACTRGSEL 0x20 // DAC Trigger Select
+ #define DAC_C0_DACSWTRG 0x10 // DAC Software Trigger
+ #define DAC_C0_LPEN 0x08 // DAC Low Power Control
+ #define DAC_C0_DACBWIEN 0x04 // DAC Buffer Watermark Interrupt Enable
+ #define DAC_C0_DACBTIEN 0x02 // DAC Buffer Read Pointer Top Flag Interrupt Enable
+ #define DAC_C0_DACBBIEN 0x01 // DAC Buffer Read Pointer Bottom Flag Interrupt Enable
-#define DAC0_C1 *(volatile uint8_t *)0x400CC022 // DAC Control Register 1
++#define DAC0_C1 *(volatile uint8_t *)0x400CC022 // DAC Control Register 1
+ #define DAC_C1_DMAEN 0x80 // DMA Enable Select
+ #define DAC_C1_DACBFWM(n) (((n) & 3) << 3) // DAC Buffer Watermark Select
+ #define DAC_C1_DACBFMD(n) (((n) & 3) << 0) // DAC Buffer Work Mode Select
+ #define DAC_C1_DACBFEN 0x00 // DAC Buffer Enable
+
-#define DAC0_C2 *(volatile uint8_t *)0x400CC023 // DAC Control Register 2
++#define DAC0_C2 *(volatile uint8_t *)0x400CC023 // DAC Control Register 2
+ #define DAC_C2_DACBFRP(n) (((n) & 15) << 4) // DAC Buffer Read Pointer
+ #define DAC_C2_DACBFUP(n) (((n) & 15) << 0) // DAC Buffer Upper Limit
+
+
+ //#define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator
-//#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
++//#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
// Chapter 32: Comparator (CMP)
#define CMP0_CR0 *(volatile uint8_t *)0x40073000 // CMP Control Register 0
#define FTM0_CNTIN *(volatile uint32_t *)0x4003804C // Counter Initial Value
#define FTM0_STATUS *(volatile uint32_t *)0x40038050 // Capture And Compare Status
#define FTM0_MODE *(volatile uint32_t *)0x40038054 // Features Mode Selection
- #define FTM_MODE_FAULTIE 0x80 // Fault Interrupt Enable
- #define FTM_MODE_FAULTM(n) (((n) & 3) << 5) // Fault Control Mode
- #define FTM_MODE_CAPTEST 0x10 // Capture Test Mode Enable
- #define FTM_MODE_PWMSYNC 0x08 // PWM Synchronization Mode
- #define FTM_MODE_WPDIS 0x04 // Write Protection Disable
- #define FTM_MODE_INIT 0x02 // Initialize The Channels Output
- #define FTM_MODE_FTMEN 0x01 // FTM Enable
+ #define FTM_MODE_FAULTIE 0x80 // Fault Interrupt Enable
+ #define FTM_MODE_FAULTM(n) (((n) & 3) << 5) // Fault Control Mode
+ #define FTM_MODE_CAPTEST 0x10 // Capture Test Mode Enable
+ #define FTM_MODE_PWMSYNC 0x08 // PWM Synchronization Mode
+ #define FTM_MODE_WPDIS 0x04 // Write Protection Disable
+ #define FTM_MODE_INIT 0x02 // Initialize The Channels Output
+ #define FTM_MODE_FTMEN 0x01 // FTM Enable
#define FTM0_SYNC *(volatile uint32_t *)0x40038058 // Synchronization
- #define FTM_SYNC_SWSYNC 0x80 //
- #define FTM_SYNC_TRIG2 0x40 //
- #define FTM_SYNC_TRIG1 0x20 //
- #define FTM_SYNC_TRIG0 0x10 //
- #define FTM_SYNC_SYNCHOM 0x08 //
- #define FTM_SYNC_REINIT 0x04 //
- #define FTM_SYNC_CNTMAX 0x02 //
- #define FTM_SYNC_CNTMIN 0x01 //
-#define FTM_SYNC_SWSYNC 0x80 //
-#define FTM_SYNC_TRIG2 0x40 //
-#define FTM_SYNC_TRIG1 0x20 //
-#define FTM_SYNC_TRIG0 0x10 //
-#define FTM_SYNC_SYNCHOM 0x08 //
-#define FTM_SYNC_REINIT 0x04 //
-#define FTM_SYNC_CNTMAX 0x02 //
-#define FTM_SYNC_CNTMIN 0x01 //
++#define FTM_SYNC_SWSYNC 0x80 //
++#define FTM_SYNC_TRIG2 0x40 //
++#define FTM_SYNC_TRIG1 0x20 //
++#define FTM_SYNC_TRIG0 0x10 //
++#define FTM_SYNC_SYNCHOM 0x08 //
++#define FTM_SYNC_REINIT 0x04 //
++#define FTM_SYNC_CNTMAX 0x02 //
++#define FTM_SYNC_CNTMIN 0x01 //
#define FTM0_OUTINIT *(volatile uint32_t *)0x4003805C // Initial State For Channels Output
#define FTM0_OUTMASK *(volatile uint32_t *)0x40038060 // Output Mask
#define FTM0_COMBINE *(volatile uint32_t *)0x40038064 // Function For Linked Channels
#define RTC_TPR *(volatile uint32_t *)0x4003D004 // RTC Time Prescaler Register
#define RTC_TAR *(volatile uint32_t *)0x4003D008 // RTC Time Alarm Register
#define RTC_TCR *(volatile uint32_t *)0x4003D00C // RTC Time Compensation Register
- #define RTC_TCR_CIC(n) (((n) & 255) << 24) // Compensation Interval Counter
- #define RTC_TCR_TCV(n) (((n) & 255) << 16) // Time Compensation Value
- #define RTC_TCR_CIR(n) (((n) & 255) << 8) // Compensation Interval Register
- #define RTC_TCR_TCR(n) (((n) & 255) << 0) // Time Compensation Register
+ #define RTC_TCR_CIC(n) (((n) & 255) << 24) // Compensation Interval Counter
+ #define RTC_TCR_TCV(n) (((n) & 255) << 16) // Time Compensation Value
+ #define RTC_TCR_CIR(n) (((n) & 255) << 8) // Compensation Interval Register
+ #define RTC_TCR_TCR(n) (((n) & 255) << 0) // Time Compensation Register
#define RTC_CR *(volatile uint32_t *)0x4003D010 // RTC Control Register
- #define RTC_CR_SC2P (uint32_t)0x00002000 //
- #define RTC_CR_SC4P (uint32_t)0x00001000 //
- #define RTC_CR_SC8P (uint32_t)0x00000800 //
- #define RTC_CR_SC16P (uint32_t)0x00000400 //
- #define RTC_CR_CLKO (uint32_t)0x00000200 //
- #define RTC_CR_OSCE (uint32_t)0x00000100 //
- #define RTC_CR_UM (uint32_t)0x00000008 //
- #define RTC_CR_SUP (uint32_t)0x00000004 //
- #define RTC_CR_WPE (uint32_t)0x00000002 //
- #define RTC_CR_SWR (uint32_t)0x00000001 //
-#define RTC_CR_SC2P (uint32_t)0x00002000 //
-#define RTC_CR_SC4P (uint32_t)0x00001000 //
-#define RTC_CR_SC8P (uint32_t)0x00000800 //
-#define RTC_CR_SC16P (uint32_t)0x00000400 //
-#define RTC_CR_CLKO (uint32_t)0x00000200 //
-#define RTC_CR_OSCE (uint32_t)0x00000100 //
-#define RTC_CR_UM (uint32_t)0x00000008 //
-#define RTC_CR_SUP (uint32_t)0x00000004 //
-#define RTC_CR_WPE (uint32_t)0x00000002 //
-#define RTC_CR_SWR (uint32_t)0x00000001 //
++#define RTC_CR_SC2P (uint32_t)0x00002000 //
++#define RTC_CR_SC4P (uint32_t)0x00001000 //
++#define RTC_CR_SC8P (uint32_t)0x00000800 //
++#define RTC_CR_SC16P (uint32_t)0x00000400 //
++#define RTC_CR_CLKO (uint32_t)0x00000200 //
++#define RTC_CR_OSCE (uint32_t)0x00000100 //
++#define RTC_CR_UM (uint32_t)0x00000008 //
++#define RTC_CR_SUP (uint32_t)0x00000004 //
++#define RTC_CR_WPE (uint32_t)0x00000002 //
++#define RTC_CR_SWR (uint32_t)0x00000001 //
#define RTC_SR *(volatile uint32_t *)0x4003D014 // RTC Status Register
- #define RTC_SR_TCE (uint32_t)0x00000010 //
- #define RTC_SR_TAF (uint32_t)0x00000004 //
- #define RTC_SR_TOF (uint32_t)0x00000002 //
- #define RTC_SR_TIF (uint32_t)0x00000001 //
-#define RTC_SR_TCE (uint32_t)0x00000010 //
-#define RTC_SR_TAF (uint32_t)0x00000004 //
-#define RTC_SR_TOF (uint32_t)0x00000002 //
-#define RTC_SR_TIF (uint32_t)0x00000001 //
++#define RTC_SR_TCE (uint32_t)0x00000010 //
++#define RTC_SR_TAF (uint32_t)0x00000004 //
++#define RTC_SR_TOF (uint32_t)0x00000002 //
++#define RTC_SR_TIF (uint32_t)0x00000001 //
#define RTC_LR *(volatile uint32_t *)0x4003D018 // RTC Lock Register
#define RTC_IER *(volatile uint32_t *)0x4003D01C // RTC Interrupt Enable Register
#define RTC_WAR *(volatile uint32_t *)0x4003D800 // RTC Write Access Register
#define USB0_REV *(const uint8_t *)0x40072008 // Peripheral Revision register
#define USB0_ADDINFO *(volatile uint8_t *)0x4007200C // Peripheral Additional Info register
#define USB0_OTGISTAT *(volatile uint8_t *)0x40072010 // OTG Interrupt Status register
- #define USB_OTGISTAT_IDCHG (uint8_t)0x80 //
- #define USB_OTGISTAT_ONEMSEC (uint8_t)0x40 //
- #define USB_OTGISTAT_LINE_STATE_CHG (uint8_t)0x20 //
- #define USB_OTGISTAT_SESSVLDCHG (uint8_t)0x08 //
- #define USB_OTGISTAT_B_SESS_CHG (uint8_t)0x04 //
- #define USB_OTGISTAT_AVBUSCHG (uint8_t)0x01 //
+ #define USB_OTGISTAT_IDCHG (uint8_t)0x80 //
+ #define USB_OTGISTAT_ONEMSEC (uint8_t)0x40 //
+ #define USB_OTGISTAT_LINE_STATE_CHG (uint8_t)0x20 //
+ #define USB_OTGISTAT_SESSVLDCHG (uint8_t)0x08 //
+ #define USB_OTGISTAT_B_SESS_CHG (uint8_t)0x04 //
+ #define USB_OTGISTAT_AVBUSCHG (uint8_t)0x01 //
#define USB0_OTGICR *(volatile uint8_t *)0x40072014 // OTG Interrupt Control Register
- #define USB_OTGICR_IDEN (uint8_t)0x80 //
- #define USB_OTGICR_ONEMSECEN (uint8_t)0x40 //
- #define USB_OTGICR_LINESTATEEN (uint8_t)0x20 //
- #define USB_OTGICR_SESSVLDEN (uint8_t)0x08 //
- #define USB_OTGICR_BSESSEN (uint8_t)0x04 //
- #define USB_OTGICR_AVBUSEN (uint8_t)0x01 //
-#define USB_OTGICR_IDEN (uint8_t)0x80 //
-#define USB_OTGICR_ONEMSECEN (uint8_t)0x40 //
-#define USB_OTGICR_LINESTATEEN (uint8_t)0x20 //
-#define USB_OTGICR_SESSVLDEN (uint8_t)0x08 //
-#define USB_OTGICR_BSESSEN (uint8_t)0x04 //
-#define USB_OTGICR_AVBUSEN (uint8_t)0x01 //
++#define USB_OTGICR_IDEN (uint8_t)0x80 //
++#define USB_OTGICR_ONEMSECEN (uint8_t)0x40 //
++#define USB_OTGICR_LINESTATEEN (uint8_t)0x20 //
++#define USB_OTGICR_SESSVLDEN (uint8_t)0x08 //
++#define USB_OTGICR_BSESSEN (uint8_t)0x04 //
++#define USB_OTGICR_AVBUSEN (uint8_t)0x01 //
#define USB0_OTGSTAT *(volatile uint8_t *)0x40072018 // OTG Status register
- #define USB_OTGSTAT_ID (uint8_t)0x80 //
- #define USB_OTGSTAT_ONEMSECEN (uint8_t)0x40 //
- #define USB_OTGSTAT_LINESTATESTABLE (uint8_t)0x20 //
- #define USB_OTGSTAT_SESS_VLD (uint8_t)0x08 //
- #define USB_OTGSTAT_BSESSEND (uint8_t)0x04 //
- #define USB_OTGSTAT_AVBUSVLD (uint8_t)0x01 //
-#define USB_OTGSTAT_ID (uint8_t)0x80 //
-#define USB_OTGSTAT_ONEMSECEN (uint8_t)0x40 //
-#define USB_OTGSTAT_LINESTATESTABLE (uint8_t)0x20 //
-#define USB_OTGSTAT_SESS_VLD (uint8_t)0x08 //
-#define USB_OTGSTAT_BSESSEND (uint8_t)0x04 //
-#define USB_OTGSTAT_AVBUSVLD (uint8_t)0x01 //
++#define USB_OTGSTAT_ID (uint8_t)0x80 //
++#define USB_OTGSTAT_ONEMSECEN (uint8_t)0x40 //
++#define USB_OTGSTAT_LINESTATESTABLE (uint8_t)0x20 //
++#define USB_OTGSTAT_SESS_VLD (uint8_t)0x08 //
++#define USB_OTGSTAT_BSESSEND (uint8_t)0x04 //
++#define USB_OTGSTAT_AVBUSVLD (uint8_t)0x01 //
#define USB0_OTGCTL *(volatile uint8_t *)0x4007201C // OTG Control Register
- #define USB_OTGCTL_DPHIGH (uint8_t)0x80 //
- #define USB_OTGCTL_DPLOW (uint8_t)0x20 //
- #define USB_OTGCTL_DMLOW (uint8_t)0x10 //
- #define USB_OTGCTL_OTGEN (uint8_t)0x04 //
-#define USB_OTGCTL_DPHIGH (uint8_t)0x80 //
-#define USB_OTGCTL_DPLOW (uint8_t)0x20 //
-#define USB_OTGCTL_DMLOW (uint8_t)0x10 //
-#define USB_OTGCTL_OTGEN (uint8_t)0x04 //
++#define USB_OTGCTL_DPHIGH (uint8_t)0x80 //
++#define USB_OTGCTL_DPLOW (uint8_t)0x20 //
++#define USB_OTGCTL_DMLOW (uint8_t)0x10 //
++#define USB_OTGCTL_OTGEN (uint8_t)0x04 //
#define USB0_ISTAT *(volatile uint8_t *)0x40072080 // Interrupt Status Register
- #define USB_ISTAT_STALL (uint8_t)0x80 //
- #define USB_ISTAT_ATTACH (uint8_t)0x40 //
- #define USB_ISTAT_RESUME (uint8_t)0x20 //
- #define USB_ISTAT_SLEEP (uint8_t)0x10 //
- #define USB_ISTAT_TOKDNE (uint8_t)0x08 //
- #define USB_ISTAT_SOFTOK (uint8_t)0x04 //
- #define USB_ISTAT_ERROR (uint8_t)0x02 //
- #define USB_ISTAT_USBRST (uint8_t)0x01 //
-#define USB_ISTAT_STALL (uint8_t)0x80 //
-#define USB_ISTAT_ATTACH (uint8_t)0x40 //
-#define USB_ISTAT_RESUME (uint8_t)0x20 //
-#define USB_ISTAT_SLEEP (uint8_t)0x10 //
-#define USB_ISTAT_TOKDNE (uint8_t)0x08 //
-#define USB_ISTAT_SOFTOK (uint8_t)0x04 //
-#define USB_ISTAT_ERROR (uint8_t)0x02 //
-#define USB_ISTAT_USBRST (uint8_t)0x01 //
++#define USB_ISTAT_STALL (uint8_t)0x80 //
++#define USB_ISTAT_ATTACH (uint8_t)0x40 //
++#define USB_ISTAT_RESUME (uint8_t)0x20 //
++#define USB_ISTAT_SLEEP (uint8_t)0x10 //
++#define USB_ISTAT_TOKDNE (uint8_t)0x08 //
++#define USB_ISTAT_SOFTOK (uint8_t)0x04 //
++#define USB_ISTAT_ERROR (uint8_t)0x02 //
++#define USB_ISTAT_USBRST (uint8_t)0x01 //
#define USB0_INTEN *(volatile uint8_t *)0x40072084 // Interrupt Enable Register
- #define USB_INTEN_STALLEN (uint8_t)0x80 //
- #define USB_INTEN_ATTACHEN (uint8_t)0x40 //
- #define USB_INTEN_RESUMEEN (uint8_t)0x20 //
- #define USB_INTEN_SLEEPEN (uint8_t)0x10 //
- #define USB_INTEN_TOKDNEEN (uint8_t)0x08 //
- #define USB_INTEN_SOFTOKEN (uint8_t)0x04 //
- #define USB_INTEN_ERROREN (uint8_t)0x02 //
- #define USB_INTEN_USBRSTEN (uint8_t)0x01 //
-#define USB_INTEN_STALLEN (uint8_t)0x80 //
-#define USB_INTEN_ATTACHEN (uint8_t)0x40 //
-#define USB_INTEN_RESUMEEN (uint8_t)0x20 //
-#define USB_INTEN_SLEEPEN (uint8_t)0x10 //
-#define USB_INTEN_TOKDNEEN (uint8_t)0x08 //
-#define USB_INTEN_SOFTOKEN (uint8_t)0x04 //
-#define USB_INTEN_ERROREN (uint8_t)0x02 //
-#define USB_INTEN_USBRSTEN (uint8_t)0x01 //
++#define USB_INTEN_STALLEN (uint8_t)0x80 //
++#define USB_INTEN_ATTACHEN (uint8_t)0x40 //
++#define USB_INTEN_RESUMEEN (uint8_t)0x20 //
++#define USB_INTEN_SLEEPEN (uint8_t)0x10 //
++#define USB_INTEN_TOKDNEEN (uint8_t)0x08 //
++#define USB_INTEN_SOFTOKEN (uint8_t)0x04 //
++#define USB_INTEN_ERROREN (uint8_t)0x02 //
++#define USB_INTEN_USBRSTEN (uint8_t)0x01 //
#define USB0_ERRSTAT *(volatile uint8_t *)0x40072088 // Error Interrupt Status Register
- #define USB_ERRSTAT_BTSERR (uint8_t)0x80 //
- #define USB_ERRSTAT_DMAERR (uint8_t)0x20 //
- #define USB_ERRSTAT_BTOERR (uint8_t)0x10 //
- #define USB_ERRSTAT_DFN8 (uint8_t)0x08 //
- #define USB_ERRSTAT_CRC16 (uint8_t)0x04 //
- #define USB_ERRSTAT_CRC5EOF (uint8_t)0x02 //
- #define USB_ERRSTAT_PIDERR (uint8_t)0x01 //
-#define USB_ERRSTAT_BTSERR (uint8_t)0x80 //
-#define USB_ERRSTAT_DMAERR (uint8_t)0x20 //
-#define USB_ERRSTAT_BTOERR (uint8_t)0x10 //
-#define USB_ERRSTAT_DFN8 (uint8_t)0x08 //
-#define USB_ERRSTAT_CRC16 (uint8_t)0x04 //
-#define USB_ERRSTAT_CRC5EOF (uint8_t)0x02 //
-#define USB_ERRSTAT_PIDERR (uint8_t)0x01 //
++#define USB_ERRSTAT_BTSERR (uint8_t)0x80 //
++#define USB_ERRSTAT_DMAERR (uint8_t)0x20 //
++#define USB_ERRSTAT_BTOERR (uint8_t)0x10 //
++#define USB_ERRSTAT_DFN8 (uint8_t)0x08 //
++#define USB_ERRSTAT_CRC16 (uint8_t)0x04 //
++#define USB_ERRSTAT_CRC5EOF (uint8_t)0x02 //
++#define USB_ERRSTAT_PIDERR (uint8_t)0x01 //
#define USB0_ERREN *(volatile uint8_t *)0x4007208C // Error Interrupt Enable Register
- #define USB_ERREN_BTSERREN (uint8_t)0x80 //
- #define USB_ERREN_DMAERREN (uint8_t)0x20 //
- #define USB_ERREN_BTOERREN (uint8_t)0x10 //
- #define USB_ERREN_DFN8EN (uint8_t)0x08 //
- #define USB_ERREN_CRC16EN (uint8_t)0x04 //
- #define USB_ERREN_CRC5EOFEN (uint8_t)0x02 //
- #define USB_ERREN_PIDERREN (uint8_t)0x01 //
-#define USB_ERREN_BTSERREN (uint8_t)0x80 //
-#define USB_ERREN_DMAERREN (uint8_t)0x20 //
-#define USB_ERREN_BTOERREN (uint8_t)0x10 //
-#define USB_ERREN_DFN8EN (uint8_t)0x08 //
-#define USB_ERREN_CRC16EN (uint8_t)0x04 //
-#define USB_ERREN_CRC5EOFEN (uint8_t)0x02 //
-#define USB_ERREN_PIDERREN (uint8_t)0x01 //
++#define USB_ERREN_BTSERREN (uint8_t)0x80 //
++#define USB_ERREN_DMAERREN (uint8_t)0x20 //
++#define USB_ERREN_BTOERREN (uint8_t)0x10 //
++#define USB_ERREN_DFN8EN (uint8_t)0x08 //
++#define USB_ERREN_CRC16EN (uint8_t)0x04 //
++#define USB_ERREN_CRC5EOFEN (uint8_t)0x02 //
++#define USB_ERREN_PIDERREN (uint8_t)0x01 //
#define USB0_STAT *(volatile uint8_t *)0x40072090 // Status Register
- #define USB_STAT_TX (uint8_t)0x08 //
- #define USB_STAT_ODD (uint8_t)0x04 //
- #define USB_STAT_ENDP(n) (uint8_t)((n) >> 4) //
-#define USB_STAT_TX (uint8_t)0x08 //
-#define USB_STAT_ODD (uint8_t)0x04 //
-#define USB_STAT_ENDP(n) (uint8_t)((n) >> 4) //
++#define USB_STAT_TX (uint8_t)0x08 //
++#define USB_STAT_ODD (uint8_t)0x04 //
++#define USB_STAT_ENDP(n) (uint8_t)((n) >> 4) //
#define USB0_CTL *(volatile uint8_t *)0x40072094 // Control Register
- #define USB_CTL_JSTATE (uint8_t)0x80 //
- #define USB_CTL_SE0 (uint8_t)0x40 //
- #define USB_CTL_TXSUSPENDTOKENBUSY (uint8_t)0x20 //
- #define USB_CTL_RESET (uint8_t)0x10 //
- #define USB_CTL_HOSTMODEEN (uint8_t)0x08 //
- #define USB_CTL_RESUME (uint8_t)0x04 //
- #define USB_CTL_ODDRST (uint8_t)0x02 //
- #define USB_CTL_USBENSOFEN (uint8_t)0x01 //
-#define USB_CTL_JSTATE (uint8_t)0x80 //
-#define USB_CTL_SE0 (uint8_t)0x40 //
-#define USB_CTL_TXSUSPENDTOKENBUSY (uint8_t)0x20 //
-#define USB_CTL_RESET (uint8_t)0x10 //
-#define USB_CTL_HOSTMODEEN (uint8_t)0x08 //
-#define USB_CTL_RESUME (uint8_t)0x04 //
-#define USB_CTL_ODDRST (uint8_t)0x02 //
-#define USB_CTL_USBENSOFEN (uint8_t)0x01 //
++#define USB_CTL_JSTATE (uint8_t)0x80 //
++#define USB_CTL_SE0 (uint8_t)0x40 //
++#define USB_CTL_TXSUSPENDTOKENBUSY (uint8_t)0x20 //
++#define USB_CTL_RESET (uint8_t)0x10 //
++#define USB_CTL_HOSTMODEEN (uint8_t)0x08 //
++#define USB_CTL_RESUME (uint8_t)0x04 //
++#define USB_CTL_ODDRST (uint8_t)0x02 //
++#define USB_CTL_USBENSOFEN (uint8_t)0x01 //
#define USB0_ADDR *(volatile uint8_t *)0x40072098 // Address Register
#define USB0_BDTPAGE1 *(volatile uint8_t *)0x4007209C // BDT Page Register 1
#define USB0_FRMNUML *(volatile uint8_t *)0x400720A0 // Frame Number Register Low
#define USB0_ENDPT14 *(volatile uint8_t *)0x400720F8 // Endpoint Control Register
#define USB0_ENDPT15 *(volatile uint8_t *)0x400720FC // Endpoint Control Register
#define USB0_USBCTRL *(volatile uint8_t *)0x40072100 // USB Control Register
- #define USB_USBCTRL_SUSP (uint8_t)0x80 // Places the USB transceiver into the suspend state.
- #define USB_USBCTRL_PDE (uint8_t)0x40 // Enables the weak pulldowns on the USB transceiver.
+ #define USB_USBCTRL_SUSP (uint8_t)0x80 // Places the USB transceiver into the suspend state.
+ #define USB_USBCTRL_PDE (uint8_t)0x40 // Enables the weak pulldowns on the USB transceiver.
#define USB0_OBSERVE *(volatile uint8_t *)0x40072104 // USB OTG Observe Register
- #define USB_OBSERVE_DPPU (uint8_t)0x80 //
- #define USB_OBSERVE_DPPD (uint8_t)0x40 //
- #define USB_OBSERVE_DMPD (uint8_t)0x10 //
-#define USB_OBSERVE_DPPU (uint8_t)0x80 //
-#define USB_OBSERVE_DPPD (uint8_t)0x40 //
-#define USB_OBSERVE_DMPD (uint8_t)0x10 //
++#define USB_OBSERVE_DPPU (uint8_t)0x80 //
++#define USB_OBSERVE_DPPD (uint8_t)0x40 //
++#define USB_OBSERVE_DMPD (uint8_t)0x10 //
#define USB0_CONTROL *(volatile uint8_t *)0x40072108 // USB OTG Control Register
- #define USB_CONTROL_DPPULLUPNONOTG (uint8_t)0x10 // Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode.
+ #define USB_CONTROL_DPPULLUPNONOTG (uint8_t)0x10 // Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode.
#define USB0_USBTRC0 *(volatile uint8_t *)0x4007210C // USB Transceiver Control Register 0
- #define USB_USBTRC_USBRESET (uint8_t)0x80 //
- #define USB_USBTRC_USBRESMEN (uint8_t)0x20 //
- #define USB_USBTRC_SYNC_DET (uint8_t)0x02 //
- #define USB_USBTRC_USB_RESUME_INT (uint8_t)0x01 //
+ #define USB_USBTRC_USBRESET (uint8_t)0x80 //
+ #define USB_USBTRC_USBRESMEN (uint8_t)0x20 //
+ #define USB_USBTRC_SYNC_DET (uint8_t)0x02 //
+ #define USB_USBTRC_USB_RESUME_INT (uint8_t)0x01 //
#define USB0_USBFRMADJUST *(volatile uint8_t *)0x40072114 // Frame Adjust Register
// Chapter 41: USB Device Charger Detection Module (USBDCD)
// Chapter 43: SPI (DSPI)
#define SPI0_MCR *(volatile uint32_t *)0x4002C000 // DSPI Module Configuration Register
- #define SPI_MCR_MSTR (uint32_t)0x80000000 // Master/Slave Mode Select
- #define SPI_MCR_CONT_SCKE (uint32_t)0x40000000 //
- #define SPI_MCR_DCONF(n) (((n) & 3) << 28) //
- #define SPI_MCR_FRZ (uint32_t)0x08000000 //
- #define SPI_MCR_MTFE (uint32_t)0x04000000 //
- #define SPI_MCR_ROOE (uint32_t)0x01000000 //
- #define SPI_MCR_PCSIS(n) (((n) & 0x1F) << 16) //
- #define SPI_MCR_DOZE (uint32_t)0x00008000 //
- #define SPI_MCR_MDIS (uint32_t)0x00004000 //
- #define SPI_MCR_DIS_TXF (uint32_t)0x00002000 //
- #define SPI_MCR_DIS_RXF (uint32_t)0x00001000 //
- #define SPI_MCR_CLR_TXF (uint32_t)0x00000800 //
- #define SPI_MCR_CLR_RXF (uint32_t)0x00000400 //
- #define SPI_MCR_SMPL_PT(n) (((n) & 3) << 8) //
- #define SPI_MCR_HALT (uint32_t)0x00000001 //
+ #define SPI_MCR_MSTR (uint32_t)0x80000000 // Master/Slave Mode Select
-#define SPI_MCR_CONT_SCKE (uint32_t)0x40000000 //
-#define SPI_MCR_DCONF(n) (((n) & 3) << 28) //
-#define SPI_MCR_FRZ (uint32_t)0x08000000 //
-#define SPI_MCR_MTFE (uint32_t)0x04000000 //
-#define SPI_MCR_ROOE (uint32_t)0x01000000 //
++#define SPI_MCR_CONT_SCKE (uint32_t)0x40000000 //
++#define SPI_MCR_DCONF(n) (((n) & 3) << 28) //
++#define SPI_MCR_FRZ (uint32_t)0x08000000 //
++#define SPI_MCR_MTFE (uint32_t)0x04000000 //
++#define SPI_MCR_ROOE (uint32_t)0x01000000 //
+ #define SPI_MCR_PCSIS(n) (((n) & 0x1F) << 16) //
-#define SPI_MCR_DOZE (uint32_t)0x00008000 //
-#define SPI_MCR_MDIS (uint32_t)0x00004000 //
-#define SPI_MCR_DIS_TXF (uint32_t)0x00002000 //
-#define SPI_MCR_DIS_RXF (uint32_t)0x00001000 //
-#define SPI_MCR_CLR_TXF (uint32_t)0x00000800 //
-#define SPI_MCR_CLR_RXF (uint32_t)0x00000400 //
++#define SPI_MCR_DOZE (uint32_t)0x00008000 //
++#define SPI_MCR_MDIS (uint32_t)0x00004000 //
++#define SPI_MCR_DIS_TXF (uint32_t)0x00002000 //
++#define SPI_MCR_DIS_RXF (uint32_t)0x00001000 //
++#define SPI_MCR_CLR_TXF (uint32_t)0x00000800 //
++#define SPI_MCR_CLR_RXF (uint32_t)0x00000400 //
+ #define SPI_MCR_SMPL_PT(n) (((n) & 3) << 8) //
-#define SPI_MCR_HALT (uint32_t)0x00000001 //
++#define SPI_MCR_HALT (uint32_t)0x00000001 //
#define SPI0_TCR *(volatile uint32_t *)0x4002C008 // DSPI Transfer Count Register
#define SPI0_CTAR0 *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Master Mode
- #define SPI_CTAR_DBR (uint32_t)0x80000000 // Double Baud Rate
- #define SPI_CTAR_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1)
- #define SPI_CTAR_CPOL (uint32_t)0x04000000 // Clock Polarity
- #define SPI_CTAR_CPHA (uint32_t)0x02000000 // Clock Phase
- #define SPI_CTAR_LSBFE (uint32_t)0x01000000 // LSB First
- #define SPI_CTAR_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler
- #define SPI_CTAR_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler
- #define SPI_CTAR_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler
- #define SPI_CTAR_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler
- #define SPI_CTAR_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler
- #define SPI_CTAR_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler
- #define SPI_CTAR_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler
- #define SPI_CTAR_BR(n) (((n) & 15) << 0) // Baud Rate Scaler
+ #define SPI_CTAR_DBR (uint32_t)0x80000000 // Double Baud Rate
+ #define SPI_CTAR_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1)
+ #define SPI_CTAR_CPOL (uint32_t)0x04000000 // Clock Polarity
+ #define SPI_CTAR_CPHA (uint32_t)0x02000000 // Clock Phase
+ #define SPI_CTAR_LSBFE (uint32_t)0x01000000 // LSB First
+ #define SPI_CTAR_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler
+ #define SPI_CTAR_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler
+ #define SPI_CTAR_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler
+ #define SPI_CTAR_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler
+ #define SPI_CTAR_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler
+ #define SPI_CTAR_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler
+ #define SPI_CTAR_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler
+ #define SPI_CTAR_BR(n) (((n) & 15) << 0) // Baud Rate Scaler
#define SPI0_CTAR0_SLAVE *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Slave Mode
#define SPI0_CTAR1 *(volatile uint32_t *)0x4002C010 // DSPI Clock and Transfer Attributes Register, In Master Mode
#define SPI0_SR *(volatile uint32_t *)0x4002C02C // DSPI Status Register
- #define SPI_SR_TCF (uint32_t)0x80000000 // Transfer Complete Flag
- #define SPI_SR_TXRXS (uint32_t)0x40000000 // TX and RX Status
- #define SPI_SR_EOQF (uint32_t)0x10000000 // End of Queue Flag
- #define SPI_SR_TFUF (uint32_t)0x08000000 // Transmit FIFO Underflow Flag
- #define SPI_SR_TFFF (uint32_t)0x02000000 // Transmit FIFO Fill Flag
- #define SPI_SR_RFOF (uint32_t)0x00080000 // Receive FIFO Overflow Flag
- #define SPI_SR_RFDF (uint32_t)0x00020000 // Receive FIFO Drain Flag
- #define SPI0_RSER *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register
- #define SPI_RSER_TCF_RE (uint32_t)0x80000000 // Transmission Complete Request Enable
- #define SPI_RSER_EOQF_RE (uint32_t)0x10000000 // DSPI Finished Request Request Enable
- #define SPI_RSER_TFUF_RE (uint32_t)0x08000000 // Transmit FIFO Underflow Request Enable
- #define SPI_RSER_TFFF_RE (uint32_t)0x02000000 // Transmit FIFO Fill Request Enable
- #define SPI_RSER_TFFF_DIRS (uint32_t)0x01000000 // Transmit FIFO FIll Dma or Interrupt Request Select
- #define SPI_RSER_RFOF_RE (uint32_t)0x00080000 // Receive FIFO Overflow Request Enable
- #define SPI_RSER_RFDF_RE (uint32_t)0x00020000 // Receive FIFO Drain Request Enable
- #define SPI_RSER_RFDF_DIRS (uint32_t)0x00010000 // Receive FIFO Drain DMA or Interrupt Request Select
- #define SPI0_PUSHR *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Master Mode
- #define SPI_PUSHR_CONT (uint32_t)0x80000000 //
- #define SPI_PUSHR_CTAS(n) (((n) & 7) << 28) //
- #define SPI_PUSHR_EOQ (uint32_t)0x08000000 //
- #define SPI_PUSHR_CTCNT (uint32_t)0x04000000 //
- #define SPI_PUSHR_PCS(n) (((n) & 31) << 16) //
- #define SPI0_PUSHR_SLAVE *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Slave Mode
- #define SPI0_POPR *(volatile uint32_t *)0x4002C038 // DSPI POP RX FIFO Register
- #define SPI0_TXFR0 *(volatile uint32_t *)0x4002C03C // DSPI Transmit FIFO Registers
- #define SPI0_TXFR1 *(volatile uint32_t *)0x4002C040 // DSPI Transmit FIFO Registers
- #define SPI0_TXFR2 *(volatile uint32_t *)0x4002C044 // DSPI Transmit FIFO Registers
- #define SPI0_TXFR3 *(volatile uint32_t *)0x4002C048 // DSPI Transmit FIFO Registers
- #define SPI0_RXFR0 *(volatile uint32_t *)0x4002C07C // DSPI Receive FIFO Registers
- #define SPI0_RXFR1 *(volatile uint32_t *)0x4002C080 // DSPI Receive FIFO Registers
- #define SPI0_RXFR2 *(volatile uint32_t *)0x4002C084 // DSPI Receive FIFO Registers
- #define SPI0_RXFR3 *(volatile uint32_t *)0x4002C088 // DSPI Receive FIFO Registers
+ #define SPI_SR_TCF (uint32_t)0x80000000 // Transfer Complete Flag
+ #define SPI_SR_TXRXS (uint32_t)0x40000000 // TX and RX Status
+ #define SPI_SR_EOQF (uint32_t)0x10000000 // End of Queue Flag
+ #define SPI_SR_TFUF (uint32_t)0x08000000 // Transmit FIFO Underflow Flag
+ #define SPI_SR_TFFF (uint32_t)0x02000000 // Transmit FIFO Fill Flag
+ #define SPI_SR_RFOF (uint32_t)0x00080000 // Receive FIFO Overflow Flag
+ #define SPI_SR_RFDF (uint32_t)0x00020000 // Receive FIFO Drain Flag
+ #define SPI0_RSER *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register
+ #define SPI_RSER_TCF_RE (uint32_t)0x80000000 // Transmission Complete Request Enable
+ #define SPI_RSER_EOQF_RE (uint32_t)0x10000000 // DSPI Finished Request Request Enable
+ #define SPI_RSER_TFUF_RE (uint32_t)0x08000000 // Transmit FIFO Underflow Request Enable
+ #define SPI_RSER_TFFF_RE (uint32_t)0x02000000 // Transmit FIFO Fill Request Enable
+ #define SPI_RSER_TFFF_DIRS (uint32_t)0x01000000 // Transmit FIFO FIll Dma or Interrupt Request Select
+ #define SPI_RSER_RFOF_RE (uint32_t)0x00080000 // Receive FIFO Overflow Request Enable
+ #define SPI_RSER_RFDF_RE (uint32_t)0x00020000 // Receive FIFO Drain Request Enable
+ #define SPI_RSER_RFDF_DIRS (uint32_t)0x00010000 // Receive FIFO Drain DMA or Interrupt Request Select
+ #define SPI0_PUSHR *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Master Mode
-#define SPI_PUSHR_CONT (uint32_t)0x80000000 //
-#define SPI_PUSHR_CTAS(n) (((n) & 7) << 28) //
-#define SPI_PUSHR_EOQ (uint32_t)0x08000000 //
-#define SPI_PUSHR_CTCNT (uint32_t)0x04000000 //
++#define SPI_PUSHR_CONT (uint32_t)0x80000000 //
++#define SPI_PUSHR_CTAS(n) (((n) & 7) << 28) //
++#define SPI_PUSHR_EOQ (uint32_t)0x08000000 //
++#define SPI_PUSHR_CTCNT (uint32_t)0x04000000 //
+ #define SPI_PUSHR_PCS(n) (((n) & 31) << 16) //
+ #define SPI0_PUSHR_SLAVE *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Slave Mode
+ #define SPI0_POPR *(volatile uint32_t *)0x4002C038 // DSPI POP RX FIFO Register
+ #define SPI0_TXFR0 *(volatile uint32_t *)0x4002C03C // DSPI Transmit FIFO Registers
+ #define SPI0_TXFR1 *(volatile uint32_t *)0x4002C040 // DSPI Transmit FIFO Registers
+ #define SPI0_TXFR2 *(volatile uint32_t *)0x4002C044 // DSPI Transmit FIFO Registers
+ #define SPI0_TXFR3 *(volatile uint32_t *)0x4002C048 // DSPI Transmit FIFO Registers
+ #define SPI0_RXFR0 *(volatile uint32_t *)0x4002C07C // DSPI Receive FIFO Registers
+ #define SPI0_RXFR1 *(volatile uint32_t *)0x4002C080 // DSPI Receive FIFO Registers
+ #define SPI0_RXFR2 *(volatile uint32_t *)0x4002C084 // DSPI Receive FIFO Registers
+ #define SPI0_RXFR3 *(volatile uint32_t *)0x4002C088 // DSPI Receive FIFO Registers
typedef struct {
- volatile uint32_t MCR; // 0
- volatile uint32_t unused1;// 4
- volatile uint32_t TCR; // 8
- volatile uint32_t CTAR0; // c
- volatile uint32_t CTAR1; // 10
- volatile uint32_t CTAR2; // 14
- volatile uint32_t CTAR3; // 18
- volatile uint32_t CTAR4; // 1c
- volatile uint32_t CTAR5; // 20
- volatile uint32_t CTAR6; // 24
- volatile uint32_t CTAR7; // 28
- volatile uint32_t SR; // 2c
- volatile uint32_t RSER; // 30
- volatile uint32_t PUSHR; // 34
- volatile uint32_t POPR; // 38
- volatile uint32_t TXFR[16]; // 3c
- volatile uint32_t RXFR[16]; // 7c
+ volatile uint32_t MCR; // 0
+ volatile uint32_t unused1;// 4
+ volatile uint32_t TCR; // 8
+ volatile uint32_t CTAR0; // c
+ volatile uint32_t CTAR1; // 10
+ volatile uint32_t CTAR2; // 14
+ volatile uint32_t CTAR3; // 18
+ volatile uint32_t CTAR4; // 1c
+ volatile uint32_t CTAR5; // 20
+ volatile uint32_t CTAR6; // 24
+ volatile uint32_t CTAR7; // 28
+ volatile uint32_t SR; // 2c
+ volatile uint32_t RSER; // 30
+ volatile uint32_t PUSHR; // 34
+ volatile uint32_t POPR; // 38
+ volatile uint32_t TXFR[16]; // 3c
+ volatile uint32_t RXFR[16]; // 7c
} SPI_t;
- #define SPI0 (*(SPI_t *)0x4002C000)
+ #define SPI0 (*(SPI_t *)0x4002C000)
// Chapter 44: Inter-Integrated Circuit (I2C)
#define I2C0_A1 *(volatile uint8_t *)0x40066000 // I2C Address Register 1
#define UART0_BDH *(volatile uint8_t *)0x4006A000 // UART Baud Rate Registers: High
#define UART0_BDL *(volatile uint8_t *)0x4006A001 // UART Baud Rate Registers: Low
#define UART0_C1 *(volatile uint8_t *)0x4006A002 // UART Control Register 1
- #define UART_C1_LOOPS (uint8_t)0x80 // When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input
- #define UART_C1_UARTSWAI (uint8_t)0x40 // UART Stops in Wait Mode
- #define UART_C1_RSRC (uint8_t)0x20 // When LOOPS is set, the RSRC field determines the source for the receiver shift register input
- #define UART_C1_M (uint8_t)0x10 // 9-bit or 8-bit Mode Select
- #define UART_C1_WAKE (uint8_t)0x08 // Determines which condition wakes the UART
- #define UART_C1_ILT (uint8_t)0x04 // Idle Line Type Select
- #define UART_C1_PE (uint8_t)0x02 // Parity Enable
- #define UART_C1_PT (uint8_t)0x01 // Parity Type, 0=even, 1=odd
+ #define UART_C1_LOOPS (uint8_t)0x80 // When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input
+ #define UART_C1_UARTSWAI (uint8_t)0x40 // UART Stops in Wait Mode
+ #define UART_C1_RSRC (uint8_t)0x20 // When LOOPS is set, the RSRC field determines the source for the receiver shift register input
+ #define UART_C1_M (uint8_t)0x10 // 9-bit or 8-bit Mode Select
+ #define UART_C1_WAKE (uint8_t)0x08 // Determines which condition wakes the UART
+ #define UART_C1_ILT (uint8_t)0x04 // Idle Line Type Select
+ #define UART_C1_PE (uint8_t)0x02 // Parity Enable
+ #define UART_C1_PT (uint8_t)0x01 // Parity Type, 0=even, 1=odd
#define UART0_C2 *(volatile uint8_t *)0x4006A003 // UART Control Register 2
- #define UART_C2_TIE (uint8_t)0x80 // Transmitter Interrupt or DMA Transfer Enable.
- #define UART_C2_TCIE (uint8_t)0x40 // Transmission Complete Interrupt Enable
- #define UART_C2_RIE (uint8_t)0x20 // Receiver Full Interrupt or DMA Transfer Enable
- #define UART_C2_ILIE (uint8_t)0x10 // Idle Line Interrupt Enable
- #define UART_C2_TE (uint8_t)0x08 // Transmitter Enable
- #define UART_C2_RE (uint8_t)0x04 // Receiver Enable
- #define UART_C2_RWU (uint8_t)0x02 // Receiver Wakeup Control
- #define UART_C2_SBK (uint8_t)0x01 // Send Break
+ #define UART_C2_TIE (uint8_t)0x80 // Transmitter Interrupt or DMA Transfer Enable.
+ #define UART_C2_TCIE (uint8_t)0x40 // Transmission Complete Interrupt Enable
+ #define UART_C2_RIE (uint8_t)0x20 // Receiver Full Interrupt or DMA Transfer Enable
+ #define UART_C2_ILIE (uint8_t)0x10 // Idle Line Interrupt Enable
+ #define UART_C2_TE (uint8_t)0x08 // Transmitter Enable
+ #define UART_C2_RE (uint8_t)0x04 // Receiver Enable
+ #define UART_C2_RWU (uint8_t)0x02 // Receiver Wakeup Control
+ #define UART_C2_SBK (uint8_t)0x01 // Send Break
#define UART0_S1 *(volatile uint8_t *)0x4006A004 // UART Status Register 1
- #define UART_S1_TDRE (uint8_t)0x80 // Transmit Data Register Empty Flag
- #define UART_S1_TC (uint8_t)0x40 // Transmit Complete Flag
- #define UART_S1_RDRF (uint8_t)0x20 // Receive Data Register Full Flag
- #define UART_S1_IDLE (uint8_t)0x10 // Idle Line Flag
- #define UART_S1_OR (uint8_t)0x08 // Receiver Overrun Flag
- #define UART_S1_NF (uint8_t)0x04 // Noise Flag
- #define UART_S1_FE (uint8_t)0x02 // Framing Error Flag
- #define UART_S1_PF (uint8_t)0x01 // Parity Error Flag
- #define UART0_S2 *(volatile uint8_t *)0x4006A005 // UART Status Register 2
- #define UART0_C3 *(volatile uint8_t *)0x4006A006 // UART Control Register 3
- #define UART0_D *(volatile uint8_t *)0x4006A007 // UART Data Register
- #define UART0_MA1 *(volatile uint8_t *)0x4006A008 // UART Match Address Registers 1
- #define UART0_MA2 *(volatile uint8_t *)0x4006A009 // UART Match Address Registers 2
- #define UART0_C4 *(volatile uint8_t *)0x4006A00A // UART Control Register 4
- #define UART0_C5 *(volatile uint8_t *)0x4006A00B // UART Control Register 5
- #define UART0_ED *(volatile uint8_t *)0x4006A00C // UART Extended Data Register
- #define UART0_MODEM *(volatile uint8_t *)0x4006A00D // UART Modem Register
- #define UART0_IR *(volatile uint8_t *)0x4006A00E // UART Infrared Register
- #define UART0_PFIFO *(volatile uint8_t *)0x4006A010 // UART FIFO Parameters
- #define UART_PFIFO_TXFE (uint8_t)0x80
+ #define UART_S1_TDRE (uint8_t)0x80 // Transmit Data Register Empty Flag
+ #define UART_S1_TC (uint8_t)0x40 // Transmit Complete Flag
+ #define UART_S1_RDRF (uint8_t)0x20 // Receive Data Register Full Flag
+ #define UART_S1_IDLE (uint8_t)0x10 // Idle Line Flag
+ #define UART_S1_OR (uint8_t)0x08 // Receiver Overrun Flag
+ #define UART_S1_NF (uint8_t)0x04 // Noise Flag
+ #define UART_S1_FE (uint8_t)0x02 // Framing Error Flag
+ #define UART_S1_PF (uint8_t)0x01 // Parity Error Flag
+ #define UART0_S2 *(volatile uint8_t *)0x4006A005 // UART Status Register 2
+ #define UART0_C3 *(volatile uint8_t *)0x4006A006 // UART Control Register 3
+ #define UART0_D *(volatile uint8_t *)0x4006A007 // UART Data Register
+ #define UART0_MA1 *(volatile uint8_t *)0x4006A008 // UART Match Address Registers 1
+ #define UART0_MA2 *(volatile uint8_t *)0x4006A009 // UART Match Address Registers 2
+ #define UART0_C4 *(volatile uint8_t *)0x4006A00A // UART Control Register 4
+ #define UART0_C5 *(volatile uint8_t *)0x4006A00B // UART Control Register 5
+ #define UART0_ED *(volatile uint8_t *)0x4006A00C // UART Extended Data Register
+ #define UART0_MODEM *(volatile uint8_t *)0x4006A00D // UART Modem Register
+ #define UART0_IR *(volatile uint8_t *)0x4006A00E // UART Infrared Register
+ #define UART0_PFIFO *(volatile uint8_t *)0x4006A010 // UART FIFO Parameters
+ #define UART_PFIFO_TXFE (uint8_t)0x80
+#define UART_PFIFO_TXFIFOSIZE (uint8_t)0x70
- #define UART_PFIFO_RXFE (uint8_t)0x08
+ #define UART_PFIFO_RXFE (uint8_t)0x08
+#define UART_PFIFO_RXFIFOSIZE (uint8_t)0x07
#define UART0_CFIFO *(volatile uint8_t *)0x4006A011 // UART FIFO Control Register
- #define UART_CFIFO_TXFLUSH (uint8_t)0x80 //
- #define UART_CFIFO_RXFLUSH (uint8_t)0x40 //
- #define UART_CFIFO_RXOFE (uint8_t)0x04 //
- #define UART_CFIFO_TXOFE (uint8_t)0x02 //
- #define UART_CFIFO_RXUFE (uint8_t)0x01 //
-#define UART_CFIFO_TXFLUSH (uint8_t)0x80 //
-#define UART_CFIFO_RXFLUSH (uint8_t)0x40 //
-#define UART_CFIFO_RXOFE (uint8_t)0x04 //
-#define UART_CFIFO_TXOFE (uint8_t)0x02 //
-#define UART_CFIFO_RXUFE (uint8_t)0x01 //
++#define UART_CFIFO_TXFLUSH (uint8_t)0x80 //
++#define UART_CFIFO_RXFLUSH (uint8_t)0x40 //
++#define UART_CFIFO_RXOFE (uint8_t)0x04 //
++#define UART_CFIFO_TXOFE (uint8_t)0x02 //
++#define UART_CFIFO_RXUFE (uint8_t)0x01 //
#define UART0_SFIFO *(volatile uint8_t *)0x4006A012 // UART FIFO Status Register
- #define UART_SFIFO_TXEMPT (uint8_t)0x80
- #define UART_SFIFO_RXEMPT (uint8_t)0x40
- #define UART_SFIFO_RXOF (uint8_t)0x04
- #define UART_SFIFO_TXOF (uint8_t)0x02
- #define UART_SFIFO_RXUF (uint8_t)0x01
+ #define UART_SFIFO_TXEMPT (uint8_t)0x80
+ #define UART_SFIFO_RXEMPT (uint8_t)0x40
+ #define UART_SFIFO_RXOF (uint8_t)0x04
+ #define UART_SFIFO_TXOF (uint8_t)0x02
+ #define UART_SFIFO_RXUF (uint8_t)0x01
#define UART0_TWFIFO *(volatile uint8_t *)0x4006A013 // UART FIFO Transmit Watermark
#define UART0_TCFIFO *(volatile uint8_t *)0x4006A014 // UART FIFO Transmit Count
#define UART0_RWFIFO *(volatile uint8_t *)0x4006A015 // UART FIFO Receive Watermark
// Chapter 48: Touch sense input (TSI)
#define TSI0_GENCS *(volatile uint32_t *)0x40045000 // General Control and Status Register
- #define TSI_GENCS_LPCLKS (uint32_t)0x10000000 //
- #define TSI_GENCS_LPSCNITV(n) (((n) & 15) << 24) //
- #define TSI_GENCS_NSCN(n) (((n) & 31) << 19) //
- #define TSI_GENCS_PS(n) (((n) & 7) << 16) //
- #define TSI_GENCS_EOSF (uint32_t)0x00008000 //
- #define TSI_GENCS_OUTRGF (uint32_t)0x00004000 //
- #define TSI_GENCS_EXTERF (uint32_t)0x00002000 //
- #define TSI_GENCS_OVRF (uint32_t)0x00001000 //
- #define TSI_GENCS_SCNIP (uint32_t)0x00000200 //
- #define TSI_GENCS_SWTS (uint32_t)0x00000100 //
- #define TSI_GENCS_TSIEN (uint32_t)0x00000080 //
- #define TSI_GENCS_TSIIE (uint32_t)0x00000040 //
- #define TSI_GENCS_ERIE (uint32_t)0x00000020 //
- #define TSI_GENCS_ESOR (uint32_t)0x00000010 //
- #define TSI_GENCS_STM (uint32_t)0x00000002 //
- #define TSI_GENCS_STPE (uint32_t)0x00000001 //
-#define TSI_GENCS_LPCLKS (uint32_t)0x10000000 //
-#define TSI_GENCS_LPSCNITV(n) (((n) & 15) << 24) //
-#define TSI_GENCS_NSCN(n) (((n) & 31) << 19) //
-#define TSI_GENCS_PS(n) (((n) & 7) << 16) //
-#define TSI_GENCS_EOSF (uint32_t)0x00008000 //
-#define TSI_GENCS_OUTRGF (uint32_t)0x00004000 //
-#define TSI_GENCS_EXTERF (uint32_t)0x00002000 //
-#define TSI_GENCS_OVRF (uint32_t)0x00001000 //
-#define TSI_GENCS_SCNIP (uint32_t)0x00000200 //
-#define TSI_GENCS_SWTS (uint32_t)0x00000100 //
-#define TSI_GENCS_TSIEN (uint32_t)0x00000080 //
-#define TSI_GENCS_TSIIE (uint32_t)0x00000040 //
-#define TSI_GENCS_ERIE (uint32_t)0x00000020 //
-#define TSI_GENCS_ESOR (uint32_t)0x00000010 //
-#define TSI_GENCS_STM (uint32_t)0x00000002 //
-#define TSI_GENCS_STPE (uint32_t)0x00000001 //
++#define TSI_GENCS_LPCLKS (uint32_t)0x10000000 //
++#define TSI_GENCS_LPSCNITV(n) (((n) & 15) << 24) //
++#define TSI_GENCS_NSCN(n) (((n) & 31) << 19) //
++#define TSI_GENCS_PS(n) (((n) & 7) << 16) //
++#define TSI_GENCS_EOSF (uint32_t)0x00008000 //
++#define TSI_GENCS_OUTRGF (uint32_t)0x00004000 //
++#define TSI_GENCS_EXTERF (uint32_t)0x00002000 //
++#define TSI_GENCS_OVRF (uint32_t)0x00001000 //
++#define TSI_GENCS_SCNIP (uint32_t)0x00000200 //
++#define TSI_GENCS_SWTS (uint32_t)0x00000100 //
++#define TSI_GENCS_TSIEN (uint32_t)0x00000080 //
++#define TSI_GENCS_TSIIE (uint32_t)0x00000040 //
++#define TSI_GENCS_ERIE (uint32_t)0x00000020 //
++#define TSI_GENCS_ESOR (uint32_t)0x00000010 //
++#define TSI_GENCS_STM (uint32_t)0x00000002 //
++#define TSI_GENCS_STPE (uint32_t)0x00000001 //
#define TSI0_SCANC *(volatile uint32_t *)0x40045004 // SCAN Control Register
- #define TSI_SCANC_REFCHRG(n) (((n) & 15) << 24) //
- #define TSI_SCANC_EXTCHRG(n) (((n) & 7) << 16) //
- #define TSI_SCANC_SMOD(n) (((n) & 255) << 8) //
- #define TSI_SCANC_AMCLKS(n) (((n) & 3) << 3) //
- #define TSI_SCANC_AMPSC(n) (((n) & 7) << 0) //
-#define TSI_SCANC_REFCHRG(n) (((n) & 15) << 24) //
-#define TSI_SCANC_EXTCHRG(n) (((n) & 7) << 16) //
-#define TSI_SCANC_SMOD(n) (((n) & 255) << 8) //
-#define TSI_SCANC_AMCLKS(n) (((n) & 3) << 3) //
-#define TSI_SCANC_AMPSC(n) (((n) & 7) << 0) //
++#define TSI_SCANC_REFCHRG(n) (((n) & 15) << 24) //
++#define TSI_SCANC_EXTCHRG(n) (((n) & 7) << 16) //
++#define TSI_SCANC_SMOD(n) (((n) & 255) << 8) //
++#define TSI_SCANC_AMCLKS(n) (((n) & 3) << 3) //
++#define TSI_SCANC_AMPSC(n) (((n) & 7) << 0) //
#define TSI0_PEN *(volatile uint32_t *)0x40045008 // Pin Enable Register
#define TSI0_WUCNTR *(volatile uint32_t *)0x4004500C // Wake-Up Channel Counter Register
#define TSI0_CNTR1 *(volatile uint32_t *)0x40045100 // Counter Register
projects / kiibohd-controller.git / commitdiff