Lib/mk20dx.c

   1 /* Teensyduino Core Library
   2  * http://www.pjrc.com/teensy/
   3  * Copyright (c) 2013 PJRC.COM, LLC.
   4  * Modifications by Jacob Alexander 2014
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * 1. The above copyright notice and this permission notice shall be
  15  * included in all copies or substantial portions of the Software.
  16  *
  17  * 2. If the Software is incorporated into a build system that allows
  18  * selection among a list of target devices, then similar target
  19  * devices manufactured by PJRC.COM must be included in the list of
  20  * target devices and selectable in the same manner.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  23  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  25  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  26  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  27  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  28  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  29  * SOFTWARE.
  30  */
  31
  32 #include "mk20dx.h"
  33
  34
  35 extern unsigned long _stext;
  36 extern unsigned long _etext;
  37 extern unsigned long _sdata;
  38 extern unsigned long _edata;
  39 extern unsigned long _sbss;
  40 extern unsigned long _ebss;
  41 extern unsigned long _estack;
  42 extern int main (void);
  43 void ResetHandler(void);
  44 void __libc_init_array(void);
  45
  46
  47 void fault_isr(void)
  48 {
  49         while (1) {
  50                 // keep polling some communication while in fault
  51                 // mode, so we don't completely die.
  52                 if (SIM_SCGC4 & SIM_SCGC4_USBOTG) usb_isr();
  53                 if (SIM_SCGC4 & SIM_SCGC4_UART0) uart0_status_isr();
  54                 if (SIM_SCGC4 & SIM_SCGC4_UART1) uart1_status_isr();
  55                 if (SIM_SCGC4 & SIM_SCGC4_UART2) uart2_status_isr();
  56         }
  57 }
  58
  59 void unused_isr(void)
  60 {
  61         fault_isr();
  62 }
  63
  64 extern volatile uint32_t systick_millis_count;
  65 void systick_default_isr(void)
  66 {
  67         systick_millis_count++;
  68 }
  69
  70 void nmi_isr(void)              __attribute__ ((weak, alias("unused_isr")));
  71 void hard_fault_isr(void)       __attribute__ ((weak, alias("unused_isr")));
  72 void memmanage_fault_isr(void)  __attribute__ ((weak, alias("unused_isr")));
  73 void bus_fault_isr(void)        __attribute__ ((weak, alias("unused_isr")));
  74 void usage_fault_isr(void)      __attribute__ ((weak, alias("unused_isr")));
  75 void svcall_isr(void)           __attribute__ ((weak, alias("unused_isr")));
  76 void debugmonitor_isr(void)     __attribute__ ((weak, alias("unused_isr")));
  77 void pendablesrvreq_isr(void)   __attribute__ ((weak, alias("unused_isr")));
  78 void systick_isr(void)          __attribute__ ((weak, alias("systick_default_isr")));
  79
  80 void dma_ch0_isr(void)          __attribute__ ((weak, alias("unused_isr")));
  81 void dma_ch1_isr(void)          __attribute__ ((weak, alias("unused_isr")));
  82 void dma_ch2_isr(void)          __attribute__ ((weak, alias("unused_isr")));
  83 void dma_ch3_isr(void)          __attribute__ ((weak, alias("unused_isr")));
  84 void dma_ch4_isr(void)          __attribute__ ((weak, alias("unused_isr")));
  85 void dma_ch5_isr(void)          __attribute__ ((weak, alias("unused_isr")));
  86 void dma_ch6_isr(void)          __attribute__ ((weak, alias("unused_isr")));
  87 void dma_ch7_isr(void)          __attribute__ ((weak, alias("unused_isr")));
  88 void dma_ch8_isr(void)          __attribute__ ((weak, alias("unused_isr")));
  89 void dma_ch9_isr(void)          __attribute__ ((weak, alias("unused_isr")));
  90 void dma_ch10_isr(void)         __attribute__ ((weak, alias("unused_isr")));
  91 void dma_ch11_isr(void)         __attribute__ ((weak, alias("unused_isr")));
  92 void dma_ch12_isr(void)         __attribute__ ((weak, alias("unused_isr")));
  93 void dma_ch13_isr(void)         __attribute__ ((weak, alias("unused_isr")));
  94 void dma_ch14_isr(void)         __attribute__ ((weak, alias("unused_isr")));
  95 void dma_ch15_isr(void)         __attribute__ ((weak, alias("unused_isr")));
  96 void dma_error_isr(void)        __attribute__ ((weak, alias("unused_isr")));
  97 void mcm_isr(void)              __attribute__ ((weak, alias("unused_isr")));
  98 void flash_cmd_isr(void)        __attribute__ ((weak, alias("unused_isr")));
  99 void flash_error_isr(void)      __attribute__ ((weak, alias("unused_isr")));
 100 void low_voltage_isr(void)      __attribute__ ((weak, alias("unused_isr")));
 101 void wakeup_isr(void)           __attribute__ ((weak, alias("unused_isr")));
 102 void watchdog_isr(void)         __attribute__ ((weak, alias("unused_isr")));
 103 void i2c0_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 104 void i2c1_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 105 void i2c2_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 106 void spi0_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 107 void spi1_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 108 void spi2_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 109 void sdhc_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 110 void can0_message_isr(void)     __attribute__ ((weak, alias("unused_isr")));
 111 void can0_bus_off_isr(void)     __attribute__ ((weak, alias("unused_isr")));
 112 void can0_error_isr(void)       __attribute__ ((weak, alias("unused_isr")));
 113 void can0_tx_warn_isr(void)     __attribute__ ((weak, alias("unused_isr")));
 114 void can0_rx_warn_isr(void)     __attribute__ ((weak, alias("unused_isr")));
 115 void can0_wakeup_isr(void)      __attribute__ ((weak, alias("unused_isr")));
 116 void i2s0_tx_isr(void)          __attribute__ ((weak, alias("unused_isr")));
 117 void i2s0_rx_isr(void)          __attribute__ ((weak, alias("unused_isr")));
 118 void uart0_lon_isr(void)        __attribute__ ((weak, alias("unused_isr")));
 119 void uart0_status_isr(void)     __attribute__ ((weak, alias("unused_isr")));
 120 void uart0_error_isr(void)      __attribute__ ((weak, alias("unused_isr")));
 121 void uart1_status_isr(void)     __attribute__ ((weak, alias("unused_isr")));
 122 void uart1_error_isr(void)      __attribute__ ((weak, alias("unused_isr")));
 123 void uart2_status_isr(void)     __attribute__ ((weak, alias("unused_isr")));
 124 void uart2_error_isr(void)      __attribute__ ((weak, alias("unused_isr")));
 125 void uart3_status_isr(void)     __attribute__ ((weak, alias("unused_isr")));
 126 void uart3_error_isr(void)      __attribute__ ((weak, alias("unused_isr")));
 127 void uart4_status_isr(void)     __attribute__ ((weak, alias("unused_isr")));
 128 void uart4_error_isr(void)      __attribute__ ((weak, alias("unused_isr")));
 129 void uart5_status_isr(void)     __attribute__ ((weak, alias("unused_isr")));
 130 void uart5_error_isr(void)      __attribute__ ((weak, alias("unused_isr")));
 131 void adc0_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 132 void adc1_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 133 void cmp0_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 134 void cmp1_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 135 void cmp2_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 136 void ftm0_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 137 void ftm1_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 138 void ftm2_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 139 void ftm3_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 140 void cmt_isr(void)              __attribute__ ((weak, alias("unused_isr")));
 141 void rtc_alarm_isr(void)        __attribute__ ((weak, alias("unused_isr")));
 142 void rtc_seconds_isr(void)      __attribute__ ((weak, alias("unused_isr")));
 143 void pit0_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 144 void pit1_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 145 void pit2_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 146 void pit3_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 147 void pdb_isr(void)              __attribute__ ((weak, alias("unused_isr")));
 148 void usb_isr(void)              __attribute__ ((weak, alias("unused_isr")));
 149 void usb_charge_isr(void)       __attribute__ ((weak, alias("unused_isr")));
 150 void dac0_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 151 void dac1_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 152 void tsi0_isr(void)             __attribute__ ((weak, alias("unused_isr")));
 153 void mcg_isr(void)              __attribute__ ((weak, alias("unused_isr")));
 154 void lptmr_isr(void)            __attribute__ ((weak, alias("unused_isr")));
 155 void porta_isr(void)            __attribute__ ((weak, alias("unused_isr")));
 156 void portb_isr(void)            __attribute__ ((weak, alias("unused_isr")));
 157 void portc_isr(void)            __attribute__ ((weak, alias("unused_isr")));
 158 void portd_isr(void)            __attribute__ ((weak, alias("unused_isr")));
 159 void porte_isr(void)            __attribute__ ((weak, alias("unused_isr")));
 160 void software_isr(void)         __attribute__ ((weak, alias("unused_isr")));
 161
 162
 163 // TODO: create AVR-stype ISR() macro, with default linkage to undefined handler
 164 //
 165 __attribute__ ((section(".vectors"), used))
 166 void (* const gVectors[])(void) =
 167 {
 168         (void (*)(void))((unsigned long)&_estack),      //  0 ARM: Initial Stack Pointer
 169         ResetHandler,                                   //  1 ARM: Initial Program Counter
 170         nmi_isr,                                        //  2 ARM: Non-maskable Interrupt (NMI)
 171         hard_fault_isr,                                 //  3 ARM: Hard Fault
 172         memmanage_fault_isr,                            //  4 ARM: MemManage Fault
 173         bus_fault_isr,                                  //  5 ARM: Bus Fault
 174         usage_fault_isr,                                //  6 ARM: Usage Fault
 175         fault_isr,                                      //  7 --
 176         fault_isr,                                      //  8 --
 177         fault_isr,                                      //  9 --
 178         fault_isr,                                      // 10 --
 179         svcall_isr,                                     // 11 ARM: Supervisor call (SVCall)
 180         debugmonitor_isr,                               // 12 ARM: Debug Monitor
 181         fault_isr,                                      // 13 --
 182         pendablesrvreq_isr,                             // 14 ARM: Pendable req serv(PendableSrvReq)
 183         systick_isr,                                    // 15 ARM: System tick timer (SysTick)
 184 #if defined(_mk20dx128_) || defined(_mk20dx128vlf5_)
 185         dma_ch0_isr,                                    // 16 DMA channel 0 transfer complete
 186         dma_ch1_isr,                                    // 17 DMA channel 1 transfer complete
 187         dma_ch2_isr,                                    // 18 DMA channel 2 transfer complete
 188         dma_ch3_isr,                                    // 19 DMA channel 3 transfer complete
 189         dma_error_isr,                                  // 20 DMA error interrupt channel
 190         unused_isr,                                     // 21 DMA --
 191         flash_cmd_isr,                                  // 22 Flash Memory Command complete
 192         flash_error_isr,                                // 23 Flash Read collision
 193         low_voltage_isr,                                // 24 Low-voltage detect/warning
 194         wakeup_isr,                                     // 25 Low Leakage Wakeup
 195         watchdog_isr,                                   // 26 Both EWM and WDOG interrupt
 196         i2c0_isr,                                       // 27 I2C0
 197         spi0_isr,                                       // 28 SPI0
 198         i2s0_tx_isr,                                    // 29 I2S0 Transmit
 199         i2s0_rx_isr,                                    // 30 I2S0 Receive
 200         uart0_lon_isr,                                  // 31 UART0 CEA709.1-B (LON) status
 201         uart0_status_isr,                               // 32 UART0 status
 202         uart0_error_isr,                                // 33 UART0 error
 203         uart1_status_isr,                               // 34 UART1 status
 204         uart1_error_isr,                                // 35 UART1 error
 205         uart2_status_isr,                               // 36 UART2 status
 206         uart2_error_isr,                                // 37 UART2 error
 207         adc0_isr,                                       // 38 ADC0
 208         cmp0_isr,                                       // 39 CMP0
 209         cmp1_isr,                                       // 40 CMP1
 210         ftm0_isr,                                       // 41 FTM0
 211         ftm1_isr,                                       // 42 FTM1
 212         cmt_isr,                                        // 43 CMT
 213         rtc_alarm_isr,                                  // 44 RTC Alarm interrupt
 214         rtc_seconds_isr,                                // 45 RTC Seconds interrupt
 215         pit0_isr,                                       // 46 PIT Channel 0
 216         pit1_isr,                                       // 47 PIT Channel 1
 217         pit2_isr,                                       // 48 PIT Channel 2
 218         pit3_isr,                                       // 49 PIT Channel 3
 219         pdb_isr,                                        // 50 PDB Programmable Delay Block
 220         usb_isr,                                        // 51 USB OTG
 221         usb_charge_isr,                                 // 52 USB Charger Detect
 222         tsi0_isr,                                       // 53 TSI0
 223         mcg_isr,                                        // 54 MCG
 224         lptmr_isr,                                      // 55 Low Power Timer
 225         porta_isr,                                      // 56 Pin detect (Port A)
 226         portb_isr,                                      // 57 Pin detect (Port B)
 227         portc_isr,                                      // 58 Pin detect (Port C)
 228         portd_isr,                                      // 59 Pin detect (Port D)
 229         porte_isr,                                      // 60 Pin detect (Port E)
 230         software_isr,                                   // 61 Software interrupt
 231 #elif defined(_mk20dx256_)
 232         dma_ch0_isr,                                    // 16 DMA channel 0 transfer complete
 233         dma_ch1_isr,                                    // 17 DMA channel 1 transfer complete
 234         dma_ch2_isr,                                    // 18 DMA channel 2 transfer complete
 235         dma_ch3_isr,                                    // 19 DMA channel 3 transfer complete
 236         dma_ch4_isr,                                    // 20 DMA channel 4 transfer complete
 237         dma_ch5_isr,                                    // 21 DMA channel 5 transfer complete
 238         dma_ch6_isr,                                    // 22 DMA channel 6 transfer complete
 239         dma_ch7_isr,                                    // 23 DMA channel 7 transfer complete
 240         dma_ch8_isr,                                    // 24 DMA channel 8 transfer complete
 241         dma_ch9_isr,                                    // 25 DMA channel 9 transfer complete
 242         dma_ch10_isr,                                   // 26 DMA channel 10 transfer complete
 243         dma_ch11_isr,                                   // 27 DMA channel 10 transfer complete
 244         dma_ch12_isr,                                   // 28 DMA channel 10 transfer complete
 245         dma_ch13_isr,                                   // 29 DMA channel 10 transfer complete
 246         dma_ch14_isr,                                   // 30 DMA channel 10 transfer complete
 247         dma_ch15_isr,                                   // 31 DMA channel 10 transfer complete
 248         dma_error_isr,                                  // 32 DMA error interrupt channel
 249         unused_isr,                                     // 33 --
 250         flash_cmd_isr,                                  // 34 Flash Memory Command complete
 251         flash_error_isr,                                // 35 Flash Read collision
 252         low_voltage_isr,                                // 36 Low-voltage detect/warning
 253         wakeup_isr,                                     // 37 Low Leakage Wakeup
 254         watchdog_isr,                                   // 38 Both EWM and WDOG interrupt
 255         unused_isr,                                     // 39 --
 256         i2c0_isr,                                       // 40 I2C0
 257         i2c1_isr,                                       // 41 I2C1
 258         spi0_isr,                                       // 42 SPI0
 259         spi1_isr,                                       // 43 SPI1
 260         unused_isr,                                     // 44 --
 261         can0_message_isr,                               // 45 CAN OR'ed Message buffer (0-15)
 262         can0_bus_off_isr,                               // 46 CAN Bus Off
 263         can0_error_isr,                                 // 47 CAN Error
 264         can0_tx_warn_isr,                               // 48 CAN Transmit Warning
 265         can0_rx_warn_isr,                               // 49 CAN Receive Warning
 266         can0_wakeup_isr,                                // 50 CAN Wake Up
 267         i2s0_tx_isr,                                    // 51 I2S0 Transmit
 268         i2s0_rx_isr,                                    // 52 I2S0 Receive
 269         unused_isr,                                     // 53 --
 270         unused_isr,                                     // 54 --
 271         unused_isr,                                     // 55 --
 272         unused_isr,                                     // 56 --
 273         unused_isr,                                     // 57 --
 274         unused_isr,                                     // 58 --
 275         unused_isr,                                     // 59 --
 276         uart0_lon_isr,                                  // 60 UART0 CEA709.1-B (LON) status
 277         uart0_status_isr,                               // 61 UART0 status
 278         uart0_error_isr,                                // 62 UART0 error
 279         uart1_status_isr,                               // 63 UART1 status
 280         uart1_error_isr,                                // 64 UART1 error
 281         uart2_status_isr,                               // 65 UART2 status
 282         uart2_error_isr,                                // 66 UART2 error
 283         unused_isr,                                     // 67 --
 284         unused_isr,                                     // 68 --
 285         unused_isr,                                     // 69 --
 286         unused_isr,                                     // 70 --
 287         unused_isr,                                     // 71 --
 288         unused_isr,                                     // 72 --
 289         adc0_isr,                                       // 73 ADC0
 290         adc1_isr,                                       // 74 ADC1
 291         cmp0_isr,                                       // 75 CMP0
 292         cmp1_isr,                                       // 76 CMP1
 293         cmp2_isr,                                       // 77 CMP2
 294         ftm0_isr,                                       // 78 FTM0
 295         ftm1_isr,                                       // 79 FTM1
 296         ftm2_isr,                                       // 80 FTM2
 297         cmt_isr,                                        // 81 CMT
 298         rtc_alarm_isr,                                  // 82 RTC Alarm interrupt
 299         rtc_seconds_isr,                                // 83 RTC Seconds interrupt
 300         pit0_isr,                                       // 84 PIT Channel 0
 301         pit1_isr,                                       // 85 PIT Channel 1
 302         pit2_isr,                                       // 86 PIT Channel 2
 303         pit3_isr,                                       // 87 PIT Channel 3
 304         pdb_isr,                                        // 88 PDB Programmable Delay Block
 305         usb_isr,                                        // 89 USB OTG
 306         usb_charge_isr,                                 // 90 USB Charger Detect
 307         unused_isr,                                     // 91 --
 308         unused_isr,                                     // 92 --
 309         unused_isr,                                     // 93 --
 310         unused_isr,                                     // 94 --
 311         unused_isr,                                     // 95 --
 312         unused_isr,                                     // 96 --
 313         dac0_isr,                                       // 97 DAC0
 314         unused_isr,                                     // 98 --
 315         tsi0_isr,                                       // 99 TSI0
 316         mcg_isr,                                        // 100 MCG
 317         lptmr_isr,                                      // 101 Low Power Timer
 318         unused_isr,                                     // 102 --
 319         porta_isr,                                      // 103 Pin detect (Port A)
 320         portb_isr,                                      // 104 Pin detect (Port B)
 321         portc_isr,                                      // 105 Pin detect (Port C)
 322         portd_isr,                                      // 106 Pin detect (Port D)
 323         porte_isr,                                      // 107 Pin detect (Port E)
 324         unused_isr,                                     // 108 --
 325         unused_isr,                                     // 109 --
 326         software_isr,                                   // 110 Software interrupt
 327 #endif
 328 };
 329
 330
 331 #if defined(_mk20dx128_) || defined(_mk20dx256_)
 332
 333 __attribute__ ((section(".flashconfig"), used))
 334 const uint8_t flashconfigbytes[16] = {
 335         0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 336         0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF
 337 };
 338
 339 #endif
 340
 341
 342 // Automatically initialize the RTC.  When the build defines the compile
 343 // time, and the user has added a crystal, the RTC will automatically
 344 // begin at the time of the first upload.
 345 #ifndef TIME_T
 346 #define TIME_T 1349049600 // default 1 Oct 2012 (never used, Arduino sets this)
 347 #endif
 348 extern void rtc_set(unsigned long t);
 349
 350
 351 __attribute__ ((section(".startup")))
 352 void ResetHandler(void)
 353 {
 354         uint32_t *src = &_etext;
 355         uint32_t *dest = &_sdata;
 356         unsigned int i;
 357
 358         /* Disable Watchdog */
 359         WDOG_UNLOCK = WDOG_UNLOCK_SEQ1;
 360         WDOG_UNLOCK = WDOG_UNLOCK_SEQ2;
 361         WDOG_STCTRLH = WDOG_STCTRLH_ALLOWUPDATE;
 362
 363         // enable clocks to always-used peripherals
 364 #if defined(_mk20dx128_) || defined(_mk20dx128vlf5_)
 365         SIM_SCGC5 = 0x00043F82;         // clocks active to all GPIO
 366         SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;
 367 #elif defined(_mk20dx256_)
 368         SIM_SCGC3 = SIM_SCGC3_ADC1 | SIM_SCGC3_FTM2;
 369         SIM_SCGC5 = 0x00043F82;         // clocks active to all GPIO
 370         SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;
 371 #endif
 372
 373         // if the RTC oscillator isn't enabled, get it started early
 374         if (!(RTC_CR & RTC_CR_OSCE)) {
 375                 RTC_SR = 0;
 376                 RTC_CR = RTC_CR_SC16P | RTC_CR_SC4P | RTC_CR_OSCE;
 377         }
 378
 379         // release I/O pins hold, if we woke up from VLLS mode
 380         if (PMC_REGSC & PMC_REGSC_ACKISO) PMC_REGSC |= PMC_REGSC_ACKISO;
 381
 382         // TODO: do this while the PLL is waiting to lock....
 383         while (dest < &_edata) *dest++ = *src++;
 384         dest = &_sbss;
 385         while (dest < &_ebss) *dest++ = 0;
 386         SCB_VTOR = 0;   // use vector table in flash
 387
 388         // default all interrupts to medium priority level
 389         for (i=0; i < NVIC_NUM_INTERRUPTS; i++) NVIC_SET_PRIORITY(i, 128);
 390
 391 #if defined(_mk20dx128vlf5_)
 392         /* FLL at 48MHz */
 393         MCG_C4 = MCG_C4_DMX32 | MCG_C4_DRST_DRS(1);
 394
 395 #if F_CPU == 96000000
 396         // config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash
 397         SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |  SIM_CLKDIV1_OUTDIV4(3);
 398 #elif F_CPU == 48000000
 399         // config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash
 400         SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) |  SIM_CLKDIV1_OUTDIV4(3);
 401 #elif F_CPU == 24000000
 402         // config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash
 403         SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) |  SIM_CLKDIV1_OUTDIV4(3);
 404 #else
 405 #error "Error, F_CPU must be 96000000, 48000000, or 24000000"
 406 #endif
 407
 408         // switch to PLL as clock source, FLL input = 16 MHz / 512
 409         MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4);
 410
 411         // configure USB for 48 MHz clock
 412         SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // USB = 96 MHz PLL / 2
 413
 414         SIM_SOPT2 = SIM_SOPT2_PLLFLLSEL;
 415
 416         // initialize the SysTick counter
 417         SYST_RVR = (F_CPU / 1000) - 1;
 418         SYST_CSR = SYST_CSR_CLKSOURCE | SYST_CSR_TICKINT | SYST_CSR_ENABLE;
 419 #else
 420         // start in FEI mode
 421         // enable capacitors for crystal
 422         OSC0_CR = OSC_SC8P | OSC_SC2P;
 423         // enable osc, 8-32 MHz range, low power mode
 424         MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS;
 425         // switch to crystal as clock source, FLL input = 16 MHz / 512
 426         MCG_C1 =  MCG_C1_CLKS(2) | MCG_C1_FRDIV(4);
 427         // wait for crystal oscillator to begin
 428         while ((MCG_S & MCG_S_OSCINIT0) == 0) ;
 429         // wait for FLL to use oscillator
 430         while ((MCG_S & MCG_S_IREFST) != 0) ;
 431         // wait for MCGOUT to use oscillator
 432         while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) ;
 433         // now we're in FBE mode
 434         // config PLL input for 16 MHz Crystal / 4 = 4 MHz
 435         MCG_C5 = MCG_C5_PRDIV0(3);
 436         // config PLL for 96 MHz output
 437         MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
 438         // wait for PLL to start using xtal as its input
 439         while (!(MCG_S & MCG_S_PLLST)) ;
 440         // wait for PLL to lock
 441         while (!(MCG_S & MCG_S_LOCK0)) ;
 442         // now we're in PBE mode
 443 #if F_CPU == 96000000
 444         // config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash
 445         SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |  SIM_CLKDIV1_OUTDIV4(3);
 446 #elif F_CPU == 48000000
 447         // config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash
 448         SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) |  SIM_CLKDIV1_OUTDIV4(3);
 449 #elif F_CPU == 24000000
 450         // config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash
 451         SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) |  SIM_CLKDIV1_OUTDIV4(3);
 452 #else
 453 #error "Error, F_CPU must be 96000000, 48000000, or 24000000"
 454 #endif
 455         // switch to PLL as clock source, FLL input = 16 MHz / 512
 456         MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4);
 457         // wait for PLL clock to be used
 458         while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) ;
 459         // now we're in PEE mode
 460         // configure USB for 48 MHz clock
 461         SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // USB = 96 MHz PLL / 2
 462         // USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0
 463         SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6);
 464
 465         // initialize the SysTick counter
 466         SYST_RVR = (F_CPU / 1000) - 1;
 467         SYST_CSR = SYST_CSR_CLKSOURCE | SYST_CSR_TICKINT | SYST_CSR_ENABLE;
 468
 469 #endif
 470         __enable_irq();
 471         __libc_init_array();
 472
 473         main();
 474         while (1) ;
 475 }
 476
 477 char *__brkval = (char *)&_ebss;
 478
 479 void * _sbrk(int incr)
 480 {
 481         //static char *heap_end = (char *)&_ebss;
 482         //char *prev = heap_end;
 483         //heap_end += incr;
 484
 485         char *prev = __brkval;
 486         __brkval += incr;
 487         return prev;
 488 }
 489
 490 int nvic_execution_priority(void)
 491 {
 492         int priority=256;
 493         uint32_t primask, faultmask, basepri, ipsr;
 494
 495         // full algorithm in ARM DDI0403D, page B1-639
 496         // this isn't quite complete, but hopefully good enough
 497         asm volatile("mrs %0, faultmask\n" : "=r" (faultmask)::);
 498         if (faultmask) return -1;
 499         asm volatile("mrs %0, primask\n" : "=r" (primask)::);
 500         if (primask) return 0;
 501         asm volatile("mrs %0, ipsr\n" : "=r" (ipsr)::);
 502         if (ipsr) {
 503                 if (ipsr < 16) priority = 0; // could be non-zero
 504                 else priority = NVIC_GET_PRIORITY(ipsr - 16);
 505         }
 506         asm volatile("mrs %0, basepri\n" : "=r" (basepri)::);
 507         if (basepri > 0 && basepri < priority) priority = basepri;
 508         return priority;
 509 }
 510