1 ;---------------------------------------------------------------------------;
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2 ; Software implemented UART module ;
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3 ; (C)ChaN, 2005 (http://elm-chan.org/) ;
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4 ;---------------------------------------------------------------------------;
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7 ; 1MHz 2MHz 4MHz 6MHz 8MHz 10MHz 12MHz 16MHz 20MHz
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8 ; 2.4kbps 138 - - - - - - - -
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9 ; 4.8kbps 68 138 - - - - - - -
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10 ; 9.6kbps 33 68 138 208 - - - - -
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11 ; 19.2kbps - 33 68 102 138 173 208 - -
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12 ; 38.4kbps - - 33 50 68 85 102 138 172
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13 ; 57.6kbps - - 21 33 44 56 68 91 114
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14 ; 115.2kbps - - - - 21 27 33 44 56
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20 #define BPS 102 /* Bit delay. (see above table) */
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21 #define BIDIR 0 /* 0:Separated Tx/Rx, 1:Shared Tx/Rx */
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23 #define OUT_1 sbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT /* Output 1 */
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24 #define OUT_0 cbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT /* Output 0 */
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25 #define SKIP_IN_1 sbis _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT /* Skip if 1 */
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26 #define SKIP_IN_0 sbic _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT /* Skip if 0 */
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34 .macro _MOVW dh,dl, sh,sl
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43 .macro _MOVW dh,dl, sh,sl
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51 ;---------------------------------------------------------------------------;
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52 ; Transmit a byte in serial format of N81
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54 ;Prototype: void xmit (uint8_t data);
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61 ldi r23, BPS-1 ;Pre-idle time for bidirectional data line
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65 in r0, _SFR_IO_ADDR(SREG) ;Save flags
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67 com r24 ;C = start bit
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68 ldi r25, 10 ;Bit counter
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69 cli ;Start critical section
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71 1: ldi r23, BPS-1 ;----- Bit transferring loop
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72 2: dec r23 ;Wait for a bit time
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74 brcs 3f ;MISO = bit to be sent
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78 4: lsr r24 ;Get next bit into C
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79 dec r25 ;All bits sent?
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80 brne 1b ; no, coutinue
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82 out _SFR_IO_ADDR(SREG), r0 ;End of critical section
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88 ;---------------------------------------------------------------------------;
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91 ;Prototype: uint8_t rcvr (void);
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97 in r0, _SFR_IO_ADDR(SREG) ;Save flags
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99 ldi r24, 0x80 ;Receiving shift reg
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100 cli ;Start critical section
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102 1: SKIP_IN_1 ;Wait for idle
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104 2: SKIP_IN_0 ;Wait for start bit
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106 ldi r25, BPS/2 ;Wait for half bit time
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110 4: ldi r25, BPS ;----- Bit receiving loop
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111 5: dec r25 ;Wait for a bit time
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114 SKIP_IN_0 ;Get a data bit into r24.7
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116 brcc 4b ;All bits received? no, continue
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118 out _SFR_IO_ADDR(SREG), r0 ;End of critical section
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123 ; Not wait for start bit. This should be called after detecting start bit.
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127 in r0, _SFR_IO_ADDR(SREG) ;Save flags
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129 ldi r24, 0x80 ;Receiving shift reg
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130 cli ;Start critical section
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132 ;1: SKIP_IN_1 ;Wait for idle
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134 ;2: SKIP_IN_0 ;Wait for start bit
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136 ldi r25, BPS/2 ;Wait for half bit time
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140 4: ldi r25, BPS ;----- Bit receiving loop
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141 5: dec r25 ;Wait for a bit time
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144 SKIP_IN_0 ;Get a data bit into r24.7
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146 brcc 4b ;All bits received? no, continue
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148 ldi r25, BPS/2 ;Wait for half bit time
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151 7: SKIP_IN_1 ;Wait for stop bit
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154 out _SFR_IO_ADDR(SREG), r0 ;End of critical section
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