1 /* Copyright 2018 ishtob
2 * Driver for DRV2605L written for QMK
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "i2c_master.h"
21 /* Initialization settings
23 * Feedback Control Settings */
25 #define FB_ERM_LRA 1 /* For ERM:0 or LRA:1*/
27 #ifndef FB_BRAKEFACTOR
28 #define FB_BRAKEFACTOR 3 /* For 1x:0, 2x:1, 3x:2, 4x:3, 6x:4, 8x:5, 16x:6, Disable Braking:7 */
31 #define FB_LOOPGAIN 1 /* For Low:0, Medium:1, High:2, Very High:3 */
35 #define RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
41 /* LRA specific settings */
54 /* Library Selection */
57 #define LIB_SELECTION 6 /* For Empty:0' TS2200 library A to D:1-5, LRA Library: 6 */
59 #define LIB_SELECTION 1
63 /* Control 1 register settings */
71 #define STARTUP_BOOST 1
74 /* Control 2 Settings */
79 #define BRAKE_STAB 1 /* Loopgain is reduced when braking is almost complete to improve stability */
85 #define BLANKING_TIME 1
91 /* Control 3 settings */
96 #define ERM_OPEN_LOOP 1
98 #ifndef SUPPLY_COMP_DIS
99 #define SUPPLY_COMP_DIS 0
101 #ifndef DATA_FORMAT_RTO
102 #define DATA_FORMAT_RTO 0
104 #ifndef LRA_DRIVE_MODE
105 #define LRA_DRIVE_MODE 0
108 #define N_PWM_ANALOG 0
110 #ifndef LRA_OPEN_LOOP
111 #define LRA_OPEN_LOOP 0
114 /* Control 4 settings */
116 #define ZC_DET_TIME 0
118 #ifndef AUTO_CAL_TIME
119 #define AUTO_CAL_TIME 3
122 /* register defines -------------------------------------------------------- */
123 #define DRV2605L_BASE_ADDRESS 0x5A /* DRV2605L Base address */
124 #define DRV_STATUS 0x00
125 #define DRV_MODE 0x01
126 #define DRV_RTP_INPUT 0x02
127 #define DRV_LIB_SELECTION 0x03
128 #define DRV_WAVEFORM_SEQ_1 0x04
129 #define DRV_WAVEFORM_SEQ_2 0x05
130 #define DRV_WAVEFORM_SEQ_3 0x06
131 #define DRV_WAVEFORM_SEQ_4 0x07
132 #define DRV_WAVEFORM_SEQ_5 0x08
133 #define DRV_WAVEFORM_SEQ_6 0x09
134 #define DRV_WAVEFORM_SEQ_7 0x0A
135 #define DRV_WAVEFORM_SEQ_8 0x0B
137 #define DRV_OVERDRIVE_TIME_OFFSET 0x0D
138 #define DRV_SUSTAIN_TIME_OFFSET_P 0x0E
139 #define DRV_SUSTAIN_TIME_OFFSET_N 0x0F
140 #define DRV_BRAKE_TIME_OFFSET 0x10
141 #define DRV_AUDIO_2_VIBE_CTRL 0x11
142 #define DRV_AUDIO_2_VIBE_MIN_IN 0x12
143 #define DRV_AUDIO_2_VIBE_MAX_IN 0x13
144 #define DRV_AUDIO_2_VIBE_MIN_OUTDRV 0x14
145 #define DRV_AUDIO_2_VIBE_MAX_OUTDRV 0x15
146 #define DRV_RATED_VOLT 0x16
147 #define DRV_OVERDRIVE_CLAMP_VOLT 0x17
148 #define DRV_AUTO_CALIB_COMP_RESULT 0x18
149 #define DRV_AUTO_CALIB_BEMF_RESULT 0x19
150 #define DRV_FEEDBACK_CTRL 0x1A
151 #define DRV_CTRL_1 0x1B
152 #define DRV_CTRL_2 0x1C
153 #define DRV_CTRL_3 0x1D
154 #define DRV_CTRL_4 0x1E
155 #define DRV_CTRL_5 0x1F
156 #define DRV_OPEN_LOOP_PERIOD 0x20
157 #define DRV_VBAT_VOLT_MONITOR 0x21
158 #define DRV_LRA_RESONANCE_PERIOD 0x22
161 void DRV_write(const uint8_t drv_register, const uint8_t settings);
162 uint8_t DRV_read(const uint8_t regaddress);
163 void DRV_pulse(const uint8_t sequence);
166 typedef enum DRV_EFFECT{
185 strong_click2_80 = 18,
186 strong_click3_60 = 19,
187 strong_click4_30 = 20,
189 medium_click2_80 = 22,
190 medium_click3_60 = 23,
194 sh_dblclick_str = 27,
195 sh_dblclick_str_80 = 28,
196 sh_dblclick_str_60 = 29,
197 sh_dblclick_str_30 = 30,
198 sh_dblclick_med = 31,
199 sh_dblclick_med_80 = 32,
200 sh_dblclick_med_60 = 33,
201 sh_dblsharp_tick = 34,
202 sh_dblsharp_tick_80 = 35,
203 sh_dblsharp_tick_60 = 36,
204 lg_dblclick_str = 37,
205 lg_dblclick_str_80 = 38,
206 lg_dblclick_str_60 = 39,
207 lg_dblclick_str_30 = 40,
208 lg_dblclick_med = 41,
209 lg_dblclick_med_80 = 42,
210 lg_dblclick_med_60 = 43,
211 lg_dblsharp_tick = 44,
212 lg_dblsharp_tick_80 = 45,
213 lg_dblsharp_tick_60 = 46,
220 pulsing_strong_80 = 53,
222 pulsing_medium_80 = 55,
224 pulsing_sharp_80 = 57,
225 transition_click = 58,
226 transition_click_80 = 59,
227 transition_click_60 = 60,
228 transition_click_40 = 61,
229 transition_click_20 = 62,
230 transition_click_10 = 63,
232 transition_hum_80 = 65,
233 transition_hum_60 = 66,
234 transition_hum_40 = 67,
235 transition_hum_20 = 68,
236 transition_hum_10 = 69,
237 transition_rampdown_long_smooth1 = 70,
238 transition_rampdown_long_smooth2 = 71,
239 transition_rampdown_med_smooth1 = 72,
240 transition_rampdown_med_smooth2 = 73,
241 transition_rampdown_short_smooth1 = 74,
242 transition_rampdown_short_smooth2 = 75,
243 transition_rampdown_long_sharp1 = 76,
244 transition_rampdown_long_sharp2 = 77,
245 transition_rampdown_med_sharp1 = 78,
246 transition_rampdown_med_sharp2 = 79,
247 transition_rampdown_short_sharp1 = 80,
248 transition_rampdown_short_sharp2 = 81,
249 transition_rampup_long_smooth1 = 82,
250 transition_rampup_long_smooth2 = 83,
251 transition_rampup_med_smooth1 = 84,
252 transition_rampup_med_smooth2 = 85,
253 transition_rampup_short_smooth1 = 86,
254 transition_rampup_short_smooth2 = 87,
255 transition_rampup_long_sharp1 = 88,
256 transition_rampup_long_sharp2 = 89,
257 transition_rampup_med_sharp1 = 90,
258 transition_rampup_med_sharp2 = 91,
259 transition_rampup_short_sharp1 = 92,
260 transition_rampup_short_sharp2 = 93,
261 transition_rampdown_long_smooth1_50 = 94,
262 transition_rampdown_long_smooth2_50 = 95,
263 transition_rampdown_med_smooth1_50 = 96,
264 transition_rampdown_med_smooth2_50 = 97,
265 transition_rampdown_short_smooth1_50 = 98,
266 transition_rampdown_short_smooth2_50 = 99,
267 transition_rampdown_long_sharp1_50 = 100,
268 transition_rampdown_long_sharp2_50 = 101,
269 transition_rampdown_med_sharp1_50 = 102,
270 transition_rampdown_med_sharp2_50 = 103,
271 transition_rampdown_short_sharp1_50 = 104,
272 transition_rampdown_short_sharp2_50 = 105,
273 transition_rampup_long_smooth1_50 = 106,
274 transition_rampup_long_smooth2_50 = 107,
275 transition_rampup_med_smooth1_50 = 108,
276 transition_rampup_med_smooth2_50 = 109,
277 transition_rampup_short_smooth1_50 = 110,
278 transition_rampup_short_smooth2_50 = 111,
279 transition_rampup_long_sharp1_50 = 112,
280 transition_rampup_long_sharp2_50 = 113,
281 transition_rampup_med_sharp1_50 = 114,
282 transition_rampup_med_sharp2_50 = 115,
283 transition_rampup_short_sharp1_50 = 116,
284 transition_rampup_short_sharp2_50 = 117,
285 long_buzz_for_programmatic_stopping = 118,
286 smooth_hum1_50 = 119,
287 smooth_hum2_40 = 120,
288 smooth_hum3_30 = 121,
289 smooth_hum4_20 = 122,
290 smooth_hum5_10 = 123,
293 /* Register bit array unions */
295 typedef union DRVREG_STATUS { /* register 0x00 */
298 uint8_t OC_DETECT :1; /* set to 1 when overcurrent event is detected */
299 uint8_t OVER_TEMP :1; /* set to 1 when device exceeds temp threshold */
300 uint8_t FB_STS :1; /* set to 1 when feedback controller has timed out */
301 /* auto-calibration routine and diagnostic result
302 * result | auto-calibation | diagnostic |
303 * 0 | passed | actuator func normal |
304 * 1 | failed | actuator func fault* |
305 * * actuator is not present or is shorted, timing out, or giving out–of-range back-EMF */
306 uint8_t DIAG_RESULT :1;
308 uint8_t DEVICE_ID :3; /* Device IDs 3: DRV2605 4: DRV2604 5: DRV2604L 6: DRV2605L */
312 typedef union DRVREG_MODE { /* register 0x01 */
315 uint8_t MODE :3; /* Mode setting */
317 uint8_t STANDBY :1; /* 0:standby 1:ready */
321 typedef union DRVREG_WAIT {
324 uint8_t WAIT_MODE :1; /* Set to 1 to interpret as wait for next 7 bits x10ms */
325 uint8_t WAIT_TIME :7;
329 typedef union DRVREG_FBR{ /* register 0x1A */
332 uint8_t BEMF_GAIN :2;
333 uint8_t LOOP_GAIN :2;
334 uint8_t BRAKE_FACTOR :3;
339 typedef union DRVREG_CTRL1{ /* register 0x1B */
342 uint8_t C1_DRIVE_TIME :5;
343 uint8_t C1_AC_COUPLE :1;
345 uint8_t C1_STARTUP_BOOST :1;
349 typedef union DRVREG_CTRL2{ /* register 0x1C */
352 uint8_t C2_IDISS_TIME :2;
353 uint8_t C2_BLANKING_TIME :2;
354 uint8_t C2_SAMPLE_TIME :2;
355 uint8_t C2_BRAKE_STAB :1;
356 uint8_t C2_BIDIR_INPUT :1;
360 typedef union DRVREG_CTRL3{ /* register 0x1D */
363 uint8_t C3_LRA_OPEN_LOOP :1;
364 uint8_t C3_N_PWM_ANALOG :1;
365 uint8_t C3_LRA_DRIVE_MODE :1;
366 uint8_t C3_DATA_FORMAT_RTO :1;
367 uint8_t C3_SUPPLY_COMP_DIS :1;
368 uint8_t C3_ERM_OPEN_LOOP :1;
369 uint8_t C3_NG_THRESH :2;
373 typedef union DRVREG_CTRL4{ /* register 0x1E */
376 uint8_t C4_OTP_PROGRAM :1;
378 uint8_t C4_OTP_STATUS :1;
380 uint8_t C4_AUTO_CAL_TIME :2;
381 uint8_t C4_ZC_DET_TIME :2;
385 typedef union DRVREG_CTRL5{ /* register 0x1F */
388 uint8_t C5_IDISS_TIME :2;
389 uint8_t C5_BLANKING_TIME :2;
390 uint8_t C5_PLAYBACK_INTERVAL :1;
391 uint8_t C5_LRA_AUTO_OPEN_LOOP :1;
392 uint8_t C5_AUTO_OL_CNT :2;