/* matrix size */
-#define MATRIX_ROWS 16
-#define MATRIX_COLS 8
+#define MATRIX_ROWS 16
+#define MATRIX_COLS 8
/* To use new keymap framework */
#define USE_KEYMAP_V2
/* key combination for command */
-#define IS_COMMAND() ( \
+#define IS_COMMAND() ( \
host_get_first_key() == KC_CANCEL \
)
-/* PC98 Serial(USART) configuration
- * asynchronous, positive logic, 19200baud, bit order: LSB first
- * 1-start bit, 8-data bit, odd parity, 1-stop bit
- */
-#define SERIAL_BAUD 19200
-#define SERIAL_PARITY_ODD
-#define SERIAL_BIT_ORDER_LSB
-#define SERIAL_LOGIC_POSITIVE
-
/* PC98 Reset Port shared with TXD */
#define PC98_RST_DDR DDRD
#define PC98_RST_PORT PORTD
#define PC98_RTY_PORT PORTD
#define PC98_RTY_BIT 5
+/*
+ * PC98 Serial(USART) configuration
+ * asynchronous, positive logic, 19200baud, bit order: LSB first
+ * 1-start bit, 8-data bit, odd parity, 1-stop bit
+ */
+/*
+ * Software Serial
+ */
+#define SERIAL_SOFT_BAUD 19200
+#define SERIAL_SOFT_PARITY_ODD
+#define SERIAL_SOFT_BIT_ORDER_LSB
+#define SERIAL_SOFT_LOGIC_POSITIVE
/* RXD Port */
-#define SERIAL_RXD_DDR DDRD
-#define SERIAL_RXD_PORT PORTD
-#define SERIAL_RXD_PIN PIND
-#define SERIAL_RXD_BIT 2
-#ifdef SERIAL_LOGIC_NEGATIVE
-#define SERIAL_RXD_READ() ~(SERIAL_RXD_PIN&(1<<SERIAL_RXD_BIT))
+#define SERIAL_SOFT_RXD_DDR DDRD
+#define SERIAL_SOFT_RXD_PORT PORTD
+#define SERIAL_SOFT_RXD_PIN PIND
+#define SERIAL_SOFT_RXD_BIT 2
+#ifdef SERIAL_SOFT_LOGIC_NEGATIVE
+ #define SERIAL_SOFT_RXD_READ() ~(SERIAL_SOFT_RXD_PIN&(1<<SERIAL_SOFT_RXD_BIT))
#else
-#define SERIAL_RXD_READ() (SERIAL_RXD_PIN&(1<<SERIAL_RXD_BIT))
+ #define SERIAL_SOFT_RXD_READ() (SERIAL_SOFT_RXD_PIN&(1<<SERIAL_SOFT_RXD_BIT))
#endif
/* RXD Interupt */
-#define SERIAL_RXD_VECT INT2_vect
-#define SERIAL_RXD_INIT() do { \
+#define SERIAL_SOFT_RXD_VECT INT2_vect
+#define SERIAL_SOFT_RXD_INIT() do { \
/* pin configuration: input with pull-up */ \
- SERIAL_RXD_DDR &= ~(1<<SERIAL_RXD_BIT); \
- SERIAL_RXD_PORT |= (1<<SERIAL_RXD_BIT); \
- /* enable interrupt: INT2(falling edge) */ \
- EICRA |= ((1<<ISC21)|(0<<ISC20)); \
- EIMSK |= (1<<INT2); \
- sei(); \
+ SERIAL_SOFT_RXD_DDR &= ~(1<<SERIAL_SOFT_RXD_BIT); \
+ SERIAL_SOFT_RXD_PORT |= (1<<SERIAL_SOFT_RXD_BIT); \
+ /* enable interrupt: INT2(falling edge) */ \
+ EICRA |= ((1<<ISC21)|(0<<ISC20)); \
+ EIMSK |= (1<<INT2); \
+ sei(); \
} while (0)
-#define SERIAL_RXD_INT_ENTER()
-#define SERIAL_RXD_INT_EXIT() do { \
- /* clear interrupt flag */ \
- EIFR = (1<<INTF2); \
+#define SERIAL_SOFT_RXD_INT_ENTER()
+#define SERIAL_SOFT_RXD_INT_EXIT() do { \
+ /* clear interrupt flag */ \
+ EIFR = (1<<INTF2); \
} while (0)
-
/* TXD Port */
-#define SERIAL_TXD_DDR DDRD
-#define SERIAL_TXD_PORT PORTD
-#define SERIAL_TXD_PIN PIND
-#define SERIAL_TXD_BIT 3
-#ifdef SERIAL_LOGIC_NEGATIVE
-#define SERIAL_TXD_ON() do { SERIAL_TXD_PORT &= ~(1<<SERIAL_TXD_BIT); } while (0)
-#define SERIAL_TXD_OFF() do { SERIAL_TXD_PORT |= (1<<SERIAL_TXD_BIT); } while (0)
+#define SERIAL_SOFT_TXD_DDR DDRD
+#define SERIAL_SOFT_TXD_PORT PORTD
+#define SERIAL_SOFT_TXD_PIN PIND
+#define SERIAL_SOFT_TXD_BIT 3
+#ifdef SERIAL_SOFT_LOGIC_NEGATIVE
+ #define SERIAL_SOFT_TXD_ON() do { \
+ SERIAL_SOFT_TXD_PORT &= ~(1<<SERIAL_SOFT_TXD_BIT); \
+ } while (0)
+ #define SERIAL_SOFT_TXD_OFF() do { \
+ SERIAL_SOFT_TXD_PORT |= (1<<SERIAL_SOFT_TXD_BIT); \
+ } while (0)
#else
-#define SERIAL_TXD_ON() do { SERIAL_TXD_PORT |= (1<<SERIAL_TXD_BIT); } while (0)
-#define SERIAL_TXD_OFF() do { SERIAL_TXD_PORT &= ~(1<<SERIAL_TXD_BIT); } while (0)
+ #define SERIAL_SOFT_TXD_ON() do { \
+ SERIAL_SOFT_TXD_PORT |= (1<<SERIAL_SOFT_TXD_BIT); \
+ } while (0)
+ #define SERIAL_SOFT_TXD_OFF() do { \
+ SERIAL_SOFT_TXD_PORT &= ~(1<<SERIAL_SOFT_TXD_BIT); \
+ } while (0)
#endif
-#define SERIAL_TXD_INIT() do { \
- /* pin configuration: output */ \
- SERIAL_TXD_DDR |= (1<<SERIAL_TXD_BIT); \
- /* idle */ \
- SERIAL_TXD_ON(); \
+#define SERIAL_SOFT_TXD_INIT() do { \
+ /* pin configuration: output */ \
+ SERIAL_SOFT_TXD_DDR |= (1<<SERIAL_SOFT_TXD_BIT); \
+ /* idle */ \
+ SERIAL_SOFT_TXD_ON(); \
} while (0)
+
+/*
+ * Hardware Serial(UART)
+ */
+#ifdef __AVR_ATmega32U4__
+ #define SERIAL_UART_BAUD 19200
+ #define SERIAL_UART_DATA UDR1
+ #define SERIAL_UART_UBRR ((F_CPU/(16UL*SERIAL_UART_BAUD))-1)
+ #define SERIAL_UART_RXD_VECT USART1_RX_vect
+ #define SERIAL_UART_TXD_READY (UCSR1A&(1<<UDRE1))
+ #define SERIAL_UART_INIT() do { \
+ UBRR1L = (uint8_t) SERIAL_UART_UBRR; /* baud rate */ \
+ UBRR1H = (uint8_t) (SERIAL_UART_UBRR>>8); /* baud rate */ \
+ UCSR1B |= (1<<RXCIE1) | (1<<RXEN1); /* RX interrupt, RX: enable */ \
+ UCSR1B |= (0<<TXCIE1) | (1<<TXEN1); /* TX interrupt, TX: enable */ \
+ UCSR1C |= (1<<UPM11) | (1<<UPM10); /* parity: none(00), even(01), odd(11) */ \
+ sei(); \
+ } while(0)
+#else
+ #error "USART configuration is needed."
+#endif
+
+
#endif
--- /dev/null
+/*
+Copyright 2013 Jun WAKO <wakojun@gmail.com>
+
+This software is licensed with a Modified BSD License.
+All of this is supposed to be Free Software, Open Source, DFSG-free,
+GPL-compatible, and OK to use in both free and proprietary applications.
+Additions and corrections to this file are welcome.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+* Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdbool.h>
+#include <avr/io.h>
+#include <avr/interrupt.h>
+#include "serial.h"
+
+
+void serial_init(void)
+{
+ SERIAL_UART_INIT();
+}
+
+// RX ring buffer
+#define RBUF_SIZE 8
+static uint8_t rbuf[RBUF_SIZE];
+static uint8_t rbuf_head = 0;
+static uint8_t rbuf_tail = 0;
+
+uint8_t serial_recv(void)
+{
+ uint8_t data = 0;
+ if (rbuf_head == rbuf_tail) {
+ return 0;
+ }
+
+ data = rbuf[rbuf_tail];
+ rbuf_tail = (rbuf_tail + 1) % RBUF_SIZE;
+ return data;
+}
+
+int16_t serial_recv2(void)
+{
+ uint8_t data = 0;
+ if (rbuf_head == rbuf_tail) {
+ return -1;
+ }
+
+ data = rbuf[rbuf_tail];
+ rbuf_tail = (rbuf_tail + 1) % RBUF_SIZE;
+ return data;
+}
+
+void serial_send(uint8_t data)
+{
+ while (!SERIAL_UART_TXD_READY) ;
+ SERIAL_UART_DATA = data;
+}
+
+// USART RX complete interrupt
+ISR(SERIAL_UART_RXD_VECT)
+{
+ uint8_t next = (rbuf_head + 1) % RBUF_SIZE;
+ if (next != rbuf_tail) {
+ rbuf[rbuf_head] = SERIAL_UART_DATA;
+ rbuf_head = next;
+ }
+}
projects / tmk_firmware.git / commitdiff