Align ARM i2c_readReg with AVR (#6314)

[qmk_firmware.git] / drivers / arm / i2c_master.h

diff --git a/drivers/arm/i2c_master.h b/drivers/arm/i2c_master.h
index 9d51245be1d12dd3a8c070f71613f5866ef5d95d..c8afa31e28d67e76cbe1a8700c5c684de8281544 100644 (file)
--- a/drivers/arm/i2c_master.h
+++ b/drivers/arm/i2c_master.h
@@ -22,18 +22,89 @@
  * Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that
  * STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file.
  */
+#pragma once
 
 #include "ch.h"
 #include <hal.h>
 
+
+#if defined(STM32F1XX) || defined(STM32F1xx) || defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32L0xx) || defined(STM32L1xx)
+    #define USE_I2CV1
+#endif
+
+#ifdef I2C1_BANK
+    #define I2C1_SCL_BANK I2C1_BANK
+    #define I2C1_SDA_BANK I2C1_BANK
+#endif
+
+#ifndef I2C1_SCL_BANK
+    #define I2C1_SCL_BANK GPIOB
+#endif
+
+#ifndef I2C1_SDA_BANK
+    #define I2C1_SDA_BANK GPIOB
+#endif
+
+#ifndef I2C1_SCL
+    #define I2C1_SCL 6
+#endif
+#ifndef I2C1_SDA
+    #define I2C1_SDA 7
+#endif
+
+#ifdef USE_I2CV1
+    #ifndef I2C1_OPMODE
+        #define I2C1_OPMODE OPMODE_I2C
+    #endif
+    #ifndef I2C1_CLOCK_SPEED
+        #define I2C1_CLOCK_SPEED 100000 /* 400000 */
+    #endif
+    #ifndef I2C1_DUTY_CYCLE
+        #define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
+    #endif
+#else
+    // The default PAL alternate modes are used to signal that the pins are used for I2C
+    #ifndef I2C1_SCL_PAL_MODE
+        #define I2C1_SCL_PAL_MODE 4
+    #endif
+    #ifndef I2C1_SDA_PAL_MODE
+        #define I2C1_SDA_PAL_MODE 4
+    #endif
+
+    // The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
+    // For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
+    #ifndef I2C1_TIMINGR_PRESC
+        #define I2C1_TIMINGR_PRESC 15U
+    #endif
+    #ifndef I2C1_TIMINGR_SCLDEL
+        #define I2C1_TIMINGR_SCLDEL 4U
+    #endif
+    #ifndef I2C1_TIMINGR_SDADEL
+        #define I2C1_TIMINGR_SDADEL 2U
+    #endif
+    #ifndef I2C1_TIMINGR_SCLH
+        #define I2C1_TIMINGR_SCLH 15U
+    #endif
+    #ifndef I2C1_TIMINGR_SCLL
+        #define I2C1_TIMINGR_SCLL 21U
+    #endif
+#endif
+
 #ifndef I2C_DRIVER
   #define I2C_DRIVER I2CD1
 #endif
 
+typedef int16_t i2c_status_t;
+
+#define I2C_STATUS_SUCCESS (0)
+#define I2C_STATUS_ERROR   (-1)
+#define I2C_STATUS_TIMEOUT (-2)
+
 void i2c_init(void);
-uint8_t i2c_start(uint8_t address);
-uint8_t i2c_transmit(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
-uint8_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
-uint8_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
-uint8_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
+i2c_status_t i2c_start(uint8_t address);
+i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
+i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
+i2c_status_t i2c_transmit_receive(uint8_t address, uint8_t * tx_body, uint16_t tx_length, uint8_t * rx_body, uint16_t rx_length);
+i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
+i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
 void i2c_stop(void);