-// Pin Name Function Hardware
+// Pin Name Function Hardware
// ----------------------------------
-// 0 B16 RX1
-// 1 B17 TX1
-// 2 D0 PCS0
-// 3 A12 FTM1_CH0 PWM (CAN TX - Teensy 3.1) I2S_TXD0
-// 4 A13 FTM1_CH1 PWM (CAN RX - Teensy 3.1) I2S_TX_FS
-// 5 D7 FTM0_CH7 PWM
-// 6 D4 FTM0_CH4 PWM PCS1
-// 7 D2 RX3 SOUT0
-// 8 D3 TX3 SIN0
-// 9 C3 FTM0_CH2 RX2 PWM PCS1 I2S_TX_BCLK
-// 10 C4 FTM0_CH3 TX2 PWM PCS0
-// 11 C6 SOUT0 I2S_RX_BCLK I2S_MCLK
-// 12 C7 SIN0 I2S_RX_FS
-// 13 C5 LED SCK0 I2S_RXD0
-// 14 D1 SCK0
-// 15 C0
-// 16 B0 (FTM1_CH0) SCL0
-// 17 B1 (FTM1_CH1) SDA0
-// 18 B3 SDA0
-// 19 B2 SCL0
-// 20 D5 FTM0_CH5 PWM PCS2
-// 21 D6 FTM0_CH6 PWM PCS3
-// 22 C1 FTM0_CH0 PWM PCS3 I2S_TXD0
-// 23 C2 FTM0_CH1 PWM PCS2 I2S_TX_FS
-// 24 A5 (FTM0_CH2) I2S_TX_BCLK
-// 25 B19 (PWM - Teensy 3.1) I2S_TX_FS
-// 26 E1
-// 27 C9 I2S_RX_BCLK
-// 28 C8 I2S_MCLK
-// 29 C10 (SCL1 - Teensy 3.1) I2S_RX_FS
-// 30 C11 (SDA1 - Teensy 3.1) I2S_RXD1
-// 31 E0
-// 32 B18 (PWM - Teensy 3.1) I2S_TX_BCLK
-// 33 A4 (FTM0_CH1)
+// 0 PTB16 RX0
+// 1 PTB17 TX0
+// 2 PTD0 PCS0
+// 3 PTA12 FTM1_CH0 PWM (CAN TX - Teensy 3.1) I2S_TXD0
+// 4 PTA13 FTM1_CH1 PWM (CAN RX - Teensy 3.1) I2S_TX_FS
+// 5 PTD7 FTM0_CH7 PWM
+// 6 PTD4 FTM0_CH4 PWM PCS1
+// 7 PTD2 RX2 SOUT0
+// 8 PTD3 TX2 SIN0
+// 9 PTC3 FTM0_CH2 RX1 PWM PCS1 I2S_TX_BCLK
+// 10 PTC4 FTM0_CH3 TX1 PWM PCS0
+// 11 PTC6 SOUT0 I2S_RX_BCLK I2S_MCLK
+// 12 PTC7 SIN0 I2S_RX_FS
+// 13 PTC5 LED SCK0 I2S_RXD0
+// 14 PTD1 SCK0
+// 15 PTC0 PCS4 I2S_TXD1
+// 16 PTB0 (FTM1_CH0) SCL0
+// 17 PTB1 (FTM1_CH1) SDA0
+// 18 PTB3 SDA0
+// 19 PTB2 SCL0
+// 20 PTD5 FTM0_CH5 PWM PCS2
+// 21 PTD6 FTM0_CH6 PWM PCS3
+// 22 PTC1 FTM0_CH0 PWM PCS3 I2S_TXD0
+// 23 PTC2 FTM0_CH1 PWM PCS2 I2S_TX_FS
+// 24 PTA5 (FTM0_CH2) I2S_TX_BCLK
+// 25 PTB19 (PWM - Teensy 3.1) I2S_TX_FS
+// 26 PTE1 RX1 SCL1
+// 27 PTC9 I2S_RX_BCLK
+// 28 PTC8 I2S_MCLK
+// 29 PTC10 (SCL1 - Teensy 3.1) I2S_RX_FS
+// 30 PTC11 (SDA1 - Teensy 3.1) I2S_RXD1
+// 31 PTE0 TX1 SDA1
+// 32 PTB18 (PWM - Teensy 3.1) I2S_TX_BCLK
+// 33 PTA4 (FTM0_CH1)
// 34 analog only
// 35 analog only
// 36 analog only
// 40 DAC/A14
// not available to user:
-// A0 FTM0_CH5 SWD Clock
-// A1 FTM0_CH6 USB ID
-// A2 FTM0_CH7 SWD Trace
-// A3 FTM0_CH0 SWD Data
-
-// misc
- C0 PCS4 I2S_TXD1
+// A0 FTM0_CH5 SWD Clock
+// A1 FTM0_CH6 USB ID
+// A2 FTM0_CH7 SWD Trace
+// A3 FTM0_CH0 SWD Data
// Analog Channel Channel
// Pin Pin Name ADC0 ADC1
* THE SOFTWARE.
*/
-#include "uart_serial.h"
+// ----- Includes -----
+
+// Compiler Includes
+#include <string.h> // For memcpy
+
+// Project Includes
#include <Lib/OutputLib.h>
#include <Lib/Interrupts.h>
-#include <string.h> // For memcpy
+
+// Local Includes
+#include "uart_serial.h"
+
+
+
+// ----- Defines -----
+
+// UART Configuration
+#if defined(_mk20dx128_) || defined(_mk20dx128vlf5_) || defined(_mk20dx256_) // UART0 Debug
+#define UART_BDH UART0_BDH
+#define UART_BDL UART0_BDL
+#define UART_C1 UART0_C1
+#define UART_C2 UART0_C2
+#define UART_C3 UART0_C3
+#define UART_C4 UART0_C4
+#define UART_CFIFO UART0_CFIFO
+#define UART_D UART0_D
+#define UART_PFIFO UART0_PFIFO
+#define UART_RCFIFO UART0_RCFIFO
+#define UART_RWFIFO UART0_RWFIFO
+#define UART_S1 UART0_S1
+#define UART_S2 UART0_S2
+#define UART_SFIFO UART0_SFIFO
+#define UART_TWFIFO UART0_TWFIFO
+
+#define SIM_SCGC4_UART SIM_SCGC4_UART0
+#define IRQ_UART_STATUS IRQ_UART0_STATUS
+
+#elif defined(_mk20dx256vlh7_) // UART2 Debug
+#define UART_BDH UART2_BDH
+#define UART_BDL UART2_BDL
+#define UART_C1 UART2_C1
+#define UART_C2 UART2_C2
+#define UART_C3 UART2_C3
+#define UART_C4 UART2_C4
+#define UART_CFIFO UART2_CFIFO
+#define UART_D UART2_D
+#define UART_PFIFO UART2_PFIFO
+#define UART_RCFIFO UART2_RCFIFO
+#define UART_RWFIFO UART2_RWFIFO
+#define UART_S1 UART2_S1
+#define UART_S2 UART2_S2
+#define UART_SFIFO UART2_SFIFO
+#define UART_TWFIFO UART2_TWFIFO
+
+#define SIM_SCGC4_UART SIM_SCGC4_UART2
+#define IRQ_UART_STATUS IRQ_UART2_STATUS
+
+#endif
+
+
// ----- Variables -----
-#define uart0_buffer_size 128 // 128 byte buffer
-volatile uint8_t uart0_buffer_head = 0;
-volatile uint8_t uart0_buffer_tail = 0;
-volatile uint8_t uart0_buffer_items = 0;
-volatile uint8_t uart0_buffer[uart0_buffer_size];
+#define uart_buffer_size 128 // 128 byte buffer
+volatile uint8_t uart_buffer_head = 0;
+volatile uint8_t uart_buffer_tail = 0;
+volatile uint8_t uart_buffer_items = 0;
+volatile uint8_t uart_buffer[uart_buffer_size];
volatile uint8_t uart_configured = 0;
// ----- Interrupt Functions -----
+#if defined(_mk20dx128_) || defined(_mk20dx128vlf5_) || defined(_mk20dx256_) // UART0 Debug
void uart0_status_isr()
+#elif defined(_mk20dx256vlh7_) // UART2 Debug
+void uart2_status_isr()
+#endif
{
cli(); // Disable Interrupts
// UART0_S1 must be read for the interrupt to be cleared
- if ( UART0_S1 & ( UART_S1_RDRF | UART_S1_IDLE ) )
+ if ( UART_S1 & ( UART_S1_RDRF | UART_S1_IDLE ) )
{
- uint8_t available = UART0_RCFIFO;
+ uint8_t available = UART_RCFIFO;
// If there was actually nothing
if ( available == 0 )
{
// Cleanup
- available = UART0_D;
- UART0_CFIFO = UART_CFIFO_RXFLUSH;
+ available = UART_D;
+ UART_CFIFO = UART_CFIFO_RXFLUSH;
sei();
return;
}
// Read UART0 into buffer until FIFO is empty
while ( available-- > 0 )
{
- uart0_buffer[uart0_buffer_tail++] = UART0_D;
- uart0_buffer_items++;
+ uart_buffer[uart_buffer_tail++] = UART_D;
+ uart_buffer_items++;
// Wrap-around of tail pointer
- if ( uart0_buffer_tail >= uart0_buffer_size )
+ if ( uart_buffer_tail >= uart_buffer_size )
{
- uart0_buffer_tail = 0;
+ uart_buffer_tail = 0;
}
// Make sure the head pointer also moves if circular buffer is overwritten
- if ( uart0_buffer_head == uart0_buffer_tail )
+ if ( uart_buffer_head == uart_buffer_tail )
{
- uart0_buffer_head++;
+ uart_buffer_head++;
}
// Wrap-around of head pointer
- if ( uart0_buffer_head >= uart0_buffer_size )
+ if ( uart_buffer_head >= uart_buffer_size )
{
- uart0_buffer_head = 0;
+ uart_buffer_head = 0;
}
}
}
uart_configured = 0;
// Setup the the UART interface for keyboard data input
- SIM_SCGC4 |= SIM_SCGC4_UART0; // Disable clock gating
+ SIM_SCGC4 |= SIM_SCGC4_UART; // Disable clock gating
-// MCHCK
+// MCHCK / Kiibohd-dfu
#if defined(_mk20dx128vlf5_)
// Pin Setup for UART0
PORTA_PCR1 = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(2); // RX Pin
PORTA_PCR2 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(2); // TX Pin
+// Kiibohd-dfu
+#elif defined(_mk20dx256vlh7_)
+ // Pin Setup for UART2
+ PORTD_PCR2 = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); // RX Pin
+ PORTD_PCR3 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); // TX Pin
+
// Teensy
#else
// Pin Setup for UART0
PORTB_PCR17 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); // TX Pin
#endif
+
+#if defined(_mk20dx128_) || defined(_mk20dx128vlf5_) || defined(_mk20dx256_) // UART0 Debug
// Setup baud rate - 115200 Baud
// 48 MHz / ( 16 * Baud ) = BDH/L
// Baud: 115200 -> 48 MHz / ( 16 * 115200 ) = 26.0416667
// Thus baud setting = 26
// NOTE: If finer baud adjustment is needed see UARTx_C4 -> BRFA in the datasheet
uint16_t baud = 26; // Max setting of 8191
- UART0_BDH = (uint8_t)(baud >> 8);
- UART0_BDL = (uint8_t)baud;
- UART0_C4 = 0x02;
+ UART_BDH = (uint8_t)(baud >> 8);
+ UART_BDL = (uint8_t)baud;
+ UART_C4 = 0x02;
+
+#elif defined(_mk20dx256vlh7_) // UART2 Debug
+ // Setup baud rate - 115200 Baud
+ // Uses Bus Clock
+ // 24 MHz / ( 16 * Baud ) = BDH/L
+ // Baud: 115200 -> 24 MHz / ( 16 * 115200 ) = 13.021
+ // Thus baud setting = 13
+ // NOTE: If finer baud adjustment is needed see UARTx_C4 -> BRFA in the datasheet
+ uint16_t baud = 13; // Max setting of 8191
+ UART_BDH = (uint8_t)(baud >> 8);
+ UART_BDL = (uint8_t)baud;
+ UART_C4 = 0x01;
+
+#endif
// 8 bit, No Parity, Idle Character bit after stop
- UART0_C1 = UART_C1_ILT;
+ UART_C1 = UART_C1_ILT;
// Interrupt notification watermarks
- UART0_TWFIFO = 2;
- UART0_RWFIFO = 4;
+#if defined(_mk20dx128_) || defined(_mk20dx128vlf5_) || defined(_mk20dx256_) // UART0 Debug
+ UART_TWFIFO = 2;
+ UART_RWFIFO = 4;
+#elif defined(_mk20dx256vlh7_) // UART2 Debug
+ // UART2 has a single byte FIFO
+ UART_TWFIFO = 1;
+ UART_RWFIFO = 1;
+#endif
- // TX FIFO Disabled, TX FIFO Size 1 (Max 8 datawords), RX FIFO Enabled, RX FIFO Size 1 (Max 8 datawords)
+ // TX FIFO Enabled, TX FIFO Size 1 (Max 8 datawords), RX FIFO Enabled, RX FIFO Size 1 (Max 8 datawords)
// TX/RX FIFO Size:
// 0x0 - 1 dataword
// 0x1 - 4 dataword
// 0x2 - 8 dataword
- UART0_PFIFO = UART_PFIFO_TXFE | UART_PFIFO_RXFE;
+ UART_PFIFO = UART_PFIFO_TXFE | UART_PFIFO_RXFE;
// Reciever Inversion Disabled, LSBF
// UART_S2_RXINV UART_S2_MSBF
- UART0_S2 |= 0x00;
+ UART_S2 |= 0x00;
// Transmit Inversion Disabled
// UART_C3_TXINV
- UART0_C3 |= 0x00;
+ UART_C3 |= 0x00;
// TX Enabled, RX Enabled, RX Interrupt Enabled, Generate idles
// UART_C2_TE UART_C2_RE UART_C2_RIE UART_C2_ILIE
- UART0_C2 = UART_C2_TE | UART_C2_RE | UART_C2_RIE | UART_C2_ILIE;
+ UART_C2 = UART_C2_TE | UART_C2_RE | UART_C2_RIE | UART_C2_ILIE;
// Add interrupt to the vector table
- NVIC_ENABLE_IRQ( IRQ_UART0_STATUS );
+ NVIC_ENABLE_IRQ( IRQ_UART_STATUS );
// UART is now ready to use
uart_configured = 1;
unsigned int value = -1;
// Check to see if the FIFO has characters
- if ( uart0_buffer_items > 0 )
+ if ( uart_buffer_items > 0 )
{
- value = uart0_buffer[uart0_buffer_head++];
- uart0_buffer_items--;
+ value = uart_buffer[uart_buffer_head++];
+ uart_buffer_items--;
// Wrap-around of head pointer
- if ( uart0_buffer_head >= uart0_buffer_size )
+ if ( uart_buffer_head >= uart_buffer_size )
{
- uart0_buffer_head = 0;
+ uart_buffer_head = 0;
}
}
// Number of bytes available in the receive buffer
int uart_serial_available()
{
- return uart0_buffer_items;
+ return uart_buffer_items;
}
// Discard any buffered input
void uart_serial_flush_input()
{
- uart0_buffer_head = 0;
- uart0_buffer_tail = 0;
- uart0_buffer_items = 0;
+ uart_buffer_head = 0;
+ uart_buffer_tail = 0;
+ uart_buffer_items = 0;
}
if ( !uart_configured )
return -1;
- while ( !( UART0_SFIFO & UART_SFIFO_TXEMPT ) ); // Wait till there is room to send
- UART0_D = c;
+ while ( !( UART_SFIFO & UART_SFIFO_TXEMPT ) ); // Wait till there is room to send
+ UART_D = c;
return 0;
}
// While buffer is not empty and transmit buffer is
while ( position < size )
{
- while ( !( UART0_SFIFO & UART_SFIFO_TXEMPT ) ); // Wait till there is room to send
- UART0_D = data[position++];
+ while ( !( UART_SFIFO & UART_SFIFO_TXEMPT ) ); // Wait till there is room to send
+ UART_D = data[position++];
}
return 0;
void uart_serial_flush_output()
{
// Delay until buffer has been sent
- while ( !( UART0_SFIFO & UART_SFIFO_TXEMPT ) ); // Wait till there is room to send
+ while ( !( UART_SFIFO & UART_SFIFO_TXEMPT ) ); // Wait till there is room to send
}
projects / kiibohd-controller.git / commitdiff