Adding 72 MHz clock support for mk20dx256vlh7

[kiibohd-controller.git] / Lib / mk20dx.c

diff --git a/Lib/mk20dx.c b/Lib/mk20dx.c
index acd98f5357a2fb1dc29a83a298c29601b807eba0..1fa3e1510719b8a7c5740bc12ef08c8a8f129ab1 100644 (file)
--- a/Lib/mk20dx.c
+++ b/Lib/mk20dx.c
@@ -394,7 +394,7 @@ const uint8_t flashconfigbytes[16] = {
        //  http://cache.freescale.com/files/microcontrollers/doc/app_note/AN4507.pdf
        //  http://cache.freescale.com/files/32bit/doc/ref_manual/K20P64M72SF1RM.pdf (28.34.6)
        //
-       0xFF, 0xFF, 0xFF, 0xFE, // Program Flash Protection Bytes FPROT0-3
+       0xFF, 0xFF, 0xFF, 0xFF, // Program Flash Protection Bytes FPROT0-3 // XXX TODO PROTECT
 
        0xBE, // Flash security byte FSEC
        0x03, // Flash nonvolatile option byte FOPT
@@ -469,8 +469,17 @@ void ResetHandler()
        //
        // Also checking for ARM lock-up signal (invalid firmware image)
        // RCM_SRS1 & 0x02
-       if ( RCM_SRS0 & 0x40 || RCM_SRS0 & 0x20 || RCM_SRS1 & 0x02 || _app_rom == 0xffffffff ||
-         memcmp( (uint8_t*)&VBAT, sys_reset_to_loader_magic, sizeof(sys_reset_to_loader_magic) ) == 0 ) // Check for soft reload
+       if (    // PIN  (External Reset Pin/Switch)
+                  RCM_SRS0 & 0x40
+               // WDOG (Watchdog timeout)
+               || RCM_SRS0 & 0x20
+               // LOCKUP (ARM Core LOCKUP event)
+               || RCM_SRS1 & 0x02
+               // Blank flash check
+               || _app_rom == 0xffffffff
+               // Software reset
+               || memcmp( (uint8_t*)&VBAT, sys_reset_to_loader_magic, sizeof(sys_reset_to_loader_magic) ) == 0
+       )
        {
                memset( (uint8_t*)&VBAT, 0, sizeof(VBAT) );
        }
@@ -563,11 +572,21 @@ void ResetHandler()
        while ( (MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST( 2 ) );
 
        // now we're in FBE mode
+#if F_CPU == 72000000
+       // config PLL input for 16 MHz Crystal / 8 = 2 MHz
+       MCG_C5 = MCG_C5_PRDIV0( 7 );
+#else
        // config PLL input for 16 MHz Crystal / 4 = 4 MHz
        MCG_C5 = MCG_C5_PRDIV0( 3 );
+#endif
 
+#if F_CPU == 72000000
+       // config PLL for 72 MHz output (36 * 2 MHz Ext PLL)
+       MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0( 12 );
+#else
        // config PLL for 96 MHz output
        MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0( 0 );
+#endif
 
        // wait for PLL to start using xtal as its input
        while ( !(MCG_S & MCG_S_PLLST) );
@@ -579,6 +598,9 @@ void ResetHandler()
 #if F_CPU == 96000000
        // config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash
        SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 0 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 3 );
+#elif F_CPU == 72000000
+       // config divisors: 72 MHz core, 36 MHz bus, 24 MHz flash
+       SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 0 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 2 );
 #elif F_CPU == 48000000
        // config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash
        SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 1 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 3 );
@@ -586,7 +608,7 @@ void ResetHandler()
        // config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash
        SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 3 ) | SIM_CLKDIV1_OUTDIV2( 3 ) | SIM_CLKDIV1_OUTDIV4( 3 );
 #else
-#error "Error, F_CPU must be 96000000, 48000000, or 24000000"
+#error "Error, F_CPU must be 96000000, 72000000, 48000000, or 24000000"
 #endif
        // switch to PLL as clock source, FLL input = 16 MHz / 512
        MCG_C1 = MCG_C1_CLKS( 0 ) | MCG_C1_FRDIV( 4 );
@@ -595,8 +617,13 @@ void ResetHandler()
        while ( (MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST( 3 ) );
 
        // now we're in PEE mode
+#if F_CPU == 72000000
+       // configure USB for 48 MHz clock
+       SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV( 2 ) | SIM_CLKDIV2_USBFRAC; // USB = 72 MHz PLL / 1.5
+#else
        // configure USB for 48 MHz clock
        SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV( 1 ); // USB = 96 MHz PLL / 2
+#endif
 
        // USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0
        SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL( 6 );