+++ /dev/null
-; * ---------------------------------------------------------------------------------------
-; * @file: startup_MKL43Z4.s
-; * @purpose: CMSIS Cortex-M0P Core Device Startup File
-; * MKL43Z4
-; * @version: 1.3
-; * @date: 2014-8-21
-; * @build: b140821
-; * ---------------------------------------------------------------------------------------
-; *
-; * Copyright (c) 1997 - 2014 , Freescale Semiconductor, Inc.
-; * All rights reserved.
-; *
-; * Redistribution and use in source and binary forms, with or without modification,
-; * are permitted provided that the following conditions are met:
-; *
-; * o Redistributions of source code must retain the above copyright notice, this list
-; * of conditions and the following disclaimer.
-; *
-; * o Redistributions in binary form must reproduce the above copyright notice, this
-; * list of conditions and the following disclaimer in the documentation and/or
-; * other materials provided with the distribution.
-; *
-; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-; * contributors may be used to endorse or promote products derived from this
-; * software without specific prior written permission.
-; *
-; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; *****************************************************************************/
-
-
-__initial_sp EQU 0x20006000 ; Top of RAM
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ;NMI Handler
- DCD HardFault_Handler ;Hard Fault Handler
- DCD 0 ;Reserved
- DCD 0 ;Reserved
- DCD 0 ;Reserved
- DCD 0 ;Reserved
- DCD 0 ;Reserved
- DCD 0 ;Reserved
- DCD 0 ;Reserved
- DCD SVC_Handler ;SVCall Handler
- DCD 0 ;Reserved
- DCD 0 ;Reserved
- DCD PendSV_Handler ;PendSV Handler
- DCD SysTick_Handler ;SysTick Handler
-
- ;External Interrupts
- DCD DMA0_IRQHandler ;DMA channel 0 transfer complete
- DCD DMA1_IRQHandler ;DMA channel 1 transfer complete
- DCD DMA2_IRQHandler ;DMA channel 2 transfer complete
- DCD DMA3_IRQHandler ;DMA channel 3 transfer complete
- DCD Reserved20_IRQHandler ;Reserved interrupt
- DCD FTFA_IRQHandler ;Command complete and read collision
- DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning
- DCD LLWU_IRQHandler ;Low leakage wakeup
- DCD I2C0_IRQHandler ;I2C0 interrupt
- DCD I2C1_IRQHandler ;I2C1 interrupt
- DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources
- DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources
- DCD LPUART0_IRQHandler ;LPUART0 status and error
- DCD LPUART1_IRQHandler ;LPUART1 status and error
- DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO
- DCD ADC0_IRQHandler ;ADC0 interrupt
- DCD CMP0_IRQHandler ;CMP0 interrupt
- DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources
- DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources
- DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources
- DCD RTC_IRQHandler ;RTC alarm
- DCD RTC_Seconds_IRQHandler ;RTC seconds
- DCD PIT_IRQHandler ;PIT interrupt
- DCD I2S0_IRQHandler ;I2S0 interrupt
- DCD USB0_IRQHandler ;USB0 interrupt
- DCD DAC0_IRQHandler ;DAC0 interrupt
- DCD Reserved42_IRQHandler ;Reserved interrupt
- DCD Reserved43_IRQHandler ;Reserved interrupt
- DCD LPTMR0_IRQHandler ;LPTMR0 interrupt
- DCD LCD_IRQHandler ;LCD interrupt
- DCD PORTA_IRQHandler ;PORTA Pin detect
- DCD PORTCD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
-; <h> Flash Configuration
-; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
-; <i> and security information that allows the MCU to restrict access to the FTFL module.
-; <h> Backdoor Comparison Key
-; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2>
-; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2>
-; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2>
-; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2>
-; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2>
-; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2>
-; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2>
-; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2>
-BackDoorK0 EQU 0xFF
-BackDoorK1 EQU 0xFF
-BackDoorK2 EQU 0xFF
-BackDoorK3 EQU 0xFF
-BackDoorK4 EQU 0xFF
-BackDoorK5 EQU 0xFF
-BackDoorK6 EQU 0xFF
-BackDoorK7 EQU 0xFF
-; </h>
-; <h> Program flash protection bytes (FPROT)
-; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
-; <i> Each bit protects a 1/32 region of the program flash memory.
-; <h> FPROT0
-; <i> Program Flash Region Protect Register 0
-; <i> 1/32 - 8/32 region
-; <o.0> FPROT0.0
-; <o.1> FPROT0.1
-; <o.2> FPROT0.2
-; <o.3> FPROT0.3
-; <o.4> FPROT0.4
-; <o.5> FPROT0.5
-; <o.6> FPROT0.6
-; <o.7> FPROT0.7
-nFPROT0 EQU 0x00
-FPROT0 EQU nFPROT0:EOR:0xFF
-; </h>
-; <h> FPROT1
-; <i> Program Flash Region Protect Register 1
-; <i> 9/32 - 16/32 region
-; <o.0> FPROT1.0
-; <o.1> FPROT1.1
-; <o.2> FPROT1.2
-; <o.3> FPROT1.3
-; <o.4> FPROT1.4
-; <o.5> FPROT1.5
-; <o.6> FPROT1.6
-; <o.7> FPROT1.7
-nFPROT1 EQU 0x00
-FPROT1 EQU nFPROT1:EOR:0xFF
-; </h>
-; <h> FPROT2
-; <i> Program Flash Region Protect Register 2
-; <i> 17/32 - 24/32 region
-; <o.0> FPROT2.0
-; <o.1> FPROT2.1
-; <o.2> FPROT2.2
-; <o.3> FPROT2.3
-; <o.4> FPROT2.4
-; <o.5> FPROT2.5
-; <o.6> FPROT2.6
-; <o.7> FPROT2.7
-nFPROT2 EQU 0x00
-FPROT2 EQU nFPROT2:EOR:0xFF
-; </h>
-; <h> FPROT3
-; <i> Program Flash Region Protect Register 3
-; <i> 25/32 - 32/32 region
-; <o.0> FPROT3.0
-; <o.1> FPROT3.1
-; <o.2> FPROT3.2
-; <o.3> FPROT3.3
-; <o.4> FPROT3.4
-; <o.5> FPROT3.5
-; <o.6> FPROT3.6
-; <o.7> FPROT3.7
-nFPROT3 EQU 0x00
-FPROT3 EQU nFPROT3:EOR:0xFF
-; </h>
-; </h>
-; <h> Flash nonvolatile option byte (FOPT)
-; <i> Allows the user to customize the operation of the MCU at boot time.
-; <o.0> LPBOOT0
-; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
-; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
-; <o.1> BOOTPIN_OPT
-; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
-; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
-; <o.2> NMI_DIS
-; <0=> NMI interrupts are always blocked
-; <1=> NMI_b pin/interrupts reset default to enabled
-; <o.3> RESET_PIN_CFG
-; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function
-; <1=> RESET_b pin is dedicated
-; <o.4> LPBOOT1
-; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
-; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
-; <o.5> FAST_INIT
-; <0=> Slower initialization
-; <1=> Fast Initialization
-; <o.6..7> BOOTSRC_SEL
-; <0=> Boot from Flash
-; <2=> Boot from ROM
-; <3=> Boot from ROM
-; <i> Boot source selection
-FOPT EQU 0x3F
-; </h>
-; <h> Flash security byte (FSEC)
-; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
-; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
-; <o.0..1> SEC
-; <2=> MCU security status is unsecure
-; <3=> MCU security status is secure
-; <i> Flash Security
-; <o.2..3> FSLACC
-; <2=> Freescale factory access denied
-; <3=> Freescale factory access granted
-; <i> Freescale Failure Analysis Access Code
-; <o.4..5> MEEN
-; <2=> Mass erase is disabled
-; <3=> Mass erase is enabled
-; <o.6..7> KEYEN
-; <2=> Backdoor key access enabled
-; <3=> Backdoor key access disabled
-; <i> Backdoor Key Security Enable
-FSEC EQU 0xFE
-; </h>
-; </h>
- IF :LNOT::DEF:RAM_TARGET
- AREA |.ARM.__at_0x400|, DATA, READONLY
-__FlashConfig
- DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
- DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
- DCB FPROT0 , FPROT1 , FPROT2 , FPROT3
- DCB FSEC , FOPT , 0xFF , 0xFF
- ENDIF
-
- AREA |.text|, CODE, READONLY
-
-; Reset Handler
-
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-NMI_Handler\
- PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler\
- PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler\
- PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler\
- PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-Default_Handler\
- PROC
- EXPORT DMA0_IRQHandler [WEAK]
- EXPORT DMA1_IRQHandler [WEAK]
- EXPORT DMA2_IRQHandler [WEAK]
- EXPORT DMA3_IRQHandler [WEAK]
- EXPORT Reserved20_IRQHandler [WEAK]
- EXPORT FTFA_IRQHandler [WEAK]
- EXPORT PMC_IRQHandler [WEAK]
- EXPORT LLWU_IRQHandler [WEAK]
- EXPORT I2C0_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT SPI0_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT LPUART0_IRQHandler [WEAK]
- EXPORT LPUART1_IRQHandler [WEAK]
- EXPORT UART2_FLEXIO_IRQHandler [WEAK]
- EXPORT ADC0_IRQHandler [WEAK]
- EXPORT CMP0_IRQHandler [WEAK]
- EXPORT TPM0_IRQHandler [WEAK]
- EXPORT TPM1_IRQHandler [WEAK]
- EXPORT TPM2_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT RTC_Seconds_IRQHandler [WEAK]
- EXPORT PIT_IRQHandler [WEAK]
- EXPORT I2S0_IRQHandler [WEAK]
- EXPORT USB0_IRQHandler [WEAK]
- EXPORT DAC0_IRQHandler [WEAK]
- EXPORT Reserved42_IRQHandler [WEAK]
- EXPORT Reserved43_IRQHandler [WEAK]
- EXPORT LPTMR0_IRQHandler [WEAK]
- EXPORT LCD_IRQHandler [WEAK]
- EXPORT PORTA_IRQHandler [WEAK]
- EXPORT PORTCD_IRQHandler [WEAK]
- EXPORT DefaultISR [WEAK]
-DMA0_IRQHandler
-DMA1_IRQHandler
-DMA2_IRQHandler
-DMA3_IRQHandler
-Reserved20_IRQHandler
-FTFA_IRQHandler
-PMC_IRQHandler
-LLWU_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-SPI0_IRQHandler
-SPI1_IRQHandler
-LPUART0_IRQHandler
-LPUART1_IRQHandler
-UART2_FLEXIO_IRQHandler
-ADC0_IRQHandler
-CMP0_IRQHandler
-TPM0_IRQHandler
-TPM1_IRQHandler
-TPM2_IRQHandler
-RTC_IRQHandler
-RTC_Seconds_IRQHandler
-PIT_IRQHandler
-I2S0_IRQHandler
-USB0_IRQHandler
-DAC0_IRQHandler
-Reserved42_IRQHandler
-Reserved43_IRQHandler
-LPTMR0_IRQHandler
-LCD_IRQHandler
-PORTA_IRQHandler
-PORTCD_IRQHandler
-DefaultISR
- B .
- ENDP
- ALIGN
-
-
- END
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