-#define I2S0_TCSR *(volatile uint32_t *)0x4002F000 // SAI Transmit Control Register
-#define I2S_TCSR_TE (uint32_t)0x80000000 // Transmitter Enable
-#define I2S_TCSR_STOPE (uint32_t)0x40000000 // Transmitter Enable in Stop mode
-#define I2S_TCSR_DBGE (uint32_t)0x20000000 // Transmitter Enable in Debug mode
-#define I2S_TCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable
-#define I2S_TCSR_FR (uint32_t)0x02000000 // FIFO Reset
-#define I2S_TCSR_SR (uint32_t)0x01000000 // Software Reset
-#define I2S_TCSR_WSF (uint32_t)0x00100000 // Word Start Flag
-#define I2S_TCSR_SEF (uint32_t)0x00080000 // Sync Error Flag
-#define I2S_TCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun)
-#define I2S_TCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty)
-#define I2S_TCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready)
-#define I2S_TCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable
-#define I2S_TCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable
-#define I2S_TCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable
-#define I2S_TCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable
-#define I2S_TCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable
-#define I2S_TCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable
-#define I2S_TCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable
-#define I2S0_TCR1 *(volatile uint32_t *)0x4002F004 // SAI Transmit Configuration 1 Register
-#define I2S_TCR1_TFW(n) ((uint32_t)n & 0x03) // Transmit FIFO watermark
-#define I2S0_TCR2 *(volatile uint32_t *)0x4002F008 // SAI Transmit Configuration 2 Register
-#define I2S_TCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2
-#define I2S_TCR2_BCD ((uint32_t)1<<24) // Bit clock direction
-#define I2S_TCR2_BCP ((uint32_t)1<<25) // Bit clock polarity
-#define I2S_TCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK
-#define I2S_TCR2_BCI ((uint32_t)1<<28) // Bit clock input
-#define I2S_TCR2_BCS ((uint32_t)1<<29) // Bit clock swap
-#define I2S_TCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver
-#define I2S0_TCR3 *(volatile uint32_t *)0x4002F00C // SAI Transmit Configuration 3 Register
-#define I2S_TCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration
-#define I2S_TCR3_TCE ((uint32_t)0x10000) // transmit channel enable
-#define I2S0_TCR4 *(volatile uint32_t *)0x4002F010 // SAI Transmit Configuration 4 Register
-#define I2S_TCR4_FSD ((uint32_t)1) // Frame Sync Direction
-#define I2S_TCR4_FSP ((uint32_t)2) // Frame Sync Polarity
-#define I2S_TCR4_FSE ((uint32_t)8) // Frame Sync Early
-#define I2S_TCR4_MF ((uint32_t)0x10) // MSB First
-#define I2S_TCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width
-#define I2S_TCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size
-#define I2S0_TCR5 *(volatile uint32_t *)0x4002F014 // SAI Transmit Configuration 5 Register
-#define I2S_TCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted
-#define I2S_TCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width
-#define I2S_TCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width
-#define I2S0_TDR0 *(volatile uint32_t *)0x4002F020 // SAI Transmit Data Register
-#define I2S0_TFR0 *(volatile uint32_t *)0x4002F040 // SAI Transmit FIFO Register
-#define I2S_TFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer
-#define I2S_TFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer
-#define I2S0_TMR *(volatile uint32_t *)0x4002F060 // SAI Transmit Mask Register
-#define I2S_TMR_TWM(n) ((uint32_t)n & 0xFFFFFFFF)
-#define I2S0_RCSR *(volatile uint32_t *)0x4002F080 // SAI Receive Control Register
-#define I2S_RCSR_RE (uint32_t)0x80000000 // Receiver Enable
-#define I2S_RCSR_STOPE (uint32_t)0x40000000 // Receiver Enable in Stop mode
-#define I2S_RCSR_DBGE (uint32_t)0x20000000 // Receiver Enable in Debug mode
-#define I2S_RCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable
-#define I2S_RCSR_FR (uint32_t)0x02000000 // FIFO Reset
-#define I2S_RCSR_SR (uint32_t)0x01000000 // Software Reset
-#define I2S_RCSR_WSF (uint32_t)0x00100000 // Word Start Flag
-#define I2S_RCSR_SEF (uint32_t)0x00080000 // Sync Error Flag
-#define I2S_RCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun)
-#define I2S_RCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty)
-#define I2S_RCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready)
-#define I2S_RCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable
-#define I2S_RCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable
-#define I2S_RCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable
-#define I2S_RCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable
-#define I2S_RCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable
-#define I2S_RCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable
-#define I2S_RCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable
-#define I2S0_RCR1 *(volatile uint32_t *)0x4002F084 // SAI Receive Configuration 1 Register
-#define I2S_RCR1_RFW(n) ((uint32_t)n & 0x03) // Receive FIFO watermark
-#define I2S0_RCR2 *(volatile uint32_t *)0x4002F088 // SAI Receive Configuration 2 Register
-#define I2S_RCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2
-#define I2S_RCR2_BCD ((uint32_t)1<<24) // Bit clock direction
-#define I2S_RCR2_BCP ((uint32_t)1<<25) // Bit clock polarity
-#define I2S_RCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK
-#define I2S_RCR2_BCI ((uint32_t)1<<28) // Bit clock input
-#define I2S_RCR2_BCS ((uint32_t)1<<29) // Bit clock swap
-#define I2S_RCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver
-#define I2S0_RCR3 *(volatile uint32_t *)0x4002F08C // SAI Receive Configuration 3 Register
-#define I2S_RCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration
-#define I2S_RCR3_RCE ((uint32_t)0x10000) // receive channel enable
-#define I2S0_RCR4 *(volatile uint32_t *)0x4002F090 // SAI Receive Configuration 4 Register
-#define I2S_RCR4_FSD ((uint32_t)1) // Frame Sync Direction
-#define I2S_RCR4_FSP ((uint32_t)2) // Frame Sync Polarity
-#define I2S_RCR4_FSE ((uint32_t)8) // Frame Sync Early
-#define I2S_RCR4_MF ((uint32_t)0x10) // MSB First
-#define I2S_RCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width
-#define I2S_RCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size
-#define I2S0_RCR5 *(volatile uint32_t *)0x4002F094 // SAI Receive Configuration 5 Register
-#define I2S_RCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted
-#define I2S_RCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width
-#define I2S_RCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width
-#define I2S0_RDR0 *(volatile uint32_t *)0x4002F0A0 // SAI Receive Data Register
-#define I2S0_RFR0 *(volatile uint32_t *)0x4002F0C0 // SAI Receive FIFO Register
-#define I2S_RFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer
-#define I2S_RFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer
-#define I2S0_RMR *(volatile uint32_t *)0x4002F0E0 // SAI Receive Mask Register
-#define I2S_RMR_RWM(n) ((uint32_t)n & 0xFFFFFFFF)
-#define I2S0_MCR *(volatile uint32_t *)0x4002F100 // SAI MCLK Control Register
-#define I2S_MCR_DUF ((uint32_t)1<<31) // Divider Update Flag
-#define I2S_MCR_MOE ((uint32_t)1<<30) // MCLK Output Enable
-#define I2S_MCR_MICS(n) ((uint32_t)(n & 3)<<24) // MCLK Input Clock Select
-#define I2S0_MDR *(volatile uint32_t *)0x4002F104 // SAI MCLK Divide Register
-#define I2S_MDR_FRACT(n) ((uint32_t)(n & 0xff)<<12) // MCLK Fraction
-#define I2S_MDR_DIVIDE(n) ((uint32_t)(n & 0xfff)) // MCLK Divide
+#define I2S0_TCSR *(volatile uint32_t *)0x4002F000 // SAI Transmit Control Register
+#define I2S_TCSR_TE (uint32_t)0x80000000 // Transmitter Enable
+#define I2S_TCSR_STOPE (uint32_t)0x40000000 // Transmitter Enable in Stop mode
+#define I2S_TCSR_DBGE (uint32_t)0x20000000 // Transmitter Enable in Debug mode
+#define I2S_TCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable
+#define I2S_TCSR_FR (uint32_t)0x02000000 // FIFO Reset
+#define I2S_TCSR_SR (uint32_t)0x01000000 // Software Reset
+#define I2S_TCSR_WSF (uint32_t)0x00100000 // Word Start Flag
+#define I2S_TCSR_SEF (uint32_t)0x00080000 // Sync Error Flag
+#define I2S_TCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun)
+#define I2S_TCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty)
+#define I2S_TCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready)
+#define I2S_TCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable
+#define I2S_TCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable
+#define I2S_TCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable
+#define I2S_TCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable
+#define I2S_TCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable
+#define I2S_TCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable
+#define I2S_TCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable
+#define I2S0_TCR1 *(volatile uint32_t *)0x4002F004 // SAI Transmit Configuration 1 Register
+#define I2S_TCR1_TFW(n) ((uint32_t)n & 0x03) // Transmit FIFO watermark
+#define I2S0_TCR2 *(volatile uint32_t *)0x4002F008 // SAI Transmit Configuration 2 Register
+#define I2S_TCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2
+#define I2S_TCR2_BCD ((uint32_t)1<<24) // Bit clock direction
+#define I2S_TCR2_BCP ((uint32_t)1<<25) // Bit clock polarity
+#define I2S_TCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK
+#define I2S_TCR2_BCI ((uint32_t)1<<28) // Bit clock input
+#define I2S_TCR2_BCS ((uint32_t)1<<29) // Bit clock swap
+#define I2S_TCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver
+#define I2S0_TCR3 *(volatile uint32_t *)0x4002F00C // SAI Transmit Configuration 3 Register
+#define I2S_TCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration
+#define I2S_TCR3_TCE ((uint32_t)0x10000) // transmit channel enable
+#define I2S0_TCR4 *(volatile uint32_t *)0x4002F010 // SAI Transmit Configuration 4 Register
+#define I2S_TCR4_FSD ((uint32_t)1) // Frame Sync Direction
+#define I2S_TCR4_FSP ((uint32_t)2) // Frame Sync Polarity
+#define I2S_TCR4_FSE ((uint32_t)8) // Frame Sync Early
+#define I2S_TCR4_MF ((uint32_t)0x10) // MSB First
+#define I2S_TCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width
+#define I2S_TCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size
+#define I2S0_TCR5 *(volatile uint32_t *)0x4002F014 // SAI Transmit Configuration 5 Register
+#define I2S_TCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted
+#define I2S_TCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width
+#define I2S_TCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width
+#define I2S0_TDR0 *(volatile uint32_t *)0x4002F020 // SAI Transmit Data Register
+#define I2S0_TFR0 *(volatile uint32_t *)0x4002F040 // SAI Transmit FIFO Register
+#define I2S_TFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer
+#define I2S_TFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer
+#define I2S0_TMR *(volatile uint32_t *)0x4002F060 // SAI Transmit Mask Register
+#define I2S_TMR_TWM(n) ((uint32_t)n & 0xFFFFFFFF)
+#define I2S0_RCSR *(volatile uint32_t *)0x4002F080 // SAI Receive Control Register
+#define I2S_RCSR_RE (uint32_t)0x80000000 // Receiver Enable
+#define I2S_RCSR_STOPE (uint32_t)0x40000000 // Receiver Enable in Stop mode
+#define I2S_RCSR_DBGE (uint32_t)0x20000000 // Receiver Enable in Debug mode
+#define I2S_RCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable
+#define I2S_RCSR_FR (uint32_t)0x02000000 // FIFO Reset
+#define I2S_RCSR_SR (uint32_t)0x01000000 // Software Reset
+#define I2S_RCSR_WSF (uint32_t)0x00100000 // Word Start Flag
+#define I2S_RCSR_SEF (uint32_t)0x00080000 // Sync Error Flag
+#define I2S_RCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun)
+#define I2S_RCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty)
+#define I2S_RCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready)
+#define I2S_RCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable
+#define I2S_RCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable
+#define I2S_RCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable
+#define I2S_RCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable
+#define I2S_RCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable
+#define I2S_RCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable
+#define I2S_RCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable
+#define I2S0_RCR1 *(volatile uint32_t *)0x4002F084 // SAI Receive Configuration 1 Register
+#define I2S_RCR1_RFW(n) ((uint32_t)n & 0x03) // Receive FIFO watermark
+#define I2S0_RCR2 *(volatile uint32_t *)0x4002F088 // SAI Receive Configuration 2 Register
+#define I2S_RCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2
+#define I2S_RCR2_BCD ((uint32_t)1<<24) // Bit clock direction
+#define I2S_RCR2_BCP ((uint32_t)1<<25) // Bit clock polarity
+#define I2S_RCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK
+#define I2S_RCR2_BCI ((uint32_t)1<<28) // Bit clock input
+#define I2S_RCR2_BCS ((uint32_t)1<<29) // Bit clock swap
+#define I2S_RCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver
+#define I2S0_RCR3 *(volatile uint32_t *)0x4002F08C // SAI Receive Configuration 3 Register
+#define I2S_RCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration
+#define I2S_RCR3_RCE ((uint32_t)0x10000) // receive channel enable
+#define I2S0_RCR4 *(volatile uint32_t *)0x4002F090 // SAI Receive Configuration 4 Register
+#define I2S_RCR4_FSD ((uint32_t)1) // Frame Sync Direction
+#define I2S_RCR4_FSP ((uint32_t)2) // Frame Sync Polarity
+#define I2S_RCR4_FSE ((uint32_t)8) // Frame Sync Early
+#define I2S_RCR4_MF ((uint32_t)0x10) // MSB First
+#define I2S_RCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width
+#define I2S_RCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size
+#define I2S0_RCR5 *(volatile uint32_t *)0x4002F094 // SAI Receive Configuration 5 Register
+#define I2S_RCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted
+#define I2S_RCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width
+#define I2S_RCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width
+#define I2S0_RDR0 *(volatile uint32_t *)0x4002F0A0 // SAI Receive Data Register
+#define I2S0_RFR0 *(volatile uint32_t *)0x4002F0C0 // SAI Receive FIFO Register
+#define I2S_RFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer
+#define I2S_RFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer
+#define I2S0_RMR *(volatile uint32_t *)0x4002F0E0 // SAI Receive Mask Register
+#define I2S_RMR_RWM(n) ((uint32_t)n & 0xFFFFFFFF)
+#define I2S0_MCR *(volatile uint32_t *)0x4002F100 // SAI MCLK Control Register
+#define I2S_MCR_DUF ((uint32_t)1<<31) // Divider Update Flag
+#define I2S_MCR_MOE ((uint32_t)1<<30) // MCLK Output Enable
+#define I2S_MCR_MICS(n) ((uint32_t)(n & 3)<<24) // MCLK Input Clock Select
+#define I2S0_MDR *(volatile uint32_t *)0x4002F104 // SAI MCLK Divide Register
+#define I2S_MDR_FRACT(n) ((uint32_t)(n & 0xff)<<12) // MCLK Fraction
+#define I2S_MDR_DIVIDE(n) ((uint32_t)(n & 0xfff)) // MCLK Divide