1 /*----------------------------------------------------------------------------
3 *----------------------------------------------------------------------------
5 * Purpose: Hardware Abstraction Layer for Cortex-M
7 *----------------------------------------------------------------------------
9 * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
10 * All rights reserved.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 * - Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * - Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * - Neither the name of ARM nor the names of its contributors may be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *---------------------------------------------------------------------------*/
35 #include "rt_TypeDef.h"
37 #include "rt_HAL_CM.h"
40 /*----------------------------------------------------------------------------
42 *---------------------------------------------------------------------------*/
48 /*----------------------------------------------------------------------------
50 *---------------------------------------------------------------------------*/
53 /*--------------------------- rt_init_stack ---------------------------------*/
55 void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
56 /* Prepare TCB and saved context for a first time start of a task. */
59 /* Prepare a complete interrupt frame for first task start */
60 size = p_TCB->priv_stack >> 2;
62 /* Write to the top of stack. */
63 stk = &p_TCB->stack[size];
65 /* Auto correct to 8-byte ARM stack alignment. */
66 if ((U32)stk & 0x04) {
72 /* Default xPSR and initial PC */
73 stk[15] = INITIAL_xPSR;
74 stk[14] = (U32)task_body;
76 /* Clear R4-R11,R0-R3,R12,LR registers. */
77 for (i = 0; i < 14; i++) {
81 /* Assign a void pointer to R0. */
82 stk[8] = (U32)p_TCB->msg;
84 /* Initial Task stack pointer. */
85 p_TCB->tsk_stack = (U32)stk;
87 /* Task entry point. */
88 p_TCB->ptask = task_body;
90 /* Set a magic word for checking of stack overflow.
91 For the main thread (ID: 0x01) the stack is in a memory area shared with the
92 heap, therefore the last word of the stack is a moving target.
93 We want to do stack/heap collision detection instead.
95 if (p_TCB->task_id != 0x01)
96 p_TCB->stack[0] = MAGIC_WORD;
100 /*--------------------------- rt_ret_val ----------------------------------*/
102 static __inline U32 *rt_ret_regs (P_TCB p_TCB) {
103 /* Get pointer to task return value registers (R0..R3) in Stack */
104 #if (__TARGET_FPU_VFP)
105 if (p_TCB->stack_frame) {
106 /* Extended Stack Frame: R4-R11,S16-S31,R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR */
107 return (U32 *)(p_TCB->tsk_stack + 8*4 + 16*4);
109 /* Basic Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
110 return (U32 *)(p_TCB->tsk_stack + 8*4);
113 /* Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
114 return (U32 *)(p_TCB->tsk_stack + 8*4);
118 void rt_ret_val (P_TCB p_TCB, U32 v0) {
121 ret = rt_ret_regs(p_TCB);
125 void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) {
128 ret = rt_ret_regs(p_TCB);
134 /*--------------------------- dbg_init --------------------------------------*/
137 void dbg_init (void) {
138 if ((DEMCR & DEMCR_TRCENA) &&
139 (ITM_CONTROL & ITM_ITMENA) &&
140 (ITM_ENABLE & (1UL << 31))) {
146 /*--------------------------- dbg_task_notify -------------------------------*/
149 void dbg_task_notify (P_TCB p_tcb, BOOL create) {
150 while (ITM_PORT31_U32 == 0);
151 ITM_PORT31_U32 = (U32)p_tcb->ptask;
152 while (ITM_PORT31_U32 == 0);
153 ITM_PORT31_U16 = (create << 8) | p_tcb->task_id;
157 /*--------------------------- dbg_task_switch -------------------------------*/
160 void dbg_task_switch (U32 task_id) {
161 while (ITM_PORT31_U32 == 0);
162 ITM_PORT31_U8 = task_id;
167 /*----------------------------------------------------------------------------
169 *---------------------------------------------------------------------------*/