1 /**********************************************************************
2 * $Id$ lpc17_emac.c 2011-11-20
5 * @brief LPC17 ethernet driver for LWIP
8 * @author NXP MCU SW Application Team
10 * Copyright(C) 2011, NXP Semiconductor
11 * All rights reserved.
13 ***********************************************************************
14 * Software that is described herein is for illustrative purposes only
15 * which provides customers with programming information regarding the
16 * products. This software is supplied "AS IS" without any warranties.
17 * NXP Semiconductors assumes no responsibility or liability for the
18 * use of the software, conveys no license or title under any patent,
19 * copyright, or mask work right to the product. NXP Semiconductors
20 * reserves the right to make changes in the software without
21 * notification. NXP Semiconductors also make no representation or
22 * warranty that such application will be suitable for the specified
23 * use without further testing or modification.
24 **********************************************************************/
30 #include "lwip/pbuf.h"
31 #include "lwip/stats.h"
32 #include "lwip/snmp.h"
33 #include "netif/etharp.h"
34 #include "netif/ppp_oe.h"
36 #include "lpc17xx_emac.h"
38 #include "lpc_emac_config.h"
42 #include "mbed_interface.h"
46 #error LPC_EMAC_RMII is not defined!
49 #if LPC_NUM_BUFF_TXDESCS < 2
50 #error LPC_NUM_BUFF_TXDESCS must be at least 2
53 #if LPC_NUM_BUFF_RXDESCS < 3
54 #error LPC_NUM_BUFF_RXDESCS must be at least 3
57 /** @defgroup lwip17xx_emac_DRIVER lpc17 EMAC driver for LWIP
64 /** \brief Driver transmit and receive thread priorities
66 * Thread priorities for receive thread and TX cleanup thread. Alter
67 * to prioritize receive or transmit bandwidth. In a heavily loaded
68 * system or with LEIP_DEBUG enabled, the priorities might be better
70 #define RX_PRIORITY (osPriorityNormal)
71 #define TX_PRIORITY (osPriorityNormal)
73 /** \brief Debug output formatter lock define
75 * When using FreeRTOS and with LWIP_DEBUG enabled, enabling this
76 * define will allow RX debug messages to not interleave with the
77 * TX messages (so they are actually readable). Not enabling this
78 * define when the system is under load will cause the output to
79 * be unreadable. There is a small tradeoff in performance for this
80 * so use it only for debug. */
81 //#define LOCK_RX_THREAD
83 /** \brief Receive group interrupts
85 #define RXINTGROUP (EMAC_INT_RX_OVERRUN | EMAC_INT_RX_ERR | EMAC_INT_RX_DONE)
87 /** \brief Transmit group interrupts
89 #define TXINTGROUP (EMAC_INT_TX_UNDERRUN | EMAC_INT_TX_ERR | EMAC_INT_TX_DONE)
91 /** \brief Signal used for ethernet ISR to signal packet_rx() thread.
100 /** \brief Structure of a TX/RX descriptor
104 volatile u32_t packet; /**< Pointer to buffer */
105 volatile u32_t control; /**< Control word */
108 /** \brief Structure of a RX status entry
112 volatile u32_t statusinfo; /**< RX status word */
113 volatile u32_t statushashcrc; /**< RX hash CRC */
116 /* LPC EMAC driver data structure */
117 struct lpc_enetdata {
118 /* prxs must be 8 byte aligned! */
119 LPC_TXRX_STATUS_T prxs[LPC_NUM_BUFF_RXDESCS]; /**< Pointer to RX statuses */
120 struct netif *netif; /**< Reference back to LWIP parent netif */
121 LPC_TXRX_DESC_T ptxd[LPC_NUM_BUFF_TXDESCS]; /**< Pointer to TX descriptor list */
122 LPC_TXRX_STATUS_T ptxs[LPC_NUM_BUFF_TXDESCS]; /**< Pointer to TX statuses */
123 LPC_TXRX_DESC_T prxd[LPC_NUM_BUFF_RXDESCS]; /**< Pointer to RX descriptor list */
124 struct pbuf *rxb[LPC_NUM_BUFF_RXDESCS]; /**< RX pbuf pointer list, zero-copy mode */
125 u32_t rx_fill_desc_index; /**< RX descriptor next available index */
126 volatile u32_t rx_free_descs; /**< Count of free RX descriptors */
127 struct pbuf *txb[LPC_NUM_BUFF_TXDESCS]; /**< TX pbuf pointer list, zero-copy mode */
128 u32_t lpc_last_tx_idx; /**< TX last descriptor index, zero-copy mode */
130 sys_thread_t RxThread; /**< RX receive thread data object pointer */
131 sys_sem_t TxCleanSem; /**< TX cleanup thread wakeup semaphore */
132 sys_mutex_t TXLockMutex; /**< TX critical section mutex */
133 sys_sem_t xTXDCountSem; /**< TX free buffer counting semaphore */
137 #if defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
138 # if defined (__ICCARM__)
139 # define ETHMEM_SECTION
140 # elif defined(TOOLCHAIN_GCC_CR)
141 # define ETHMEM_SECTION __attribute__((section(".data.$RamPeriph32"), aligned))
143 # define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned))
145 #elif defined(TARGET_LPC1768)
146 # if defined(TOOLCHAIN_GCC_ARM)
147 # define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned))
151 #ifndef ETHMEM_SECTION
152 #define ETHMEM_SECTION ALIGNED(8)
155 /** \brief LPC EMAC driver work data
157 ETHMEM_SECTION struct lpc_enetdata lpc_enetdata;
159 /** \brief Queues a pbuf into the RX descriptor list
161 * \param[in] lpc_enetif Pointer to the drvier data structure
162 * \param[in] p Pointer to pbuf to queue
164 static void lpc_rxqueue_pbuf(struct lpc_enetdata *lpc_enetif, struct pbuf *p)
168 /* Get next free descriptor index */
169 idx = lpc_enetif->rx_fill_desc_index;
171 /* Setup descriptor and clear statuses */
172 lpc_enetif->prxd[idx].control = EMAC_RCTRL_INT | ((u32_t) (p->len - 1));
173 lpc_enetif->prxd[idx].packet = (u32_t) p->payload;
174 lpc_enetif->prxs[idx].statusinfo = 0xFFFFFFFF;
175 lpc_enetif->prxs[idx].statushashcrc = 0xFFFFFFFF;
177 /* Save pbuf pointer for push to network layer later */
178 lpc_enetif->rxb[idx] = p;
180 /* Wrap at end of descriptor list */
182 if (idx >= LPC_NUM_BUFF_RXDESCS)
185 /* Queue descriptor(s) */
186 lpc_enetif->rx_free_descs -= 1;
187 lpc_enetif->rx_fill_desc_index = idx;
188 LPC_EMAC->RxConsumeIndex = idx;
190 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
191 ("lpc_rxqueue_pbuf: pbuf packet queued: %p (free desc=%d)\n", p,
192 lpc_enetif->rx_free_descs));
195 /** \brief Attempt to allocate and requeue a new pbuf for RX
197 * \param[in] netif Pointer to the netif structure
198 * \returns 1 if a packet was allocated and requeued, otherwise 0
200 s32_t lpc_rx_queue(struct netif *netif)
202 struct lpc_enetdata *lpc_enetif = netif->state;
206 /* Attempt to requeue as many packets as possible */
207 while (lpc_enetif->rx_free_descs > 0) {
208 /* Allocate a pbuf from the pool. We need to allocate at the
209 maximum size as we don't know the size of the yet to be
211 p = pbuf_alloc(PBUF_RAW, (u16_t) EMAC_ETH_MAX_FLEN, PBUF_RAM);
213 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
214 ("lpc_rx_queue: could not allocate RX pbuf (free desc=%d)\n",
215 lpc_enetif->rx_free_descs));
219 /* pbufs allocated from the RAM pool should be non-chained. */
220 LWIP_ASSERT("lpc_rx_queue: pbuf is not contiguous (chained)",
224 lpc_rxqueue_pbuf(lpc_enetif, p);
226 /* Update queued count */
233 /** \brief Sets up the RX descriptor ring buffers.
235 * This function sets up the descriptor list used for receive packets.
237 * \param[in] lpc_enetif Pointer to driver data structure
238 * \returns Always returns ERR_OK
240 static err_t lpc_rx_setup(struct lpc_enetdata *lpc_enetif)
242 /* Setup pointers to RX structures */
243 LPC_EMAC->RxDescriptor = (u32_t) &lpc_enetif->prxd[0];
244 LPC_EMAC->RxStatus = (u32_t) &lpc_enetif->prxs[0];
245 LPC_EMAC->RxDescriptorNumber = LPC_NUM_BUFF_RXDESCS - 1;
247 lpc_enetif->rx_free_descs = LPC_NUM_BUFF_RXDESCS;
248 lpc_enetif->rx_fill_desc_index = 0;
250 /* Build RX buffer and descriptors */
251 lpc_rx_queue(lpc_enetif->netif);
256 /** \brief Allocates a pbuf and returns the data from the incoming packet.
258 * \param[in] netif the lwip network interface structure for this lpc_enetif
259 * \return a pbuf filled with the received packet (including MAC header)
260 * NULL on memory error
262 static struct pbuf *lpc_low_level_input(struct netif *netif)
264 struct lpc_enetdata *lpc_enetif = netif->state;
265 struct pbuf *p = NULL;
269 #ifdef LOCK_RX_THREAD
271 /* Get exclusive access */
272 sys_mutex_lock(&lpc_enetif->TXLockMutex);
276 /* Monitor RX overrun status. This should never happen unless
277 (possibly) the internal bus is behing held up by something.
278 Unless your system is running at a very low clock speed or
279 there are possibilities that the internal buses may be held
280 up for a long time, this can probably safely be removed. */
281 if (LPC_EMAC->IntStatus & EMAC_INT_RX_OVERRUN) {
282 LINK_STATS_INC(link.err);
283 LINK_STATS_INC(link.drop);
285 /* Temporarily disable RX */
286 LPC_EMAC->MAC1 &= ~EMAC_MAC1_REC_EN;
288 /* Reset the RX side */
289 LPC_EMAC->MAC1 |= EMAC_MAC1_RES_RX;
290 LPC_EMAC->IntClear = EMAC_INT_RX_OVERRUN;
292 /* De-allocate all queued RX pbufs */
293 for (idx = 0; idx < LPC_NUM_BUFF_RXDESCS; idx++) {
294 if (lpc_enetif->rxb[idx] != NULL) {
295 pbuf_free(lpc_enetif->rxb[idx]);
296 lpc_enetif->rxb[idx] = NULL;
300 /* Start RX side again */
301 lpc_rx_setup(lpc_enetif);
304 LPC_EMAC->MAC1 |= EMAC_MAC1_REC_EN;
306 #ifdef LOCK_RX_THREAD
308 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
315 /* Determine if a frame has been received */
317 idx = LPC_EMAC->RxConsumeIndex;
318 if (LPC_EMAC->RxProduceIndex != idx) {
320 if (lpc_enetif->prxs[idx].statusinfo & (EMAC_RINFO_CRC_ERR |
321 EMAC_RINFO_SYM_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_LEN_ERR)) {
323 if (lpc_enetif->prxs[idx].statusinfo & (EMAC_RINFO_CRC_ERR |
324 EMAC_RINFO_SYM_ERR | EMAC_RINFO_ALIGN_ERR))
325 LINK_STATS_INC(link.chkerr);
326 if (lpc_enetif->prxs[idx].statusinfo & EMAC_RINFO_LEN_ERR)
327 LINK_STATS_INC(link.lenerr);
331 LINK_STATS_INC(link.drop);
333 /* Re-queue the pbuf for receive */
334 lpc_enetif->rx_free_descs++;
335 p = lpc_enetif->rxb[idx];
336 lpc_enetif->rxb[idx] = NULL;
337 lpc_rxqueue_pbuf(lpc_enetif, p);
339 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
340 ("lpc_low_level_input: Packet dropped with errors (0x%x)\n",
341 lpc_enetif->prxs[idx].statusinfo));
345 /* A packet is waiting, get length */
346 length = (lpc_enetif->prxs[idx].statusinfo & 0x7FF) + 1;
349 p = lpc_enetif->rxb[idx];
351 p->len = (u16_t) length;
353 /* Free pbuf from descriptor */
354 lpc_enetif->rxb[idx] = NULL;
355 lpc_enetif->rx_free_descs++;
357 /* Attempt to queue new buffer(s) */
358 if (lpc_rx_queue(lpc_enetif->netif) == 0) {
359 /* Drop the frame due to OOM. */
360 LINK_STATS_INC(link.drop);
362 /* Re-queue the pbuf for receive */
364 lpc_rxqueue_pbuf(lpc_enetif, p);
366 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
367 ("lpc_low_level_input: Packet index %d dropped for OOM\n",
370 #ifdef LOCK_RX_THREAD
372 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
379 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
380 ("lpc_low_level_input: Packet received: %p, size %d (index=%d)\n",
384 p->tot_len = (u16_t) length;
385 LINK_STATS_INC(link.recv);
389 #ifdef LOCK_RX_THREAD
391 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
398 /** \brief Attempt to read a packet from the EMAC interface.
400 * \param[in] netif the lwip network interface structure for this lpc_enetif
402 void lpc_enetif_input(struct netif *netif)
404 struct eth_hdr *ethhdr;
407 /* move received packet into a new pbuf */
408 p = lpc_low_level_input(netif);
412 /* points to packet payload, which starts with an Ethernet header */
415 switch (htons(ethhdr->type)) {
419 case ETHTYPE_PPPOEDISC:
421 #endif /* PPPOE_SUPPORT */
422 /* full packet send to tcpip_thread to process */
423 if (netif->input(p, netif) != ERR_OK) {
424 LWIP_DEBUGF(NETIF_DEBUG, ("lpc_enetif_input: IP input error\n"));
437 /** \brief Determine if the passed address is usable for the ethernet
440 * \param[in] addr Address of packet to check for DMA safe operation
441 * \return 1 if the packet address is not safe, otherwise 0
443 static s32_t lpc_packet_addr_notsafe(void *addr) {
444 /* Check for legal address ranges */
445 #if defined(TARGET_LPC1768)
446 if ((((u32_t) addr >= 0x2007C000) && ((u32_t) addr < 0x20083FFF))) {
447 #elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
448 if ((((u32_t) addr >= 0x20000000) && ((u32_t) addr < 0x20007FFF))) {
455 /** \brief Sets up the TX descriptor ring buffers.
457 * This function sets up the descriptor list used for transmit packets.
459 * \param[in] lpc_enetif Pointer to driver data structure
461 static err_t lpc_tx_setup(struct lpc_enetdata *lpc_enetif)
465 /* Build TX descriptors for local buffers */
466 for (idx = 0; idx < LPC_NUM_BUFF_TXDESCS; idx++) {
467 lpc_enetif->ptxd[idx].control = 0;
468 lpc_enetif->ptxs[idx].statusinfo = 0xFFFFFFFF;
471 /* Setup pointers to TX structures */
472 LPC_EMAC->TxDescriptor = (u32_t) &lpc_enetif->ptxd[0];
473 LPC_EMAC->TxStatus = (u32_t) &lpc_enetif->ptxs[0];
474 LPC_EMAC->TxDescriptorNumber = LPC_NUM_BUFF_TXDESCS - 1;
476 lpc_enetif->lpc_last_tx_idx = 0;
481 /** \brief Free TX buffers that are complete
483 * \param[in] lpc_enetif Pointer to driver data structure
484 * \param[in] cidx EMAC current descriptor comsumer index
486 static void lpc_tx_reclaim_st(struct lpc_enetdata *lpc_enetif, u32_t cidx)
489 /* Get exclusive access */
490 sys_mutex_lock(&lpc_enetif->TXLockMutex);
493 while (cidx != lpc_enetif->lpc_last_tx_idx) {
494 if (lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx] != NULL) {
495 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
496 ("lpc_tx_reclaim_st: Freeing packet %p (index %d)\n",
497 lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx],
498 lpc_enetif->lpc_last_tx_idx));
499 pbuf_free(lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx]);
500 lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx] = NULL;
504 osSemaphoreRelease(lpc_enetif->xTXDCountSem.id);
506 lpc_enetif->lpc_last_tx_idx++;
507 if (lpc_enetif->lpc_last_tx_idx >= LPC_NUM_BUFF_TXDESCS)
508 lpc_enetif->lpc_last_tx_idx = 0;
513 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
517 /** \brief User call for freeingTX buffers that are complete
519 * \param[in] netif the lwip network interface structure for this lpc_enetif
521 void lpc_tx_reclaim(struct netif *netif)
523 lpc_tx_reclaim_st((struct lpc_enetdata *) netif->state,
524 LPC_EMAC->TxConsumeIndex);
527 /** \brief Polls if an available TX descriptor is ready. Can be used to
528 * determine if the low level transmit function will block.
530 * \param[in] netif the lwip network interface structure for this lpc_enetif
531 * \return 0 if no descriptors are read, or >0
533 s32_t lpc_tx_ready(struct netif *netif)
538 cidx = LPC_EMAC->TxConsumeIndex;
539 idx = LPC_EMAC->TxProduceIndex;
541 /* Determine number of free buffers */
543 fb = LPC_NUM_BUFF_TXDESCS;
545 fb = (LPC_NUM_BUFF_TXDESCS - 1) -
546 ((idx + LPC_NUM_BUFF_TXDESCS) - cidx);
548 fb = (LPC_NUM_BUFF_TXDESCS - 1) - (cidx - idx);
553 /** \brief Low level output of a packet. Never call this from an
554 * interrupt context, as it may block until TX descriptors
557 * \param[in] netif the lwip network interface structure for this lpc_enetif
558 * \param[in] p the MAC packet to send (e.g. IP packet including MAC addresses and type)
559 * \return ERR_OK if the packet could be sent or an err_t value if the packet couldn't be sent
561 static err_t lpc_low_level_output(struct netif *netif, struct pbuf *p)
563 struct lpc_enetdata *lpc_enetif = netif->state;
566 u32_t idx, notdmasafe = 0;
570 /* Zero-copy TX buffers may be fragmented across mutliple payload
571 chains. Determine the number of descriptors needed for the
572 transfer. The pbuf chaining can be a mess! */
573 dn = (s32_t) pbuf_clen(p);
575 /* Test to make sure packet addresses are DMA safe. A DMA safe
576 address is once that uses external memory or periphheral RAM.
577 IRAM and FLASH are not safe! */
578 for (q = p; q != NULL; q = q->next)
579 notdmasafe += lpc_packet_addr_notsafe(q->payload);
581 #if LPC_TX_PBUF_BOUNCE_EN==1
582 /* If the pbuf is not DMA safe, a new bounce buffer (pbuf) will be
583 created that will be used instead. This requires an copy from the
584 non-safe DMA region to the new pbuf */
586 /* Allocate a pbuf in DMA memory */
587 np = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
591 /* This buffer better be contiguous! */
592 LWIP_ASSERT("lpc_low_level_output: New transmit pbuf is chained",
593 (pbuf_clen(np) == 1));
595 /* Copy to DMA safe pbuf */
596 dst = (u8_t *) np->payload;
597 for(q = p; q != NULL; q = q->next) {
598 /* Copy the buffer to the descriptor's buffer */
599 MEMCPY(dst, (u8_t *) q->payload, q->len);
602 np->len = p->tot_len;
604 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
605 ("lpc_low_level_output: Switched to DMA safe buffer, old=%p, new=%p\n",
608 /* use the new buffer for descrptor queueing. The original pbuf will
609 be de-allocated outsuide this driver. */
615 LWIP_ASSERT("lpc_low_level_output: Not a DMA safe pbuf",
619 /* Wait until enough descriptors are available for the transfer. */
620 /* THIS WILL BLOCK UNTIL THERE ARE ENOUGH DESCRIPTORS AVAILABLE */
621 while (dn > lpc_tx_ready(netif))
623 osSemaphoreWait(lpc_enetif->xTXDCountSem.id, osWaitForever);
628 /* Get free TX buffer index */
629 idx = LPC_EMAC->TxProduceIndex;
632 /* Get exclusive access */
633 sys_mutex_lock(&lpc_enetif->TXLockMutex);
636 /* Prevent LWIP from de-allocating this pbuf. The driver will
637 free it once it's been transmitted. */
641 /* Setup transfers */
646 /* Only save pointer to free on last descriptor */
648 /* Save size of packet and signal it's ready */
649 lpc_enetif->ptxd[idx].control = (q->len - 1) | EMAC_TCTRL_INT |
651 lpc_enetif->txb[idx] = p;
654 /* Save size of packet, descriptor is not last */
655 lpc_enetif->ptxd[idx].control = (q->len - 1) | EMAC_TCTRL_INT;
656 lpc_enetif->txb[idx] = NULL;
659 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
660 ("lpc_low_level_output: pbuf packet(%p) sent, chain#=%d,"
661 " size = %d (index=%d)\n", q->payload, dn, q->len, idx));
663 lpc_enetif->ptxd[idx].packet = (u32_t) q->payload;
668 if (idx >= LPC_NUM_BUFF_TXDESCS)
672 LPC_EMAC->TxProduceIndex = idx;
674 LINK_STATS_INC(link.xmit);
678 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
684 /** \brief LPC EMAC interrupt handler.
686 * This function handles the transmit, receive, and error interrupt of
687 * the LPC177x_8x. This is meant to be used when NO_SYS=0.
689 void ENET_IRQHandler(void)
692 /* Interrupts are not used without an RTOS */
693 NVIC_DisableIRQ(ENET_IRQn);
697 /* Interrupts are of 2 groups - transmit or receive. Based on the
698 interrupt, kick off the receive or transmit (cleanup) task */
700 /* Get pending interrupts */
701 ints = LPC_EMAC->IntStatus;
703 if (ints & RXINTGROUP) {
704 /* RX group interrupt(s): Give signal to wakeup RX receive task.*/
705 osSignalSet(lpc_enetdata.RxThread->id, RX_SIGNAL);
708 if (ints & TXINTGROUP) {
709 /* TX group interrupt(s): Give semaphore to wakeup TX cleanup task. */
710 sys_sem_signal(&lpc_enetdata.TxCleanSem);
713 /* Clear pending interrupts */
714 LPC_EMAC->IntClear = ints;
719 /** \brief Packet reception task
721 * This task is called when a packet is received. It will
722 * pass the packet to the LWIP core.
724 * \param[in] pvParameters Not used yet
726 static void packet_rx(void* pvParameters) {
727 struct lpc_enetdata *lpc_enetif = pvParameters;
730 /* Wait for receive task to wakeup */
731 osSignalWait(RX_SIGNAL, osWaitForever);
733 /* Process packets until all empty */
734 while (LPC_EMAC->RxConsumeIndex != LPC_EMAC->RxProduceIndex)
735 lpc_enetif_input(lpc_enetif->netif);
739 /** \brief Transmit cleanup task
741 * This task is called when a transmit interrupt occurs and
742 * reclaims the pbuf and descriptor used for the packet once
743 * the packet has been transferred.
745 * \param[in] pvParameters Not used yet
747 static void packet_tx(void* pvParameters) {
748 struct lpc_enetdata *lpc_enetif = pvParameters;
752 /* Wait for transmit cleanup task to wakeup */
753 sys_arch_sem_wait(&lpc_enetif->TxCleanSem, 0);
755 /* Error handling for TX underruns. This should never happen unless
756 something is holding the bus or the clocks are going too slow. It
757 can probably be safely removed. */
758 if (LPC_EMAC->IntStatus & EMAC_INT_TX_UNDERRUN) {
759 LINK_STATS_INC(link.err);
760 LINK_STATS_INC(link.drop);
763 /* Get exclusive access */
764 sys_mutex_lock(&lpc_enetif->TXLockMutex);
766 /* Reset the TX side */
767 LPC_EMAC->MAC1 |= EMAC_MAC1_RES_TX;
768 LPC_EMAC->IntClear = EMAC_INT_TX_UNDERRUN;
770 /* De-allocate all queued TX pbufs */
771 for (idx = 0; idx < LPC_NUM_BUFF_TXDESCS; idx++) {
772 if (lpc_enetif->txb[idx] != NULL) {
773 pbuf_free(lpc_enetif->txb[idx]);
774 lpc_enetif->txb[idx] = NULL;
780 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
782 /* Start TX side again */
783 lpc_tx_setup(lpc_enetif);
785 /* Free TX buffers that are done sending */
786 lpc_tx_reclaim(lpc_enetdata.netif);
792 /** \brief Low level init of the MAC and PHY.
794 * \param[in] netif Pointer to LWIP netif structure
796 static err_t low_level_init(struct netif *netif)
798 struct lpc_enetdata *lpc_enetif = netif->state;
801 /* Enable MII clocking */
802 LPC_SC->PCONP |= CLKPWR_PCONP_PCENET;
804 #if defined(TARGET_LPC1768)
805 LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */
806 LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
807 #elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
808 LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */
809 LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */
810 LPC_IOCON->P1_1 &= ~0x07;
811 LPC_IOCON->P1_1 |= 0x01; /* ENET_TXD1 */
812 LPC_IOCON->P1_4 &= ~0x07;
813 LPC_IOCON->P1_4 |= 0x01; /* ENET_TXEN */
814 LPC_IOCON->P1_8 &= ~0x07;
815 LPC_IOCON->P1_8 |= 0x01; /* ENET_CRS */
816 LPC_IOCON->P1_9 &= ~0x07;
817 LPC_IOCON->P1_9 |= 0x01; /* ENET_RXD0 */
818 LPC_IOCON->P1_10 &= ~0x07;
819 LPC_IOCON->P1_10 |= 0x01; /* ENET_RXD1 */
820 LPC_IOCON->P1_14 &= ~0x07;
821 LPC_IOCON->P1_14 |= 0x01; /* ENET_RX_ER */
822 LPC_IOCON->P1_15 &= ~0x07;
823 LPC_IOCON->P1_15 |= 0x01; /* ENET_REF_CLK */
824 LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */
825 LPC_IOCON->P1_16 |= 0x01; /* ENET_MDC */
826 LPC_IOCON->P1_17 &= ~0x07;
827 LPC_IOCON->P1_17 |= 0x01; /* ENET_MDIO */
830 /* Reset all MAC logic */
831 LPC_EMAC->MAC1 = EMAC_MAC1_RES_TX | EMAC_MAC1_RES_MCS_TX |
832 EMAC_MAC1_RES_RX | EMAC_MAC1_RES_MCS_RX | EMAC_MAC1_SIM_RES |
834 LPC_EMAC->Command = EMAC_CR_REG_RES | EMAC_CR_TX_RES | EMAC_CR_RX_RES |
835 EMAC_CR_PASS_RUNT_FRM;
838 /* Initial MAC initialization */
839 LPC_EMAC->MAC1 = EMAC_MAC1_PASS_ALL;
840 LPC_EMAC->MAC2 = EMAC_MAC2_CRC_EN | EMAC_MAC2_PAD_EN |
841 EMAC_MAC2_VLAN_PAD_EN;
842 LPC_EMAC->MAXF = EMAC_ETH_MAX_FLEN;
844 /* Set RMII management clock rate to lowest speed */
845 LPC_EMAC->MCFG = EMAC_MCFG_CLK_SEL(11) | EMAC_MCFG_RES_MII;
846 LPC_EMAC->MCFG &= ~EMAC_MCFG_RES_MII;
848 /* Maximum number of retries, 0x37 collision window, gap */
849 LPC_EMAC->CLRT = EMAC_CLRT_DEF;
850 LPC_EMAC->IPGR = EMAC_IPGR_P1_DEF | EMAC_IPGR_P2_DEF;
854 LPC_EMAC->Command = EMAC_CR_PASS_RUNT_FRM | EMAC_CR_RMII;
857 LPC_EMAC->CR = EMAC_CR_PASS_RUNT_FRM;
860 /* Initialize the PHY and reset */
861 err = lpc_phy_init(netif, LPC_EMAC_RMII);
865 /* Save station address */
866 LPC_EMAC->SA2 = (u32_t) netif->hwaddr[0] |
867 (((u32_t) netif->hwaddr[1]) << 8);
868 LPC_EMAC->SA1 = (u32_t) netif->hwaddr[2] |
869 (((u32_t) netif->hwaddr[3]) << 8);
870 LPC_EMAC->SA0 = (u32_t) netif->hwaddr[4] |
871 (((u32_t) netif->hwaddr[5]) << 8);
873 /* Setup transmit and receive descriptors */
874 if (lpc_tx_setup(lpc_enetif) != ERR_OK)
876 if (lpc_rx_setup(lpc_enetif) != ERR_OK)
879 /* Enable packet reception */
880 #if IP_SOF_BROADCAST_RECV
881 LPC_EMAC->RxFilterCtrl = EMAC_RFC_PERFECT_EN | EMAC_RFC_BCAST_EN | EMAC_RFC_MCAST_EN;
883 LPC_EMAC->RxFilterCtrl = EMAC_RFC_PERFECT_EN;
886 /* Clear and enable rx/tx interrupts */
887 LPC_EMAC->IntClear = 0xFFFF;
888 LPC_EMAC->IntEnable = RXINTGROUP | TXINTGROUP;
890 /* Enable RX and TX */
891 LPC_EMAC->Command |= EMAC_CR_RX_EN | EMAC_CR_TX_EN;
892 LPC_EMAC->MAC1 |= EMAC_MAC1_REC_EN;
897 /* This function provides a method for the PHY to setup the EMAC
898 for the PHY negotiated duplex mode */
899 void lpc_emac_set_duplex(int full_duplex)
902 LPC_EMAC->MAC2 |= EMAC_MAC2_FULL_DUP;
903 LPC_EMAC->Command |= EMAC_CR_FULL_DUP;
904 LPC_EMAC->IPGT = EMAC_IPGT_FULL_DUP;
906 LPC_EMAC->MAC2 &= ~EMAC_MAC2_FULL_DUP;
907 LPC_EMAC->Command &= ~EMAC_CR_FULL_DUP;
908 LPC_EMAC->IPGT = EMAC_IPGT_HALF_DUP;
912 /* This function provides a method for the PHY to setup the EMAC
913 for the PHY negotiated bit rate */
914 void lpc_emac_set_speed(int mbs_100)
917 LPC_EMAC->SUPP = EMAC_SUPP_SPEED;
923 * This function is the ethernet packet send function. It calls
924 * etharp_output after checking link status.
926 * \param[in] netif the lwip network interface structure for this lpc_enetif
927 * \param[in] q Pointer to pbug to send
928 * \param[in] ipaddr IP address
929 * \return ERR_OK or error code
931 err_t lpc_etharp_output(struct netif *netif, struct pbuf *q,
934 /* Only send packet is link is up */
935 if (netif->flags & NETIF_FLAG_LINK_UP)
936 return etharp_output(netif, q, ipaddr);
942 /* periodic PHY status update */
943 void phy_update(void const *nif) {
944 lpc_phy_sts_sm((struct netif*)nif);
946 osTimerDef(phy_update, phy_update);
950 * Should be called at the beginning of the program to set up the
953 * This function should be passed as a parameter to netif_add().
955 * @param[in] netif the lwip network interface structure for this lpc_enetif
956 * @return ERR_OK if the loopif is initialized
957 * ERR_MEM if private data couldn't be allocated
958 * any other err_t on error
960 err_t eth_arch_enetif_init(struct netif *netif)
964 LWIP_ASSERT("netif != NULL", (netif != NULL));
966 lpc_enetdata.netif = netif;
968 /* set MAC hardware address */
969 #if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
970 netif->hwaddr[0] = MBED_MAC_ADDR_0;
971 netif->hwaddr[1] = MBED_MAC_ADDR_1;
972 netif->hwaddr[2] = MBED_MAC_ADDR_2;
973 netif->hwaddr[3] = MBED_MAC_ADDR_3;
974 netif->hwaddr[4] = MBED_MAC_ADDR_4;
975 netif->hwaddr[5] = MBED_MAC_ADDR_5;
977 mbed_mac_address((char *)netif->hwaddr);
979 netif->hwaddr_len = ETHARP_HWADDR_LEN;
981 /* maximum transfer unit */
984 /* device capabilities */
985 netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP;
987 /* Initialize the hardware */
988 netif->state = &lpc_enetdata;
989 err = low_level_init(netif);
993 #if LWIP_NETIF_HOSTNAME
994 /* Initialize interface hostname */
995 netif->hostname = "lwiplpc";
996 #endif /* LWIP_NETIF_HOSTNAME */
998 netif->name[0] = 'e';
999 netif->name[1] = 'n';
1001 netif->output = lpc_etharp_output;
1002 netif->linkoutput = lpc_low_level_output;
1004 /* CMSIS-RTOS, start tasks */
1007 memset(lpc_enetdata.xTXDCountSem.data, 0, sizeof(lpc_enetdata.xTXDCountSem.data));
1008 lpc_enetdata.xTXDCountSem.def.semaphore = lpc_enetdata.xTXDCountSem.data;
1010 lpc_enetdata.xTXDCountSem.id = osSemaphoreCreate(&lpc_enetdata.xTXDCountSem.def, LPC_NUM_BUFF_TXDESCS);
1011 LWIP_ASSERT("xTXDCountSem creation error", (lpc_enetdata.xTXDCountSem.id != NULL));
1013 err = sys_mutex_new(&lpc_enetdata.TXLockMutex);
1014 LWIP_ASSERT("TXLockMutex creation error", (err == ERR_OK));
1016 /* Packet receive task */
1017 lpc_enetdata.RxThread = sys_thread_new("receive_thread", packet_rx, netif->state, DEFAULT_THREAD_STACKSIZE, RX_PRIORITY);
1018 LWIP_ASSERT("RxThread creation error", (lpc_enetdata.RxThread));
1020 /* Transmit cleanup task */
1021 err = sys_sem_new(&lpc_enetdata.TxCleanSem, 0);
1022 LWIP_ASSERT("TxCleanSem creation error", (err == ERR_OK));
1023 sys_thread_new("txclean_thread", packet_tx, netif->state, DEFAULT_THREAD_STACKSIZE, TX_PRIORITY);
1025 /* periodic PHY status update */
1026 osTimerId phy_timer = osTimerCreate(osTimer(phy_update), osTimerPeriodic, (void *)netif);
1027 osTimerStart(phy_timer, 250);
1033 void eth_arch_enable_interrupts(void) {
1034 NVIC_SetPriority(ENET_IRQn, ((0x01 << 3) | 0x01));
1035 NVIC_EnableIRQ(ENET_IRQn);
1038 void eth_arch_disable_interrupts(void) {
1039 NVIC_DisableIRQ(ENET_IRQn);
1046 /* --------------------------------- End Of File ------------------------------ */