1 /* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
16 * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
19 #include "gpio_irq_api.h"
20 #include "mbed_error.h"
23 /* The LPC43xx implements GPIO pin and group interrupts. Any pin in the
24 * 8 32-bit GPIO ports can interrupt. On group interrupts a pin can
25 * only interrupt on the rising or falling edge, not both as required
26 * by mbed. Also, group interrupts can't be cleared individually.
27 * This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
28 * A future implementation may provide group interrupt support.
36 static uint32_t channel_ids[CHANNEL_MAX] = {0};
37 static uint8_t channel = 0;
38 static gpio_irq_handler irq_handler;
40 static void handle_interrupt_in(void) {
41 uint32_t rise = LPC_GPIO_PIN_INT->RISE;
42 uint32_t fall = LPC_GPIO_PIN_INT->FALL;
46 for (i = 0; i < CHANNEL_MAX; i++) {
49 /* Rising edge interrupts */
50 if (channel_ids[i] != 0) {
51 irq_handler(channel_ids[i], IRQ_RISE);
53 /* Clear rising edge detected */
54 LPC_GPIO_PIN_INT->RISE = pmask;
57 /* Falling edge interrupts */
58 if (channel_ids[i] != 0) {
59 irq_handler(channel_ids[i], IRQ_FALL);
61 /* Clear falling edge detected */
62 LPC_GPIO_PIN_INT->FALL = pmask;
67 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
68 uint32_t portnum, pinnum; //, pmask;
70 if (pin == NC) return -1;
72 irq_handler = handler;
74 /* Set port and pin numbers */
75 obj->port = portnum = MBED_GPIO_PORT(pin);
76 obj->pin = pinnum = MBED_GPIO_PIN(pin);
78 /* Add to channel table */
79 channel_ids[channel] = id;
82 /* Clear rising and falling edge detection */
83 //pmask = (1 << channel);
84 //LPC_GPIO_PIN_INT->IST = pmask;
88 LPC_SCU->PINTSEL0 &= ~(0xFF << (portnum << 3));
89 LPC_SCU->PINTSEL0 |= (((portnum << 5) | pinnum) << (channel << 3));
91 LPC_SCU->PINTSEL1 &= ~(0xFF << ((portnum - 4) << 3));
92 LPC_SCU->PINTSEL1 |= (((portnum << 5) | pinnum) << ((channel - 4) << 3));
96 NVIC_SetVector((IRQn_Type)(PIN_INT0_IRQn + channel), (uint32_t)handle_interrupt_in);
97 NVIC_EnableIRQ((IRQn_Type)(PIN_INT0_IRQn + channel));
99 NVIC_SetVector((IRQn_Type)PIN_INT4_IRQn, (uint32_t)handle_interrupt_in);
100 NVIC_EnableIRQ((IRQn_Type)PIN_INT4_IRQn);
103 // Increment channel number
105 channel %= CHANNEL_MAX;
110 void gpio_irq_free(gpio_irq_t *obj) {
111 channel_ids[obj->ch] = 0;
114 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
117 /* Clear pending interrupts */
118 pmask = (1 << obj->ch);
119 LPC_GPIO_PIN_INT->IST = pmask;
121 /* Configure pin interrupt */
122 LPC_GPIO_PIN_INT->ISEL &= ~pmask;
123 if (event == IRQ_RISE) {
124 /* Rising edge interrupts */
126 LPC_GPIO_PIN_INT->SIENR |= pmask;
128 LPC_GPIO_PIN_INT->CIENR |= pmask;
131 /* Falling edge interrupts */
133 LPC_GPIO_PIN_INT->SIENF |= pmask;
135 LPC_GPIO_PIN_INT->CIENF |= pmask;
140 void gpio_irq_enable(gpio_irq_t *obj) {
141 #if !defined(CORE_M0)
142 NVIC_EnableIRQ((IRQn_Type)(PIN_INT0_IRQn + obj->ch));
144 NVIC_EnableIRQ((IRQn_Type)(PIN_INT4_IRQn + obj->ch));
148 void gpio_irq_disable(gpio_irq_t *obj) {
149 #if !defined(CORE_M0)
150 NVIC_DisableIRQ((IRQn_Type)(PIN_INT0_IRQn + obj->ch));
152 NVIC_DisableIRQ((IRQn_Type)(PIN_INT4_IRQn + obj->ch));