1 /* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
17 #include "gpio_irq_api.h"
18 #include "mbed_error.h"
21 #define CHANNEL_NUM 64
23 static uint32_t channel_ids[CHANNEL_NUM] = {0};
24 static gpio_irq_handler irq_handler;
26 static void handle_interrupt_in(void) {
27 // Read in all current interrupt registers. We do this once as the
28 // GPIO interrupt registers are on the APB bus, and this is slow.
29 uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
30 uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
31 uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
32 uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
36 // Continue as long as there are interrupts pending
38 // CLZ returns number of leading zeros, 31 minus that is location of
39 // first pending interrupt
40 bitloc = 31 - __CLZ(rise0);
41 if (channel_ids[bitloc] != 0)
42 irq_handler(channel_ids[bitloc], IRQ_RISE); //Run that interrupt
44 // Both clear the interrupt with clear register, and remove it from
45 // our local copy of the interrupt pending register
46 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
50 // Continue as long as there are interrupts pending
52 // CLZ returns number of leading zeros, 31 minus that is location of
53 // first pending interrupt
54 bitloc = 31 - __CLZ(fall0);
55 if (channel_ids[bitloc] != 0)
56 irq_handler(channel_ids[bitloc], IRQ_FALL); //Run that interrupt
58 // Both clear the interrupt with clear register, and remove it from
59 // our local copy of the interrupt pending register
60 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
66 // Continue as long as there are interrupts pending
68 // CLZ returns number of leading zeros, 31 minus that is location of
69 // first pending interrupt
70 bitloc = 31 - __CLZ(rise2);
71 if (channel_ids[bitloc+32] != 0)
72 irq_handler(channel_ids[bitloc+32], IRQ_RISE); //Run that interrupt
74 // Both clear the interrupt with clear register, and remove it from
75 // our local copy of the interrupt pending register
76 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
80 // Continue as long as there are interrupts pending
82 // CLZ returns number of leading zeros, 31 minus that is location of
83 // first pending interrupt
84 bitloc = 31 - __CLZ(fall2);
85 if (channel_ids[bitloc+32] != 0)
86 irq_handler(channel_ids[bitloc+32], IRQ_FALL); //Run that interrupt
88 // Both clear the interrupt with clear register, and remove it from
89 // our local copy of the interrupt pending register
90 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
95 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
96 if (pin == NC) return -1;
98 irq_handler = handler;
100 obj->port = ((int)(LPC_GPIO0_BASE+pin) & ~0x1F);
101 obj->pin = (int)pin % 32;
103 // Interrupts available only on GPIO0 and GPIO2
104 if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
105 error("pins on this port cannot generate interrupts");
108 // put us in the interrupt table
109 int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
110 channel_ids[index] = id;
113 NVIC_SetVector(GPIO_IRQn, (uint32_t)handle_interrupt_in);
114 NVIC_EnableIRQ(GPIO_IRQn);
119 void gpio_irq_free(gpio_irq_t *obj) {
120 channel_ids[obj->ch] = 0;
123 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
124 // ensure nothing is pending
126 case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
127 case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
130 // enable the pin interrupt
131 if (event == IRQ_RISE) {
135 LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
137 LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
142 LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
144 LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
152 LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
154 LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
159 LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
161 LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
168 void gpio_irq_enable(gpio_irq_t *obj) {
169 NVIC_EnableIRQ(GPIO_IRQn);
172 void gpio_irq_disable(gpio_irq_t *obj) {
173 NVIC_DisableIRQ(GPIO_IRQn);