1 /* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
19 #include "gpio_irq_api.h"
20 #include "mbed_error.h"
23 #define LPC_GPIO_X LPC_PINT
24 #define PININT_IRQ PIN_INT0_IRQn
26 static uint32_t channel_ids[CHANNEL_NUM] = {0};
27 static gpio_irq_handler irq_handler;
29 static inline void handle_interrupt_in(uint32_t channel) {
30 uint32_t ch_bit = (1 << channel);
31 // Return immediately if:
32 // * The interrupt was already served
33 // * There is no user handler
34 // * It is a level interrupt, not an edge interrupt
35 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
36 (channel_ids[channel] == 0 ) ||
37 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
39 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
40 irq_handler(channel_ids[channel], IRQ_RISE);
41 LPC_GPIO_X->RISE = ch_bit;
43 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
44 irq_handler(channel_ids[channel], IRQ_FALL);
45 LPC_GPIO_X->FALL = ch_bit;
47 LPC_GPIO_X->IST = ch_bit;
50 void gpio_irq0(void) {handle_interrupt_in(0);}
51 void gpio_irq1(void) {handle_interrupt_in(1);}
52 void gpio_irq2(void) {handle_interrupt_in(2);}
53 void gpio_irq3(void) {handle_interrupt_in(3);}
54 void gpio_irq4(void) {handle_interrupt_in(4);}
55 void gpio_irq5(void) {handle_interrupt_in(5);}
56 void gpio_irq6(void) {handle_interrupt_in(6);}
57 void gpio_irq7(void) {handle_interrupt_in(7);}
59 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
60 // PINT only supprt GPIO port 0 and 1 interrupt
61 if (pin >= P2_0) return -1;
63 irq_handler = handler;
65 int found_free_channel = 0;
67 for (i=0; i<CHANNEL_NUM; i++) {
68 if (channel_ids[i] == 0) {
71 found_free_channel = 1;
75 if (!found_free_channel) return -1;
77 /* Enable AHB clock to the PIN, GPIO0/1, IOCON and MUX domain. */
78 LPC_SYSCON->SYSAHBCLKCTRL0 |= ((1 << 18) | (0x1D << 11));
80 LPC_INMUX->PINTSEL[obj->ch] = pin;
82 // Interrupt Wake-Up Enable
83 LPC_SYSCON->STARTERP0 |= (1 << (obj->ch + 5));
85 LPC_GPIO_PORT->DIR[pin >> 5] &= ~(1 << (pin & 0x1F));
87 void (*channels_irq)(void) = NULL;
89 case 0: channels_irq = &gpio_irq0; break;
90 case 1: channels_irq = &gpio_irq1; break;
91 case 2: channels_irq = &gpio_irq2; break;
92 case 3: channels_irq = &gpio_irq3; break;
93 case 4: channels_irq = &gpio_irq4; break;
94 case 5: channels_irq = &gpio_irq5; break;
95 case 6: channels_irq = &gpio_irq6; break;
96 case 7: channels_irq = &gpio_irq7; break;
98 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
99 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
104 void gpio_irq_free(gpio_irq_t *obj) {
105 channel_ids[obj->ch] = 0;
106 LPC_SYSCON->STARTERP0 &= ~(1 << (obj->ch + 5));
109 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
110 unsigned int ch_bit = (1 << obj->ch);
113 if (!(LPC_GPIO_X->ISEL & ch_bit))
114 LPC_GPIO_X->IST = ch_bit;
117 LPC_GPIO_X->ISEL &= ~ch_bit;
118 if (event == IRQ_RISE) {
120 LPC_GPIO_X->IENR |= ch_bit;
122 LPC_GPIO_X->IENR &= ~ch_bit;
126 LPC_GPIO_X->IENF |= ch_bit;
128 LPC_GPIO_X->IENF &= ~ch_bit;
133 void gpio_irq_enable(gpio_irq_t *obj) {
134 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
137 void gpio_irq_disable(gpio_irq_t *obj) {
138 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));