1 /* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
16 #include "mbed_assert.h"
17 #include "analogin_api.h"
21 #define ANALOGIN_MEDIAN_FILTER 1
23 #define ADC_10BIT_RANGE 0x3FF
24 #define ADC_12BIT_RANGE 0xFFF
26 #define ADC_RANGE ADC_12BIT_RANGE
28 static const PinMap PinMap_ADC[] = {
55 void analogin_init(analogin_t *obj, PinName pin) {
56 obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
57 MBED_ASSERT(obj->adc != (ADCName)NC);
59 uint32_t port = (pin >> 5);
60 // enable clock for GPIOx
61 LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << (14 + port));
63 LPC_SWM->PINENABLE0 &= ~(1UL << obj->adc);
64 // configure GPIO as input
65 LPC_GPIO_PORT->DIR[port] &= ~(1UL << (pin & 0x1F));
68 if (obj->adc < ADC1_0)
71 LPC_SYSCON->PDRUNCFG &= ~(1 << 10);
72 LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 27);
76 LPC_SYSCON->PDRUNCFG &= ~(1 << 11);
77 LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 28);
80 // select IRC as asynchronous clock, divided by 1
81 LPC_SYSCON->ADCASYNCCLKSEL = 0;
82 LPC_SYSCON->ADCASYNCCLKDIV = 1;
84 __IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
86 // determine the system clock divider for a 500kHz ADC clock during calibration
87 uint32_t clkdiv = (SystemCoreClock / 500000) - 1;
89 // perform a self-calibration
90 adc_reg->CTRL = (1UL << 30) | (clkdiv & 0xFF);
91 while ((adc_reg->CTRL & (1UL << 30)) != 0);
93 // switch to asynchronous mode
94 adc_reg->CTRL = (1UL << 8);
97 static inline uint32_t adc_read(analogin_t *obj) {
100 __IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
102 if (obj->adc >= ADC1_0)
103 channels = ((obj->adc - ADC1_0) & 0x1F);
105 channels = (obj->adc & 0x1F);
108 adc_reg->SEQA_CTRL &= ~(0xFFF);
109 adc_reg->SEQA_CTRL |= (1UL << channels);
111 // start conversion and sequence enable
112 adc_reg->SEQA_CTRL |= ((1UL << 26) | (1UL << 31));
114 // Repeatedly get the sample data until DONE bit
115 volatile uint32_t data;
117 data = adc_reg->SEQA_GDAT;
118 } while ((data & (1UL << 31)) == 0);
121 adc_reg->SEQA_CTRL &= ~(1UL << 31);
123 return ((data >> 4) & ADC_RANGE);
126 static inline void order(uint32_t *a, uint32_t *b) {
134 static inline uint32_t adc_read_u32(analogin_t *obj) {
136 #if ANALOGIN_MEDIAN_FILTER
137 uint32_t v1 = adc_read(obj);
138 uint32_t v2 = adc_read(obj);
139 uint32_t v3 = adc_read(obj);
145 value = adc_read(obj);
150 uint16_t analogin_read_u16(analogin_t *obj) {
151 uint32_t value = adc_read_u32(obj);
152 return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
155 float analogin_read(analogin_t *obj) {
156 uint32_t value = adc_read_u32(obj);
157 return (float)value * (1.0f / (float)ADC_RANGE);