1 /* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
16 #include "mbed_assert.h"
21 #include "mbed_error.h"
23 static const PinMap PinMap_SPI_SCLK[] = {
25 // {P0_10, SPI_0, 0x02}, -- should be mapped to SWCLK only
31 static const PinMap PinMap_SPI_MOSI[] = {
37 static const PinMap PinMap_SPI_MISO[] = {
43 static const PinMap PinMap_SPI_SSEL[] = {
49 static inline int ssp_disable(spi_t *obj);
50 static inline int ssp_enable(spi_t *obj);
52 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
53 // determine the SPI to use
54 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
55 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
56 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
57 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
58 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
59 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
61 obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
62 MBED_ASSERT((int)obj->spi != NC);
64 // enable power and clocking
65 switch ((int)obj->spi) {
67 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
68 LPC_SYSCON->SSP0CLKDIV = 0x01;
69 LPC_SYSCON->PRESETCTRL |= 1 << 0;
71 LPC_IOCON->SCK_LOC = 0x02;
74 LPC_IOCON->SCK_LOC = 0x01;
78 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
79 LPC_SYSCON->SSP1CLKDIV = 0x01;
80 LPC_SYSCON->PRESETCTRL |= 1 << 2;
81 LPC_IOCON->SCK1_LOC = 0x00;
82 LPC_IOCON->MISO1_LOC = 0x00;
83 LPC_IOCON->MOSI1_LOC = 0x00;
85 LPC_IOCON->SSEL1_LOC = 0x00;
90 // set default format and frequency
92 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
94 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
96 spi_frequency(obj, 1000000);
98 // enable the ssp channel
101 // pin out the spi pins
102 pinmap_pinout(mosi, PinMap_SPI_MOSI);
103 pinmap_pinout(miso, PinMap_SPI_MISO);
104 pinmap_pinout(sclk, PinMap_SPI_SCLK);
106 pinmap_pinout(ssel, PinMap_SPI_SSEL);
110 void spi_free(spi_t *obj) {}
112 void spi_format(spi_t *obj, int bits, int mode, int slave) {
113 MBED_ASSERT((bits >= 4 && bits <= 16) || (mode >= 0 && mode <= 3));
116 int polarity = (mode & 0x2) ? 1 : 0;
117 int phase = (mode & 0x1) ? 1 : 0;
120 int DSS = bits - 1; // DSS (data select size)
121 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
122 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
124 int FRF = 0; // FRF (frame format) = SPI
125 uint32_t tmp = obj->spi->CR0;
135 tmp |= 0 << 0 // LBM - loop back mode - off
136 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
137 | 0 << 3; // SOD - slave output disable - na
143 void spi_frequency(spi_t *obj, int hz) {
146 uint32_t PCLK = SystemCoreClock;
150 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
151 int prescale_hz = PCLK / prescaler;
153 // calculate the divider
154 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
156 // check we can support the divider
159 obj->spi->CPSR = prescaler;
162 obj->spi->CR0 &= ~(0xFFFF << 8);
163 obj->spi->CR0 |= (divider - 1) << 8;
168 error("Couldn't setup requested SPI frequency");
171 static inline int ssp_disable(spi_t *obj) {
172 return obj->spi->CR1 &= ~(1 << 1);
175 static inline int ssp_enable(spi_t *obj) {
176 return obj->spi->CR1 |= (1 << 1);
179 static inline int ssp_readable(spi_t *obj) {
180 return obj->spi->SR & (1 << 2);
183 static inline int ssp_writeable(spi_t *obj) {
184 return obj->spi->SR & (1 << 1);
187 static inline void ssp_write(spi_t *obj, int value) {
188 while (!ssp_writeable(obj));
189 obj->spi->DR = value;
192 static inline int ssp_read(spi_t *obj) {
193 while (!ssp_readable(obj));
197 static inline int ssp_busy(spi_t *obj) {
198 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
201 int spi_master_write(spi_t *obj, int value) {
202 ssp_write(obj, value);
203 return ssp_read(obj);
206 int spi_slave_receive(spi_t *obj) {
207 return ssp_readable(obj) ? (1) : (0);
210 int spi_slave_read(spi_t *obj) {
211 return obj->spi->DR & 0xFFFF;
214 void spi_slave_write(spi_t *obj, int value) {
215 while (ssp_writeable(obj) == 0) ;
216 obj->spi->DR = value;
219 int spi_busy(spi_t *obj) {
220 return ssp_busy(obj);