1 /* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
18 #include "gpio_irq_api.h"
19 #include "mbed_error.h"
22 // The chip is capable of 42 GPIO interrupts.
23 // PIO0_0..PIO0_11, PIO1_0..PIO1_11, PIO2_0..PIO2_11, PIO3_0..PIO3_5
24 #define CHANNEL_NUM 42
26 static uint32_t channel_ids[CHANNEL_NUM] = {0};
27 static gpio_irq_handler irq_handler;
29 static inline int numofbits(uint32_t bits)
31 // Count number of bits
32 bits = (bits & 0x55555555) + (bits >> 1 & 0x55555555);
33 bits = (bits & 0x33333333) + (bits >> 2 & 0x33333333);
34 bits = (bits & 0x0f0f0f0f) + (bits >> 4 & 0x0f0f0f0f);
35 bits = (bits & 0x00ff00ff) + (bits >> 8 & 0x00ff00ff);
36 return (bits & 0x0000ffff) + (bits >>16 & 0x0000ffff);
39 static inline void handle_interrupt_in(uint32_t port) {
40 // Find out whether the interrupt has been triggered by a high or low value...
41 // As the LPC1114 doesn't have a specific register for this, we'll just have to read
42 // the level of the pin as if it were just a normal input...
46 // Get the number of the pin being used and the port typedef
47 LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (port * 0x10000)));
49 // Get index of function table from Mask Interrupt Status register
50 channel = numofbits(port_reg->MIS - 1) + (port * 12);
52 if (port_reg->MIS & port_reg->IBE) {
53 // both edge, read the level of pin
54 if ((port_reg->DATA & port_reg->MIS) != 0)
55 irq_handler(channel_ids[channel], IRQ_RISE);
57 irq_handler(channel_ids[channel], IRQ_FALL);
59 else if (port_reg->MIS & port_reg->IEV) {
60 irq_handler(channel_ids[channel], IRQ_RISE);
63 irq_handler(channel_ids[channel], IRQ_FALL);
66 // Clear the interrupt...
67 port_reg->IC = port_reg->MIS;
70 void gpio_irq0(void) {handle_interrupt_in(0);}
71 void gpio_irq1(void) {handle_interrupt_in(1);}
72 void gpio_irq2(void) {handle_interrupt_in(2);}
73 void gpio_irq3(void) {handle_interrupt_in(3);}
75 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
79 if (pin == NC) return -1;
81 // Firstly, we'll put some data in *obj so we can keep track of stuff.
84 // Set the handler to be the pointer at the top...
85 irq_handler = handler;
87 // Which port are we using?
88 port_num = ((pin & 0xF000) >> PORT_SHIFT);
92 NVIC_SetVector(EINT0_IRQn, (uint32_t)gpio_irq0);
93 NVIC_EnableIRQ(EINT0_IRQn);
96 NVIC_SetVector(EINT1_IRQn, (uint32_t)gpio_irq1);
97 NVIC_EnableIRQ(EINT1_IRQn);
100 NVIC_SetVector(EINT2_IRQn, (uint32_t)gpio_irq2);
101 NVIC_EnableIRQ(EINT2_IRQn);
104 NVIC_SetVector(EINT3_IRQn, (uint32_t)gpio_irq3);
105 NVIC_EnableIRQ(EINT3_IRQn);
111 // Generate index of function pointer table
112 // PIO0_0 - PIO0_11 : 0..11
113 // PIO1_0 - PIO1_11 : 12..23
114 // PIO2_0 - PIO2_11 : 24..35
115 // PIO3_0 - PIO3_5 : 36..41
116 channel = (port_num * 12) + ((pin & 0x0F00) >> PIN_SHIFT);
118 channel_ids[channel] = id;
124 void gpio_irq_free(gpio_irq_t *obj) {
125 channel_ids[obj->ch] = 0;
128 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
129 // Firstly, check if there is an existing event stored...
131 LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (((obj->pin & 0xF000) >> PORT_SHIFT) * 0x10000)));
133 // Need to get the pin number of the pin, not the value of the enum
134 uint32_t pin_num = (1 << ((obj->pin & 0x0f00) >> PIN_SHIFT));
137 port_reg->IC |= pin_num;
139 // Make it edge sensitive.
140 port_reg->IS &= ~pin_num;
142 if ( (port_reg->IE & pin_num) != 0) {
144 // Enable both edge interrupts.
147 port_reg->IBE |= pin_num;
148 port_reg->IE |= pin_num;
151 // These all need to be opposite, to reenable the other one.
152 port_reg->IBE &= ~pin_num;
154 if (event == IRQ_RISE)
155 port_reg->IEV &= ~pin_num;
157 port_reg->IEV |= pin_num;
159 port_reg->IE |= pin_num;
164 port_reg->IBE &= ~pin_num;
166 if (event == IRQ_RISE)
167 port_reg->IEV |= pin_num;
169 port_reg->IEV &= ~pin_num;
172 port_reg->IE |= pin_num;
178 void gpio_irq_enable(gpio_irq_t *obj) {
179 uint32_t port_num = ((obj->pin & 0xF000) >> PORT_SHIFT);
182 NVIC_EnableIRQ(EINT0_IRQn);
185 NVIC_EnableIRQ(EINT1_IRQn);
188 NVIC_EnableIRQ(EINT2_IRQn);
191 NVIC_EnableIRQ(EINT3_IRQn);
198 void gpio_irq_disable(gpio_irq_t *obj) {
199 uint32_t port_num = ((obj->pin & 0xF000) >> PORT_SHIFT);
202 NVIC_DisableIRQ(EINT0_IRQn);
205 NVIC_DisableIRQ(EINT1_IRQn);
208 NVIC_DisableIRQ(EINT2_IRQn);
211 NVIC_DisableIRQ(EINT3_IRQn);