1 /* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
20 #define SPIM1_SCK_PIN 11u /**< SPI clock GPIO pin number. */
21 #define SPIM1_MOSI_PIN 15u /**< SPI Master Out Slave In GPIO pin number. */
22 #define SPIM1_MISO_PIN 9u /**< SPI Master In Slave Out GPIO pin number. */
23 #define SPIM1_SS_PIN 28u /**< SPI Slave Select GPIO pin number. */
25 #define CMD_POWER_UP (0xAB)
26 #define CMD_POWER_DOWN (0xB9)
28 void spi_flash_init(void)
30 NRF_GPIO->PIN_CNF[SPIM1_MOSI_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
31 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
32 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
33 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
34 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
35 NRF_GPIO->PIN_CNF[SPIM1_MISO_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
36 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
37 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
38 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
39 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
40 NRF_GPIO->PIN_CNF[SPIM1_SCK_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
41 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
42 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
43 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
44 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
46 NRF_GPIO->PIN_CNF[SPIM1_SS_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
47 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
48 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
49 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
50 | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
52 NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
55 NRF_SPI1->PSELSCK = SPIM1_SCK_PIN;
56 NRF_SPI1->PSELMOSI = SPIM1_MISO_PIN;
57 NRF_SPI1->PSELMISO = SPIM1_MOSI_PIN;
58 //spi.frequency(1000000);
59 NRF_SPI1->FREQUENCY = 0x10000000; //1MHz
62 uint32_t config_mode = 0;
63 config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos); //mode 0
64 NRF_SPI1->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
66 NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos);
67 //spi.write(CMD_POWER_UP);
68 while (!NRF_SPI1->EVENTS_READY == 0) {
70 NRF_SPI1->TXD = (uint32_t)CMD_POWER_UP;
71 while (!NRF_SPI1->EVENTS_READY == 1) {
73 NRF_SPI1->EVENTS_READY = 0;
76 // Deselect the device
78 NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
82 void spi_flash_powerDown(void)
84 NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos);
85 //spi.write(CMD_POWER_DOWN);
86 while (!NRF_SPI1->EVENTS_READY == 0) {
88 NRF_SPI1->TXD = (uint32_t)CMD_POWER_DOWN;
89 while (!NRF_SPI1->EVENTS_READY == 1) {
91 NRF_SPI1->EVENTS_READY = 0;
93 NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
101 // Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path
102 NRF_GPIO->PIN_CNF[19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
103 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
104 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
105 | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
106 | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
108 NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos);
110 // Config External Crystal to 32MHz
111 NRF_CLOCK->XTALFREQ = 0x00;
112 NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
113 NRF_CLOCK->TASKS_HFCLKSTART = 1;
114 while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0)
121 spi_flash_powerDown();