2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_UART_REGISTERS_H__
81 #define __HW_UART_REGISTERS_H__
84 #include "fsl_bitaccess.h"
89 * Serial Communication Interface
91 * Registers defined in this header file:
92 * - HW_UART_BDH - UART Baud Rate Registers: High
93 * - HW_UART_BDL - UART Baud Rate Registers: Low
94 * - HW_UART_C1 - UART Control Register 1
95 * - HW_UART_C2 - UART Control Register 2
96 * - HW_UART_S1 - UART Status Register 1
97 * - HW_UART_S2 - UART Status Register 2
98 * - HW_UART_C3 - UART Control Register 3
99 * - HW_UART_D - UART Data Register
100 * - HW_UART_MA1 - UART Match Address Registers 1
101 * - HW_UART_MA2 - UART Match Address Registers 2
102 * - HW_UART_C4 - UART Control Register 4
103 * - HW_UART_C5 - UART Control Register 5
104 * - HW_UART_ED - UART Extended Data Register
105 * - HW_UART_MODEM - UART Modem Register
106 * - HW_UART_IR - UART Infrared Register
107 * - HW_UART_PFIFO - UART FIFO Parameters
108 * - HW_UART_CFIFO - UART FIFO Control Register
109 * - HW_UART_SFIFO - UART FIFO Status Register
110 * - HW_UART_TWFIFO - UART FIFO Transmit Watermark
111 * - HW_UART_TCFIFO - UART FIFO Transmit Count
112 * - HW_UART_RWFIFO - UART FIFO Receive Watermark
113 * - HW_UART_RCFIFO - UART FIFO Receive Count
114 * - HW_UART_C7816 - UART 7816 Control Register
115 * - HW_UART_IE7816 - UART 7816 Interrupt Enable Register
116 * - HW_UART_IS7816 - UART 7816 Interrupt Status Register
117 * - HW_UART_WP7816T0 - UART 7816 Wait Parameter Register
118 * - HW_UART_WP7816T1 - UART 7816 Wait Parameter Register
119 * - HW_UART_WN7816 - UART 7816 Wait N Register
120 * - HW_UART_WF7816 - UART 7816 Wait FD Register
121 * - HW_UART_ET7816 - UART 7816 Error Threshold Register
122 * - HW_UART_TL7816 - UART 7816 Transmit Length Register
124 * - hw_uart_t - Struct containing all module registers.
127 #define HW_UART_INSTANCE_COUNT (6U) /*!< Number of instances of the UART module. */
128 #define HW_UART0 (0U) /*!< Instance number for UART0. */
129 #define HW_UART1 (1U) /*!< Instance number for UART1. */
130 #define HW_UART2 (2U) /*!< Instance number for UART2. */
131 #define HW_UART3 (3U) /*!< Instance number for UART3. */
132 #define HW_UART4 (4U) /*!< Instance number for UART4. */
133 #define HW_UART5 (5U) /*!< Instance number for UART5. */
135 /*******************************************************************************
136 * HW_UART_BDH - UART Baud Rate Registers: High
137 ******************************************************************************/
140 * @brief HW_UART_BDH - UART Baud Rate Registers: High (RW)
144 * This register, along with the BDL register, controls the prescale divisor for
145 * UART baud rate generation. To update the 13-bit baud rate setting
146 * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
147 * to BDL. The working value in BDH does not change until BDL is written. BDL is
148 * reset to a nonzero value, but after reset, the baud rate generator remains
149 * disabled until the first time the receiver or transmitter is enabled, that is,
150 * when C2[RE] or C2[TE] is set.
152 typedef union _hw_uart_bdh
155 struct _hw_uart_bdh_bitfields
157 uint8_t SBR : 5; /*!< [4:0] UART Baud Rate Bits */
158 uint8_t SBNS : 1; /*!< [5] Stop Bit Number Select */
159 uint8_t RXEDGIE : 1; /*!< [6] RxD Input Active Edge Interrupt Enable
161 uint8_t LBKDIE : 1; /*!< [7] LIN Break Detect Interrupt or DMA
167 * @name Constants and macros for entire UART_BDH register
170 #define HW_UART_BDH_ADDR(x) ((x) + 0x0U)
172 #define HW_UART_BDH(x) (*(__IO hw_uart_bdh_t *) HW_UART_BDH_ADDR(x))
173 #define HW_UART_BDH_RD(x) (HW_UART_BDH(x).U)
174 #define HW_UART_BDH_WR(x, v) (HW_UART_BDH(x).U = (v))
175 #define HW_UART_BDH_SET(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) | (v)))
176 #define HW_UART_BDH_CLR(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) & ~(v)))
177 #define HW_UART_BDH_TOG(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) ^ (v)))
181 * Constants & macros for individual UART_BDH bitfields
185 * @name Register UART_BDH, field SBR[4:0] (RW)
187 * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
188 * generation for details. The baud rate generator is disabled until C2[TE] or
189 * C2[RE] is set for the first time after reset.The baud rate generator is disabled
190 * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
191 * writing to BDH puts the data in a temporary location until BDL is written.
194 #define BP_UART_BDH_SBR (0U) /*!< Bit position for UART_BDH_SBR. */
195 #define BM_UART_BDH_SBR (0x1FU) /*!< Bit mask for UART_BDH_SBR. */
196 #define BS_UART_BDH_SBR (5U) /*!< Bit field size in bits for UART_BDH_SBR. */
198 /*! @brief Read current value of the UART_BDH_SBR field. */
199 #define BR_UART_BDH_SBR(x) (HW_UART_BDH(x).B.SBR)
201 /*! @brief Format value for bitfield UART_BDH_SBR. */
202 #define BF_UART_BDH_SBR(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_SBR) & BM_UART_BDH_SBR)
204 /*! @brief Set the SBR field to a new value. */
205 #define BW_UART_BDH_SBR(x, v) (HW_UART_BDH_WR(x, (HW_UART_BDH_RD(x) & ~BM_UART_BDH_SBR) | BF_UART_BDH_SBR(v)))
209 * @name Register UART_BDH, field SBNS[5] (RW)
211 * SBNS selects the number of stop bits present in a data frame. This field
212 * valid for all 8, 9 and 10 bit data formats available. This field is not valid when
213 * C7816[ISO7816E] is enabled.
216 * - 0 - Data frame consists of a single stop bit.
217 * - 1 - Data frame consists of two stop bits.
220 #define BP_UART_BDH_SBNS (5U) /*!< Bit position for UART_BDH_SBNS. */
221 #define BM_UART_BDH_SBNS (0x20U) /*!< Bit mask for UART_BDH_SBNS. */
222 #define BS_UART_BDH_SBNS (1U) /*!< Bit field size in bits for UART_BDH_SBNS. */
224 /*! @brief Read current value of the UART_BDH_SBNS field. */
225 #define BR_UART_BDH_SBNS(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS))
227 /*! @brief Format value for bitfield UART_BDH_SBNS. */
228 #define BF_UART_BDH_SBNS(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_SBNS) & BM_UART_BDH_SBNS)
230 /*! @brief Set the SBNS field to a new value. */
231 #define BW_UART_BDH_SBNS(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS) = (v))
235 * @name Register UART_BDH, field RXEDGIE[6] (RW)
237 * Enables the receive input active edge, RXEDGIF, to generate interrupt
241 * - 0 - Hardware interrupts from RXEDGIF disabled using polling.
242 * - 1 - RXEDGIF interrupt request enabled.
245 #define BP_UART_BDH_RXEDGIE (6U) /*!< Bit position for UART_BDH_RXEDGIE. */
246 #define BM_UART_BDH_RXEDGIE (0x40U) /*!< Bit mask for UART_BDH_RXEDGIE. */
247 #define BS_UART_BDH_RXEDGIE (1U) /*!< Bit field size in bits for UART_BDH_RXEDGIE. */
249 /*! @brief Read current value of the UART_BDH_RXEDGIE field. */
250 #define BR_UART_BDH_RXEDGIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE))
252 /*! @brief Format value for bitfield UART_BDH_RXEDGIE. */
253 #define BF_UART_BDH_RXEDGIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_RXEDGIE) & BM_UART_BDH_RXEDGIE)
255 /*! @brief Set the RXEDGIE field to a new value. */
256 #define BW_UART_BDH_RXEDGIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE) = (v))
260 * @name Register UART_BDH, field LBKDIE[7] (RW)
262 * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests
263 * based on the state of LBKDDMAS. or DMA transfer requests,
266 * - 0 - LBKDIF interrupt and DMA transfer requests disabled.
267 * - 1 - LBKDIF interrupt or DMA transfer requests enabled.
270 #define BP_UART_BDH_LBKDIE (7U) /*!< Bit position for UART_BDH_LBKDIE. */
271 #define BM_UART_BDH_LBKDIE (0x80U) /*!< Bit mask for UART_BDH_LBKDIE. */
272 #define BS_UART_BDH_LBKDIE (1U) /*!< Bit field size in bits for UART_BDH_LBKDIE. */
274 /*! @brief Read current value of the UART_BDH_LBKDIE field. */
275 #define BR_UART_BDH_LBKDIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE))
277 /*! @brief Format value for bitfield UART_BDH_LBKDIE. */
278 #define BF_UART_BDH_LBKDIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_LBKDIE) & BM_UART_BDH_LBKDIE)
280 /*! @brief Set the LBKDIE field to a new value. */
281 #define BW_UART_BDH_LBKDIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE) = (v))
284 /*******************************************************************************
285 * HW_UART_BDL - UART Baud Rate Registers: Low
286 ******************************************************************************/
289 * @brief HW_UART_BDL - UART Baud Rate Registers: Low (RW)
293 * This register, along with the BDH register, controls the prescale divisor for
294 * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
295 * first write to BDH to buffer the high half of the new value and then write to
296 * BDL. The working value in BDH does not change until BDL is written. BDL is
297 * reset to a nonzero value, but after reset, the baud rate generator remains
298 * disabled until the first time the receiver or transmitter is enabled, that is, when
299 * C2[RE] or C2[TE] is set.
301 typedef union _hw_uart_bdl
304 struct _hw_uart_bdl_bitfields
306 uint8_t SBR : 8; /*!< [7:0] UART Baud Rate Bits */
311 * @name Constants and macros for entire UART_BDL register
314 #define HW_UART_BDL_ADDR(x) ((x) + 0x1U)
316 #define HW_UART_BDL(x) (*(__IO hw_uart_bdl_t *) HW_UART_BDL_ADDR(x))
317 #define HW_UART_BDL_RD(x) (HW_UART_BDL(x).U)
318 #define HW_UART_BDL_WR(x, v) (HW_UART_BDL(x).U = (v))
319 #define HW_UART_BDL_SET(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) | (v)))
320 #define HW_UART_BDL_CLR(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) & ~(v)))
321 #define HW_UART_BDL_TOG(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) ^ (v)))
325 * Constants & macros for individual UART_BDL bitfields
329 * @name Register UART_BDL, field SBR[7:0] (RW)
331 * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
332 * generation for details. The baud rate generator is disabled until C2[TE] or
333 * C2[RE] is set for the first time after reset.The baud rate generator is disabled
334 * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
335 * writing to BDH puts the data in a temporary location until BDL is written. When
336 * the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate
337 * fields must be even, the least significant bit is 0. See MODEM register for more
341 #define BP_UART_BDL_SBR (0U) /*!< Bit position for UART_BDL_SBR. */
342 #define BM_UART_BDL_SBR (0xFFU) /*!< Bit mask for UART_BDL_SBR. */
343 #define BS_UART_BDL_SBR (8U) /*!< Bit field size in bits for UART_BDL_SBR. */
345 /*! @brief Read current value of the UART_BDL_SBR field. */
346 #define BR_UART_BDL_SBR(x) (HW_UART_BDL(x).U)
348 /*! @brief Format value for bitfield UART_BDL_SBR. */
349 #define BF_UART_BDL_SBR(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDL_SBR) & BM_UART_BDL_SBR)
351 /*! @brief Set the SBR field to a new value. */
352 #define BW_UART_BDL_SBR(x, v) (HW_UART_BDL_WR(x, v))
355 /*******************************************************************************
356 * HW_UART_C1 - UART Control Register 1
357 ******************************************************************************/
360 * @brief HW_UART_C1 - UART Control Register 1 (RW)
364 * This read/write register controls various optional features of the UART
367 typedef union _hw_uart_c1
370 struct _hw_uart_c1_bitfields
372 uint8_t PT : 1; /*!< [0] Parity Type */
373 uint8_t PE : 1; /*!< [1] Parity Enable */
374 uint8_t ILT : 1; /*!< [2] Idle Line Type Select */
375 uint8_t WAKE : 1; /*!< [3] Receiver Wakeup Method Select */
376 uint8_t M : 1; /*!< [4] 9-bit or 8-bit Mode Select */
377 uint8_t RSRC : 1; /*!< [5] Receiver Source Select */
378 uint8_t UARTSWAI : 1; /*!< [6] UART Stops in Wait Mode */
379 uint8_t LOOPS : 1; /*!< [7] Loop Mode Select */
384 * @name Constants and macros for entire UART_C1 register
387 #define HW_UART_C1_ADDR(x) ((x) + 0x2U)
389 #define HW_UART_C1(x) (*(__IO hw_uart_c1_t *) HW_UART_C1_ADDR(x))
390 #define HW_UART_C1_RD(x) (HW_UART_C1(x).U)
391 #define HW_UART_C1_WR(x, v) (HW_UART_C1(x).U = (v))
392 #define HW_UART_C1_SET(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) | (v)))
393 #define HW_UART_C1_CLR(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) & ~(v)))
394 #define HW_UART_C1_TOG(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) ^ (v)))
398 * Constants & macros for individual UART_C1 bitfields
402 * @name Register UART_C1, field PT[0] (RW)
404 * Determines whether the UART generates and checks for even parity or odd
405 * parity. With even parity, an even number of 1s clears the parity bit and an odd
406 * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
407 * parity bit and an even number of 1s sets the parity bit. This field must be
408 * cleared when C7816[ISO_7816E] is set/enabled.
415 #define BP_UART_C1_PT (0U) /*!< Bit position for UART_C1_PT. */
416 #define BM_UART_C1_PT (0x01U) /*!< Bit mask for UART_C1_PT. */
417 #define BS_UART_C1_PT (1U) /*!< Bit field size in bits for UART_C1_PT. */
419 /*! @brief Read current value of the UART_C1_PT field. */
420 #define BR_UART_C1_PT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT))
422 /*! @brief Format value for bitfield UART_C1_PT. */
423 #define BF_UART_C1_PT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_PT) & BM_UART_C1_PT)
425 /*! @brief Set the PT field to a new value. */
426 #define BW_UART_C1_PT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT) = (v))
430 * @name Register UART_C1, field PE[1] (RW)
432 * Enables the parity function. When parity is enabled, parity function inserts
433 * a parity bit in the bit position immediately preceding the stop bit. This
434 * field must be set when C7816[ISO_7816E] is set/enabled.
437 * - 0 - Parity function disabled.
438 * - 1 - Parity function enabled.
441 #define BP_UART_C1_PE (1U) /*!< Bit position for UART_C1_PE. */
442 #define BM_UART_C1_PE (0x02U) /*!< Bit mask for UART_C1_PE. */
443 #define BS_UART_C1_PE (1U) /*!< Bit field size in bits for UART_C1_PE. */
445 /*! @brief Read current value of the UART_C1_PE field. */
446 #define BR_UART_C1_PE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE))
448 /*! @brief Format value for bitfield UART_C1_PE. */
449 #define BF_UART_C1_PE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_PE) & BM_UART_C1_PE)
451 /*! @brief Set the PE field to a new value. */
452 #define BW_UART_C1_PE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE) = (v))
456 * @name Register UART_C1, field ILT[2] (RW)
458 * Determines when the receiver starts counting logic 1s as idle character bits.
459 * The count begins either after a valid start bit or after the stop bit. If the
460 * count begins after the start bit, then a string of logic 1s preceding the
461 * stop bit can cause false recognition of an idle character. Beginning the count
462 * after the stop bit avoids false idle character recognition, but requires
463 * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
464 * logic of 1'b0 is automatically shifted after a received stop bit, therefore
465 * resetting the idle count. In case the UART is programmed for IDLE line wakeup
466 * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
467 * logic 1s as idle character bits. In idle line wakeup, an idle character is
468 * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
469 * and C4[M10] fields.
472 * - 0 - Idle character bit count starts after start bit.
473 * - 1 - Idle character bit count starts after stop bit.
476 #define BP_UART_C1_ILT (2U) /*!< Bit position for UART_C1_ILT. */
477 #define BM_UART_C1_ILT (0x04U) /*!< Bit mask for UART_C1_ILT. */
478 #define BS_UART_C1_ILT (1U) /*!< Bit field size in bits for UART_C1_ILT. */
480 /*! @brief Read current value of the UART_C1_ILT field. */
481 #define BR_UART_C1_ILT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT))
483 /*! @brief Format value for bitfield UART_C1_ILT. */
484 #define BF_UART_C1_ILT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_ILT) & BM_UART_C1_ILT)
486 /*! @brief Set the ILT field to a new value. */
487 #define BW_UART_C1_ILT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT) = (v))
491 * @name Register UART_C1, field WAKE[3] (RW)
493 * Determines which condition wakes the UART: Address mark in the most
494 * significant bit position of a received data character, or An idle condition on the
495 * receive pin input signal.
498 * - 0 - Idle line wakeup.
499 * - 1 - Address mark wakeup.
502 #define BP_UART_C1_WAKE (3U) /*!< Bit position for UART_C1_WAKE. */
503 #define BM_UART_C1_WAKE (0x08U) /*!< Bit mask for UART_C1_WAKE. */
504 #define BS_UART_C1_WAKE (1U) /*!< Bit field size in bits for UART_C1_WAKE. */
506 /*! @brief Read current value of the UART_C1_WAKE field. */
507 #define BR_UART_C1_WAKE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE))
509 /*! @brief Format value for bitfield UART_C1_WAKE. */
510 #define BF_UART_C1_WAKE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_WAKE) & BM_UART_C1_WAKE)
512 /*! @brief Set the WAKE field to a new value. */
513 #define BW_UART_C1_WAKE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE) = (v))
517 * @name Register UART_C1, field M[4] (RW)
519 * This field must be set when C7816[ISO_7816E] is set/enabled.
522 * - 0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
523 * - 1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
526 #define BP_UART_C1_M (4U) /*!< Bit position for UART_C1_M. */
527 #define BM_UART_C1_M (0x10U) /*!< Bit mask for UART_C1_M. */
528 #define BS_UART_C1_M (1U) /*!< Bit field size in bits for UART_C1_M. */
530 /*! @brief Read current value of the UART_C1_M field. */
531 #define BR_UART_C1_M(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M))
533 /*! @brief Format value for bitfield UART_C1_M. */
534 #define BF_UART_C1_M(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_M) & BM_UART_C1_M)
536 /*! @brief Set the M field to a new value. */
537 #define BW_UART_C1_M(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M) = (v))
541 * @name Register UART_C1, field RSRC[5] (RW)
543 * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
544 * is set, the RSRC field determines the source for the receiver shift register
548 * - 0 - Selects internal loop back mode. The receiver input is internally
549 * connected to transmitter output.
550 * - 1 - Single wire UART mode where the receiver input is connected to the
551 * transmit pin input signal.
554 #define BP_UART_C1_RSRC (5U) /*!< Bit position for UART_C1_RSRC. */
555 #define BM_UART_C1_RSRC (0x20U) /*!< Bit mask for UART_C1_RSRC. */
556 #define BS_UART_C1_RSRC (1U) /*!< Bit field size in bits for UART_C1_RSRC. */
558 /*! @brief Read current value of the UART_C1_RSRC field. */
559 #define BR_UART_C1_RSRC(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC))
561 /*! @brief Format value for bitfield UART_C1_RSRC. */
562 #define BF_UART_C1_RSRC(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_RSRC) & BM_UART_C1_RSRC)
564 /*! @brief Set the RSRC field to a new value. */
565 #define BW_UART_C1_RSRC(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC) = (v))
569 * @name Register UART_C1, field UARTSWAI[6] (RW)
572 * - 0 - UART clock continues to run in Wait mode.
573 * - 1 - UART clock freezes while CPU is in Wait mode.
576 #define BP_UART_C1_UARTSWAI (6U) /*!< Bit position for UART_C1_UARTSWAI. */
577 #define BM_UART_C1_UARTSWAI (0x40U) /*!< Bit mask for UART_C1_UARTSWAI. */
578 #define BS_UART_C1_UARTSWAI (1U) /*!< Bit field size in bits for UART_C1_UARTSWAI. */
580 /*! @brief Read current value of the UART_C1_UARTSWAI field. */
581 #define BR_UART_C1_UARTSWAI(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI))
583 /*! @brief Format value for bitfield UART_C1_UARTSWAI. */
584 #define BF_UART_C1_UARTSWAI(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_UARTSWAI) & BM_UART_C1_UARTSWAI)
586 /*! @brief Set the UARTSWAI field to a new value. */
587 #define BW_UART_C1_UARTSWAI(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI) = (v))
591 * @name Register UART_C1, field LOOPS[7] (RW)
593 * When LOOPS is set, the RxD pin is disconnected from the UART and the
594 * transmitter output is internally connected to the receiver input. The transmitter and
595 * the receiver must be enabled to use the loop function.
598 * - 0 - Normal operation.
599 * - 1 - Loop mode where transmitter output is internally connected to receiver
600 * input. The receiver input is determined by RSRC.
603 #define BP_UART_C1_LOOPS (7U) /*!< Bit position for UART_C1_LOOPS. */
604 #define BM_UART_C1_LOOPS (0x80U) /*!< Bit mask for UART_C1_LOOPS. */
605 #define BS_UART_C1_LOOPS (1U) /*!< Bit field size in bits for UART_C1_LOOPS. */
607 /*! @brief Read current value of the UART_C1_LOOPS field. */
608 #define BR_UART_C1_LOOPS(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS))
610 /*! @brief Format value for bitfield UART_C1_LOOPS. */
611 #define BF_UART_C1_LOOPS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_LOOPS) & BM_UART_C1_LOOPS)
613 /*! @brief Set the LOOPS field to a new value. */
614 #define BW_UART_C1_LOOPS(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS) = (v))
617 /*******************************************************************************
618 * HW_UART_C2 - UART Control Register 2
619 ******************************************************************************/
622 * @brief HW_UART_C2 - UART Control Register 2 (RW)
626 * This register can be read or written at any time.
628 typedef union _hw_uart_c2
631 struct _hw_uart_c2_bitfields
633 uint8_t SBK : 1; /*!< [0] Send Break */
634 uint8_t RWU : 1; /*!< [1] Receiver Wakeup Control */
635 uint8_t RE : 1; /*!< [2] Receiver Enable */
636 uint8_t TE : 1; /*!< [3] Transmitter Enable */
637 uint8_t ILIE : 1; /*!< [4] Idle Line Interrupt DMA Transfer Enable */
638 uint8_t RIE : 1; /*!< [5] Receiver Full Interrupt or DMA Transfer
640 uint8_t TCIE : 1; /*!< [6] Transmission Complete Interrupt or DMA
642 uint8_t TIE : 1; /*!< [7] Transmitter Interrupt or DMA Transfer
648 * @name Constants and macros for entire UART_C2 register
651 #define HW_UART_C2_ADDR(x) ((x) + 0x3U)
653 #define HW_UART_C2(x) (*(__IO hw_uart_c2_t *) HW_UART_C2_ADDR(x))
654 #define HW_UART_C2_RD(x) (HW_UART_C2(x).U)
655 #define HW_UART_C2_WR(x, v) (HW_UART_C2(x).U = (v))
656 #define HW_UART_C2_SET(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) | (v)))
657 #define HW_UART_C2_CLR(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) & ~(v)))
658 #define HW_UART_C2_TOG(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) ^ (v)))
662 * Constants & macros for individual UART_C2 bitfields
666 * @name Register UART_C2, field SBK[0] (RW)
668 * Toggling SBK sends one break character from the following: See Transmitting
669 * break characters for the number of logic 0s for the different configurations.
670 * Toggling implies clearing the SBK field before the break character has finished
671 * transmitting. As long as SBK is set, the transmitter continues to send
672 * complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits).
673 * Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit.
674 * 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13]
675 * is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when
676 * C7816[ISO_7816E] is set.
679 * - 0 - Normal transmitter operation.
680 * - 1 - Queue break characters to be sent.
683 #define BP_UART_C2_SBK (0U) /*!< Bit position for UART_C2_SBK. */
684 #define BM_UART_C2_SBK (0x01U) /*!< Bit mask for UART_C2_SBK. */
685 #define BS_UART_C2_SBK (1U) /*!< Bit field size in bits for UART_C2_SBK. */
687 /*! @brief Read current value of the UART_C2_SBK field. */
688 #define BR_UART_C2_SBK(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK))
690 /*! @brief Format value for bitfield UART_C2_SBK. */
691 #define BF_UART_C2_SBK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_SBK) & BM_UART_C2_SBK)
693 /*! @brief Set the SBK field to a new value. */
694 #define BW_UART_C2_SBK(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK) = (v))
698 * @name Register UART_C2, field RWU[1] (RW)
700 * This field can be set to place the UART receiver in a standby state. RWU
701 * automatically clears when an RWU event occurs, that is, an IDLE event when
702 * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
703 * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
704 * on idle) if the channel is currently not idle. This can be determined by
705 * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
706 * idle, it is possible that the UART will discard data. This is because the data
707 * must be received or a LIN break detected after an IDLE is detected before IDLE
708 * is allowed to reasserted.
711 * - 0 - Normal operation.
712 * - 1 - RWU enables the wakeup function and inhibits further receiver interrupt
713 * requests. Normally, hardware wakes the receiver by automatically clearing
717 #define BP_UART_C2_RWU (1U) /*!< Bit position for UART_C2_RWU. */
718 #define BM_UART_C2_RWU (0x02U) /*!< Bit mask for UART_C2_RWU. */
719 #define BS_UART_C2_RWU (1U) /*!< Bit field size in bits for UART_C2_RWU. */
721 /*! @brief Read current value of the UART_C2_RWU field. */
722 #define BR_UART_C2_RWU(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU))
724 /*! @brief Format value for bitfield UART_C2_RWU. */
725 #define BF_UART_C2_RWU(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RWU) & BM_UART_C2_RWU)
727 /*! @brief Set the RWU field to a new value. */
728 #define BW_UART_C2_RWU(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU) = (v))
732 * @name Register UART_C2, field RE[2] (RW)
734 * Enables the UART receiver.
737 * - 0 - Receiver off.
741 #define BP_UART_C2_RE (2U) /*!< Bit position for UART_C2_RE. */
742 #define BM_UART_C2_RE (0x04U) /*!< Bit mask for UART_C2_RE. */
743 #define BS_UART_C2_RE (1U) /*!< Bit field size in bits for UART_C2_RE. */
745 /*! @brief Read current value of the UART_C2_RE field. */
746 #define BR_UART_C2_RE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE))
748 /*! @brief Format value for bitfield UART_C2_RE. */
749 #define BF_UART_C2_RE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RE) & BM_UART_C2_RE)
751 /*! @brief Set the RE field to a new value. */
752 #define BW_UART_C2_RE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE) = (v))
756 * @name Register UART_C2, field TE[3] (RW)
758 * Enables the UART transmitter. TE can be used to queue an idle preamble by
759 * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
760 * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
761 * transmitted. This condition is detected when TL7816[TLEN] = 0 and four
762 * additional characters are transmitted.
765 * - 0 - Transmitter off.
766 * - 1 - Transmitter on.
769 #define BP_UART_C2_TE (3U) /*!< Bit position for UART_C2_TE. */
770 #define BM_UART_C2_TE (0x08U) /*!< Bit mask for UART_C2_TE. */
771 #define BS_UART_C2_TE (1U) /*!< Bit field size in bits for UART_C2_TE. */
773 /*! @brief Read current value of the UART_C2_TE field. */
774 #define BR_UART_C2_TE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE))
776 /*! @brief Format value for bitfield UART_C2_TE. */
777 #define BF_UART_C2_TE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TE) & BM_UART_C2_TE)
779 /*! @brief Set the TE field to a new value. */
780 #define BW_UART_C2_TE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE) = (v))
784 * @name Register UART_C2, field ILIE[4] (RW)
786 * Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA
787 * transfer requests based on the state of C5[ILDMAS].
790 * - 0 - IDLE interrupt requests disabled. and DMA transfer
791 * - 1 - IDLE interrupt requests enabled. or DMA transfer
794 #define BP_UART_C2_ILIE (4U) /*!< Bit position for UART_C2_ILIE. */
795 #define BM_UART_C2_ILIE (0x10U) /*!< Bit mask for UART_C2_ILIE. */
796 #define BS_UART_C2_ILIE (1U) /*!< Bit field size in bits for UART_C2_ILIE. */
798 /*! @brief Read current value of the UART_C2_ILIE field. */
799 #define BR_UART_C2_ILIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE))
801 /*! @brief Format value for bitfield UART_C2_ILIE. */
802 #define BF_UART_C2_ILIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_ILIE) & BM_UART_C2_ILIE)
804 /*! @brief Set the ILIE field to a new value. */
805 #define BW_UART_C2_ILIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE) = (v))
809 * @name Register UART_C2, field RIE[5] (RW)
811 * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
812 * based on the state of C5[RDMAS].
815 * - 0 - RDRF interrupt and DMA transfer requests disabled.
816 * - 1 - RDRF interrupt or DMA transfer requests enabled.
819 #define BP_UART_C2_RIE (5U) /*!< Bit position for UART_C2_RIE. */
820 #define BM_UART_C2_RIE (0x20U) /*!< Bit mask for UART_C2_RIE. */
821 #define BS_UART_C2_RIE (1U) /*!< Bit field size in bits for UART_C2_RIE. */
823 /*! @brief Read current value of the UART_C2_RIE field. */
824 #define BR_UART_C2_RIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE))
826 /*! @brief Format value for bitfield UART_C2_RIE. */
827 #define BF_UART_C2_RIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RIE) & BM_UART_C2_RIE)
829 /*! @brief Set the RIE field to a new value. */
830 #define BW_UART_C2_RIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE) = (v))
834 * @name Register UART_C2, field TCIE[6] (RW)
836 * Enables the transmission complete flag, S1[TC], to generate interrupt
837 * requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and
838 * C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be
839 * written unless servicing a DMA request.
842 * - 0 - TC interrupt and DMA transfer requests disabled.
843 * - 1 - TC interrupt or DMA transfer requests enabled.
846 #define BP_UART_C2_TCIE (6U) /*!< Bit position for UART_C2_TCIE. */
847 #define BM_UART_C2_TCIE (0x40U) /*!< Bit mask for UART_C2_TCIE. */
848 #define BS_UART_C2_TCIE (1U) /*!< Bit field size in bits for UART_C2_TCIE. */
850 /*! @brief Read current value of the UART_C2_TCIE field. */
851 #define BR_UART_C2_TCIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE))
853 /*! @brief Format value for bitfield UART_C2_TCIE. */
854 #define BF_UART_C2_TCIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TCIE) & BM_UART_C2_TCIE)
856 /*! @brief Set the TCIE field to a new value. */
857 #define BW_UART_C2_TCIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE) = (v))
861 * @name Register UART_C2, field TIE[7] (RW)
863 * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
864 * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
865 * must be cleared, and D[D] must not be written unless servicing a DMA request.
868 * - 0 - TDRE interrupt and DMA transfer requests disabled.
869 * - 1 - TDRE interrupt or DMA transfer requests enabled.
872 #define BP_UART_C2_TIE (7U) /*!< Bit position for UART_C2_TIE. */
873 #define BM_UART_C2_TIE (0x80U) /*!< Bit mask for UART_C2_TIE. */
874 #define BS_UART_C2_TIE (1U) /*!< Bit field size in bits for UART_C2_TIE. */
876 /*! @brief Read current value of the UART_C2_TIE field. */
877 #define BR_UART_C2_TIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE))
879 /*! @brief Format value for bitfield UART_C2_TIE. */
880 #define BF_UART_C2_TIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TIE) & BM_UART_C2_TIE)
882 /*! @brief Set the TIE field to a new value. */
883 #define BW_UART_C2_TIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE) = (v))
886 /*******************************************************************************
887 * HW_UART_S1 - UART Status Register 1
888 ******************************************************************************/
891 * @brief HW_UART_S1 - UART Status Register 1 (RO)
895 * The S1 register provides inputs to the MCU for generation of UART interrupts
896 * or DMA requests. This register can also be polled by the MCU to check the
897 * status of its fields. To clear a flag, the status register should be read followed
898 * by a read or write to D register, depending on the interrupt flag type. Other
899 * instructions can be executed between the two steps as long the handling of
900 * I/O is not compromised, but the order of operations is important for flag
901 * clearing. When a flag is configured to trigger a DMA request, assertion of the
902 * associated DMA done signal from the DMA controller clears the flag. If the
903 * condition that results in the assertion of the flag, interrupt, or DMA request is not
904 * resolved prior to clearing the flag, the flag, and interrupt/DMA request,
905 * reasserts. For example, if the DMA or interrupt service routine fails to write
906 * sufficient data to the transmit buffer to raise it above the watermark level, the
907 * flag reasserts and generates another interrupt or DMA request. Reading an
908 * empty data register to clear one of the flags of the S1 register causes the FIFO
909 * pointers to become misaligned. A receive FIFO flush reinitializes the
910 * pointers. A better way to prevent this situation is to always leave one byte in FIFO
911 * and this byte will be read eventually in clearing the flag bit.
913 typedef union _hw_uart_s1
916 struct _hw_uart_s1_bitfields
918 uint8_t PF : 1; /*!< [0] Parity Error Flag */
919 uint8_t FE : 1; /*!< [1] Framing Error Flag */
920 uint8_t NF : 1; /*!< [2] Noise Flag */
921 uint8_t OR : 1; /*!< [3] Receiver Overrun Flag */
922 uint8_t IDLE : 1; /*!< [4] Idle Line Flag */
923 uint8_t RDRF : 1; /*!< [5] Receive Data Register Full Flag */
924 uint8_t TC : 1; /*!< [6] Transmit Complete Flag */
925 uint8_t TDRE : 1; /*!< [7] Transmit Data Register Empty Flag */
930 * @name Constants and macros for entire UART_S1 register
933 #define HW_UART_S1_ADDR(x) ((x) + 0x4U)
935 #define HW_UART_S1(x) (*(__I hw_uart_s1_t *) HW_UART_S1_ADDR(x))
936 #define HW_UART_S1_RD(x) (HW_UART_S1(x).U)
940 * Constants & macros for individual UART_S1 bitfields
944 * @name Register UART_S1, field PF[0] (RO)
946 * PF is set when PE is set and the parity of the received data does not match
947 * its parity bit. The PF is not set in the case of an overrun condition. When PF
948 * is set, it indicates only that a dataword was received with parity error since
949 * the last time it was cleared. There is no guarantee that the first dataword
950 * read from the receive buffer has a parity error or that there is only one
951 * dataword in the buffer that was received with a parity error, unless the receive
952 * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is
953 * disabled, Within the receive buffer structure the received dataword is tagged
954 * if it is received with a parity error. This information is available by reading
955 * the ED register prior to reading the D register.
958 * - 0 - No parity error detected since the last time this flag was cleared. If
959 * the receive buffer has a depth greater than 1, then there may be data in
960 * the receive buffer what was received with a parity error.
961 * - 1 - At least one dataword was received with a parity error since the last
962 * time this flag was cleared.
965 #define BP_UART_S1_PF (0U) /*!< Bit position for UART_S1_PF. */
966 #define BM_UART_S1_PF (0x01U) /*!< Bit mask for UART_S1_PF. */
967 #define BS_UART_S1_PF (1U) /*!< Bit field size in bits for UART_S1_PF. */
969 /*! @brief Read current value of the UART_S1_PF field. */
970 #define BR_UART_S1_PF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_PF))
974 * @name Register UART_S1, field FE[1] (RO)
976 * FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set,
977 * then FE will set when a logic 0 is accepted for either of the two stop bits.
978 * FE does not set in the case of an overrun or while the LIN break detect feature
979 * is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is
980 * cleared. To clear FE, read S1 with FE set and then read D. The last data in the
981 * receive buffer represents the data that was received with the frame error
982 * enabled. Framing errors are not supported when 7816E is set/enabled. However, if
983 * this flag is set, data is still not received in 7816 mode.
986 * - 0 - No framing error detected.
987 * - 1 - Framing error.
990 #define BP_UART_S1_FE (1U) /*!< Bit position for UART_S1_FE. */
991 #define BM_UART_S1_FE (0x02U) /*!< Bit mask for UART_S1_FE. */
992 #define BS_UART_S1_FE (1U) /*!< Bit field size in bits for UART_S1_FE. */
994 /*! @brief Read current value of the UART_S1_FE field. */
995 #define BR_UART_S1_FE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_FE))
999 * @name Register UART_S1, field NF[2] (RO)
1001 * NF is set when the UART detects noise on the receiver input. NF does not
1002 * become set in the case of an overrun or while the LIN break detect feature is
1003 * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has
1004 * been received with noise since the last time it was cleared. There is no
1005 * guarantee that the first dataword read from the receive buffer has noise or that there
1006 * is only one dataword in the buffer that was received with noise unless the
1007 * receive buffer has a depth of one. To clear NF, read S1 and then read D.
1010 * - 0 - No noise detected since the last time this flag was cleared. If the
1011 * receive buffer has a depth greater than 1 then there may be data in the
1012 * receiver buffer that was received with noise.
1013 * - 1 - At least one dataword was received with noise detected since the last
1014 * time the flag was cleared.
1017 #define BP_UART_S1_NF (2U) /*!< Bit position for UART_S1_NF. */
1018 #define BM_UART_S1_NF (0x04U) /*!< Bit mask for UART_S1_NF. */
1019 #define BS_UART_S1_NF (1U) /*!< Bit field size in bits for UART_S1_NF. */
1021 /*! @brief Read current value of the UART_S1_NF field. */
1022 #define BR_UART_S1_NF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_NF))
1026 * @name Register UART_S1, field OR[3] (RO)
1028 * OR is set when software fails to prevent the receive data register from
1029 * overflowing with data. The OR bit is set immediately after the stop bit has been
1030 * completely received for the dataword that overflows the buffer and all the other
1031 * error flags (FE, NF, and PF) are prevented from setting. The data in the
1032 * shift register is lost, but the data already in the UART data registers is not
1033 * affected. If the OR flag is set, no data is stored in the data buffer even if
1034 * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
1035 * flags are blocked from asserting, that is, transition from an inactive to an
1036 * active state. To clear OR, read S1 when OR is set and then read D. See
1037 * functional description for more details regarding the operation of the OR bit.If
1038 * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF]
1039 * is not cleared before the next data character is received. In 7816 mode, it is
1040 * possible to configure a NACK to be returned by programing C7816[ONACK].
1043 * - 0 - No overrun has occurred since the last time the flag was cleared.
1044 * - 1 - Overrun has occurred or the overrun flag has not been cleared since the
1045 * last overrun occured.
1048 #define BP_UART_S1_OR (3U) /*!< Bit position for UART_S1_OR. */
1049 #define BM_UART_S1_OR (0x08U) /*!< Bit mask for UART_S1_OR. */
1050 #define BS_UART_S1_OR (1U) /*!< Bit field size in bits for UART_S1_OR. */
1052 /*! @brief Read current value of the UART_S1_OR field. */
1053 #define BR_UART_S1_OR(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_OR))
1057 * @name Register UART_S1, field IDLE[4] (RO)
1059 * After the IDLE flag is cleared, a frame must be received (although not
1060 * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN
1061 * break character must set the S2[LBKDIF] flag before an idle condition can set the
1062 * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
1063 * IDLE is set when either of the following appear on the receiver input: 10
1064 * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10]
1065 * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle
1066 * detection is not supported when 7816E is set/enabled and hence this flag is
1067 * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE
1068 * flag if RWUID is set, else the IDLE flag does not become set.
1071 * - 0 - Receiver input is either active now or has never become active since
1072 * the IDLE flag was last cleared.
1073 * - 1 - Receiver input has become idle or the flag has not been cleared since
1077 #define BP_UART_S1_IDLE (4U) /*!< Bit position for UART_S1_IDLE. */
1078 #define BM_UART_S1_IDLE (0x10U) /*!< Bit mask for UART_S1_IDLE. */
1079 #define BS_UART_S1_IDLE (1U) /*!< Bit field size in bits for UART_S1_IDLE. */
1081 /*! @brief Read current value of the UART_S1_IDLE field. */
1082 #define BR_UART_S1_IDLE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_IDLE))
1086 * @name Register UART_S1, field RDRF[5] (RO)
1088 * RDRF is set when the number of datawords in the receive buffer is equal to or
1089 * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
1090 * process of being received is not included in the count. To clear RDRF, read S1
1091 * when RDRF is set and then read D. For more efficient interrupt and DMA
1092 * operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
1093 * Then read S1 and the final data value, resulting in the clearing of the RDRF
1094 * flag. Even if RDRF is set, data will continue to be received until an overrun
1095 * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
1096 * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive
1097 * buffer but over-write each other.
1100 * - 0 - The number of datawords in the receive buffer is less than the number
1101 * indicated by RXWATER.
1102 * - 1 - The number of datawords in the receive buffer is equal to or greater
1103 * than the number indicated by RXWATER at some point in time since this flag
1107 #define BP_UART_S1_RDRF (5U) /*!< Bit position for UART_S1_RDRF. */
1108 #define BM_UART_S1_RDRF (0x20U) /*!< Bit mask for UART_S1_RDRF. */
1109 #define BS_UART_S1_RDRF (1U) /*!< Bit field size in bits for UART_S1_RDRF. */
1111 /*! @brief Read current value of the UART_S1_RDRF field. */
1112 #define BR_UART_S1_RDRF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_RDRF))
1116 * @name Register UART_S1, field TC[6] (RO)
1118 * TC is set when the transmit buffer is empty and no data, preamble, or break
1119 * character is being transmitted. When TC is set, the transmit data output signal
1120 * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
1121 * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
1122 * set after any NACK signal has been received, but prior to any corresponding
1123 * guard times expiring. Writing to D to transmit new data. Queuing a preamble by
1124 * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
1128 * - 0 - Transmitter active (sending data, a preamble, or a break).
1129 * - 1 - Transmitter idle (transmission activity complete).
1132 #define BP_UART_S1_TC (6U) /*!< Bit position for UART_S1_TC. */
1133 #define BM_UART_S1_TC (0x40U) /*!< Bit mask for UART_S1_TC. */
1134 #define BS_UART_S1_TC (1U) /*!< Bit field size in bits for UART_S1_TC. */
1136 /*! @brief Read current value of the UART_S1_TC field. */
1137 #define BR_UART_S1_TC(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TC))
1141 * @name Register UART_S1, field TDRE[7] (RO)
1143 * TDRE will set when the number of datawords in the transmit buffer (D and
1144 * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
1145 * character that is in the process of being transmitted is not included in the count.
1146 * To clear TDRE, read S1 when TDRE is set and then write to the UART data
1147 * register (D). For more efficient interrupt servicing, all data except the final value
1148 * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
1149 * before writing the final data value, resulting in the clearing of the TRDE
1150 * flag. This is more efficient because the TDRE reasserts until the watermark has
1151 * been exceeded. So, attempting to clear the TDRE with every write will be
1152 * ineffective until sufficient data has been written.
1155 * - 0 - The amount of data in the transmit buffer is greater than the value
1156 * indicated by TWFIFO[TXWATER].
1157 * - 1 - The amount of data in the transmit buffer is less than or equal to the
1158 * value indicated by TWFIFO[TXWATER] at some point in time since the flag
1162 #define BP_UART_S1_TDRE (7U) /*!< Bit position for UART_S1_TDRE. */
1163 #define BM_UART_S1_TDRE (0x80U) /*!< Bit mask for UART_S1_TDRE. */
1164 #define BS_UART_S1_TDRE (1U) /*!< Bit field size in bits for UART_S1_TDRE. */
1166 /*! @brief Read current value of the UART_S1_TDRE field. */
1167 #define BR_UART_S1_TDRE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TDRE))
1170 /*******************************************************************************
1171 * HW_UART_S2 - UART Status Register 2
1172 ******************************************************************************/
1175 * @brief HW_UART_S2 - UART Status Register 2 (RW)
1177 * Reset value: 0x00U
1179 * The S2 register provides inputs to the MCU for generation of UART interrupts
1180 * or DMA requests. Also, this register can be polled by the MCU to check the
1181 * status of these bits. This register can be read or written at any time, with the
1182 * exception of the MSBF and RXINV bits, which should be changed by the user only
1183 * between transmit and receive packets.
1185 typedef union _hw_uart_s2
1188 struct _hw_uart_s2_bitfields
1190 uint8_t RAF : 1; /*!< [0] Receiver Active Flag */
1191 uint8_t LBKDE : 1; /*!< [1] LIN Break Detection Enable */
1192 uint8_t BRK13 : 1; /*!< [2] Break Transmit Character Length */
1193 uint8_t RWUID : 1; /*!< [3] Receive Wakeup Idle Detect */
1194 uint8_t RXINV : 1; /*!< [4] Receive Data Inversion */
1195 uint8_t MSBF : 1; /*!< [5] Most Significant Bit First */
1196 uint8_t RXEDGIF : 1; /*!< [6] RxD Pin Active Edge Interrupt Flag */
1197 uint8_t LBKDIF : 1; /*!< [7] LIN Break Detect Interrupt Flag */
1202 * @name Constants and macros for entire UART_S2 register
1205 #define HW_UART_S2_ADDR(x) ((x) + 0x5U)
1207 #define HW_UART_S2(x) (*(__IO hw_uart_s2_t *) HW_UART_S2_ADDR(x))
1208 #define HW_UART_S2_RD(x) (HW_UART_S2(x).U)
1209 #define HW_UART_S2_WR(x, v) (HW_UART_S2(x).U = (v))
1210 #define HW_UART_S2_SET(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) | (v)))
1211 #define HW_UART_S2_CLR(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) & ~(v)))
1212 #define HW_UART_S2_TOG(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) ^ (v)))
1216 * Constants & macros for individual UART_S2 bitfields
1220 * @name Register UART_S2, field RAF[0] (RO)
1222 * RAF is set when the UART receiver detects a logic 0 during the RT1 time
1223 * period of the start bit search. RAF is cleared when the receiver detects an idle
1224 * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
1225 * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
1226 * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
1227 * to configure the guard time to 12. However, if a NACK is required to be
1228 * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
1229 * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
1230 * prior to actually being inactive.
1233 * - 0 - UART receiver idle/inactive waiting for a start bit.
1234 * - 1 - UART receiver active, RxD input not idle.
1237 #define BP_UART_S2_RAF (0U) /*!< Bit position for UART_S2_RAF. */
1238 #define BM_UART_S2_RAF (0x01U) /*!< Bit mask for UART_S2_RAF. */
1239 #define BS_UART_S2_RAF (1U) /*!< Bit field size in bits for UART_S2_RAF. */
1241 /*! @brief Read current value of the UART_S2_RAF field. */
1242 #define BR_UART_S2_RAF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RAF))
1246 * @name Register UART_S2, field LBKDE[1] (RW)
1248 * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF],
1249 * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see .
1250 * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set.
1253 * - 0 - Break character detection is disabled.
1254 * - 1 - Break character is detected at length of 11 bit times if C1[M] = 0 or
1255 * 12 bits time if C1[M] = 1.
1258 #define BP_UART_S2_LBKDE (1U) /*!< Bit position for UART_S2_LBKDE. */
1259 #define BM_UART_S2_LBKDE (0x02U) /*!< Bit mask for UART_S2_LBKDE. */
1260 #define BS_UART_S2_LBKDE (1U) /*!< Bit field size in bits for UART_S2_LBKDE. */
1262 /*! @brief Read current value of the UART_S2_LBKDE field. */
1263 #define BR_UART_S2_LBKDE(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE))
1265 /*! @brief Format value for bitfield UART_S2_LBKDE. */
1266 #define BF_UART_S2_LBKDE(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_LBKDE) & BM_UART_S2_LBKDE)
1268 /*! @brief Set the LBKDE field to a new value. */
1269 #define BW_UART_S2_LBKDE(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE) = (v))
1273 * @name Register UART_S2, field BRK13[2] (RW)
1275 * Determines whether the transmit break character is 10, 11, or 12 bits long,
1276 * or 13 or 14 bits long. See for the length of the break character for the
1277 * different configurations. The detection of a framing error is not affected by this
1278 * field. Transmitting break characters
1281 * - 0 - Break character is 10, 11, or 12 bits long.
1282 * - 1 - Break character is 13 or 14 bits long.
1285 #define BP_UART_S2_BRK13 (2U) /*!< Bit position for UART_S2_BRK13. */
1286 #define BM_UART_S2_BRK13 (0x04U) /*!< Bit mask for UART_S2_BRK13. */
1287 #define BS_UART_S2_BRK13 (1U) /*!< Bit field size in bits for UART_S2_BRK13. */
1289 /*! @brief Read current value of the UART_S2_BRK13 field. */
1290 #define BR_UART_S2_BRK13(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13))
1292 /*! @brief Format value for bitfield UART_S2_BRK13. */
1293 #define BF_UART_S2_BRK13(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_BRK13) & BM_UART_S2_BRK13)
1295 /*! @brief Set the BRK13 field to a new value. */
1296 #define BW_UART_S2_BRK13(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13) = (v))
1300 * @name Register UART_S2, field RWUID[3] (RW)
1302 * When RWU is set and WAKE is cleared, this field controls whether the idle
1303 * character that wakes the receiver sets S1[IDLE]. This field must be cleared when
1304 * C7816[ISO7816E] is set/enabled.
1307 * - 0 - S1[IDLE] is not set upon detection of an idle character.
1308 * - 1 - S1[IDLE] is set upon detection of an idle character.
1311 #define BP_UART_S2_RWUID (3U) /*!< Bit position for UART_S2_RWUID. */
1312 #define BM_UART_S2_RWUID (0x08U) /*!< Bit mask for UART_S2_RWUID. */
1313 #define BS_UART_S2_RWUID (1U) /*!< Bit field size in bits for UART_S2_RWUID. */
1315 /*! @brief Read current value of the UART_S2_RWUID field. */
1316 #define BR_UART_S2_RWUID(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID))
1318 /*! @brief Format value for bitfield UART_S2_RWUID. */
1319 #define BF_UART_S2_RWUID(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RWUID) & BM_UART_S2_RWUID)
1321 /*! @brief Set the RWUID field to a new value. */
1322 #define BW_UART_S2_RWUID(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID) = (v))
1326 * @name Register UART_S2, field RXINV[4] (RW)
1328 * Setting this field reverses the polarity of the received data input. In NRZ
1329 * format, a one is represented by a mark and a zero is represented by a space for
1330 * normal polarity, and the opposite for inverted polarity. In IrDA format, a
1331 * zero is represented by short high pulse in the middle of a bit time remaining
1332 * idle low for a one for normal polarity. A zero is represented by a short low
1333 * pulse in the middle of a bit time remaining idle high for a one for inverted
1334 * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are
1335 * enabled and an initial character is detected in T = 0 protocol mode. Setting
1336 * RXINV inverts the RxD input for data bits, start and stop bits, break, and
1337 * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit
1341 * - 0 - Receive data is not inverted.
1342 * - 1 - Receive data is inverted.
1345 #define BP_UART_S2_RXINV (4U) /*!< Bit position for UART_S2_RXINV. */
1346 #define BM_UART_S2_RXINV (0x10U) /*!< Bit mask for UART_S2_RXINV. */
1347 #define BS_UART_S2_RXINV (1U) /*!< Bit field size in bits for UART_S2_RXINV. */
1349 /*! @brief Read current value of the UART_S2_RXINV field. */
1350 #define BR_UART_S2_RXINV(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV))
1352 /*! @brief Format value for bitfield UART_S2_RXINV. */
1353 #define BF_UART_S2_RXINV(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RXINV) & BM_UART_S2_RXINV)
1355 /*! @brief Set the RXINV field to a new value. */
1356 #define BW_UART_S2_RXINV(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV) = (v))
1360 * @name Register UART_S2, field MSBF[5] (RW)
1362 * Setting this field reverses the order of the bits that are transmitted and
1363 * received on the wire. This field does not affect the polarity of the bits, the
1364 * location of the parity bit, or the location of the start or stop bits. This
1365 * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
1366 * an initial character is detected in T = 0 protocol mode.
1369 * - 0 - LSB (bit0) is the first bit that is transmitted following the start
1370 * bit. Further, the first bit received after the start bit is identified as
1372 * - 1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted following
1373 * the start bit, depending on the setting of C1[M] and C1[PE]. Further, the
1374 * first bit received after the start bit is identified as bit8, bit7, or
1375 * bit6, depending on the setting of C1[M] and C1[PE].
1378 #define BP_UART_S2_MSBF (5U) /*!< Bit position for UART_S2_MSBF. */
1379 #define BM_UART_S2_MSBF (0x20U) /*!< Bit mask for UART_S2_MSBF. */
1380 #define BS_UART_S2_MSBF (1U) /*!< Bit field size in bits for UART_S2_MSBF. */
1382 /*! @brief Read current value of the UART_S2_MSBF field. */
1383 #define BR_UART_S2_MSBF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF))
1385 /*! @brief Format value for bitfield UART_S2_MSBF. */
1386 #define BF_UART_S2_MSBF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_MSBF) & BM_UART_S2_MSBF)
1388 /*! @brief Set the MSBF field to a new value. */
1389 #define BW_UART_S2_MSBF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF) = (v))
1393 * @name Register UART_S2, field RXEDGIF[6] (W1C)
1395 * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
1396 * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
1397 * to it. See for additional details. RXEDGIF description The active edge is
1398 * detected only in two wire mode and on receiving data coming from the RxD pin.
1401 * - 0 - No active edge on the receive pin has occurred.
1402 * - 1 - An active edge on the receive pin has occurred.
1405 #define BP_UART_S2_RXEDGIF (6U) /*!< Bit position for UART_S2_RXEDGIF. */
1406 #define BM_UART_S2_RXEDGIF (0x40U) /*!< Bit mask for UART_S2_RXEDGIF. */
1407 #define BS_UART_S2_RXEDGIF (1U) /*!< Bit field size in bits for UART_S2_RXEDGIF. */
1409 /*! @brief Read current value of the UART_S2_RXEDGIF field. */
1410 #define BR_UART_S2_RXEDGIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF))
1412 /*! @brief Format value for bitfield UART_S2_RXEDGIF. */
1413 #define BF_UART_S2_RXEDGIF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RXEDGIF) & BM_UART_S2_RXEDGIF)
1415 /*! @brief Set the RXEDGIF field to a new value. */
1416 #define BW_UART_S2_RXEDGIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF) = (v))
1420 * @name Register UART_S2, field LBKDIF[7] (W1C)
1422 * LBKDIF is set when LBKDE is set and a LIN break character is detected on the
1423 * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M]
1424 * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the
1425 * last LIN break character. LBKDIF is cleared by writing a 1 to it.
1428 * - 0 - No LIN break character detected.
1429 * - 1 - LIN break character detected.
1432 #define BP_UART_S2_LBKDIF (7U) /*!< Bit position for UART_S2_LBKDIF. */
1433 #define BM_UART_S2_LBKDIF (0x80U) /*!< Bit mask for UART_S2_LBKDIF. */
1434 #define BS_UART_S2_LBKDIF (1U) /*!< Bit field size in bits for UART_S2_LBKDIF. */
1436 /*! @brief Read current value of the UART_S2_LBKDIF field. */
1437 #define BR_UART_S2_LBKDIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF))
1439 /*! @brief Format value for bitfield UART_S2_LBKDIF. */
1440 #define BF_UART_S2_LBKDIF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_LBKDIF) & BM_UART_S2_LBKDIF)
1442 /*! @brief Set the LBKDIF field to a new value. */
1443 #define BW_UART_S2_LBKDIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF) = (v))
1446 /*******************************************************************************
1447 * HW_UART_C3 - UART Control Register 3
1448 ******************************************************************************/
1451 * @brief HW_UART_C3 - UART Control Register 3 (RW)
1453 * Reset value: 0x00U
1455 * Writing R8 does not have any effect. TXDIR and TXINV can be changed only
1456 * between transmit and receive packets.
1458 typedef union _hw_uart_c3
1461 struct _hw_uart_c3_bitfields
1463 uint8_t PEIE : 1; /*!< [0] Parity Error Interrupt Enable */
1464 uint8_t FEIE : 1; /*!< [1] Framing Error Interrupt Enable */
1465 uint8_t NEIE : 1; /*!< [2] Noise Error Interrupt Enable */
1466 uint8_t ORIE : 1; /*!< [3] Overrun Error Interrupt Enable */
1467 uint8_t TXINV : 1; /*!< [4] Transmit Data Inversion. */
1468 uint8_t TXDIR : 1; /*!< [5] Transmitter Pin Data Direction in
1469 * Single-Wire mode */
1470 uint8_t T8 : 1; /*!< [6] Transmit Bit 8 */
1471 uint8_t R8 : 1; /*!< [7] Received Bit 8 */
1476 * @name Constants and macros for entire UART_C3 register
1479 #define HW_UART_C3_ADDR(x) ((x) + 0x6U)
1481 #define HW_UART_C3(x) (*(__IO hw_uart_c3_t *) HW_UART_C3_ADDR(x))
1482 #define HW_UART_C3_RD(x) (HW_UART_C3(x).U)
1483 #define HW_UART_C3_WR(x, v) (HW_UART_C3(x).U = (v))
1484 #define HW_UART_C3_SET(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) | (v)))
1485 #define HW_UART_C3_CLR(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) & ~(v)))
1486 #define HW_UART_C3_TOG(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) ^ (v)))
1490 * Constants & macros for individual UART_C3 bitfields
1494 * @name Register UART_C3, field PEIE[0] (RW)
1496 * Enables the parity error flag, S1[PF], to generate interrupt requests.
1499 * - 0 - PF interrupt requests are disabled.
1500 * - 1 - PF interrupt requests are enabled.
1503 #define BP_UART_C3_PEIE (0U) /*!< Bit position for UART_C3_PEIE. */
1504 #define BM_UART_C3_PEIE (0x01U) /*!< Bit mask for UART_C3_PEIE. */
1505 #define BS_UART_C3_PEIE (1U) /*!< Bit field size in bits for UART_C3_PEIE. */
1507 /*! @brief Read current value of the UART_C3_PEIE field. */
1508 #define BR_UART_C3_PEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE))
1510 /*! @brief Format value for bitfield UART_C3_PEIE. */
1511 #define BF_UART_C3_PEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_PEIE) & BM_UART_C3_PEIE)
1513 /*! @brief Set the PEIE field to a new value. */
1514 #define BW_UART_C3_PEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE) = (v))
1518 * @name Register UART_C3, field FEIE[1] (RW)
1520 * Enables the framing error flag, S1[FE], to generate interrupt requests.
1523 * - 0 - FE interrupt requests are disabled.
1524 * - 1 - FE interrupt requests are enabled.
1527 #define BP_UART_C3_FEIE (1U) /*!< Bit position for UART_C3_FEIE. */
1528 #define BM_UART_C3_FEIE (0x02U) /*!< Bit mask for UART_C3_FEIE. */
1529 #define BS_UART_C3_FEIE (1U) /*!< Bit field size in bits for UART_C3_FEIE. */
1531 /*! @brief Read current value of the UART_C3_FEIE field. */
1532 #define BR_UART_C3_FEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE))
1534 /*! @brief Format value for bitfield UART_C3_FEIE. */
1535 #define BF_UART_C3_FEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_FEIE) & BM_UART_C3_FEIE)
1537 /*! @brief Set the FEIE field to a new value. */
1538 #define BW_UART_C3_FEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE) = (v))
1542 * @name Register UART_C3, field NEIE[2] (RW)
1544 * Enables the noise flag, S1[NF], to generate interrupt requests.
1547 * - 0 - NF interrupt requests are disabled.
1548 * - 1 - NF interrupt requests are enabled.
1551 #define BP_UART_C3_NEIE (2U) /*!< Bit position for UART_C3_NEIE. */
1552 #define BM_UART_C3_NEIE (0x04U) /*!< Bit mask for UART_C3_NEIE. */
1553 #define BS_UART_C3_NEIE (1U) /*!< Bit field size in bits for UART_C3_NEIE. */
1555 /*! @brief Read current value of the UART_C3_NEIE field. */
1556 #define BR_UART_C3_NEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE))
1558 /*! @brief Format value for bitfield UART_C3_NEIE. */
1559 #define BF_UART_C3_NEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_NEIE) & BM_UART_C3_NEIE)
1561 /*! @brief Set the NEIE field to a new value. */
1562 #define BW_UART_C3_NEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE) = (v))
1566 * @name Register UART_C3, field ORIE[3] (RW)
1568 * Enables the overrun error flag, S1[OR], to generate interrupt requests.
1571 * - 0 - OR interrupts are disabled.
1572 * - 1 - OR interrupt requests are enabled.
1575 #define BP_UART_C3_ORIE (3U) /*!< Bit position for UART_C3_ORIE. */
1576 #define BM_UART_C3_ORIE (0x08U) /*!< Bit mask for UART_C3_ORIE. */
1577 #define BS_UART_C3_ORIE (1U) /*!< Bit field size in bits for UART_C3_ORIE. */
1579 /*! @brief Read current value of the UART_C3_ORIE field. */
1580 #define BR_UART_C3_ORIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE))
1582 /*! @brief Format value for bitfield UART_C3_ORIE. */
1583 #define BF_UART_C3_ORIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_ORIE) & BM_UART_C3_ORIE)
1585 /*! @brief Set the ORIE field to a new value. */
1586 #define BW_UART_C3_ORIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE) = (v))
1590 * @name Register UART_C3, field TXINV[4] (RW)
1592 * Setting this field reverses the polarity of the transmitted data output. In
1593 * NRZ format, a one is represented by a mark and a zero is represented by a space
1594 * for normal polarity, and the opposite for inverted polarity. In IrDA format,
1595 * a zero is represented by short high pulse in the middle of a bit time
1596 * remaining idle low for a one for normal polarity, and a zero is represented by short
1597 * low pulse in the middle of a bit time remaining idle high for a one for
1598 * inverted polarity. This field is automatically set when C7816[INIT] and
1599 * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
1600 * Setting TXINV inverts all transmitted values, including idle, break, start, and
1601 * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit
1602 * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only
1603 * the transmitted data bits and parity bit are inverted.
1606 * - 0 - Transmit data is not inverted.
1607 * - 1 - Transmit data is inverted.
1610 #define BP_UART_C3_TXINV (4U) /*!< Bit position for UART_C3_TXINV. */
1611 #define BM_UART_C3_TXINV (0x10U) /*!< Bit mask for UART_C3_TXINV. */
1612 #define BS_UART_C3_TXINV (1U) /*!< Bit field size in bits for UART_C3_TXINV. */
1614 /*! @brief Read current value of the UART_C3_TXINV field. */
1615 #define BR_UART_C3_TXINV(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV))
1617 /*! @brief Format value for bitfield UART_C3_TXINV. */
1618 #define BF_UART_C3_TXINV(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_TXINV) & BM_UART_C3_TXINV)
1620 /*! @brief Set the TXINV field to a new value. */
1621 #define BW_UART_C3_TXINV(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV) = (v))
1625 * @name Register UART_C3, field TXDIR[5] (RW)
1627 * Determines whether the TXD pin is used as an input or output in the
1628 * single-wire mode of operation. This field is relevant only to the single wire mode.
1629 * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
1630 * automatically cleared after the requested block is transmitted. This condition is
1631 * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
1632 * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
1633 * being transmitted, the hardware automatically overrides this field as needed. In
1634 * this situation, TXDIR does not reflect the temporary state associated with
1638 * - 0 - TXD pin is an input in single wire mode.
1639 * - 1 - TXD pin is an output in single wire mode.
1642 #define BP_UART_C3_TXDIR (5U) /*!< Bit position for UART_C3_TXDIR. */
1643 #define BM_UART_C3_TXDIR (0x20U) /*!< Bit mask for UART_C3_TXDIR. */
1644 #define BS_UART_C3_TXDIR (1U) /*!< Bit field size in bits for UART_C3_TXDIR. */
1646 /*! @brief Read current value of the UART_C3_TXDIR field. */
1647 #define BR_UART_C3_TXDIR(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR))
1649 /*! @brief Format value for bitfield UART_C3_TXDIR. */
1650 #define BF_UART_C3_TXDIR(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_TXDIR) & BM_UART_C3_TXDIR)
1652 /*! @brief Set the TXDIR field to a new value. */
1653 #define BW_UART_C3_TXDIR(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR) = (v))
1657 * @name Register UART_C3, field T8[6] (RW)
1659 * T8 is the ninth data bit transmitted when the UART is configured for 9-bit
1660 * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
1661 * same as in the previous transmission, T8 does not have to be rewritten. The same
1662 * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
1663 * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
1664 * the remaining data.
1667 #define BP_UART_C3_T8 (6U) /*!< Bit position for UART_C3_T8. */
1668 #define BM_UART_C3_T8 (0x40U) /*!< Bit mask for UART_C3_T8. */
1669 #define BS_UART_C3_T8 (1U) /*!< Bit field size in bits for UART_C3_T8. */
1671 /*! @brief Read current value of the UART_C3_T8 field. */
1672 #define BR_UART_C3_T8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8))
1674 /*! @brief Format value for bitfield UART_C3_T8. */
1675 #define BF_UART_C3_T8(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_T8) & BM_UART_C3_T8)
1677 /*! @brief Set the T8 field to a new value. */
1678 #define BW_UART_C3_T8(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8) = (v))
1682 * @name Register UART_C3, field R8[7] (RO)
1684 * R8 is the ninth data bit received when the UART is configured for 9-bit data
1685 * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
1686 * current data value in the UARTx_D register. To read the 9th bit, read the
1687 * value of UARTx_C3[R8], then read the UARTx_D register.
1690 #define BP_UART_C3_R8 (7U) /*!< Bit position for UART_C3_R8. */
1691 #define BM_UART_C3_R8 (0x80U) /*!< Bit mask for UART_C3_R8. */
1692 #define BS_UART_C3_R8 (1U) /*!< Bit field size in bits for UART_C3_R8. */
1694 /*! @brief Read current value of the UART_C3_R8 field. */
1695 #define BR_UART_C3_R8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_R8))
1698 /*******************************************************************************
1699 * HW_UART_D - UART Data Register
1700 ******************************************************************************/
1703 * @brief HW_UART_D - UART Data Register (RW)
1705 * Reset value: 0x00U
1707 * This register is actually two separate registers. Reads return the contents
1708 * of the read-only receive data register and writes go to the write-only transmit
1709 * data register. In 8-bit or 9-bit data format, only UART data register (D)
1710 * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
1711 * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
1712 * register, only if the ninth bit of data needs to be captured. Similarly, the
1713 * ED register needs to be read, prior to the D register, only if the additional
1714 * flag data for the dataword needs to be captured. In the normal 8-bit mode (M
1715 * bit cleared) if the parity is enabled, you get seven data bits and one parity
1716 * bit. That one parity bit is loaded into the D register. So, for the data bits,
1717 * mask off the parity bit from the value you read out of this register. When
1718 * transmitting in 9-bit data format and using 8-bit write instructions, write first
1719 * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
1720 * C3[T8] stores the data in a temporary register. If D register is written first,
1721 * and then the new data on data bus is stored in D, the temporary value written by
1722 * the last write to C3[T8] gets stored in the C3[T8] register.
1724 typedef union _hw_uart_d
1727 struct _hw_uart_d_bitfields
1729 uint8_t RT : 8; /*!< [7:0] */
1734 * @name Constants and macros for entire UART_D register
1737 #define HW_UART_D_ADDR(x) ((x) + 0x7U)
1739 #define HW_UART_D(x) (*(__IO hw_uart_d_t *) HW_UART_D_ADDR(x))
1740 #define HW_UART_D_RD(x) (HW_UART_D(x).U)
1741 #define HW_UART_D_WR(x, v) (HW_UART_D(x).U = (v))
1742 #define HW_UART_D_SET(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) | (v)))
1743 #define HW_UART_D_CLR(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) & ~(v)))
1744 #define HW_UART_D_TOG(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) ^ (v)))
1748 * Constants & macros for individual UART_D bitfields
1752 * @name Register UART_D, field RT[7:0] (RW)
1754 * Reads return the contents of the read-only receive data register and writes
1755 * go to the write-only transmit data register.
1758 #define BP_UART_D_RT (0U) /*!< Bit position for UART_D_RT. */
1759 #define BM_UART_D_RT (0xFFU) /*!< Bit mask for UART_D_RT. */
1760 #define BS_UART_D_RT (8U) /*!< Bit field size in bits for UART_D_RT. */
1762 /*! @brief Read current value of the UART_D_RT field. */
1763 #define BR_UART_D_RT(x) (HW_UART_D(x).U)
1765 /*! @brief Format value for bitfield UART_D_RT. */
1766 #define BF_UART_D_RT(v) ((uint8_t)((uint8_t)(v) << BP_UART_D_RT) & BM_UART_D_RT)
1768 /*! @brief Set the RT field to a new value. */
1769 #define BW_UART_D_RT(x, v) (HW_UART_D_WR(x, v))
1772 /*******************************************************************************
1773 * HW_UART_MA1 - UART Match Address Registers 1
1774 ******************************************************************************/
1777 * @brief HW_UART_MA1 - UART Match Address Registers 1 (RW)
1779 * Reset value: 0x00U
1781 * The MA1 and MA2 registers are compared to input data addresses when the most
1782 * significant bit is set and the associated C4[MAEN] field is set. If a match
1783 * occurs, the following data is transferred to the data register. If a match
1784 * fails, the following data is discarded. These registers can be read and written at
1787 typedef union _hw_uart_ma1
1790 struct _hw_uart_ma1_bitfields
1792 uint8_t MA : 8; /*!< [7:0] Match Address */
1797 * @name Constants and macros for entire UART_MA1 register
1800 #define HW_UART_MA1_ADDR(x) ((x) + 0x8U)
1802 #define HW_UART_MA1(x) (*(__IO hw_uart_ma1_t *) HW_UART_MA1_ADDR(x))
1803 #define HW_UART_MA1_RD(x) (HW_UART_MA1(x).U)
1804 #define HW_UART_MA1_WR(x, v) (HW_UART_MA1(x).U = (v))
1805 #define HW_UART_MA1_SET(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) | (v)))
1806 #define HW_UART_MA1_CLR(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) & ~(v)))
1807 #define HW_UART_MA1_TOG(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) ^ (v)))
1811 * Constants & macros for individual UART_MA1 bitfields
1815 * @name Register UART_MA1, field MA[7:0] (RW)
1818 #define BP_UART_MA1_MA (0U) /*!< Bit position for UART_MA1_MA. */
1819 #define BM_UART_MA1_MA (0xFFU) /*!< Bit mask for UART_MA1_MA. */
1820 #define BS_UART_MA1_MA (8U) /*!< Bit field size in bits for UART_MA1_MA. */
1822 /*! @brief Read current value of the UART_MA1_MA field. */
1823 #define BR_UART_MA1_MA(x) (HW_UART_MA1(x).U)
1825 /*! @brief Format value for bitfield UART_MA1_MA. */
1826 #define BF_UART_MA1_MA(v) ((uint8_t)((uint8_t)(v) << BP_UART_MA1_MA) & BM_UART_MA1_MA)
1828 /*! @brief Set the MA field to a new value. */
1829 #define BW_UART_MA1_MA(x, v) (HW_UART_MA1_WR(x, v))
1832 /*******************************************************************************
1833 * HW_UART_MA2 - UART Match Address Registers 2
1834 ******************************************************************************/
1837 * @brief HW_UART_MA2 - UART Match Address Registers 2 (RW)
1839 * Reset value: 0x00U
1841 * These registers can be read and written at anytime. The MA1 and MA2 registers
1842 * are compared to input data addresses when the most significant bit is set and
1843 * the associated C4[MAEN] field is set. If a match occurs, the following data
1844 * is transferred to the data register. If a match fails, the following data is
1847 typedef union _hw_uart_ma2
1850 struct _hw_uart_ma2_bitfields
1852 uint8_t MA : 8; /*!< [7:0] Match Address */
1857 * @name Constants and macros for entire UART_MA2 register
1860 #define HW_UART_MA2_ADDR(x) ((x) + 0x9U)
1862 #define HW_UART_MA2(x) (*(__IO hw_uart_ma2_t *) HW_UART_MA2_ADDR(x))
1863 #define HW_UART_MA2_RD(x) (HW_UART_MA2(x).U)
1864 #define HW_UART_MA2_WR(x, v) (HW_UART_MA2(x).U = (v))
1865 #define HW_UART_MA2_SET(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) | (v)))
1866 #define HW_UART_MA2_CLR(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) & ~(v)))
1867 #define HW_UART_MA2_TOG(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) ^ (v)))
1871 * Constants & macros for individual UART_MA2 bitfields
1875 * @name Register UART_MA2, field MA[7:0] (RW)
1878 #define BP_UART_MA2_MA (0U) /*!< Bit position for UART_MA2_MA. */
1879 #define BM_UART_MA2_MA (0xFFU) /*!< Bit mask for UART_MA2_MA. */
1880 #define BS_UART_MA2_MA (8U) /*!< Bit field size in bits for UART_MA2_MA. */
1882 /*! @brief Read current value of the UART_MA2_MA field. */
1883 #define BR_UART_MA2_MA(x) (HW_UART_MA2(x).U)
1885 /*! @brief Format value for bitfield UART_MA2_MA. */
1886 #define BF_UART_MA2_MA(v) ((uint8_t)((uint8_t)(v) << BP_UART_MA2_MA) & BM_UART_MA2_MA)
1888 /*! @brief Set the MA field to a new value. */
1889 #define BW_UART_MA2_MA(x, v) (HW_UART_MA2_WR(x, v))
1892 /*******************************************************************************
1893 * HW_UART_C4 - UART Control Register 4
1894 ******************************************************************************/
1897 * @brief HW_UART_C4 - UART Control Register 4 (RW)
1899 * Reset value: 0x00U
1901 typedef union _hw_uart_c4
1904 struct _hw_uart_c4_bitfields
1906 uint8_t BRFA : 5; /*!< [4:0] Baud Rate Fine Adjust */
1907 uint8_t M10 : 1; /*!< [5] 10-bit Mode select */
1908 uint8_t MAEN2 : 1; /*!< [6] Match Address Mode Enable 2 */
1909 uint8_t MAEN1 : 1; /*!< [7] Match Address Mode Enable 1 */
1914 * @name Constants and macros for entire UART_C4 register
1917 #define HW_UART_C4_ADDR(x) ((x) + 0xAU)
1919 #define HW_UART_C4(x) (*(__IO hw_uart_c4_t *) HW_UART_C4_ADDR(x))
1920 #define HW_UART_C4_RD(x) (HW_UART_C4(x).U)
1921 #define HW_UART_C4_WR(x, v) (HW_UART_C4(x).U = (v))
1922 #define HW_UART_C4_SET(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) | (v)))
1923 #define HW_UART_C4_CLR(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) & ~(v)))
1924 #define HW_UART_C4_TOG(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) ^ (v)))
1928 * Constants & macros for individual UART_C4 bitfields
1932 * @name Register UART_C4, field BRFA[4:0] (RW)
1934 * This bit field is used to add more timing resolution to the average baud
1935 * frequency, in increments of 1/32. See Baud rate generation for more information.
1938 #define BP_UART_C4_BRFA (0U) /*!< Bit position for UART_C4_BRFA. */
1939 #define BM_UART_C4_BRFA (0x1FU) /*!< Bit mask for UART_C4_BRFA. */
1940 #define BS_UART_C4_BRFA (5U) /*!< Bit field size in bits for UART_C4_BRFA. */
1942 /*! @brief Read current value of the UART_C4_BRFA field. */
1943 #define BR_UART_C4_BRFA(x) (HW_UART_C4(x).B.BRFA)
1945 /*! @brief Format value for bitfield UART_C4_BRFA. */
1946 #define BF_UART_C4_BRFA(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_BRFA) & BM_UART_C4_BRFA)
1948 /*! @brief Set the BRFA field to a new value. */
1949 #define BW_UART_C4_BRFA(x, v) (HW_UART_C4_WR(x, (HW_UART_C4_RD(x) & ~BM_UART_C4_BRFA) | BF_UART_C4_BRFA(v)))
1953 * @name Register UART_C4, field M10[5] (RW)
1955 * Causes a tenth, non-memory mapped bit to be part of the serial transmission.
1956 * This tenth bit is generated and interpreted as a parity bit. The M10 field
1957 * does not affect the LIN send or detect break behavior. If M10 is set, then both
1958 * C1[M] and C1[PE] must also be set. This field must be cleared when
1959 * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
1962 * - 0 - The parity bit is the ninth bit in the serial transmission.
1963 * - 1 - The parity bit is the tenth bit in the serial transmission.
1966 #define BP_UART_C4_M10 (5U) /*!< Bit position for UART_C4_M10. */
1967 #define BM_UART_C4_M10 (0x20U) /*!< Bit mask for UART_C4_M10. */
1968 #define BS_UART_C4_M10 (1U) /*!< Bit field size in bits for UART_C4_M10. */
1970 /*! @brief Read current value of the UART_C4_M10 field. */
1971 #define BR_UART_C4_M10(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10))
1973 /*! @brief Format value for bitfield UART_C4_M10. */
1974 #define BF_UART_C4_M10(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_M10) & BM_UART_C4_M10)
1976 /*! @brief Set the M10 field to a new value. */
1977 #define BW_UART_C4_M10(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10) = (v))
1981 * @name Register UART_C4, field MAEN2[6] (RW)
1983 * See Match address operation for more information.
1986 * - 0 - All data received is transferred to the data buffer if MAEN1 is cleared.
1987 * - 1 - All data received with the most significant bit cleared, is discarded.
1988 * All data received with the most significant bit set, is compared with
1989 * contents of MA2 register. If no match occurs, the data is discarded. If a
1990 * match occurs, data is transferred to the data buffer. This field must be
1991 * cleared when C7816[ISO7816E] is set/enabled.
1994 #define BP_UART_C4_MAEN2 (6U) /*!< Bit position for UART_C4_MAEN2. */
1995 #define BM_UART_C4_MAEN2 (0x40U) /*!< Bit mask for UART_C4_MAEN2. */
1996 #define BS_UART_C4_MAEN2 (1U) /*!< Bit field size in bits for UART_C4_MAEN2. */
1998 /*! @brief Read current value of the UART_C4_MAEN2 field. */
1999 #define BR_UART_C4_MAEN2(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2))
2001 /*! @brief Format value for bitfield UART_C4_MAEN2. */
2002 #define BF_UART_C4_MAEN2(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_MAEN2) & BM_UART_C4_MAEN2)
2004 /*! @brief Set the MAEN2 field to a new value. */
2005 #define BW_UART_C4_MAEN2(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2) = (v))
2009 * @name Register UART_C4, field MAEN1[7] (RW)
2011 * See Match address operation for more information.
2014 * - 0 - All data received is transferred to the data buffer if MAEN2 is cleared.
2015 * - 1 - All data received with the most significant bit cleared, is discarded.
2016 * All data received with the most significant bit set, is compared with
2017 * contents of MA1 register. If no match occurs, the data is discarded. If match
2018 * occurs, data is transferred to the data buffer. This field must be cleared
2019 * when C7816[ISO7816E] is set/enabled.
2022 #define BP_UART_C4_MAEN1 (7U) /*!< Bit position for UART_C4_MAEN1. */
2023 #define BM_UART_C4_MAEN1 (0x80U) /*!< Bit mask for UART_C4_MAEN1. */
2024 #define BS_UART_C4_MAEN1 (1U) /*!< Bit field size in bits for UART_C4_MAEN1. */
2026 /*! @brief Read current value of the UART_C4_MAEN1 field. */
2027 #define BR_UART_C4_MAEN1(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1))
2029 /*! @brief Format value for bitfield UART_C4_MAEN1. */
2030 #define BF_UART_C4_MAEN1(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_MAEN1) & BM_UART_C4_MAEN1)
2032 /*! @brief Set the MAEN1 field to a new value. */
2033 #define BW_UART_C4_MAEN1(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1) = (v))
2036 /*******************************************************************************
2037 * HW_UART_C5 - UART Control Register 5
2038 ******************************************************************************/
2041 * @brief HW_UART_C5 - UART Control Register 5 (RW)
2043 * Reset value: 0x00U
2045 typedef union _hw_uart_c5
2048 struct _hw_uart_c5_bitfields
2050 uint8_t RESERVED0 : 3; /*!< [2:0] */
2051 uint8_t LBKDDMAS : 1; /*!< [3] LIN Break Detect DMA Select Bit */
2052 uint8_t ILDMAS : 1; /*!< [4] Idle Line DMA Select */
2053 uint8_t RDMAS : 1; /*!< [5] Receiver Full DMA Select */
2054 uint8_t TCDMAS : 1; /*!< [6] Transmission Complete DMA Select */
2055 uint8_t TDMAS : 1; /*!< [7] Transmitter DMA Select */
2060 * @name Constants and macros for entire UART_C5 register
2063 #define HW_UART_C5_ADDR(x) ((x) + 0xBU)
2065 #define HW_UART_C5(x) (*(__IO hw_uart_c5_t *) HW_UART_C5_ADDR(x))
2066 #define HW_UART_C5_RD(x) (HW_UART_C5(x).U)
2067 #define HW_UART_C5_WR(x, v) (HW_UART_C5(x).U = (v))
2068 #define HW_UART_C5_SET(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) | (v)))
2069 #define HW_UART_C5_CLR(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) & ~(v)))
2070 #define HW_UART_C5_TOG(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) ^ (v)))
2074 * Constants & macros for individual UART_C5 bitfields
2078 * @name Register UART_C5, field LBKDDMAS[3] (RW)
2080 * Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or
2081 * DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is
2082 * set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless
2083 * of the state of LBKDDMAS.
2086 * - 0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is
2087 * asserted to request an interrupt service.
2088 * - 1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is
2089 * asserted to request a DMA transfer.
2092 #define BP_UART_C5_LBKDDMAS (3U) /*!< Bit position for UART_C5_LBKDDMAS. */
2093 #define BM_UART_C5_LBKDDMAS (0x08U) /*!< Bit mask for UART_C5_LBKDDMAS. */
2094 #define BS_UART_C5_LBKDDMAS (1U) /*!< Bit field size in bits for UART_C5_LBKDDMAS. */
2096 /*! @brief Read current value of the UART_C5_LBKDDMAS field. */
2097 #define BR_UART_C5_LBKDDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS))
2099 /*! @brief Format value for bitfield UART_C5_LBKDDMAS. */
2100 #define BF_UART_C5_LBKDDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_LBKDDMAS) & BM_UART_C5_LBKDDMAS)
2102 /*! @brief Set the LBKDDMAS field to a new value. */
2103 #define BW_UART_C5_LBKDDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS) = (v))
2107 * @name Register UART_C5, field ILDMAS[4] (RW)
2109 * Configures the idle line flag, S1[IDLE], to generate interrupt or DMA
2110 * requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE
2111 * DMA and IDLE interrupt request signals are not asserted, regardless of the state
2115 * - 0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is
2116 * asserted to request an interrupt service.
2117 * - 1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is
2118 * asserted to request a DMA transfer.
2121 #define BP_UART_C5_ILDMAS (4U) /*!< Bit position for UART_C5_ILDMAS. */
2122 #define BM_UART_C5_ILDMAS (0x10U) /*!< Bit mask for UART_C5_ILDMAS. */
2123 #define BS_UART_C5_ILDMAS (1U) /*!< Bit field size in bits for UART_C5_ILDMAS. */
2125 /*! @brief Read current value of the UART_C5_ILDMAS field. */
2126 #define BR_UART_C5_ILDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS))
2128 /*! @brief Format value for bitfield UART_C5_ILDMAS. */
2129 #define BF_UART_C5_ILDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_ILDMAS) & BM_UART_C5_ILDMAS)
2131 /*! @brief Set the ILDMAS field to a new value. */
2132 #define BW_UART_C5_ILDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS) = (v))
2136 * @name Register UART_C5, field RDMAS[5] (RW)
2138 * Configures the receiver data register full flag, S1[RDRF], to generate
2139 * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
2140 * set, the RDRF DMA and RDFR interrupt request signals are not asserted,
2141 * regardless of the state of RDMAS.
2144 * - 0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
2145 * asserted to request an interrupt service.
2146 * - 1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
2147 * asserted to request a DMA transfer.
2150 #define BP_UART_C5_RDMAS (5U) /*!< Bit position for UART_C5_RDMAS. */
2151 #define BM_UART_C5_RDMAS (0x20U) /*!< Bit mask for UART_C5_RDMAS. */
2152 #define BS_UART_C5_RDMAS (1U) /*!< Bit field size in bits for UART_C5_RDMAS. */
2154 /*! @brief Read current value of the UART_C5_RDMAS field. */
2155 #define BR_UART_C5_RDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS))
2157 /*! @brief Format value for bitfield UART_C5_RDMAS. */
2158 #define BF_UART_C5_RDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_RDMAS) & BM_UART_C5_RDMAS)
2160 /*! @brief Set the RDMAS field to a new value. */
2161 #define BW_UART_C5_RDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS) = (v))
2165 * @name Register UART_C5, field TCDMAS[6] (RW)
2167 * Configures the transmission complete flag, S1[TC], to generate interrupt or
2168 * DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC
2169 * interrupt request signals are not asserted when the S1[TC] flag is set, regardless
2170 * of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE]
2171 * must be cleared, and D must not be written unless a DMA request is being serviced.
2174 * - 0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request
2175 * signal is asserted to request an interrupt service.
2176 * - 1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request
2177 * signal is asserted to request a DMA transfer.
2180 #define BP_UART_C5_TCDMAS (6U) /*!< Bit position for UART_C5_TCDMAS. */
2181 #define BM_UART_C5_TCDMAS (0x40U) /*!< Bit mask for UART_C5_TCDMAS. */
2182 #define BS_UART_C5_TCDMAS (1U) /*!< Bit field size in bits for UART_C5_TCDMAS. */
2184 /*! @brief Read current value of the UART_C5_TCDMAS field. */
2185 #define BR_UART_C5_TCDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS))
2187 /*! @brief Format value for bitfield UART_C5_TCDMAS. */
2188 #define BF_UART_C5_TCDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_TCDMAS) & BM_UART_C5_TCDMAS)
2190 /*! @brief Set the TCDMAS field to a new value. */
2191 #define BW_UART_C5_TCDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS) = (v))
2195 * @name Register UART_C5, field TDMAS[7] (RW)
2197 * Configures the transmit data register empty flag, S1[TDRE], to generate
2198 * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
2199 * TDRE interrupt request signals are not asserted when the TDRE flag is set,
2200 * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
2201 * must be cleared, and D must not be written unless a DMA request is being
2205 * - 0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
2206 * request signal is asserted to request interrupt service.
2207 * - 1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
2208 * signal is asserted to request a DMA transfer.
2211 #define BP_UART_C5_TDMAS (7U) /*!< Bit position for UART_C5_TDMAS. */
2212 #define BM_UART_C5_TDMAS (0x80U) /*!< Bit mask for UART_C5_TDMAS. */
2213 #define BS_UART_C5_TDMAS (1U) /*!< Bit field size in bits for UART_C5_TDMAS. */
2215 /*! @brief Read current value of the UART_C5_TDMAS field. */
2216 #define BR_UART_C5_TDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS))
2218 /*! @brief Format value for bitfield UART_C5_TDMAS. */
2219 #define BF_UART_C5_TDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_TDMAS) & BM_UART_C5_TDMAS)
2221 /*! @brief Set the TDMAS field to a new value. */
2222 #define BW_UART_C5_TDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS) = (v))
2225 /*******************************************************************************
2226 * HW_UART_ED - UART Extended Data Register
2227 ******************************************************************************/
2230 * @brief HW_UART_ED - UART Extended Data Register (RO)
2232 * Reset value: 0x00U
2234 * This register contains additional information flags that are stored with a
2235 * received dataword. This register may be read at any time but contains valid data
2236 * only if there is a dataword in the receive FIFO. The data contained in this
2237 * register represents additional information regarding the conditions on which a
2238 * dataword was received. The importance of this data varies with the
2239 * application, and in some cases maybe completely optional. These fields automatically
2240 * update to reflect the conditions of the next dataword whenever D is read. If
2241 * S1[NF] and S1[PF] have not been set since the last time the receive buffer was
2242 * empty, the NOISY and PARITYE fields will be zero.
2244 typedef union _hw_uart_ed
2247 struct _hw_uart_ed_bitfields
2249 uint8_t RESERVED0 : 6; /*!< [5:0] */
2250 uint8_t PARITYE : 1; /*!< [6] */
2251 uint8_t NOISY : 1; /*!< [7] */
2256 * @name Constants and macros for entire UART_ED register
2259 #define HW_UART_ED_ADDR(x) ((x) + 0xCU)
2261 #define HW_UART_ED(x) (*(__I hw_uart_ed_t *) HW_UART_ED_ADDR(x))
2262 #define HW_UART_ED_RD(x) (HW_UART_ED(x).U)
2266 * Constants & macros for individual UART_ED bitfields
2270 * @name Register UART_ED, field PARITYE[6] (RO)
2272 * The current received dataword contained in D and C3[R8] was received with a
2276 * - 0 - The dataword was received without a parity error.
2277 * - 1 - The dataword was received with a parity error.
2280 #define BP_UART_ED_PARITYE (6U) /*!< Bit position for UART_ED_PARITYE. */
2281 #define BM_UART_ED_PARITYE (0x40U) /*!< Bit mask for UART_ED_PARITYE. */
2282 #define BS_UART_ED_PARITYE (1U) /*!< Bit field size in bits for UART_ED_PARITYE. */
2284 /*! @brief Read current value of the UART_ED_PARITYE field. */
2285 #define BR_UART_ED_PARITYE(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_PARITYE))
2289 * @name Register UART_ED, field NOISY[7] (RO)
2291 * The current received dataword contained in D and C3[R8] was received with
2295 * - 0 - The dataword was received without noise.
2296 * - 1 - The data was received with noise.
2299 #define BP_UART_ED_NOISY (7U) /*!< Bit position for UART_ED_NOISY. */
2300 #define BM_UART_ED_NOISY (0x80U) /*!< Bit mask for UART_ED_NOISY. */
2301 #define BS_UART_ED_NOISY (1U) /*!< Bit field size in bits for UART_ED_NOISY. */
2303 /*! @brief Read current value of the UART_ED_NOISY field. */
2304 #define BR_UART_ED_NOISY(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_NOISY))
2307 /*******************************************************************************
2308 * HW_UART_MODEM - UART Modem Register
2309 ******************************************************************************/
2312 * @brief HW_UART_MODEM - UART Modem Register (RW)
2314 * Reset value: 0x00U
2316 * The MODEM register controls options for setting the modem configuration.
2317 * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is
2318 * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The
2319 * ISO-7816 protocol does not use the RTS and CTS signals.
2321 typedef union _hw_uart_modem
2324 struct _hw_uart_modem_bitfields
2326 uint8_t TXCTSE : 1; /*!< [0] Transmitter clear-to-send enable */
2327 uint8_t TXRTSE : 1; /*!< [1] Transmitter request-to-send enable */
2328 uint8_t TXRTSPOL : 1; /*!< [2] Transmitter request-to-send polarity */
2329 uint8_t RXRTSE : 1; /*!< [3] Receiver request-to-send enable */
2330 uint8_t RESERVED0 : 4; /*!< [7:4] */
2335 * @name Constants and macros for entire UART_MODEM register
2338 #define HW_UART_MODEM_ADDR(x) ((x) + 0xDU)
2340 #define HW_UART_MODEM(x) (*(__IO hw_uart_modem_t *) HW_UART_MODEM_ADDR(x))
2341 #define HW_UART_MODEM_RD(x) (HW_UART_MODEM(x).U)
2342 #define HW_UART_MODEM_WR(x, v) (HW_UART_MODEM(x).U = (v))
2343 #define HW_UART_MODEM_SET(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) | (v)))
2344 #define HW_UART_MODEM_CLR(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) & ~(v)))
2345 #define HW_UART_MODEM_TOG(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) ^ (v)))
2349 * Constants & macros for individual UART_MODEM bitfields
2353 * @name Register UART_MODEM, field TXCTSE[0] (RW)
2355 * TXCTSE controls the operation of the transmitter. TXCTSE can be set
2356 * independently from the state of TXRTSE and RXRTSE.
2359 * - 0 - CTS has no effect on the transmitter.
2360 * - 1 - Enables clear-to-send operation. The transmitter checks the state of
2361 * CTS each time it is ready to send a character. If CTS is asserted, the
2362 * character is sent. If CTS is deasserted, the signal TXD remains in the mark
2363 * state and transmission is delayed until CTS is asserted. Changes in CTS as a
2364 * character is being sent do not affect its transmission.
2367 #define BP_UART_MODEM_TXCTSE (0U) /*!< Bit position for UART_MODEM_TXCTSE. */
2368 #define BM_UART_MODEM_TXCTSE (0x01U) /*!< Bit mask for UART_MODEM_TXCTSE. */
2369 #define BS_UART_MODEM_TXCTSE (1U) /*!< Bit field size in bits for UART_MODEM_TXCTSE. */
2371 /*! @brief Read current value of the UART_MODEM_TXCTSE field. */
2372 #define BR_UART_MODEM_TXCTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE))
2374 /*! @brief Format value for bitfield UART_MODEM_TXCTSE. */
2375 #define BF_UART_MODEM_TXCTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXCTSE) & BM_UART_MODEM_TXCTSE)
2377 /*! @brief Set the TXCTSE field to a new value. */
2378 #define BW_UART_MODEM_TXCTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE) = (v))
2382 * @name Register UART_MODEM, field TXRTSE[1] (RW)
2384 * Controls RTS before and after a transmission.
2387 * - 0 - The transmitter has no effect on RTS.
2388 * - 1 - When a character is placed into an empty transmitter data buffer , RTS
2389 * asserts one bit time before the start bit is transmitted. RTS deasserts
2390 * one bit time after all characters in the transmitter data buffer and shift
2391 * register are completely sent, including the last stop bit. (FIFO) (FIFO)
2394 #define BP_UART_MODEM_TXRTSE (1U) /*!< Bit position for UART_MODEM_TXRTSE. */
2395 #define BM_UART_MODEM_TXRTSE (0x02U) /*!< Bit mask for UART_MODEM_TXRTSE. */
2396 #define BS_UART_MODEM_TXRTSE (1U) /*!< Bit field size in bits for UART_MODEM_TXRTSE. */
2398 /*! @brief Read current value of the UART_MODEM_TXRTSE field. */
2399 #define BR_UART_MODEM_TXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE))
2401 /*! @brief Format value for bitfield UART_MODEM_TXRTSE. */
2402 #define BF_UART_MODEM_TXRTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXRTSE) & BM_UART_MODEM_TXRTSE)
2404 /*! @brief Set the TXRTSE field to a new value. */
2405 #define BW_UART_MODEM_TXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE) = (v))
2409 * @name Register UART_MODEM, field TXRTSPOL[2] (RW)
2411 * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
2412 * polarity of the receiver RTS. RTS will remain negated in the active low state
2413 * unless TXRTSE is set.
2416 * - 0 - Transmitter RTS is active low.
2417 * - 1 - Transmitter RTS is active high.
2420 #define BP_UART_MODEM_TXRTSPOL (2U) /*!< Bit position for UART_MODEM_TXRTSPOL. */
2421 #define BM_UART_MODEM_TXRTSPOL (0x04U) /*!< Bit mask for UART_MODEM_TXRTSPOL. */
2422 #define BS_UART_MODEM_TXRTSPOL (1U) /*!< Bit field size in bits for UART_MODEM_TXRTSPOL. */
2424 /*! @brief Read current value of the UART_MODEM_TXRTSPOL field. */
2425 #define BR_UART_MODEM_TXRTSPOL(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL))
2427 /*! @brief Format value for bitfield UART_MODEM_TXRTSPOL. */
2428 #define BF_UART_MODEM_TXRTSPOL(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXRTSPOL) & BM_UART_MODEM_TXRTSPOL)
2430 /*! @brief Set the TXRTSPOL field to a new value. */
2431 #define BW_UART_MODEM_TXRTSPOL(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL) = (v))
2435 * @name Register UART_MODEM, field RXRTSE[3] (RW)
2437 * Allows the RTS output to control the CTS input of the transmitting device to
2438 * prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
2441 * - 0 - The receiver has no effect on RTS.
2442 * - 1 - RTS is deasserted if the number of characters in the receiver data
2443 * register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted
2444 * when the number of characters in the receiver data register (FIFO) is less
2445 * than RWFIFO[RXWATER].
2448 #define BP_UART_MODEM_RXRTSE (3U) /*!< Bit position for UART_MODEM_RXRTSE. */
2449 #define BM_UART_MODEM_RXRTSE (0x08U) /*!< Bit mask for UART_MODEM_RXRTSE. */
2450 #define BS_UART_MODEM_RXRTSE (1U) /*!< Bit field size in bits for UART_MODEM_RXRTSE. */
2452 /*! @brief Read current value of the UART_MODEM_RXRTSE field. */
2453 #define BR_UART_MODEM_RXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE))
2455 /*! @brief Format value for bitfield UART_MODEM_RXRTSE. */
2456 #define BF_UART_MODEM_RXRTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_RXRTSE) & BM_UART_MODEM_RXRTSE)
2458 /*! @brief Set the RXRTSE field to a new value. */
2459 #define BW_UART_MODEM_RXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE) = (v))
2462 /*******************************************************************************
2463 * HW_UART_IR - UART Infrared Register
2464 ******************************************************************************/
2467 * @brief HW_UART_IR - UART Infrared Register (RW)
2469 * Reset value: 0x00U
2471 * The IR register controls options for setting the infrared configuration.
2473 typedef union _hw_uart_ir
2476 struct _hw_uart_ir_bitfields
2478 uint8_t TNP : 2; /*!< [1:0] Transmitter narrow pulse */
2479 uint8_t IREN : 1; /*!< [2] Infrared enable */
2480 uint8_t RESERVED0 : 5; /*!< [7:3] */
2485 * @name Constants and macros for entire UART_IR register
2488 #define HW_UART_IR_ADDR(x) ((x) + 0xEU)
2490 #define HW_UART_IR(x) (*(__IO hw_uart_ir_t *) HW_UART_IR_ADDR(x))
2491 #define HW_UART_IR_RD(x) (HW_UART_IR(x).U)
2492 #define HW_UART_IR_WR(x, v) (HW_UART_IR(x).U = (v))
2493 #define HW_UART_IR_SET(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) | (v)))
2494 #define HW_UART_IR_CLR(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) & ~(v)))
2495 #define HW_UART_IR_TOG(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) ^ (v)))
2499 * Constants & macros for individual UART_IR bitfields
2503 * @name Register UART_IR, field TNP[1:0] (RW)
2505 * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse.
2514 #define BP_UART_IR_TNP (0U) /*!< Bit position for UART_IR_TNP. */
2515 #define BM_UART_IR_TNP (0x03U) /*!< Bit mask for UART_IR_TNP. */
2516 #define BS_UART_IR_TNP (2U) /*!< Bit field size in bits for UART_IR_TNP. */
2518 /*! @brief Read current value of the UART_IR_TNP field. */
2519 #define BR_UART_IR_TNP(x) (HW_UART_IR(x).B.TNP)
2521 /*! @brief Format value for bitfield UART_IR_TNP. */
2522 #define BF_UART_IR_TNP(v) ((uint8_t)((uint8_t)(v) << BP_UART_IR_TNP) & BM_UART_IR_TNP)
2524 /*! @brief Set the TNP field to a new value. */
2525 #define BW_UART_IR_TNP(x, v) (HW_UART_IR_WR(x, (HW_UART_IR_RD(x) & ~BM_UART_IR_TNP) | BF_UART_IR_TNP(v)))
2529 * @name Register UART_IR, field IREN[2] (RW)
2531 * Enables/disables the infrared modulation/demodulation.
2534 * - 0 - IR disabled.
2538 #define BP_UART_IR_IREN (2U) /*!< Bit position for UART_IR_IREN. */
2539 #define BM_UART_IR_IREN (0x04U) /*!< Bit mask for UART_IR_IREN. */
2540 #define BS_UART_IR_IREN (1U) /*!< Bit field size in bits for UART_IR_IREN. */
2542 /*! @brief Read current value of the UART_IR_IREN field. */
2543 #define BR_UART_IR_IREN(x) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN))
2545 /*! @brief Format value for bitfield UART_IR_IREN. */
2546 #define BF_UART_IR_IREN(v) ((uint8_t)((uint8_t)(v) << BP_UART_IR_IREN) & BM_UART_IR_IREN)
2548 /*! @brief Set the IREN field to a new value. */
2549 #define BW_UART_IR_IREN(x, v) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN) = (v))
2552 /*******************************************************************************
2553 * HW_UART_PFIFO - UART FIFO Parameters
2554 ******************************************************************************/
2557 * @brief HW_UART_PFIFO - UART FIFO Parameters (RW)
2559 * Reset value: 0x00U
2561 * This register provides the ability for the programmer to turn on and off FIFO
2562 * functionality. It also provides the size of the FIFO that has been
2563 * implemented. This register may be read at any time. This register must be written only
2564 * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is
2567 typedef union _hw_uart_pfifo
2570 struct _hw_uart_pfifo_bitfields
2572 uint8_t RXFIFOSIZE : 3; /*!< [2:0] Receive FIFO. Buffer Depth */
2573 uint8_t RXFE : 1; /*!< [3] Receive FIFO Enable */
2574 uint8_t TXFIFOSIZE : 3; /*!< [6:4] Transmit FIFO. Buffer Depth */
2575 uint8_t TXFE : 1; /*!< [7] Transmit FIFO Enable */
2580 * @name Constants and macros for entire UART_PFIFO register
2583 #define HW_UART_PFIFO_ADDR(x) ((x) + 0x10U)
2585 #define HW_UART_PFIFO(x) (*(__IO hw_uart_pfifo_t *) HW_UART_PFIFO_ADDR(x))
2586 #define HW_UART_PFIFO_RD(x) (HW_UART_PFIFO(x).U)
2587 #define HW_UART_PFIFO_WR(x, v) (HW_UART_PFIFO(x).U = (v))
2588 #define HW_UART_PFIFO_SET(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) | (v)))
2589 #define HW_UART_PFIFO_CLR(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) & ~(v)))
2590 #define HW_UART_PFIFO_TOG(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) ^ (v)))
2594 * Constants & macros for individual UART_PFIFO bitfields
2598 * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO)
2600 * The maximum number of receive datawords that can be stored in the receive
2601 * buffer before an overrun occurs. This field is read only.
2604 * - 000 - Receive FIFO/Buffer depth = 1 dataword.
2605 * - 001 - Receive FIFO/Buffer depth = 4 datawords.
2606 * - 010 - Receive FIFO/Buffer depth = 8 datawords.
2607 * - 011 - Receive FIFO/Buffer depth = 16 datawords.
2608 * - 100 - Receive FIFO/Buffer depth = 32 datawords.
2609 * - 101 - Receive FIFO/Buffer depth = 64 datawords.
2610 * - 110 - Receive FIFO/Buffer depth = 128 datawords.
2614 #define BP_UART_PFIFO_RXFIFOSIZE (0U) /*!< Bit position for UART_PFIFO_RXFIFOSIZE. */
2615 #define BM_UART_PFIFO_RXFIFOSIZE (0x07U) /*!< Bit mask for UART_PFIFO_RXFIFOSIZE. */
2616 #define BS_UART_PFIFO_RXFIFOSIZE (3U) /*!< Bit field size in bits for UART_PFIFO_RXFIFOSIZE. */
2618 /*! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field. */
2619 #define BR_UART_PFIFO_RXFIFOSIZE(x) (HW_UART_PFIFO(x).B.RXFIFOSIZE)
2623 * @name Register UART_PFIFO, field RXFE[3] (RW)
2625 * When this field is set, the built in FIFO structure for the receive buffer is
2626 * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field.
2627 * If this field is not set, the receive buffer operates as a FIFO of depth one
2628 * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
2629 * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH
2630 * commands must be issued immediately after changing this field.
2633 * - 0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
2634 * - 1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
2637 #define BP_UART_PFIFO_RXFE (3U) /*!< Bit position for UART_PFIFO_RXFE. */
2638 #define BM_UART_PFIFO_RXFE (0x08U) /*!< Bit mask for UART_PFIFO_RXFE. */
2639 #define BS_UART_PFIFO_RXFE (1U) /*!< Bit field size in bits for UART_PFIFO_RXFE. */
2641 /*! @brief Read current value of the UART_PFIFO_RXFE field. */
2642 #define BR_UART_PFIFO_RXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE))
2644 /*! @brief Format value for bitfield UART_PFIFO_RXFE. */
2645 #define BF_UART_PFIFO_RXFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_PFIFO_RXFE) & BM_UART_PFIFO_RXFE)
2647 /*! @brief Set the RXFE field to a new value. */
2648 #define BW_UART_PFIFO_RXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE) = (v))
2652 * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO)
2654 * The maximum number of transmit datawords that can be stored in the transmit
2655 * buffer. This field is read only.
2658 * - 000 - Transmit FIFO/Buffer depth = 1 dataword.
2659 * - 001 - Transmit FIFO/Buffer depth = 4 datawords.
2660 * - 010 - Transmit FIFO/Buffer depth = 8 datawords.
2661 * - 011 - Transmit FIFO/Buffer depth = 16 datawords.
2662 * - 100 - Transmit FIFO/Buffer depth = 32 datawords.
2663 * - 101 - Transmit FIFO/Buffer depth = 64 datawords.
2664 * - 110 - Transmit FIFO/Buffer depth = 128 datawords.
2668 #define BP_UART_PFIFO_TXFIFOSIZE (4U) /*!< Bit position for UART_PFIFO_TXFIFOSIZE. */
2669 #define BM_UART_PFIFO_TXFIFOSIZE (0x70U) /*!< Bit mask for UART_PFIFO_TXFIFOSIZE. */
2670 #define BS_UART_PFIFO_TXFIFOSIZE (3U) /*!< Bit field size in bits for UART_PFIFO_TXFIFOSIZE. */
2672 /*! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field. */
2673 #define BR_UART_PFIFO_TXFIFOSIZE(x) (HW_UART_PFIFO(x).B.TXFIFOSIZE)
2677 * @name Register UART_PFIFO, field TXFE[7] (RW)
2679 * When this field is set, the built in FIFO structure for the transmit buffer
2680 * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this
2681 * field is not set, the transmit buffer operates as a FIFO of depth one dataword
2682 * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared
2683 * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must
2684 * be issued immediately after changing this field.
2687 * - 0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
2688 * - 1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
2691 #define BP_UART_PFIFO_TXFE (7U) /*!< Bit position for UART_PFIFO_TXFE. */
2692 #define BM_UART_PFIFO_TXFE (0x80U) /*!< Bit mask for UART_PFIFO_TXFE. */
2693 #define BS_UART_PFIFO_TXFE (1U) /*!< Bit field size in bits for UART_PFIFO_TXFE. */
2695 /*! @brief Read current value of the UART_PFIFO_TXFE field. */
2696 #define BR_UART_PFIFO_TXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE))
2698 /*! @brief Format value for bitfield UART_PFIFO_TXFE. */
2699 #define BF_UART_PFIFO_TXFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_PFIFO_TXFE) & BM_UART_PFIFO_TXFE)
2701 /*! @brief Set the TXFE field to a new value. */
2702 #define BW_UART_PFIFO_TXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE) = (v))
2705 /*******************************************************************************
2706 * HW_UART_CFIFO - UART FIFO Control Register
2707 ******************************************************************************/
2710 * @brief HW_UART_CFIFO - UART FIFO Control Register (RW)
2712 * Reset value: 0x00U
2714 * This register provides the ability to program various control fields for FIFO
2715 * operation. This register may be read or written at any time. Note that
2716 * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action
2717 * to prevent unintended/unpredictable behavior. Therefore, it is recommended that
2718 * TE and RE be cleared prior to flushing the corresponding FIFO.
2720 typedef union _hw_uart_cfifo
2723 struct _hw_uart_cfifo_bitfields
2725 uint8_t RXUFE : 1; /*!< [0] Receive FIFO Underflow Interrupt Enable */
2726 uint8_t TXOFE : 1; /*!< [1] Transmit FIFO Overflow Interrupt Enable */
2727 uint8_t RXOFE : 1; /*!< [2] Receive FIFO Overflow Interrupt Enable */
2728 uint8_t RESERVED0 : 3; /*!< [5:3] */
2729 uint8_t RXFLUSH : 1; /*!< [6] Receive FIFO/Buffer Flush */
2730 uint8_t TXFLUSH : 1; /*!< [7] Transmit FIFO/Buffer Flush */
2735 * @name Constants and macros for entire UART_CFIFO register
2738 #define HW_UART_CFIFO_ADDR(x) ((x) + 0x11U)
2740 #define HW_UART_CFIFO(x) (*(__IO hw_uart_cfifo_t *) HW_UART_CFIFO_ADDR(x))
2741 #define HW_UART_CFIFO_RD(x) (HW_UART_CFIFO(x).U)
2742 #define HW_UART_CFIFO_WR(x, v) (HW_UART_CFIFO(x).U = (v))
2743 #define HW_UART_CFIFO_SET(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) | (v)))
2744 #define HW_UART_CFIFO_CLR(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) & ~(v)))
2745 #define HW_UART_CFIFO_TOG(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) ^ (v)))
2749 * Constants & macros for individual UART_CFIFO bitfields
2753 * @name Register UART_CFIFO, field RXUFE[0] (RW)
2755 * When this field is set, the RXUF flag generates an interrupt to the host.
2758 * - 0 - RXUF flag does not generate an interrupt to the host.
2759 * - 1 - RXUF flag generates an interrupt to the host.
2762 #define BP_UART_CFIFO_RXUFE (0U) /*!< Bit position for UART_CFIFO_RXUFE. */
2763 #define BM_UART_CFIFO_RXUFE (0x01U) /*!< Bit mask for UART_CFIFO_RXUFE. */
2764 #define BS_UART_CFIFO_RXUFE (1U) /*!< Bit field size in bits for UART_CFIFO_RXUFE. */
2766 /*! @brief Read current value of the UART_CFIFO_RXUFE field. */
2767 #define BR_UART_CFIFO_RXUFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE))
2769 /*! @brief Format value for bitfield UART_CFIFO_RXUFE. */
2770 #define BF_UART_CFIFO_RXUFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXUFE) & BM_UART_CFIFO_RXUFE)
2772 /*! @brief Set the RXUFE field to a new value. */
2773 #define BW_UART_CFIFO_RXUFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE) = (v))
2777 * @name Register UART_CFIFO, field TXOFE[1] (RW)
2779 * When this field is set, the TXOF flag generates an interrupt to the host.
2782 * - 0 - TXOF flag does not generate an interrupt to the host.
2783 * - 1 - TXOF flag generates an interrupt to the host.
2786 #define BP_UART_CFIFO_TXOFE (1U) /*!< Bit position for UART_CFIFO_TXOFE. */
2787 #define BM_UART_CFIFO_TXOFE (0x02U) /*!< Bit mask for UART_CFIFO_TXOFE. */
2788 #define BS_UART_CFIFO_TXOFE (1U) /*!< Bit field size in bits for UART_CFIFO_TXOFE. */
2790 /*! @brief Read current value of the UART_CFIFO_TXOFE field. */
2791 #define BR_UART_CFIFO_TXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE))
2793 /*! @brief Format value for bitfield UART_CFIFO_TXOFE. */
2794 #define BF_UART_CFIFO_TXOFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_TXOFE) & BM_UART_CFIFO_TXOFE)
2796 /*! @brief Set the TXOFE field to a new value. */
2797 #define BW_UART_CFIFO_TXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE) = (v))
2801 * @name Register UART_CFIFO, field RXOFE[2] (RW)
2803 * When this field is set, the RXOF flag generates an interrupt to the host.
2806 * - 0 - RXOF flag does not generate an interrupt to the host.
2807 * - 1 - RXOF flag generates an interrupt to the host.
2810 #define BP_UART_CFIFO_RXOFE (2U) /*!< Bit position for UART_CFIFO_RXOFE. */
2811 #define BM_UART_CFIFO_RXOFE (0x04U) /*!< Bit mask for UART_CFIFO_RXOFE. */
2812 #define BS_UART_CFIFO_RXOFE (1U) /*!< Bit field size in bits for UART_CFIFO_RXOFE. */
2814 /*! @brief Read current value of the UART_CFIFO_RXOFE field. */
2815 #define BR_UART_CFIFO_RXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE))
2817 /*! @brief Format value for bitfield UART_CFIFO_RXOFE. */
2818 #define BF_UART_CFIFO_RXOFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXOFE) & BM_UART_CFIFO_RXOFE)
2820 /*! @brief Set the RXOFE field to a new value. */
2821 #define BW_UART_CFIFO_RXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE) = (v))
2825 * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ)
2827 * Writing to this field causes all data that is stored in the receive
2828 * FIFO/buffer to be flushed. This does not affect data that is in the receive shift
2832 * - 0 - No flush operation occurs.
2833 * - 1 - All data in the receive FIFO/buffer is cleared out.
2836 #define BP_UART_CFIFO_RXFLUSH (6U) /*!< Bit position for UART_CFIFO_RXFLUSH. */
2837 #define BM_UART_CFIFO_RXFLUSH (0x40U) /*!< Bit mask for UART_CFIFO_RXFLUSH. */
2838 #define BS_UART_CFIFO_RXFLUSH (1U) /*!< Bit field size in bits for UART_CFIFO_RXFLUSH. */
2840 /*! @brief Format value for bitfield UART_CFIFO_RXFLUSH. */
2841 #define BF_UART_CFIFO_RXFLUSH(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXFLUSH) & BM_UART_CFIFO_RXFLUSH)
2843 /*! @brief Set the RXFLUSH field to a new value. */
2844 #define BW_UART_CFIFO_RXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXFLUSH) = (v))
2848 * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ)
2850 * Writing to this field causes all data that is stored in the transmit
2851 * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift
2855 * - 0 - No flush operation occurs.
2856 * - 1 - All data in the transmit FIFO/Buffer is cleared out.
2859 #define BP_UART_CFIFO_TXFLUSH (7U) /*!< Bit position for UART_CFIFO_TXFLUSH. */
2860 #define BM_UART_CFIFO_TXFLUSH (0x80U) /*!< Bit mask for UART_CFIFO_TXFLUSH. */
2861 #define BS_UART_CFIFO_TXFLUSH (1U) /*!< Bit field size in bits for UART_CFIFO_TXFLUSH. */
2863 /*! @brief Format value for bitfield UART_CFIFO_TXFLUSH. */
2864 #define BF_UART_CFIFO_TXFLUSH(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_TXFLUSH) & BM_UART_CFIFO_TXFLUSH)
2866 /*! @brief Set the TXFLUSH field to a new value. */
2867 #define BW_UART_CFIFO_TXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXFLUSH) = (v))
2870 /*******************************************************************************
2871 * HW_UART_SFIFO - UART FIFO Status Register
2872 ******************************************************************************/
2875 * @brief HW_UART_SFIFO - UART FIFO Status Register (RW)
2877 * Reset value: 0xC0U
2879 * This register provides status information regarding the transmit and receiver
2880 * buffers/FIFOs, including interrupt information. This register may be written
2881 * to or read at any time.
2883 typedef union _hw_uart_sfifo
2886 struct _hw_uart_sfifo_bitfields
2888 uint8_t RXUF : 1; /*!< [0] Receiver Buffer Underflow Flag */
2889 uint8_t TXOF : 1; /*!< [1] Transmitter Buffer Overflow Flag */
2890 uint8_t RXOF : 1; /*!< [2] Receiver Buffer Overflow Flag */
2891 uint8_t RESERVED0 : 3; /*!< [5:3] */
2892 uint8_t RXEMPT : 1; /*!< [6] Receive Buffer/FIFO Empty */
2893 uint8_t TXEMPT : 1; /*!< [7] Transmit Buffer/FIFO Empty */
2898 * @name Constants and macros for entire UART_SFIFO register
2901 #define HW_UART_SFIFO_ADDR(x) ((x) + 0x12U)
2903 #define HW_UART_SFIFO(x) (*(__IO hw_uart_sfifo_t *) HW_UART_SFIFO_ADDR(x))
2904 #define HW_UART_SFIFO_RD(x) (HW_UART_SFIFO(x).U)
2905 #define HW_UART_SFIFO_WR(x, v) (HW_UART_SFIFO(x).U = (v))
2906 #define HW_UART_SFIFO_SET(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) | (v)))
2907 #define HW_UART_SFIFO_CLR(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) & ~(v)))
2908 #define HW_UART_SFIFO_TOG(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) ^ (v)))
2912 * Constants & macros for individual UART_SFIFO bitfields
2916 * @name Register UART_SFIFO, field RXUF[0] (W1C)
2918 * Indicates that more data has been read from the receive buffer than was
2919 * present. This field will assert regardless of the value of CFIFO[RXUFE]. However,
2920 * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag
2921 * is cleared by writing a 1.
2924 * - 0 - No receive buffer underflow has occurred since the last time the flag
2926 * - 1 - At least one receive buffer underflow has occurred since the last time
2927 * the flag was cleared.
2930 #define BP_UART_SFIFO_RXUF (0U) /*!< Bit position for UART_SFIFO_RXUF. */
2931 #define BM_UART_SFIFO_RXUF (0x01U) /*!< Bit mask for UART_SFIFO_RXUF. */
2932 #define BS_UART_SFIFO_RXUF (1U) /*!< Bit field size in bits for UART_SFIFO_RXUF. */
2934 /*! @brief Read current value of the UART_SFIFO_RXUF field. */
2935 #define BR_UART_SFIFO_RXUF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF))
2937 /*! @brief Format value for bitfield UART_SFIFO_RXUF. */
2938 #define BF_UART_SFIFO_RXUF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_RXUF) & BM_UART_SFIFO_RXUF)
2940 /*! @brief Set the RXUF field to a new value. */
2941 #define BW_UART_SFIFO_RXUF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF) = (v))
2945 * @name Register UART_SFIFO, field TXOF[1] (W1C)
2947 * Indicates that more data has been written to the transmit buffer than it can
2948 * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However,
2949 * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This
2950 * flag is cleared by writing a 1.
2953 * - 0 - No transmit buffer overflow has occurred since the last time the flag
2955 * - 1 - At least one transmit buffer overflow has occurred since the last time
2956 * the flag was cleared.
2959 #define BP_UART_SFIFO_TXOF (1U) /*!< Bit position for UART_SFIFO_TXOF. */
2960 #define BM_UART_SFIFO_TXOF (0x02U) /*!< Bit mask for UART_SFIFO_TXOF. */
2961 #define BS_UART_SFIFO_TXOF (1U) /*!< Bit field size in bits for UART_SFIFO_TXOF. */
2963 /*! @brief Read current value of the UART_SFIFO_TXOF field. */
2964 #define BR_UART_SFIFO_TXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF))
2966 /*! @brief Format value for bitfield UART_SFIFO_TXOF. */
2967 #define BF_UART_SFIFO_TXOF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_TXOF) & BM_UART_SFIFO_TXOF)
2969 /*! @brief Set the TXOF field to a new value. */
2970 #define BW_UART_SFIFO_TXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF) = (v))
2974 * @name Register UART_SFIFO, field RXOF[2] (W1C)
2976 * Indicates that more data has been written to the receive buffer than it can
2977 * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However,
2978 * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag
2979 * is cleared by writing a 1.
2982 * - 0 - No receive buffer overflow has occurred since the last time the flag
2984 * - 1 - At least one receive buffer overflow has occurred since the last time
2985 * the flag was cleared.
2988 #define BP_UART_SFIFO_RXOF (2U) /*!< Bit position for UART_SFIFO_RXOF. */
2989 #define BM_UART_SFIFO_RXOF (0x04U) /*!< Bit mask for UART_SFIFO_RXOF. */
2990 #define BS_UART_SFIFO_RXOF (1U) /*!< Bit field size in bits for UART_SFIFO_RXOF. */
2992 /*! @brief Read current value of the UART_SFIFO_RXOF field. */
2993 #define BR_UART_SFIFO_RXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF))
2995 /*! @brief Format value for bitfield UART_SFIFO_RXOF. */
2996 #define BF_UART_SFIFO_RXOF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_RXOF) & BM_UART_SFIFO_RXOF)
2998 /*! @brief Set the RXOF field to a new value. */
2999 #define BW_UART_SFIFO_RXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF) = (v))
3003 * @name Register UART_SFIFO, field RXEMPT[6] (RO)
3005 * Asserts when there is no data in the receive FIFO/Buffer. This field does not
3006 * take into account data that is in the receive shift register.
3009 * - 0 - Receive buffer is not empty.
3010 * - 1 - Receive buffer is empty.
3013 #define BP_UART_SFIFO_RXEMPT (6U) /*!< Bit position for UART_SFIFO_RXEMPT. */
3014 #define BM_UART_SFIFO_RXEMPT (0x40U) /*!< Bit mask for UART_SFIFO_RXEMPT. */
3015 #define BS_UART_SFIFO_RXEMPT (1U) /*!< Bit field size in bits for UART_SFIFO_RXEMPT. */
3017 /*! @brief Read current value of the UART_SFIFO_RXEMPT field. */
3018 #define BR_UART_SFIFO_RXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXEMPT))
3022 * @name Register UART_SFIFO, field TXEMPT[7] (RO)
3024 * Asserts when there is no data in the Transmit FIFO/buffer. This field does
3025 * not take into account data that is in the transmit shift register.
3028 * - 0 - Transmit buffer is not empty.
3029 * - 1 - Transmit buffer is empty.
3032 #define BP_UART_SFIFO_TXEMPT (7U) /*!< Bit position for UART_SFIFO_TXEMPT. */
3033 #define BM_UART_SFIFO_TXEMPT (0x80U) /*!< Bit mask for UART_SFIFO_TXEMPT. */
3034 #define BS_UART_SFIFO_TXEMPT (1U) /*!< Bit field size in bits for UART_SFIFO_TXEMPT. */
3036 /*! @brief Read current value of the UART_SFIFO_TXEMPT field. */
3037 #define BR_UART_SFIFO_TXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXEMPT))
3040 /*******************************************************************************
3041 * HW_UART_TWFIFO - UART FIFO Transmit Watermark
3042 ******************************************************************************/
3045 * @brief HW_UART_TWFIFO - UART FIFO Transmit Watermark (RW)
3047 * Reset value: 0x00U
3049 * This register provides the ability to set a programmable threshold for
3050 * notification of needing additional transmit data. This register may be read at any
3051 * time but must be written only when C2[TE] is not set. Changing the value of the
3052 * watermark will not clear the S1[TDRE] flag.
3054 typedef union _hw_uart_twfifo
3057 struct _hw_uart_twfifo_bitfields
3059 uint8_t TXWATER : 8; /*!< [7:0] Transmit Watermark */
3064 * @name Constants and macros for entire UART_TWFIFO register
3067 #define HW_UART_TWFIFO_ADDR(x) ((x) + 0x13U)
3069 #define HW_UART_TWFIFO(x) (*(__IO hw_uart_twfifo_t *) HW_UART_TWFIFO_ADDR(x))
3070 #define HW_UART_TWFIFO_RD(x) (HW_UART_TWFIFO(x).U)
3071 #define HW_UART_TWFIFO_WR(x, v) (HW_UART_TWFIFO(x).U = (v))
3072 #define HW_UART_TWFIFO_SET(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) | (v)))
3073 #define HW_UART_TWFIFO_CLR(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) & ~(v)))
3074 #define HW_UART_TWFIFO_TOG(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) ^ (v)))
3078 * Constants & macros for individual UART_TWFIFO bitfields
3082 * @name Register UART_TWFIFO, field TXWATER[7:0] (RW)
3084 * When the number of datawords in the transmit FIFO/buffer is equal to or less
3085 * than the value in this register field, an interrupt via S1[TDRE] or a DMA
3086 * request via C5[TDMAS] is generated as determined by C5[TDMAS] and C2[TIE]. For
3087 * proper operation, the value in TXWATER must be set to be less than the size of
3088 * the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE].
3091 #define BP_UART_TWFIFO_TXWATER (0U) /*!< Bit position for UART_TWFIFO_TXWATER. */
3092 #define BM_UART_TWFIFO_TXWATER (0xFFU) /*!< Bit mask for UART_TWFIFO_TXWATER. */
3093 #define BS_UART_TWFIFO_TXWATER (8U) /*!< Bit field size in bits for UART_TWFIFO_TXWATER. */
3095 /*! @brief Read current value of the UART_TWFIFO_TXWATER field. */
3096 #define BR_UART_TWFIFO_TXWATER(x) (HW_UART_TWFIFO(x).U)
3098 /*! @brief Format value for bitfield UART_TWFIFO_TXWATER. */
3099 #define BF_UART_TWFIFO_TXWATER(v) ((uint8_t)((uint8_t)(v) << BP_UART_TWFIFO_TXWATER) & BM_UART_TWFIFO_TXWATER)
3101 /*! @brief Set the TXWATER field to a new value. */
3102 #define BW_UART_TWFIFO_TXWATER(x, v) (HW_UART_TWFIFO_WR(x, v))
3105 /*******************************************************************************
3106 * HW_UART_TCFIFO - UART FIFO Transmit Count
3107 ******************************************************************************/
3110 * @brief HW_UART_TCFIFO - UART FIFO Transmit Count (RO)
3112 * Reset value: 0x00U
3114 * This is a read only register that indicates how many datawords are currently
3115 * in the transmit buffer/FIFO. It may be read at any time.
3117 typedef union _hw_uart_tcfifo
3120 struct _hw_uart_tcfifo_bitfields
3122 uint8_t TXCOUNT : 8; /*!< [7:0] Transmit Counter */
3127 * @name Constants and macros for entire UART_TCFIFO register
3130 #define HW_UART_TCFIFO_ADDR(x) ((x) + 0x14U)
3132 #define HW_UART_TCFIFO(x) (*(__I hw_uart_tcfifo_t *) HW_UART_TCFIFO_ADDR(x))
3133 #define HW_UART_TCFIFO_RD(x) (HW_UART_TCFIFO(x).U)
3137 * Constants & macros for individual UART_TCFIFO bitfields
3141 * @name Register UART_TCFIFO, field TXCOUNT[7:0] (RO)
3143 * The value in this register indicates the number of datawords that are in the
3144 * transmit FIFO/buffer. If a dataword is being transmitted, that is, in the
3145 * transmit shift register, it is not included in the count. This value may be used
3146 * in conjunction with PFIFO[TXFIFOSIZE] to calculate how much room is left in the
3147 * transmit FIFO/buffer.
3150 #define BP_UART_TCFIFO_TXCOUNT (0U) /*!< Bit position for UART_TCFIFO_TXCOUNT. */
3151 #define BM_UART_TCFIFO_TXCOUNT (0xFFU) /*!< Bit mask for UART_TCFIFO_TXCOUNT. */
3152 #define BS_UART_TCFIFO_TXCOUNT (8U) /*!< Bit field size in bits for UART_TCFIFO_TXCOUNT. */
3154 /*! @brief Read current value of the UART_TCFIFO_TXCOUNT field. */
3155 #define BR_UART_TCFIFO_TXCOUNT(x) (HW_UART_TCFIFO(x).U)
3158 /*******************************************************************************
3159 * HW_UART_RWFIFO - UART FIFO Receive Watermark
3160 ******************************************************************************/
3163 * @brief HW_UART_RWFIFO - UART FIFO Receive Watermark (RW)
3165 * Reset value: 0x01U
3167 * This register provides the ability to set a programmable threshold for
3168 * notification of the need to remove data from the receiver FIFO/buffer. This register
3169 * may be read at any time but must be written only when C2[RE] is not asserted.
3170 * Changing the value in this register will not clear S1[RDRF].
3172 typedef union _hw_uart_rwfifo
3175 struct _hw_uart_rwfifo_bitfields
3177 uint8_t RXWATER : 8; /*!< [7:0] Receive Watermark */
3182 * @name Constants and macros for entire UART_RWFIFO register
3185 #define HW_UART_RWFIFO_ADDR(x) ((x) + 0x15U)
3187 #define HW_UART_RWFIFO(x) (*(__IO hw_uart_rwfifo_t *) HW_UART_RWFIFO_ADDR(x))
3188 #define HW_UART_RWFIFO_RD(x) (HW_UART_RWFIFO(x).U)
3189 #define HW_UART_RWFIFO_WR(x, v) (HW_UART_RWFIFO(x).U = (v))
3190 #define HW_UART_RWFIFO_SET(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) | (v)))
3191 #define HW_UART_RWFIFO_CLR(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) & ~(v)))
3192 #define HW_UART_RWFIFO_TOG(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) ^ (v)))
3196 * Constants & macros for individual UART_RWFIFO bitfields
3200 * @name Register UART_RWFIFO, field RXWATER[7:0] (RW)
3202 * When the number of datawords in the receive FIFO/buffer is equal to or
3203 * greater than the value in this register field, an interrupt via S1[RDRF] or a DMA
3204 * request via C5[RDMAS] is generated as determined by C5[RDMAS] and C2[RIE]. For
3205 * proper operation, the value in RXWATER must be set to be less than the receive
3206 * FIFO/buffer size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and must be
3210 #define BP_UART_RWFIFO_RXWATER (0U) /*!< Bit position for UART_RWFIFO_RXWATER. */
3211 #define BM_UART_RWFIFO_RXWATER (0xFFU) /*!< Bit mask for UART_RWFIFO_RXWATER. */
3212 #define BS_UART_RWFIFO_RXWATER (8U) /*!< Bit field size in bits for UART_RWFIFO_RXWATER. */
3214 /*! @brief Read current value of the UART_RWFIFO_RXWATER field. */
3215 #define BR_UART_RWFIFO_RXWATER(x) (HW_UART_RWFIFO(x).U)
3217 /*! @brief Format value for bitfield UART_RWFIFO_RXWATER. */
3218 #define BF_UART_RWFIFO_RXWATER(v) ((uint8_t)((uint8_t)(v) << BP_UART_RWFIFO_RXWATER) & BM_UART_RWFIFO_RXWATER)
3220 /*! @brief Set the RXWATER field to a new value. */
3221 #define BW_UART_RWFIFO_RXWATER(x, v) (HW_UART_RWFIFO_WR(x, v))
3224 /*******************************************************************************
3225 * HW_UART_RCFIFO - UART FIFO Receive Count
3226 ******************************************************************************/
3229 * @brief HW_UART_RCFIFO - UART FIFO Receive Count (RO)
3231 * Reset value: 0x00U
3233 * This is a read only register that indicates how many datawords are currently
3234 * in the receive FIFO/buffer. It may be read at any time.
3236 typedef union _hw_uart_rcfifo
3239 struct _hw_uart_rcfifo_bitfields
3241 uint8_t RXCOUNT : 8; /*!< [7:0] Receive Counter */
3246 * @name Constants and macros for entire UART_RCFIFO register
3249 #define HW_UART_RCFIFO_ADDR(x) ((x) + 0x16U)
3251 #define HW_UART_RCFIFO(x) (*(__I hw_uart_rcfifo_t *) HW_UART_RCFIFO_ADDR(x))
3252 #define HW_UART_RCFIFO_RD(x) (HW_UART_RCFIFO(x).U)
3256 * Constants & macros for individual UART_RCFIFO bitfields
3260 * @name Register UART_RCFIFO, field RXCOUNT[7:0] (RO)
3262 * The value in this register indicates the number of datawords that are in the
3263 * receive FIFO/buffer. If a dataword is being received, that is, in the receive
3264 * shift register, it is not included in the count. This value may be used in
3265 * conjunction with PFIFO[RXFIFOSIZE] to calculate how much room is left in the
3266 * receive FIFO/buffer.
3269 #define BP_UART_RCFIFO_RXCOUNT (0U) /*!< Bit position for UART_RCFIFO_RXCOUNT. */
3270 #define BM_UART_RCFIFO_RXCOUNT (0xFFU) /*!< Bit mask for UART_RCFIFO_RXCOUNT. */
3271 #define BS_UART_RCFIFO_RXCOUNT (8U) /*!< Bit field size in bits for UART_RCFIFO_RXCOUNT. */
3273 /*! @brief Read current value of the UART_RCFIFO_RXCOUNT field. */
3274 #define BR_UART_RCFIFO_RXCOUNT(x) (HW_UART_RCFIFO(x).U)
3277 /*******************************************************************************
3278 * HW_UART_C7816 - UART 7816 Control Register
3279 ******************************************************************************/
3282 * @brief HW_UART_C7816 - UART 7816 Control Register (RW)
3284 * Reset value: 0x00U
3286 * The C7816 register is the primary control register for ISO-7816 specific
3287 * functionality. This register is specific to 7816 functionality and the values in
3288 * this register have no effect on UART operation and should be ignored if
3289 * ISO_7816E is not set/enabled. This register may be read at any time but values must
3290 * be changed only when ISO_7816E is not set.
3292 typedef union _hw_uart_c7816
3295 struct _hw_uart_c7816_bitfields
3297 uint8_t ISO_7816E : 1; /*!< [0] ISO-7816 Functionality Enabled */
3298 uint8_t TTYPE : 1; /*!< [1] Transfer Type */
3299 uint8_t INIT : 1; /*!< [2] Detect Initial Character */
3300 uint8_t ANACK : 1; /*!< [3] Generate NACK on Error */
3301 uint8_t ONACK : 1; /*!< [4] Generate NACK on Overflow */
3302 uint8_t RESERVED0 : 3; /*!< [7:5] */
3307 * @name Constants and macros for entire UART_C7816 register
3310 #define HW_UART_C7816_ADDR(x) ((x) + 0x18U)
3312 #define HW_UART_C7816(x) (*(__IO hw_uart_c7816_t *) HW_UART_C7816_ADDR(x))
3313 #define HW_UART_C7816_RD(x) (HW_UART_C7816(x).U)
3314 #define HW_UART_C7816_WR(x, v) (HW_UART_C7816(x).U = (v))
3315 #define HW_UART_C7816_SET(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) | (v)))
3316 #define HW_UART_C7816_CLR(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) & ~(v)))
3317 #define HW_UART_C7816_TOG(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) ^ (v)))
3321 * Constants & macros for individual UART_C7816 bitfields
3325 * @name Register UART_C7816, field ISO_7816E[0] (RW)
3327 * Indicates that the UART is operating according to the ISO-7816 protocol. This
3328 * field must be modified only when no transmit or receive is occurring. If this
3329 * field is changed during a data transfer, the data being transmitted or
3330 * received may be transferred incorrectly.
3333 * - 0 - ISO-7816 functionality is turned off/not enabled.
3334 * - 1 - ISO-7816 functionality is turned on/enabled.
3337 #define BP_UART_C7816_ISO_7816E (0U) /*!< Bit position for UART_C7816_ISO_7816E. */
3338 #define BM_UART_C7816_ISO_7816E (0x01U) /*!< Bit mask for UART_C7816_ISO_7816E. */
3339 #define BS_UART_C7816_ISO_7816E (1U) /*!< Bit field size in bits for UART_C7816_ISO_7816E. */
3341 /*! @brief Read current value of the UART_C7816_ISO_7816E field. */
3342 #define BR_UART_C7816_ISO_7816E(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E))
3344 /*! @brief Format value for bitfield UART_C7816_ISO_7816E. */
3345 #define BF_UART_C7816_ISO_7816E(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ISO_7816E) & BM_UART_C7816_ISO_7816E)
3347 /*! @brief Set the ISO_7816E field to a new value. */
3348 #define BW_UART_C7816_ISO_7816E(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E) = (v))
3352 * @name Register UART_C7816, field TTYPE[1] (RW)
3354 * Indicates the transfer protocol being used. See ISO-7816 / smartcard support
3358 * - 0 - T = 0 per the ISO-7816 specification.
3359 * - 1 - T = 1 per the ISO-7816 specification.
3362 #define BP_UART_C7816_TTYPE (1U) /*!< Bit position for UART_C7816_TTYPE. */
3363 #define BM_UART_C7816_TTYPE (0x02U) /*!< Bit mask for UART_C7816_TTYPE. */
3364 #define BS_UART_C7816_TTYPE (1U) /*!< Bit field size in bits for UART_C7816_TTYPE. */
3366 /*! @brief Read current value of the UART_C7816_TTYPE field. */
3367 #define BR_UART_C7816_TTYPE(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE))
3369 /*! @brief Format value for bitfield UART_C7816_TTYPE. */
3370 #define BF_UART_C7816_TTYPE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_TTYPE) & BM_UART_C7816_TTYPE)
3372 /*! @brief Set the TTYPE field to a new value. */
3373 #define BW_UART_C7816_TTYPE(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE) = (v))
3377 * @name Register UART_C7816, field INIT[2] (RW)
3379 * When this field is set, all received characters are searched for a valid
3380 * initial character. If an invalid initial character is identified, and ANACK is
3381 * set, a NACK is sent. All received data is discarded and error flags blocked
3382 * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV])
3383 * until a valid initial character is detected. Upon detecting a valid initial
3384 * character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are
3385 * automatically updated to reflect the initial character that was received. The
3386 * actual INIT data value is not stored in the receive buffer. Additionally, upon
3387 * detection of a valid initial character, IS7816[INITD] is set and an interrupt
3388 * issued as programmed by IE7816[INITDE]. When a valid initial character is
3389 * detected, INIT is automatically cleared. This Initial Character Detect feature is
3390 * supported only in T = 0 protocol mode.
3393 * - 0 - Normal operating mode. Receiver does not seek to identify initial
3395 * - 1 - Receiver searches for initial character.
3398 #define BP_UART_C7816_INIT (2U) /*!< Bit position for UART_C7816_INIT. */
3399 #define BM_UART_C7816_INIT (0x04U) /*!< Bit mask for UART_C7816_INIT. */
3400 #define BS_UART_C7816_INIT (1U) /*!< Bit field size in bits for UART_C7816_INIT. */
3402 /*! @brief Read current value of the UART_C7816_INIT field. */
3403 #define BR_UART_C7816_INIT(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT))
3405 /*! @brief Format value for bitfield UART_C7816_INIT. */
3406 #define BF_UART_C7816_INIT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_INIT) & BM_UART_C7816_INIT)
3408 /*! @brief Set the INIT field to a new value. */
3409 #define BW_UART_C7816_INIT(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT) = (v))
3413 * @name Register UART_C7816, field ANACK[3] (RW)
3415 * When this field is set, the receiver automatically generates a NACK response
3416 * if a parity error occurs or if INIT is set and an invalid initial character is
3417 * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
3418 * attempts to retransmit the data indefinitely. To stop retransmission attempts,
3419 * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
3422 * - 0 - No NACK is automatically generated.
3423 * - 1 - A NACK is automatically generated if a parity error is detected or if
3424 * an invalid initial character is detected.
3427 #define BP_UART_C7816_ANACK (3U) /*!< Bit position for UART_C7816_ANACK. */
3428 #define BM_UART_C7816_ANACK (0x08U) /*!< Bit mask for UART_C7816_ANACK. */
3429 #define BS_UART_C7816_ANACK (1U) /*!< Bit field size in bits for UART_C7816_ANACK. */
3431 /*! @brief Read current value of the UART_C7816_ANACK field. */
3432 #define BR_UART_C7816_ANACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK))
3434 /*! @brief Format value for bitfield UART_C7816_ANACK. */
3435 #define BF_UART_C7816_ANACK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ANACK) & BM_UART_C7816_ANACK)
3437 /*! @brief Set the ANACK field to a new value. */
3438 #define BW_UART_C7816_ANACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK) = (v))
3442 * @name Register UART_C7816, field ONACK[4] (RW)
3444 * When this field is set, the receiver automatically generates a NACK response
3445 * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
3446 * this results in the transmitter resending the packet that overflowed until the
3447 * retransmit threshold for that transmitter is reached. A NACK is generated only
3448 * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
3452 * - 0 - The received data does not generate a NACK when the receipt of the data
3453 * results in an overflow event.
3454 * - 1 - If the receiver buffer overflows, a NACK is automatically sent on a
3455 * received character.
3458 #define BP_UART_C7816_ONACK (4U) /*!< Bit position for UART_C7816_ONACK. */
3459 #define BM_UART_C7816_ONACK (0x10U) /*!< Bit mask for UART_C7816_ONACK. */
3460 #define BS_UART_C7816_ONACK (1U) /*!< Bit field size in bits for UART_C7816_ONACK. */
3462 /*! @brief Read current value of the UART_C7816_ONACK field. */
3463 #define BR_UART_C7816_ONACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK))
3465 /*! @brief Format value for bitfield UART_C7816_ONACK. */
3466 #define BF_UART_C7816_ONACK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ONACK) & BM_UART_C7816_ONACK)
3468 /*! @brief Set the ONACK field to a new value. */
3469 #define BW_UART_C7816_ONACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK) = (v))
3472 /*******************************************************************************
3473 * HW_UART_IE7816 - UART 7816 Interrupt Enable Register
3474 ******************************************************************************/
3477 * @brief HW_UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
3479 * Reset value: 0x00U
3481 * The IE7816 register controls which flags result in an interrupt being issued.
3482 * This register is specific to 7816 functionality, the corresponding flags that
3483 * drive the interrupts are not asserted when 7816E is not set/enabled. However,
3484 * these flags may remain set if they are asserted while 7816E was set and not
3485 * subsequently cleared. This register may be read or written to at any time.
3487 typedef union _hw_uart_ie7816
3490 struct _hw_uart_ie7816_bitfields
3492 uint8_t RXTE : 1; /*!< [0] Receive Threshold Exceeded Interrupt
3494 uint8_t TXTE : 1; /*!< [1] Transmit Threshold Exceeded Interrupt
3496 uint8_t GTVE : 1; /*!< [2] Guard Timer Violated Interrupt Enable */
3497 uint8_t RESERVED0 : 1; /*!< [3] */
3498 uint8_t INITDE : 1; /*!< [4] Initial Character Detected Interrupt
3500 uint8_t BWTE : 1; /*!< [5] Block Wait Timer Interrupt Enable */
3501 uint8_t CWTE : 1; /*!< [6] Character Wait Timer Interrupt Enable */
3502 uint8_t WTE : 1; /*!< [7] Wait Timer Interrupt Enable */
3507 * @name Constants and macros for entire UART_IE7816 register
3510 #define HW_UART_IE7816_ADDR(x) ((x) + 0x19U)
3512 #define HW_UART_IE7816(x) (*(__IO hw_uart_ie7816_t *) HW_UART_IE7816_ADDR(x))
3513 #define HW_UART_IE7816_RD(x) (HW_UART_IE7816(x).U)
3514 #define HW_UART_IE7816_WR(x, v) (HW_UART_IE7816(x).U = (v))
3515 #define HW_UART_IE7816_SET(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) | (v)))
3516 #define HW_UART_IE7816_CLR(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) & ~(v)))
3517 #define HW_UART_IE7816_TOG(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) ^ (v)))
3521 * Constants & macros for individual UART_IE7816 bitfields
3525 * @name Register UART_IE7816, field RXTE[0] (RW)
3528 * - 0 - The assertion of IS7816[RXT] does not result in the generation of an
3530 * - 1 - The assertion of IS7816[RXT] results in the generation of an interrupt.
3533 #define BP_UART_IE7816_RXTE (0U) /*!< Bit position for UART_IE7816_RXTE. */
3534 #define BM_UART_IE7816_RXTE (0x01U) /*!< Bit mask for UART_IE7816_RXTE. */
3535 #define BS_UART_IE7816_RXTE (1U) /*!< Bit field size in bits for UART_IE7816_RXTE. */
3537 /*! @brief Read current value of the UART_IE7816_RXTE field. */
3538 #define BR_UART_IE7816_RXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE))
3540 /*! @brief Format value for bitfield UART_IE7816_RXTE. */
3541 #define BF_UART_IE7816_RXTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_RXTE) & BM_UART_IE7816_RXTE)
3543 /*! @brief Set the RXTE field to a new value. */
3544 #define BW_UART_IE7816_RXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE) = (v))
3548 * @name Register UART_IE7816, field TXTE[1] (RW)
3551 * - 0 - The assertion of IS7816[TXT] does not result in the generation of an
3553 * - 1 - The assertion of IS7816[TXT] results in the generation of an interrupt.
3556 #define BP_UART_IE7816_TXTE (1U) /*!< Bit position for UART_IE7816_TXTE. */
3557 #define BM_UART_IE7816_TXTE (0x02U) /*!< Bit mask for UART_IE7816_TXTE. */
3558 #define BS_UART_IE7816_TXTE (1U) /*!< Bit field size in bits for UART_IE7816_TXTE. */
3560 /*! @brief Read current value of the UART_IE7816_TXTE field. */
3561 #define BR_UART_IE7816_TXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE))
3563 /*! @brief Format value for bitfield UART_IE7816_TXTE. */
3564 #define BF_UART_IE7816_TXTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_TXTE) & BM_UART_IE7816_TXTE)
3566 /*! @brief Set the TXTE field to a new value. */
3567 #define BW_UART_IE7816_TXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE) = (v))
3571 * @name Register UART_IE7816, field GTVE[2] (RW)
3574 * - 0 - The assertion of IS7816[GTV] does not result in the generation of an
3576 * - 1 - The assertion of IS7816[GTV] results in the generation of an interrupt.
3579 #define BP_UART_IE7816_GTVE (2U) /*!< Bit position for UART_IE7816_GTVE. */
3580 #define BM_UART_IE7816_GTVE (0x04U) /*!< Bit mask for UART_IE7816_GTVE. */
3581 #define BS_UART_IE7816_GTVE (1U) /*!< Bit field size in bits for UART_IE7816_GTVE. */
3583 /*! @brief Read current value of the UART_IE7816_GTVE field. */
3584 #define BR_UART_IE7816_GTVE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE))
3586 /*! @brief Format value for bitfield UART_IE7816_GTVE. */
3587 #define BF_UART_IE7816_GTVE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_GTVE) & BM_UART_IE7816_GTVE)
3589 /*! @brief Set the GTVE field to a new value. */
3590 #define BW_UART_IE7816_GTVE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE) = (v))
3594 * @name Register UART_IE7816, field INITDE[4] (RW)
3597 * - 0 - The assertion of IS7816[INITD] does not result in the generation of an
3599 * - 1 - The assertion of IS7816[INITD] results in the generation of an
3603 #define BP_UART_IE7816_INITDE (4U) /*!< Bit position for UART_IE7816_INITDE. */
3604 #define BM_UART_IE7816_INITDE (0x10U) /*!< Bit mask for UART_IE7816_INITDE. */
3605 #define BS_UART_IE7816_INITDE (1U) /*!< Bit field size in bits for UART_IE7816_INITDE. */
3607 /*! @brief Read current value of the UART_IE7816_INITDE field. */
3608 #define BR_UART_IE7816_INITDE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE))
3610 /*! @brief Format value for bitfield UART_IE7816_INITDE. */
3611 #define BF_UART_IE7816_INITDE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_INITDE) & BM_UART_IE7816_INITDE)
3613 /*! @brief Set the INITDE field to a new value. */
3614 #define BW_UART_IE7816_INITDE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE) = (v))
3618 * @name Register UART_IE7816, field BWTE[5] (RW)
3621 * - 0 - The assertion of IS7816[BWT] does not result in the generation of an
3623 * - 1 - The assertion of IS7816[BWT] results in the generation of an interrupt.
3626 #define BP_UART_IE7816_BWTE (5U) /*!< Bit position for UART_IE7816_BWTE. */
3627 #define BM_UART_IE7816_BWTE (0x20U) /*!< Bit mask for UART_IE7816_BWTE. */
3628 #define BS_UART_IE7816_BWTE (1U) /*!< Bit field size in bits for UART_IE7816_BWTE. */
3630 /*! @brief Read current value of the UART_IE7816_BWTE field. */
3631 #define BR_UART_IE7816_BWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE))
3633 /*! @brief Format value for bitfield UART_IE7816_BWTE. */
3634 #define BF_UART_IE7816_BWTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_BWTE) & BM_UART_IE7816_BWTE)
3636 /*! @brief Set the BWTE field to a new value. */
3637 #define BW_UART_IE7816_BWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE) = (v))
3641 * @name Register UART_IE7816, field CWTE[6] (RW)
3644 * - 0 - The assertion of IS7816[CWT] does not result in the generation of an
3646 * - 1 - The assertion of IS7816[CWT] results in the generation of an interrupt.
3649 #define BP_UART_IE7816_CWTE (6U) /*!< Bit position for UART_IE7816_CWTE. */
3650 #define BM_UART_IE7816_CWTE (0x40U) /*!< Bit mask for UART_IE7816_CWTE. */
3651 #define BS_UART_IE7816_CWTE (1U) /*!< Bit field size in bits for UART_IE7816_CWTE. */
3653 /*! @brief Read current value of the UART_IE7816_CWTE field. */
3654 #define BR_UART_IE7816_CWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE))
3656 /*! @brief Format value for bitfield UART_IE7816_CWTE. */
3657 #define BF_UART_IE7816_CWTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_CWTE) & BM_UART_IE7816_CWTE)
3659 /*! @brief Set the CWTE field to a new value. */
3660 #define BW_UART_IE7816_CWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE) = (v))
3664 * @name Register UART_IE7816, field WTE[7] (RW)
3667 * - 0 - The assertion of IS7816[WT] does not result in the generation of an
3669 * - 1 - The assertion of IS7816[WT] results in the generation of an interrupt.
3672 #define BP_UART_IE7816_WTE (7U) /*!< Bit position for UART_IE7816_WTE. */
3673 #define BM_UART_IE7816_WTE (0x80U) /*!< Bit mask for UART_IE7816_WTE. */
3674 #define BS_UART_IE7816_WTE (1U) /*!< Bit field size in bits for UART_IE7816_WTE. */
3676 /*! @brief Read current value of the UART_IE7816_WTE field. */
3677 #define BR_UART_IE7816_WTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE))
3679 /*! @brief Format value for bitfield UART_IE7816_WTE. */
3680 #define BF_UART_IE7816_WTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_WTE) & BM_UART_IE7816_WTE)
3682 /*! @brief Set the WTE field to a new value. */
3683 #define BW_UART_IE7816_WTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE) = (v))
3686 /*******************************************************************************
3687 * HW_UART_IS7816 - UART 7816 Interrupt Status Register
3688 ******************************************************************************/
3691 * @brief HW_UART_IS7816 - UART 7816 Interrupt Status Register (RW)
3693 * Reset value: 0x00U
3695 * The IS7816 register provides a mechanism to read and clear the interrupt
3696 * flags. All flags/interrupts are cleared by writing a 1 to the field location.
3697 * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
3698 * the flag condition that occurred since the last time the bit was cleared, not
3699 * that the condition currently exists. The status flags are set regardless of
3700 * whether the corresponding field in the IE7816 is set or cleared. The IE7816
3701 * controls only if an interrupt is issued to the host processor. This register is
3702 * specific to 7816 functionality and the values in this register have no affect on
3703 * UART operation and should be ignored if 7816E is not set/enabled. This
3704 * register may be read or written at anytime.
3706 typedef union _hw_uart_is7816
3709 struct _hw_uart_is7816_bitfields
3711 uint8_t RXT : 1; /*!< [0] Receive Threshold Exceeded Interrupt */
3712 uint8_t TXT : 1; /*!< [1] Transmit Threshold Exceeded Interrupt */
3713 uint8_t GTV : 1; /*!< [2] Guard Timer Violated Interrupt */
3714 uint8_t RESERVED0 : 1; /*!< [3] */
3715 uint8_t INITD : 1; /*!< [4] Initial Character Detected Interrupt */
3716 uint8_t BWT : 1; /*!< [5] Block Wait Timer Interrupt */
3717 uint8_t CWT : 1; /*!< [6] Character Wait Timer Interrupt */
3718 uint8_t WT : 1; /*!< [7] Wait Timer Interrupt */
3723 * @name Constants and macros for entire UART_IS7816 register
3726 #define HW_UART_IS7816_ADDR(x) ((x) + 0x1AU)
3728 #define HW_UART_IS7816(x) (*(__IO hw_uart_is7816_t *) HW_UART_IS7816_ADDR(x))
3729 #define HW_UART_IS7816_RD(x) (HW_UART_IS7816(x).U)
3730 #define HW_UART_IS7816_WR(x, v) (HW_UART_IS7816(x).U = (v))
3731 #define HW_UART_IS7816_SET(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) | (v)))
3732 #define HW_UART_IS7816_CLR(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) & ~(v)))
3733 #define HW_UART_IS7816_TOG(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) ^ (v)))
3737 * Constants & macros for individual UART_IS7816 bitfields
3741 * @name Register UART_IS7816, field RXT[0] (W1C)
3743 * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
3744 * generated in response to parity errors on received data. This flag requires ANACK
3745 * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
3746 * Clearing this field also resets the counter keeping track of consecutive NACKS. The
3747 * UART will continue to attempt to receive data regardless of whether this flag
3748 * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
3749 * or packet is received without needing to issue a NACK, the internal NACK
3750 * detection counter is cleared and the count restarts from zero on the next
3751 * transmitted NACK. This interrupt is cleared by writing 1.
3754 * - 0 - The number of consecutive NACKS generated as a result of parity errors
3755 * and buffer overruns is less than or equal to the value in
3756 * ET7816[RXTHRESHOLD].
3757 * - 1 - The number of consecutive NACKS generated as a result of parity errors
3758 * and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
3761 #define BP_UART_IS7816_RXT (0U) /*!< Bit position for UART_IS7816_RXT. */
3762 #define BM_UART_IS7816_RXT (0x01U) /*!< Bit mask for UART_IS7816_RXT. */
3763 #define BS_UART_IS7816_RXT (1U) /*!< Bit field size in bits for UART_IS7816_RXT. */
3765 /*! @brief Read current value of the UART_IS7816_RXT field. */
3766 #define BR_UART_IS7816_RXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT))
3768 /*! @brief Format value for bitfield UART_IS7816_RXT. */
3769 #define BF_UART_IS7816_RXT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_RXT) & BM_UART_IS7816_RXT)
3771 /*! @brief Set the RXT field to a new value. */
3772 #define BW_UART_IS7816_RXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT) = (v))
3776 * @name Register UART_IS7816, field TXT[1] (W1C)
3778 * Indicates that the transmit NACK threshold has been exceeded as indicated by
3779 * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
3780 * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
3781 * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
3782 * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
3783 * internal NACK detection counter is cleared and the count restarts from zero on
3784 * the next received NACK. This interrupt is cleared by writing 1.
3787 * - 0 - The number of retries and corresponding NACKS does not exceed the value
3788 * in ET7816[TXTHRESHOLD].
3789 * - 1 - The number of retries and corresponding NACKS exceeds the value in
3790 * ET7816[TXTHRESHOLD].
3793 #define BP_UART_IS7816_TXT (1U) /*!< Bit position for UART_IS7816_TXT. */
3794 #define BM_UART_IS7816_TXT (0x02U) /*!< Bit mask for UART_IS7816_TXT. */
3795 #define BS_UART_IS7816_TXT (1U) /*!< Bit field size in bits for UART_IS7816_TXT. */
3797 /*! @brief Read current value of the UART_IS7816_TXT field. */
3798 #define BR_UART_IS7816_TXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT))
3800 /*! @brief Format value for bitfield UART_IS7816_TXT. */
3801 #define BF_UART_IS7816_TXT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_TXT) & BM_UART_IS7816_TXT)
3803 /*! @brief Set the TXT field to a new value. */
3804 #define BW_UART_IS7816_TXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT) = (v))
3808 * @name Register UART_IS7816, field GTV[2] (W1C)
3810 * Indicates that one or more of the character guard time, block guard time, or
3811 * guard time are violated. This interrupt is cleared by writing 1.
3814 * - 0 - A guard time (GT, CGT, or BGT) has not been violated.
3815 * - 1 - A guard time (GT, CGT, or BGT) has been violated.
3818 #define BP_UART_IS7816_GTV (2U) /*!< Bit position for UART_IS7816_GTV. */
3819 #define BM_UART_IS7816_GTV (0x04U) /*!< Bit mask for UART_IS7816_GTV. */
3820 #define BS_UART_IS7816_GTV (1U) /*!< Bit field size in bits for UART_IS7816_GTV. */
3822 /*! @brief Read current value of the UART_IS7816_GTV field. */
3823 #define BR_UART_IS7816_GTV(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV))
3825 /*! @brief Format value for bitfield UART_IS7816_GTV. */
3826 #define BF_UART_IS7816_GTV(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_GTV) & BM_UART_IS7816_GTV)
3828 /*! @brief Set the GTV field to a new value. */
3829 #define BW_UART_IS7816_GTV(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV) = (v))
3833 * @name Register UART_IS7816, field INITD[4] (W1C)
3835 * Indicates that a valid initial character is received. This interrupt is
3836 * cleared by writing 1.
3839 * - 0 - A valid initial character has not been received.
3840 * - 1 - A valid initial character has been received.
3843 #define BP_UART_IS7816_INITD (4U) /*!< Bit position for UART_IS7816_INITD. */
3844 #define BM_UART_IS7816_INITD (0x10U) /*!< Bit mask for UART_IS7816_INITD. */
3845 #define BS_UART_IS7816_INITD (1U) /*!< Bit field size in bits for UART_IS7816_INITD. */
3847 /*! @brief Read current value of the UART_IS7816_INITD field. */
3848 #define BR_UART_IS7816_INITD(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD))
3850 /*! @brief Format value for bitfield UART_IS7816_INITD. */
3851 #define BF_UART_IS7816_INITD(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_INITD) & BM_UART_IS7816_INITD)
3853 /*! @brief Set the INITD field to a new value. */
3854 #define BW_UART_IS7816_INITD(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD) = (v))
3858 * @name Register UART_IS7816, field BWT[5] (W1C)
3860 * Indicates that the block wait time, the time between the leading edge of
3861 * first received character of a block and the leading edge of the last character the
3862 * previously transmitted block, has exceeded the programmed value. This flag
3863 * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
3866 * - 0 - Block wait time (BWT) has not been violated.
3867 * - 1 - Block wait time (BWT) has been violated.
3870 #define BP_UART_IS7816_BWT (5U) /*!< Bit position for UART_IS7816_BWT. */
3871 #define BM_UART_IS7816_BWT (0x20U) /*!< Bit mask for UART_IS7816_BWT. */
3872 #define BS_UART_IS7816_BWT (1U) /*!< Bit field size in bits for UART_IS7816_BWT. */
3874 /*! @brief Read current value of the UART_IS7816_BWT field. */
3875 #define BR_UART_IS7816_BWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT))
3877 /*! @brief Format value for bitfield UART_IS7816_BWT. */
3878 #define BF_UART_IS7816_BWT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_BWT) & BM_UART_IS7816_BWT)
3880 /*! @brief Set the BWT field to a new value. */
3881 #define BW_UART_IS7816_BWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT) = (v))
3885 * @name Register UART_IS7816, field CWT[6] (W1C)
3887 * Indicates that the character wait time, the time between the leading edges of
3888 * two consecutive characters in a block, has exceeded the programmed value.
3889 * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
3893 * - 0 - Character wait time (CWT) has not been violated.
3894 * - 1 - Character wait time (CWT) has been violated.
3897 #define BP_UART_IS7816_CWT (6U) /*!< Bit position for UART_IS7816_CWT. */
3898 #define BM_UART_IS7816_CWT (0x40U) /*!< Bit mask for UART_IS7816_CWT. */
3899 #define BS_UART_IS7816_CWT (1U) /*!< Bit field size in bits for UART_IS7816_CWT. */
3901 /*! @brief Read current value of the UART_IS7816_CWT field. */
3902 #define BR_UART_IS7816_CWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT))
3904 /*! @brief Format value for bitfield UART_IS7816_CWT. */
3905 #define BF_UART_IS7816_CWT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_CWT) & BM_UART_IS7816_CWT)
3907 /*! @brief Set the CWT field to a new value. */
3908 #define BW_UART_IS7816_CWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT) = (v))
3912 * @name Register UART_IS7816, field WT[7] (W1C)
3914 * Indicates that the wait time, the time between the leading edge of a
3915 * character being transmitted and the leading edge of the next response character, has
3916 * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
3917 * This interrupt is cleared by writing 1.
3920 * - 0 - Wait time (WT) has not been violated.
3921 * - 1 - Wait time (WT) has been violated.
3924 #define BP_UART_IS7816_WT (7U) /*!< Bit position for UART_IS7816_WT. */
3925 #define BM_UART_IS7816_WT (0x80U) /*!< Bit mask for UART_IS7816_WT. */
3926 #define BS_UART_IS7816_WT (1U) /*!< Bit field size in bits for UART_IS7816_WT. */
3928 /*! @brief Read current value of the UART_IS7816_WT field. */
3929 #define BR_UART_IS7816_WT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT))
3931 /*! @brief Format value for bitfield UART_IS7816_WT. */
3932 #define BF_UART_IS7816_WT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_WT) & BM_UART_IS7816_WT)
3934 /*! @brief Set the WT field to a new value. */
3935 #define BW_UART_IS7816_WT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT) = (v))
3938 /*******************************************************************************
3939 * HW_UART_WP7816T0 - UART 7816 Wait Parameter Register
3940 ******************************************************************************/
3943 * @brief HW_UART_WP7816T0 - UART 7816 Wait Parameter Register (RW)
3945 * Reset value: 0x0AU
3947 * The WP7816 register contains constants used in the generation of various wait
3948 * timer counters. To save register space, this register is used differently
3949 * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
3950 * time. This register must be written to only when C7816[ISO_7816E] is not set.
3952 typedef union _hw_uart_wp7816t0
3955 struct _hw_uart_wp7816t0_bitfields
3957 uint8_t WI : 8; /*!< [7:0] Wait Time Integer (C7816[TTYPE] = 0) */
3959 } hw_uart_wp7816t0_t;
3962 * @name Constants and macros for entire UART_WP7816T0 register
3965 #define HW_UART_WP7816T0_ADDR(x) ((x) + 0x1BU)
3967 #define HW_UART_WP7816T0(x) (*(__IO hw_uart_wp7816t0_t *) HW_UART_WP7816T0_ADDR(x))
3968 #define HW_UART_WP7816T0_RD(x) (HW_UART_WP7816T0(x).U)
3969 #define HW_UART_WP7816T0_WR(x, v) (HW_UART_WP7816T0(x).U = (v))
3970 #define HW_UART_WP7816T0_SET(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) | (v)))
3971 #define HW_UART_WP7816T0_CLR(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) & ~(v)))
3972 #define HW_UART_WP7816T0_TOG(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) ^ (v)))
3976 * Constants & macros for individual UART_WP7816T0 bitfields
3980 * @name Register UART_WP7816T0, field WI[7:0] (RW)
3982 * Used to calculate the value used for the WT counter. It represents a value
3983 * between 1 and 255. The value of zero is not valid. This value is used only when
3984 * C7816[TTYPE] = 0. See Wait time and guard time parameters.
3987 #define BP_UART_WP7816T0_WI (0U) /*!< Bit position for UART_WP7816T0_WI. */
3988 #define BM_UART_WP7816T0_WI (0xFFU) /*!< Bit mask for UART_WP7816T0_WI. */
3989 #define BS_UART_WP7816T0_WI (8U) /*!< Bit field size in bits for UART_WP7816T0_WI. */
3991 /*! @brief Read current value of the UART_WP7816T0_WI field. */
3992 #define BR_UART_WP7816T0_WI(x) (HW_UART_WP7816T0(x).U)
3994 /*! @brief Format value for bitfield UART_WP7816T0_WI. */
3995 #define BF_UART_WP7816T0_WI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T0_WI) & BM_UART_WP7816T0_WI)
3997 /*! @brief Set the WI field to a new value. */
3998 #define BW_UART_WP7816T0_WI(x, v) (HW_UART_WP7816T0_WR(x, v))
4000 /*******************************************************************************
4001 * HW_UART_WP7816T1 - UART 7816 Wait Parameter Register
4002 ******************************************************************************/
4005 * @brief HW_UART_WP7816T1 - UART 7816 Wait Parameter Register (RW)
4007 * Reset value: 0x0AU
4009 * The WP7816 register contains constants used in the generation of various wait
4010 * timer counters. To save register space, this register is used differently
4011 * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
4012 * time. This register must be written to only when C7816[ISO_7816E] is not set.
4014 typedef union _hw_uart_wp7816t1
4017 struct _hw_uart_wp7816t1_bitfields
4019 uint8_t BWI : 4; /*!< [3:0] Block Wait Time Integer(C7816[TTYPE] = 1)
4021 uint8_t CWI : 4; /*!< [7:4] Character Wait Time Integer (C7816[TTYPE]
4024 } hw_uart_wp7816t1_t;
4027 * @name Constants and macros for entire UART_WP7816T1 register
4030 #define HW_UART_WP7816T1_ADDR(x) ((x) + 0x1BU)
4032 #define HW_UART_WP7816T1(x) (*(__IO hw_uart_wp7816t1_t *) HW_UART_WP7816T1_ADDR(x))
4033 #define HW_UART_WP7816T1_RD(x) (HW_UART_WP7816T1(x).U)
4034 #define HW_UART_WP7816T1_WR(x, v) (HW_UART_WP7816T1(x).U = (v))
4035 #define HW_UART_WP7816T1_SET(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) | (v)))
4036 #define HW_UART_WP7816T1_CLR(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) & ~(v)))
4037 #define HW_UART_WP7816T1_TOG(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) ^ (v)))
4041 * Constants & macros for individual UART_WP7816T1 bitfields
4045 * @name Register UART_WP7816T1, field BWI[3:0] (RW)
4047 * Used to calculate the value used for the BWT counter. It represent a value
4048 * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
4049 * and guard time parameters .
4052 #define BP_UART_WP7816T1_BWI (0U) /*!< Bit position for UART_WP7816T1_BWI. */
4053 #define BM_UART_WP7816T1_BWI (0x0FU) /*!< Bit mask for UART_WP7816T1_BWI. */
4054 #define BS_UART_WP7816T1_BWI (4U) /*!< Bit field size in bits for UART_WP7816T1_BWI. */
4056 /*! @brief Read current value of the UART_WP7816T1_BWI field. */
4057 #define BR_UART_WP7816T1_BWI(x) (HW_UART_WP7816T1(x).B.BWI)
4059 /*! @brief Format value for bitfield UART_WP7816T1_BWI. */
4060 #define BF_UART_WP7816T1_BWI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T1_BWI) & BM_UART_WP7816T1_BWI)
4062 /*! @brief Set the BWI field to a new value. */
4063 #define BW_UART_WP7816T1_BWI(x, v) (HW_UART_WP7816T1_WR(x, (HW_UART_WP7816T1_RD(x) & ~BM_UART_WP7816T1_BWI) | BF_UART_WP7816T1_BWI(v)))
4067 * @name Register UART_WP7816T1, field CWI[7:4] (RW)
4069 * Used to calculate the value used for the CWT counter. It represents a value
4070 * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
4071 * and guard time parameters .
4074 #define BP_UART_WP7816T1_CWI (4U) /*!< Bit position for UART_WP7816T1_CWI. */
4075 #define BM_UART_WP7816T1_CWI (0xF0U) /*!< Bit mask for UART_WP7816T1_CWI. */
4076 #define BS_UART_WP7816T1_CWI (4U) /*!< Bit field size in bits for UART_WP7816T1_CWI. */
4078 /*! @brief Read current value of the UART_WP7816T1_CWI field. */
4079 #define BR_UART_WP7816T1_CWI(x) (HW_UART_WP7816T1(x).B.CWI)
4081 /*! @brief Format value for bitfield UART_WP7816T1_CWI. */
4082 #define BF_UART_WP7816T1_CWI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T1_CWI) & BM_UART_WP7816T1_CWI)
4084 /*! @brief Set the CWI field to a new value. */
4085 #define BW_UART_WP7816T1_CWI(x, v) (HW_UART_WP7816T1_WR(x, (HW_UART_WP7816T1_RD(x) & ~BM_UART_WP7816T1_CWI) | BF_UART_WP7816T1_CWI(v)))
4088 /*******************************************************************************
4089 * HW_UART_WN7816 - UART 7816 Wait N Register
4090 ******************************************************************************/
4093 * @brief HW_UART_WN7816 - UART 7816 Wait N Register (RW)
4095 * Reset value: 0x00U
4097 * The WN7816 register contains a parameter that is used in the calculation of
4098 * the guard time counter. This register may be read at any time. This register
4099 * must be written to only when C7816[ISO_7816E] is not set.
4101 typedef union _hw_uart_wn7816
4104 struct _hw_uart_wn7816_bitfields
4106 uint8_t GTN : 8; /*!< [7:0] Guard Band N */
4111 * @name Constants and macros for entire UART_WN7816 register
4114 #define HW_UART_WN7816_ADDR(x) ((x) + 0x1CU)
4116 #define HW_UART_WN7816(x) (*(__IO hw_uart_wn7816_t *) HW_UART_WN7816_ADDR(x))
4117 #define HW_UART_WN7816_RD(x) (HW_UART_WN7816(x).U)
4118 #define HW_UART_WN7816_WR(x, v) (HW_UART_WN7816(x).U = (v))
4119 #define HW_UART_WN7816_SET(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) | (v)))
4120 #define HW_UART_WN7816_CLR(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) & ~(v)))
4121 #define HW_UART_WN7816_TOG(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) ^ (v)))
4125 * Constants & macros for individual UART_WN7816 bitfields
4129 * @name Register UART_WN7816, field GTN[7:0] (RW)
4131 * Defines a parameter used in the calculation of GT, CGT, and BGT counters. The
4132 * value represents an integer number between 0 and 255. See Wait time and guard
4136 #define BP_UART_WN7816_GTN (0U) /*!< Bit position for UART_WN7816_GTN. */
4137 #define BM_UART_WN7816_GTN (0xFFU) /*!< Bit mask for UART_WN7816_GTN. */
4138 #define BS_UART_WN7816_GTN (8U) /*!< Bit field size in bits for UART_WN7816_GTN. */
4140 /*! @brief Read current value of the UART_WN7816_GTN field. */
4141 #define BR_UART_WN7816_GTN(x) (HW_UART_WN7816(x).U)
4143 /*! @brief Format value for bitfield UART_WN7816_GTN. */
4144 #define BF_UART_WN7816_GTN(v) ((uint8_t)((uint8_t)(v) << BP_UART_WN7816_GTN) & BM_UART_WN7816_GTN)
4146 /*! @brief Set the GTN field to a new value. */
4147 #define BW_UART_WN7816_GTN(x, v) (HW_UART_WN7816_WR(x, v))
4150 /*******************************************************************************
4151 * HW_UART_WF7816 - UART 7816 Wait FD Register
4152 ******************************************************************************/
4155 * @brief HW_UART_WF7816 - UART 7816 Wait FD Register (RW)
4157 * Reset value: 0x01U
4159 * The WF7816 contains parameters that are used in the generation of various
4160 * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
4161 * time. This register must be written to only when C7816[ISO_7816E] is not set.
4163 typedef union _hw_uart_wf7816
4166 struct _hw_uart_wf7816_bitfields
4168 uint8_t GTFD : 8; /*!< [7:0] FD Multiplier */
4173 * @name Constants and macros for entire UART_WF7816 register
4176 #define HW_UART_WF7816_ADDR(x) ((x) + 0x1DU)
4178 #define HW_UART_WF7816(x) (*(__IO hw_uart_wf7816_t *) HW_UART_WF7816_ADDR(x))
4179 #define HW_UART_WF7816_RD(x) (HW_UART_WF7816(x).U)
4180 #define HW_UART_WF7816_WR(x, v) (HW_UART_WF7816(x).U = (v))
4181 #define HW_UART_WF7816_SET(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) | (v)))
4182 #define HW_UART_WF7816_CLR(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) & ~(v)))
4183 #define HW_UART_WF7816_TOG(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) ^ (v)))
4187 * Constants & macros for individual UART_WF7816 bitfields
4191 * @name Register UART_WF7816, field GTFD[7:0] (RW)
4193 * Used as another multiplier in the calculation of WT and BWT. This value
4194 * represents a number between 1 and 255. The value of 0 is invalid. This value is not
4195 * used in baud rate generation. See Wait time and guard time parameters and
4196 * Baud rate generation .
4199 #define BP_UART_WF7816_GTFD (0U) /*!< Bit position for UART_WF7816_GTFD. */
4200 #define BM_UART_WF7816_GTFD (0xFFU) /*!< Bit mask for UART_WF7816_GTFD. */
4201 #define BS_UART_WF7816_GTFD (8U) /*!< Bit field size in bits for UART_WF7816_GTFD. */
4203 /*! @brief Read current value of the UART_WF7816_GTFD field. */
4204 #define BR_UART_WF7816_GTFD(x) (HW_UART_WF7816(x).U)
4206 /*! @brief Format value for bitfield UART_WF7816_GTFD. */
4207 #define BF_UART_WF7816_GTFD(v) ((uint8_t)((uint8_t)(v) << BP_UART_WF7816_GTFD) & BM_UART_WF7816_GTFD)
4209 /*! @brief Set the GTFD field to a new value. */
4210 #define BW_UART_WF7816_GTFD(x, v) (HW_UART_WF7816_WR(x, v))
4213 /*******************************************************************************
4214 * HW_UART_ET7816 - UART 7816 Error Threshold Register
4215 ******************************************************************************/
4218 * @brief HW_UART_ET7816 - UART 7816 Error Threshold Register (RW)
4220 * Reset value: 0x00U
4222 * The ET7816 register contains fields that determine the number of NACKs that
4223 * must be received or transmitted before the host processor is notified. This
4224 * register may be read at anytime. This register must be written to only when
4225 * C7816[ISO_7816E] is not set.
4227 typedef union _hw_uart_et7816
4230 struct _hw_uart_et7816_bitfields
4232 uint8_t RXTHRESHOLD : 4; /*!< [3:0] Receive NACK Threshold */
4233 uint8_t TXTHRESHOLD : 4; /*!< [7:4] Transmit NACK Threshold */
4238 * @name Constants and macros for entire UART_ET7816 register
4241 #define HW_UART_ET7816_ADDR(x) ((x) + 0x1EU)
4243 #define HW_UART_ET7816(x) (*(__IO hw_uart_et7816_t *) HW_UART_ET7816_ADDR(x))
4244 #define HW_UART_ET7816_RD(x) (HW_UART_ET7816(x).U)
4245 #define HW_UART_ET7816_WR(x, v) (HW_UART_ET7816(x).U = (v))
4246 #define HW_UART_ET7816_SET(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) | (v)))
4247 #define HW_UART_ET7816_CLR(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) & ~(v)))
4248 #define HW_UART_ET7816_TOG(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) ^ (v)))
4252 * Constants & macros for individual UART_ET7816 bitfields
4256 * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
4258 * The value written to this field indicates the maximum number of consecutive
4259 * NACKs generated as a result of a parity error or receiver buffer overruns
4260 * before the host processor is notified. After the counter exceeds that value in the
4261 * field, the IS7816[RXT] is asserted. This field is meaningful only when
4262 * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
4263 * NACKs that have been transmitted since the last successful reception. This
4264 * counter saturates at 4'hF and does not wrap around. Regardless of the number of
4265 * NACKs sent, the UART continues to receive valid packets indefinitely. For
4266 * additional information, see IS7816[RXT] field description.
4269 #define BP_UART_ET7816_RXTHRESHOLD (0U) /*!< Bit position for UART_ET7816_RXTHRESHOLD. */
4270 #define BM_UART_ET7816_RXTHRESHOLD (0x0FU) /*!< Bit mask for UART_ET7816_RXTHRESHOLD. */
4271 #define BS_UART_ET7816_RXTHRESHOLD (4U) /*!< Bit field size in bits for UART_ET7816_RXTHRESHOLD. */
4273 /*! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. */
4274 #define BR_UART_ET7816_RXTHRESHOLD(x) (HW_UART_ET7816(x).B.RXTHRESHOLD)
4276 /*! @brief Format value for bitfield UART_ET7816_RXTHRESHOLD. */
4277 #define BF_UART_ET7816_RXTHRESHOLD(v) ((uint8_t)((uint8_t)(v) << BP_UART_ET7816_RXTHRESHOLD) & BM_UART_ET7816_RXTHRESHOLD)
4279 /*! @brief Set the RXTHRESHOLD field to a new value. */
4280 #define BW_UART_ET7816_RXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_RXTHRESHOLD) | BF_UART_ET7816_RXTHRESHOLD(v)))
4284 * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
4286 * The value written to this field indicates the maximum number of failed
4287 * attempts (NACKs) a transmitted character can have before the host processor is
4288 * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
4289 * The value read from this field represents the number of consecutive NACKs
4290 * that have been received since the last successful transmission. This counter
4291 * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
4292 * received, the UART continues to retransmit indefinitely. This flag only
4293 * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
4297 * - 0 - TXT asserts on the first NACK that is received.
4298 * - 1 - TXT asserts on the second NACK that is received.
4301 #define BP_UART_ET7816_TXTHRESHOLD (4U) /*!< Bit position for UART_ET7816_TXTHRESHOLD. */
4302 #define BM_UART_ET7816_TXTHRESHOLD (0xF0U) /*!< Bit mask for UART_ET7816_TXTHRESHOLD. */
4303 #define BS_UART_ET7816_TXTHRESHOLD (4U) /*!< Bit field size in bits for UART_ET7816_TXTHRESHOLD. */
4305 /*! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. */
4306 #define BR_UART_ET7816_TXTHRESHOLD(x) (HW_UART_ET7816(x).B.TXTHRESHOLD)
4308 /*! @brief Format value for bitfield UART_ET7816_TXTHRESHOLD. */
4309 #define BF_UART_ET7816_TXTHRESHOLD(v) ((uint8_t)((uint8_t)(v) << BP_UART_ET7816_TXTHRESHOLD) & BM_UART_ET7816_TXTHRESHOLD)
4311 /*! @brief Set the TXTHRESHOLD field to a new value. */
4312 #define BW_UART_ET7816_TXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_TXTHRESHOLD) | BF_UART_ET7816_TXTHRESHOLD(v)))
4315 /*******************************************************************************
4316 * HW_UART_TL7816 - UART 7816 Transmit Length Register
4317 ******************************************************************************/
4320 * @brief HW_UART_TL7816 - UART 7816 Transmit Length Register (RW)
4322 * Reset value: 0x00U
4324 * The TL7816 register is used to indicate the number of characters contained in
4325 * the block being transmitted. This register is used only when C7816[TTYPE] =
4326 * 1. This register may be read at anytime. This register must be written only
4327 * when C2[TE] is not enabled.
4329 typedef union _hw_uart_tl7816
4332 struct _hw_uart_tl7816_bitfields
4334 uint8_t TLEN : 8; /*!< [7:0] Transmit Length */
4339 * @name Constants and macros for entire UART_TL7816 register
4342 #define HW_UART_TL7816_ADDR(x) ((x) + 0x1FU)
4344 #define HW_UART_TL7816(x) (*(__IO hw_uart_tl7816_t *) HW_UART_TL7816_ADDR(x))
4345 #define HW_UART_TL7816_RD(x) (HW_UART_TL7816(x).U)
4346 #define HW_UART_TL7816_WR(x, v) (HW_UART_TL7816(x).U = (v))
4347 #define HW_UART_TL7816_SET(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) | (v)))
4348 #define HW_UART_TL7816_CLR(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) & ~(v)))
4349 #define HW_UART_TL7816_TOG(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) ^ (v)))
4353 * Constants & macros for individual UART_TL7816 bitfields
4357 * @name Register UART_TL7816, field TLEN[7:0] (RW)
4359 * This value plus four indicates the number of characters contained in the
4360 * block being transmitted. This register is automatically decremented by 1 for each
4361 * character in the information field portion of the block. Additionally, this
4362 * register is automatically decremented by 1 for the first character of a CRC in
4363 * the epilogue field. Therefore, this register must be programmed with the number
4364 * of bytes in the data packet if an LRC is being transmitted, and the number of
4365 * bytes + 1 if a CRC is being transmitted. This register is not decremented for
4366 * characters that are assumed to be part of the Prologue field, that is, the
4367 * first three characters transmitted in a block, or the LRC or last CRC character
4368 * in the Epilogue field, that is, the last character transmitted. This field
4369 * must be programed or adjusted only when C2[TE] is cleared.
4372 #define BP_UART_TL7816_TLEN (0U) /*!< Bit position for UART_TL7816_TLEN. */
4373 #define BM_UART_TL7816_TLEN (0xFFU) /*!< Bit mask for UART_TL7816_TLEN. */
4374 #define BS_UART_TL7816_TLEN (8U) /*!< Bit field size in bits for UART_TL7816_TLEN. */
4376 /*! @brief Read current value of the UART_TL7816_TLEN field. */
4377 #define BR_UART_TL7816_TLEN(x) (HW_UART_TL7816(x).U)
4379 /*! @brief Format value for bitfield UART_TL7816_TLEN. */
4380 #define BF_UART_TL7816_TLEN(v) ((uint8_t)((uint8_t)(v) << BP_UART_TL7816_TLEN) & BM_UART_TL7816_TLEN)
4382 /*! @brief Set the TLEN field to a new value. */
4383 #define BW_UART_TL7816_TLEN(x, v) (HW_UART_TL7816_WR(x, v))
4387 ** Start of section using anonymous unions
4390 #if defined(__ARMCC_VERSION)
4393 #elif defined(__CWCC__)
4395 #pragma cpp_extensions on
4396 #elif defined(__GNUC__)
4397 /* anonymous unions are enabled by default */
4398 #elif defined(__IAR_SYSTEMS_ICC__)
4399 #pragma language=extended
4401 #error Not supported compiler type
4404 /*******************************************************************************
4405 * hw_uart_t - module struct
4406 ******************************************************************************/
4408 * @brief All UART module registers.
4411 typedef struct _hw_uart
4413 __IO hw_uart_bdh_t BDH; /*!< [0x0] UART Baud Rate Registers: High */
4414 __IO hw_uart_bdl_t BDL; /*!< [0x1] UART Baud Rate Registers: Low */
4415 __IO hw_uart_c1_t C1; /*!< [0x2] UART Control Register 1 */
4416 __IO hw_uart_c2_t C2; /*!< [0x3] UART Control Register 2 */
4417 __I hw_uart_s1_t S1; /*!< [0x4] UART Status Register 1 */
4418 __IO hw_uart_s2_t S2; /*!< [0x5] UART Status Register 2 */
4419 __IO hw_uart_c3_t C3; /*!< [0x6] UART Control Register 3 */
4420 __IO hw_uart_d_t D; /*!< [0x7] UART Data Register */
4421 __IO hw_uart_ma1_t MA1; /*!< [0x8] UART Match Address Registers 1 */
4422 __IO hw_uart_ma2_t MA2; /*!< [0x9] UART Match Address Registers 2 */
4423 __IO hw_uart_c4_t C4; /*!< [0xA] UART Control Register 4 */
4424 __IO hw_uart_c5_t C5; /*!< [0xB] UART Control Register 5 */
4425 __I hw_uart_ed_t ED; /*!< [0xC] UART Extended Data Register */
4426 __IO hw_uart_modem_t MODEM; /*!< [0xD] UART Modem Register */
4427 __IO hw_uart_ir_t IR; /*!< [0xE] UART Infrared Register */
4428 uint8_t _reserved0[1];
4429 __IO hw_uart_pfifo_t PFIFO; /*!< [0x10] UART FIFO Parameters */
4430 __IO hw_uart_cfifo_t CFIFO; /*!< [0x11] UART FIFO Control Register */
4431 __IO hw_uart_sfifo_t SFIFO; /*!< [0x12] UART FIFO Status Register */
4432 __IO hw_uart_twfifo_t TWFIFO; /*!< [0x13] UART FIFO Transmit Watermark */
4433 __I hw_uart_tcfifo_t TCFIFO; /*!< [0x14] UART FIFO Transmit Count */
4434 __IO hw_uart_rwfifo_t RWFIFO; /*!< [0x15] UART FIFO Receive Watermark */
4435 __I hw_uart_rcfifo_t RCFIFO; /*!< [0x16] UART FIFO Receive Count */
4436 uint8_t _reserved1[1];
4437 __IO hw_uart_c7816_t C7816; /*!< [0x18] UART 7816 Control Register */
4438 __IO hw_uart_ie7816_t IE7816; /*!< [0x19] UART 7816 Interrupt Enable Register */
4439 __IO hw_uart_is7816_t IS7816; /*!< [0x1A] UART 7816 Interrupt Status Register */
4441 __IO hw_uart_wp7816t0_t WP7816T0; /*!< [0x1B] UART 7816 Wait Parameter Register */
4442 __IO hw_uart_wp7816t1_t WP7816T1; /*!< [0x1B] UART 7816 Wait Parameter Register */
4444 __IO hw_uart_wn7816_t WN7816; /*!< [0x1C] UART 7816 Wait N Register */
4445 __IO hw_uart_wf7816_t WF7816; /*!< [0x1D] UART 7816 Wait FD Register */
4446 __IO hw_uart_et7816_t ET7816; /*!< [0x1E] UART 7816 Error Threshold Register */
4447 __IO hw_uart_tl7816_t TL7816; /*!< [0x1F] UART 7816 Transmit Length Register */
4451 /*! @brief Macro to access all UART registers. */
4452 /*! @param x UART module instance base address. */
4453 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
4454 * use the '&' operator, like <code>&HW_UART(UART0_BASE)</code>. */
4455 #define HW_UART(x) (*(hw_uart_t *)(x))
4458 ** End of section using anonymous unions
4461 #if defined(__ARMCC_VERSION)
4463 #elif defined(__CWCC__)
4465 #elif defined(__GNUC__)
4466 /* leave anonymous unions enabled */
4467 #elif defined(__IAR_SYSTEMS_ICC__)
4468 #pragma language=default
4470 #error Not supported compiler type
4473 #endif /* __HW_UART_REGISTERS_H__ */