2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_SIM_REGISTERS_H__
81 #define __HW_SIM_REGISTERS_H__
84 #include "fsl_bitaccess.h"
89 * System Integration Module
91 * Registers defined in this header file:
92 * - HW_SIM_SOPT1 - System Options Register 1
93 * - HW_SIM_SOPT1CFG - SOPT1 Configuration Register
94 * - HW_SIM_SOPT2 - System Options Register 2
95 * - HW_SIM_SOPT4 - System Options Register 4
96 * - HW_SIM_SOPT5 - System Options Register 5
97 * - HW_SIM_SOPT7 - System Options Register 7
98 * - HW_SIM_SDID - System Device Identification Register
99 * - HW_SIM_SCGC1 - System Clock Gating Control Register 1
100 * - HW_SIM_SCGC2 - System Clock Gating Control Register 2
101 * - HW_SIM_SCGC3 - System Clock Gating Control Register 3
102 * - HW_SIM_SCGC4 - System Clock Gating Control Register 4
103 * - HW_SIM_SCGC5 - System Clock Gating Control Register 5
104 * - HW_SIM_SCGC6 - System Clock Gating Control Register 6
105 * - HW_SIM_SCGC7 - System Clock Gating Control Register 7
106 * - HW_SIM_CLKDIV1 - System Clock Divider Register 1
107 * - HW_SIM_CLKDIV2 - System Clock Divider Register 2
108 * - HW_SIM_FCFG1 - Flash Configuration Register 1
109 * - HW_SIM_FCFG2 - Flash Configuration Register 2
110 * - HW_SIM_UIDH - Unique Identification Register High
111 * - HW_SIM_UIDMH - Unique Identification Register Mid-High
112 * - HW_SIM_UIDML - Unique Identification Register Mid Low
113 * - HW_SIM_UIDL - Unique Identification Register Low
115 * - hw_sim_t - Struct containing all module registers.
118 #define HW_SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */
120 /*******************************************************************************
121 * HW_SIM_SOPT1 - System Options Register 1
122 ******************************************************************************/
125 * @brief HW_SIM_SOPT1 - System Options Register 1 (RW)
127 * Reset value: 0x80000000U
129 * The SOPT1 register is only reset on POR or LVD.
131 typedef union _hw_sim_sopt1
134 struct _hw_sim_sopt1_bitfields
136 uint32_t RESERVED0 : 12; /*!< [11:0] */
137 uint32_t RAMSIZE : 4; /*!< [15:12] RAM size */
138 uint32_t RESERVED1 : 2; /*!< [17:16] */
139 uint32_t OSC32KSEL : 2; /*!< [19:18] 32K oscillator clock select */
140 uint32_t RESERVED2 : 9; /*!< [28:20] */
141 uint32_t USBVSTBY : 1; /*!< [29] USB voltage regulator in standby
142 * mode during VLPR and VLPW modes */
143 uint32_t USBSSTBY : 1; /*!< [30] USB voltage regulator in standby
144 * mode during Stop, VLPS, LLS and VLLS modes. */
145 uint32_t USBREGEN : 1; /*!< [31] USB voltage regulator enable */
150 * @name Constants and macros for entire SIM_SOPT1 register
153 #define HW_SIM_SOPT1_ADDR(x) ((x) + 0x0U)
155 #define HW_SIM_SOPT1(x) (*(__IO hw_sim_sopt1_t *) HW_SIM_SOPT1_ADDR(x))
156 #define HW_SIM_SOPT1_RD(x) (HW_SIM_SOPT1(x).U)
157 #define HW_SIM_SOPT1_WR(x, v) (HW_SIM_SOPT1(x).U = (v))
158 #define HW_SIM_SOPT1_SET(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) | (v)))
159 #define HW_SIM_SOPT1_CLR(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) & ~(v)))
160 #define HW_SIM_SOPT1_TOG(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) ^ (v)))
164 * Constants & macros for individual SIM_SOPT1 bitfields
168 * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
170 * This field specifies the amount of system RAM available on the device.
184 #define BP_SIM_SOPT1_RAMSIZE (12U) /*!< Bit position for SIM_SOPT1_RAMSIZE. */
185 #define BM_SIM_SOPT1_RAMSIZE (0x0000F000U) /*!< Bit mask for SIM_SOPT1_RAMSIZE. */
186 #define BS_SIM_SOPT1_RAMSIZE (4U) /*!< Bit field size in bits for SIM_SOPT1_RAMSIZE. */
188 /*! @brief Read current value of the SIM_SOPT1_RAMSIZE field. */
189 #define BR_SIM_SOPT1_RAMSIZE(x) (HW_SIM_SOPT1(x).B.RAMSIZE)
193 * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
195 * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
199 * - 00 - System oscillator (OSC32KCLK)
201 * - 10 - RTC 32.768kHz oscillator
205 #define BP_SIM_SOPT1_OSC32KSEL (18U) /*!< Bit position for SIM_SOPT1_OSC32KSEL. */
206 #define BM_SIM_SOPT1_OSC32KSEL (0x000C0000U) /*!< Bit mask for SIM_SOPT1_OSC32KSEL. */
207 #define BS_SIM_SOPT1_OSC32KSEL (2U) /*!< Bit field size in bits for SIM_SOPT1_OSC32KSEL. */
209 /*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */
210 #define BR_SIM_SOPT1_OSC32KSEL(x) (HW_SIM_SOPT1(x).B.OSC32KSEL)
212 /*! @brief Format value for bitfield SIM_SOPT1_OSC32KSEL. */
213 #define BF_SIM_SOPT1_OSC32KSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_OSC32KSEL) & BM_SIM_SOPT1_OSC32KSEL)
215 /*! @brief Set the OSC32KSEL field to a new value. */
216 #define BW_SIM_SOPT1_OSC32KSEL(x, v) (HW_SIM_SOPT1_WR(x, (HW_SIM_SOPT1_RD(x) & ~BM_SIM_SOPT1_OSC32KSEL) | BF_SIM_SOPT1_OSC32KSEL(v)))
220 * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
222 * Controls whether the USB voltage regulator is placed in standby mode during
223 * VLPR and VLPW modes.
226 * - 0 - USB voltage regulator not in standby during VLPR and VLPW modes.
227 * - 1 - USB voltage regulator in standby during VLPR and VLPW modes.
230 #define BP_SIM_SOPT1_USBVSTBY (29U) /*!< Bit position for SIM_SOPT1_USBVSTBY. */
231 #define BM_SIM_SOPT1_USBVSTBY (0x20000000U) /*!< Bit mask for SIM_SOPT1_USBVSTBY. */
232 #define BS_SIM_SOPT1_USBVSTBY (1U) /*!< Bit field size in bits for SIM_SOPT1_USBVSTBY. */
234 /*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */
235 #define BR_SIM_SOPT1_USBVSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY))
237 /*! @brief Format value for bitfield SIM_SOPT1_USBVSTBY. */
238 #define BF_SIM_SOPT1_USBVSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBVSTBY) & BM_SIM_SOPT1_USBVSTBY)
240 /*! @brief Set the USBVSTBY field to a new value. */
241 #define BW_SIM_SOPT1_USBVSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY) = (v))
245 * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
247 * Controls whether the USB voltage regulator is placed in standby mode during
248 * Stop, VLPS, LLS and VLLS modes.
251 * - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
253 * - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
256 #define BP_SIM_SOPT1_USBSSTBY (30U) /*!< Bit position for SIM_SOPT1_USBSSTBY. */
257 #define BM_SIM_SOPT1_USBSSTBY (0x40000000U) /*!< Bit mask for SIM_SOPT1_USBSSTBY. */
258 #define BS_SIM_SOPT1_USBSSTBY (1U) /*!< Bit field size in bits for SIM_SOPT1_USBSSTBY. */
260 /*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */
261 #define BR_SIM_SOPT1_USBSSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY))
263 /*! @brief Format value for bitfield SIM_SOPT1_USBSSTBY. */
264 #define BF_SIM_SOPT1_USBSSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBSSTBY) & BM_SIM_SOPT1_USBSSTBY)
266 /*! @brief Set the USBSSTBY field to a new value. */
267 #define BW_SIM_SOPT1_USBSSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY) = (v))
271 * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
273 * Controls whether the USB voltage regulator is enabled.
276 * - 0 - USB voltage regulator is disabled.
277 * - 1 - USB voltage regulator is enabled.
280 #define BP_SIM_SOPT1_USBREGEN (31U) /*!< Bit position for SIM_SOPT1_USBREGEN. */
281 #define BM_SIM_SOPT1_USBREGEN (0x80000000U) /*!< Bit mask for SIM_SOPT1_USBREGEN. */
282 #define BS_SIM_SOPT1_USBREGEN (1U) /*!< Bit field size in bits for SIM_SOPT1_USBREGEN. */
284 /*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */
285 #define BR_SIM_SOPT1_USBREGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN))
287 /*! @brief Format value for bitfield SIM_SOPT1_USBREGEN. */
288 #define BF_SIM_SOPT1_USBREGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBREGEN) & BM_SIM_SOPT1_USBREGEN)
290 /*! @brief Set the USBREGEN field to a new value. */
291 #define BW_SIM_SOPT1_USBREGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN) = (v))
294 /*******************************************************************************
295 * HW_SIM_SOPT1CFG - SOPT1 Configuration Register
296 ******************************************************************************/
299 * @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
301 * Reset value: 0x00000000U
303 * The SOPT1CFG register is reset on System Reset not VLLS.
305 typedef union _hw_sim_sopt1cfg
308 struct _hw_sim_sopt1cfg_bitfields
310 uint32_t RESERVED0 : 24; /*!< [23:0] */
311 uint32_t URWE : 1; /*!< [24] USB voltage regulator enable write
313 uint32_t UVSWE : 1; /*!< [25] USB voltage regulator VLP standby write
315 uint32_t USSWE : 1; /*!< [26] USB voltage regulator stop standby
317 uint32_t RESERVED1 : 5; /*!< [31:27] */
322 * @name Constants and macros for entire SIM_SOPT1CFG register
325 #define HW_SIM_SOPT1CFG_ADDR(x) ((x) + 0x4U)
327 #define HW_SIM_SOPT1CFG(x) (*(__IO hw_sim_sopt1cfg_t *) HW_SIM_SOPT1CFG_ADDR(x))
328 #define HW_SIM_SOPT1CFG_RD(x) (HW_SIM_SOPT1CFG(x).U)
329 #define HW_SIM_SOPT1CFG_WR(x, v) (HW_SIM_SOPT1CFG(x).U = (v))
330 #define HW_SIM_SOPT1CFG_SET(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) | (v)))
331 #define HW_SIM_SOPT1CFG_CLR(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) & ~(v)))
332 #define HW_SIM_SOPT1CFG_TOG(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) ^ (v)))
336 * Constants & macros for individual SIM_SOPT1CFG bitfields
340 * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
342 * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
343 * register bit clears after a write to USBREGEN.
346 * - 0 - SOPT1 USBREGEN cannot be written.
347 * - 1 - SOPT1 USBREGEN can be written.
350 #define BP_SIM_SOPT1CFG_URWE (24U) /*!< Bit position for SIM_SOPT1CFG_URWE. */
351 #define BM_SIM_SOPT1CFG_URWE (0x01000000U) /*!< Bit mask for SIM_SOPT1CFG_URWE. */
352 #define BS_SIM_SOPT1CFG_URWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_URWE. */
354 /*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */
355 #define BR_SIM_SOPT1CFG_URWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE))
357 /*! @brief Format value for bitfield SIM_SOPT1CFG_URWE. */
358 #define BF_SIM_SOPT1CFG_URWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_URWE) & BM_SIM_SOPT1CFG_URWE)
360 /*! @brief Set the URWE field to a new value. */
361 #define BW_SIM_SOPT1CFG_URWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE) = (v))
365 * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
367 * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
368 * This register bit clears after a write to USBVSTBY.
371 * - 0 - SOPT1 USBVSTBY cannot be written.
372 * - 1 - SOPT1 USBVSTBY can be written.
375 #define BP_SIM_SOPT1CFG_UVSWE (25U) /*!< Bit position for SIM_SOPT1CFG_UVSWE. */
376 #define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) /*!< Bit mask for SIM_SOPT1CFG_UVSWE. */
377 #define BS_SIM_SOPT1CFG_UVSWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_UVSWE. */
379 /*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */
380 #define BR_SIM_SOPT1CFG_UVSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE))
382 /*! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE. */
383 #define BF_SIM_SOPT1CFG_UVSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_UVSWE) & BM_SIM_SOPT1CFG_UVSWE)
385 /*! @brief Set the UVSWE field to a new value. */
386 #define BW_SIM_SOPT1CFG_UVSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE) = (v))
390 * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
392 * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
393 * This register bit clears after a write to USBSSTBY.
396 * - 0 - SOPT1 USBSSTBY cannot be written.
397 * - 1 - SOPT1 USBSSTBY can be written.
400 #define BP_SIM_SOPT1CFG_USSWE (26U) /*!< Bit position for SIM_SOPT1CFG_USSWE. */
401 #define BM_SIM_SOPT1CFG_USSWE (0x04000000U) /*!< Bit mask for SIM_SOPT1CFG_USSWE. */
402 #define BS_SIM_SOPT1CFG_USSWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_USSWE. */
404 /*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */
405 #define BR_SIM_SOPT1CFG_USSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE))
407 /*! @brief Format value for bitfield SIM_SOPT1CFG_USSWE. */
408 #define BF_SIM_SOPT1CFG_USSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_USSWE) & BM_SIM_SOPT1CFG_USSWE)
410 /*! @brief Set the USSWE field to a new value. */
411 #define BW_SIM_SOPT1CFG_USSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE) = (v))
414 /*******************************************************************************
415 * HW_SIM_SOPT2 - System Options Register 2
416 ******************************************************************************/
419 * @brief HW_SIM_SOPT2 - System Options Register 2 (RW)
421 * Reset value: 0x00001000U
423 * SOPT2 contains the controls for selecting many of the module clock source
424 * options on this device. See the Clock Distribution chapter for more information
425 * including clocking diagrams and definitions of device clocks.
427 typedef union _hw_sim_sopt2
430 struct _hw_sim_sopt2_bitfields
432 uint32_t RESERVED0 : 4; /*!< [3:0] */
433 uint32_t RTCCLKOUTSEL : 1; /*!< [4] RTC clock out select */
434 uint32_t CLKOUTSEL : 3; /*!< [7:5] CLKOUT select */
435 uint32_t FBSL : 2; /*!< [9:8] FlexBus security level */
436 uint32_t RESERVED1 : 1; /*!< [10] */
437 uint32_t PTD7PAD : 1; /*!< [11] PTD7 pad drive strength */
438 uint32_t TRACECLKSEL : 1; /*!< [12] Debug trace clock select */
439 uint32_t RESERVED2 : 3; /*!< [15:13] */
440 uint32_t PLLFLLSEL : 2; /*!< [17:16] PLL/FLL clock select */
441 uint32_t USBSRC : 1; /*!< [18] USB clock source select */
442 uint32_t RMIISRC : 1; /*!< [19] RMII clock source select */
443 uint32_t TIMESRC : 2; /*!< [21:20] IEEE 1588 timestamp clock source
445 uint32_t RESERVED3 : 6; /*!< [27:22] */
446 uint32_t SDHCSRC : 2; /*!< [29:28] SDHC clock source select */
447 uint32_t RESERVED4 : 2; /*!< [31:30] */
452 * @name Constants and macros for entire SIM_SOPT2 register
455 #define HW_SIM_SOPT2_ADDR(x) ((x) + 0x1004U)
457 #define HW_SIM_SOPT2(x) (*(__IO hw_sim_sopt2_t *) HW_SIM_SOPT2_ADDR(x))
458 #define HW_SIM_SOPT2_RD(x) (HW_SIM_SOPT2(x).U)
459 #define HW_SIM_SOPT2_WR(x, v) (HW_SIM_SOPT2(x).U = (v))
460 #define HW_SIM_SOPT2_SET(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) | (v)))
461 #define HW_SIM_SOPT2_CLR(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) & ~(v)))
462 #define HW_SIM_SOPT2_TOG(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) ^ (v)))
466 * Constants & macros for individual SIM_SOPT2 bitfields
470 * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
472 * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
476 * - 0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
477 * - 1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
480 #define BP_SIM_SOPT2_RTCCLKOUTSEL (4U) /*!< Bit position for SIM_SOPT2_RTCCLKOUTSEL. */
481 #define BM_SIM_SOPT2_RTCCLKOUTSEL (0x00000010U) /*!< Bit mask for SIM_SOPT2_RTCCLKOUTSEL. */
482 #define BS_SIM_SOPT2_RTCCLKOUTSEL (1U) /*!< Bit field size in bits for SIM_SOPT2_RTCCLKOUTSEL. */
484 /*! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. */
485 #define BR_SIM_SOPT2_RTCCLKOUTSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL))
487 /*! @brief Format value for bitfield SIM_SOPT2_RTCCLKOUTSEL. */
488 #define BF_SIM_SOPT2_RTCCLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RTCCLKOUTSEL) & BM_SIM_SOPT2_RTCCLKOUTSEL)
490 /*! @brief Set the RTCCLKOUTSEL field to a new value. */
491 #define BW_SIM_SOPT2_RTCCLKOUTSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL) = (v))
495 * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
497 * Selects the clock to output on the CLKOUT pin.
500 * - 000 - FlexBus CLKOUT
502 * - 010 - Flash clock
503 * - 011 - LPO clock (1 kHz)
505 * - 101 - RTC 32.768kHz clock
507 * - 111 - IRC 48 MHz clock
510 #define BP_SIM_SOPT2_CLKOUTSEL (5U) /*!< Bit position for SIM_SOPT2_CLKOUTSEL. */
511 #define BM_SIM_SOPT2_CLKOUTSEL (0x000000E0U) /*!< Bit mask for SIM_SOPT2_CLKOUTSEL. */
512 #define BS_SIM_SOPT2_CLKOUTSEL (3U) /*!< Bit field size in bits for SIM_SOPT2_CLKOUTSEL. */
514 /*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */
515 #define BR_SIM_SOPT2_CLKOUTSEL(x) (HW_SIM_SOPT2(x).B.CLKOUTSEL)
517 /*! @brief Format value for bitfield SIM_SOPT2_CLKOUTSEL. */
518 #define BF_SIM_SOPT2_CLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_CLKOUTSEL) & BM_SIM_SOPT2_CLKOUTSEL)
520 /*! @brief Set the CLKOUTSEL field to a new value. */
521 #define BW_SIM_SOPT2_CLKOUTSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_CLKOUTSEL) | BF_SIM_SOPT2_CLKOUTSEL(v)))
525 * @name Register SIM_SOPT2, field FBSL[9:8] (RW)
527 * If flash security is enabled, then this field affects what CPU operations can
528 * access off-chip via the FlexBus interface. This field has no effect if flash
529 * security is not enabled.
532 * - 00 - All off-chip accesses (instruction and data) via the FlexBus are
534 * - 01 - All off-chip accesses (instruction and data) via the FlexBus are
536 * - 10 - Off-chip instruction accesses are disallowed. Data accesses are
538 * - 11 - Off-chip instruction accesses and data accesses are allowed.
541 #define BP_SIM_SOPT2_FBSL (8U) /*!< Bit position for SIM_SOPT2_FBSL. */
542 #define BM_SIM_SOPT2_FBSL (0x00000300U) /*!< Bit mask for SIM_SOPT2_FBSL. */
543 #define BS_SIM_SOPT2_FBSL (2U) /*!< Bit field size in bits for SIM_SOPT2_FBSL. */
545 /*! @brief Read current value of the SIM_SOPT2_FBSL field. */
546 #define BR_SIM_SOPT2_FBSL(x) (HW_SIM_SOPT2(x).B.FBSL)
548 /*! @brief Format value for bitfield SIM_SOPT2_FBSL. */
549 #define BF_SIM_SOPT2_FBSL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_FBSL) & BM_SIM_SOPT2_FBSL)
551 /*! @brief Set the FBSL field to a new value. */
552 #define BW_SIM_SOPT2_FBSL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_FBSL) | BF_SIM_SOPT2_FBSL(v)))
556 * @name Register SIM_SOPT2, field PTD7PAD[11] (RW)
558 * Controls the output drive strength of the PTD7 pin by selecting either one or
559 * two pads to drive it.
562 * - 0 - Single-pad drive strength for PTD7.
563 * - 1 - Double pad drive strength for PTD7.
566 #define BP_SIM_SOPT2_PTD7PAD (11U) /*!< Bit position for SIM_SOPT2_PTD7PAD. */
567 #define BM_SIM_SOPT2_PTD7PAD (0x00000800U) /*!< Bit mask for SIM_SOPT2_PTD7PAD. */
568 #define BS_SIM_SOPT2_PTD7PAD (1U) /*!< Bit field size in bits for SIM_SOPT2_PTD7PAD. */
570 /*! @brief Read current value of the SIM_SOPT2_PTD7PAD field. */
571 #define BR_SIM_SOPT2_PTD7PAD(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_PTD7PAD))
573 /*! @brief Format value for bitfield SIM_SOPT2_PTD7PAD. */
574 #define BF_SIM_SOPT2_PTD7PAD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PTD7PAD) & BM_SIM_SOPT2_PTD7PAD)
576 /*! @brief Set the PTD7PAD field to a new value. */
577 #define BW_SIM_SOPT2_PTD7PAD(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_PTD7PAD) = (v))
581 * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
583 * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
588 * - 1 - Core/system clock
591 #define BP_SIM_SOPT2_TRACECLKSEL (12U) /*!< Bit position for SIM_SOPT2_TRACECLKSEL. */
592 #define BM_SIM_SOPT2_TRACECLKSEL (0x00001000U) /*!< Bit mask for SIM_SOPT2_TRACECLKSEL. */
593 #define BS_SIM_SOPT2_TRACECLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT2_TRACECLKSEL. */
595 /*! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. */
596 #define BR_SIM_SOPT2_TRACECLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL))
598 /*! @brief Format value for bitfield SIM_SOPT2_TRACECLKSEL. */
599 #define BF_SIM_SOPT2_TRACECLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TRACECLKSEL) & BM_SIM_SOPT2_TRACECLKSEL)
601 /*! @brief Set the TRACECLKSEL field to a new value. */
602 #define BW_SIM_SOPT2_TRACECLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL) = (v))
606 * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
608 * Selects the high frequency clock for various peripheral clocking options.
611 * - 00 - MCGFLLCLK clock
612 * - 01 - MCGPLLCLK clock
614 * - 11 - IRC48 MHz clock
617 #define BP_SIM_SOPT2_PLLFLLSEL (16U) /*!< Bit position for SIM_SOPT2_PLLFLLSEL. */
618 #define BM_SIM_SOPT2_PLLFLLSEL (0x00030000U) /*!< Bit mask for SIM_SOPT2_PLLFLLSEL. */
619 #define BS_SIM_SOPT2_PLLFLLSEL (2U) /*!< Bit field size in bits for SIM_SOPT2_PLLFLLSEL. */
621 /*! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. */
622 #define BR_SIM_SOPT2_PLLFLLSEL(x) (HW_SIM_SOPT2(x).B.PLLFLLSEL)
624 /*! @brief Format value for bitfield SIM_SOPT2_PLLFLLSEL. */
625 #define BF_SIM_SOPT2_PLLFLLSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PLLFLLSEL) & BM_SIM_SOPT2_PLLFLLSEL)
627 /*! @brief Set the PLLFLLSEL field to a new value. */
628 #define BW_SIM_SOPT2_PLLFLLSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_PLLFLLSEL) | BF_SIM_SOPT2_PLLFLLSEL(v)))
632 * @name Register SIM_SOPT2, field USBSRC[18] (RW)
634 * Selects the clock source for the USB 48 MHz clock.
637 * - 0 - External bypass clock (USB_CLKIN).
638 * - 1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
639 * SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
640 * SIM_CLKDIV2[USBFRAC, USBDIV].
643 #define BP_SIM_SOPT2_USBSRC (18U) /*!< Bit position for SIM_SOPT2_USBSRC. */
644 #define BM_SIM_SOPT2_USBSRC (0x00040000U) /*!< Bit mask for SIM_SOPT2_USBSRC. */
645 #define BS_SIM_SOPT2_USBSRC (1U) /*!< Bit field size in bits for SIM_SOPT2_USBSRC. */
647 /*! @brief Read current value of the SIM_SOPT2_USBSRC field. */
648 #define BR_SIM_SOPT2_USBSRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC))
650 /*! @brief Format value for bitfield SIM_SOPT2_USBSRC. */
651 #define BF_SIM_SOPT2_USBSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_USBSRC) & BM_SIM_SOPT2_USBSRC)
653 /*! @brief Set the USBSRC field to a new value. */
654 #define BW_SIM_SOPT2_USBSRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC) = (v))
658 * @name Register SIM_SOPT2, field RMIISRC[19] (RW)
660 * Selects the clock source for the Ethernet RMII interface
664 * - 1 - External bypass clock (ENET_1588_CLKIN).
667 #define BP_SIM_SOPT2_RMIISRC (19U) /*!< Bit position for SIM_SOPT2_RMIISRC. */
668 #define BM_SIM_SOPT2_RMIISRC (0x00080000U) /*!< Bit mask for SIM_SOPT2_RMIISRC. */
669 #define BS_SIM_SOPT2_RMIISRC (1U) /*!< Bit field size in bits for SIM_SOPT2_RMIISRC. */
671 /*! @brief Read current value of the SIM_SOPT2_RMIISRC field. */
672 #define BR_SIM_SOPT2_RMIISRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RMIISRC))
674 /*! @brief Format value for bitfield SIM_SOPT2_RMIISRC. */
675 #define BF_SIM_SOPT2_RMIISRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RMIISRC) & BM_SIM_SOPT2_RMIISRC)
677 /*! @brief Set the RMIISRC field to a new value. */
678 #define BW_SIM_SOPT2_RMIISRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RMIISRC) = (v))
682 * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
684 * Selects the clock source for the Ethernet timestamp clock.
687 * - 00 - Core/system clock.
688 * - 01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
690 * - 10 - OSCERCLK clock
691 * - 11 - External bypass clock (ENET_1588_CLKIN).
694 #define BP_SIM_SOPT2_TIMESRC (20U) /*!< Bit position for SIM_SOPT2_TIMESRC. */
695 #define BM_SIM_SOPT2_TIMESRC (0x00300000U) /*!< Bit mask for SIM_SOPT2_TIMESRC. */
696 #define BS_SIM_SOPT2_TIMESRC (2U) /*!< Bit field size in bits for SIM_SOPT2_TIMESRC. */
698 /*! @brief Read current value of the SIM_SOPT2_TIMESRC field. */
699 #define BR_SIM_SOPT2_TIMESRC(x) (HW_SIM_SOPT2(x).B.TIMESRC)
701 /*! @brief Format value for bitfield SIM_SOPT2_TIMESRC. */
702 #define BF_SIM_SOPT2_TIMESRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TIMESRC) & BM_SIM_SOPT2_TIMESRC)
704 /*! @brief Set the TIMESRC field to a new value. */
705 #define BW_SIM_SOPT2_TIMESRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_TIMESRC) | BF_SIM_SOPT2_TIMESRC(v)))
709 * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW)
711 * Selects the clock source for the SDHC clock .
714 * - 00 - Core/system clock.
715 * - 01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by
717 * - 10 - OSCERCLK clock
718 * - 11 - External bypass clock (SDHC0_CLKIN)
721 #define BP_SIM_SOPT2_SDHCSRC (28U) /*!< Bit position for SIM_SOPT2_SDHCSRC. */
722 #define BM_SIM_SOPT2_SDHCSRC (0x30000000U) /*!< Bit mask for SIM_SOPT2_SDHCSRC. */
723 #define BS_SIM_SOPT2_SDHCSRC (2U) /*!< Bit field size in bits for SIM_SOPT2_SDHCSRC. */
725 /*! @brief Read current value of the SIM_SOPT2_SDHCSRC field. */
726 #define BR_SIM_SOPT2_SDHCSRC(x) (HW_SIM_SOPT2(x).B.SDHCSRC)
728 /*! @brief Format value for bitfield SIM_SOPT2_SDHCSRC. */
729 #define BF_SIM_SOPT2_SDHCSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_SDHCSRC) & BM_SIM_SOPT2_SDHCSRC)
731 /*! @brief Set the SDHCSRC field to a new value. */
732 #define BW_SIM_SOPT2_SDHCSRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_SDHCSRC) | BF_SIM_SOPT2_SDHCSRC(v)))
735 /*******************************************************************************
736 * HW_SIM_SOPT4 - System Options Register 4
737 ******************************************************************************/
740 * @brief HW_SIM_SOPT4 - System Options Register 4 (RW)
742 * Reset value: 0x00000000U
744 typedef union _hw_sim_sopt4
747 struct _hw_sim_sopt4_bitfields
749 uint32_t FTM0FLT0 : 1; /*!< [0] FTM0 Fault 0 Select */
750 uint32_t FTM0FLT1 : 1; /*!< [1] FTM0 Fault 1 Select */
751 uint32_t FTM0FLT2 : 1; /*!< [2] FTM0 Fault 2 Select */
752 uint32_t RESERVED0 : 1; /*!< [3] */
753 uint32_t FTM1FLT0 : 1; /*!< [4] FTM1 Fault 0 Select */
754 uint32_t RESERVED1 : 3; /*!< [7:5] */
755 uint32_t FTM2FLT0 : 1; /*!< [8] FTM2 Fault 0 Select */
756 uint32_t RESERVED2 : 3; /*!< [11:9] */
757 uint32_t FTM3FLT0 : 1; /*!< [12] FTM3 Fault 0 Select */
758 uint32_t RESERVED3 : 5; /*!< [17:13] */
759 uint32_t FTM1CH0SRC : 2; /*!< [19:18] FTM1 channel 0 input capture
761 uint32_t FTM2CH0SRC : 2; /*!< [21:20] FTM2 channel 0 input capture
763 uint32_t RESERVED4 : 2; /*!< [23:22] */
764 uint32_t FTM0CLKSEL : 1; /*!< [24] FlexTimer 0 External Clock Pin
766 uint32_t FTM1CLKSEL : 1; /*!< [25] FTM1 External Clock Pin Select */
767 uint32_t FTM2CLKSEL : 1; /*!< [26] FlexTimer 2 External Clock Pin
769 uint32_t FTM3CLKSEL : 1; /*!< [27] FlexTimer 3 External Clock Pin
771 uint32_t FTM0TRG0SRC : 1; /*!< [28] FlexTimer 0 Hardware Trigger 0
773 uint32_t FTM0TRG1SRC : 1; /*!< [29] FlexTimer 0 Hardware Trigger 1
775 uint32_t FTM3TRG0SRC : 1; /*!< [30] FlexTimer 3 Hardware Trigger 0
777 uint32_t FTM3TRG1SRC : 1; /*!< [31] FlexTimer 3 Hardware Trigger 1
783 * @name Constants and macros for entire SIM_SOPT4 register
786 #define HW_SIM_SOPT4_ADDR(x) ((x) + 0x100CU)
788 #define HW_SIM_SOPT4(x) (*(__IO hw_sim_sopt4_t *) HW_SIM_SOPT4_ADDR(x))
789 #define HW_SIM_SOPT4_RD(x) (HW_SIM_SOPT4(x).U)
790 #define HW_SIM_SOPT4_WR(x, v) (HW_SIM_SOPT4(x).U = (v))
791 #define HW_SIM_SOPT4_SET(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) | (v)))
792 #define HW_SIM_SOPT4_CLR(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) & ~(v)))
793 #define HW_SIM_SOPT4_TOG(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) ^ (v)))
797 * Constants & macros for individual SIM_SOPT4 bitfields
801 * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
803 * Selects the source of FTM0 fault 0. The pin source for fault 0 must be
804 * configured for the FTM module fault function through the appropriate pin control
805 * register in the port control module.
808 * - 0 - FTM0_FLT0 pin
812 #define BP_SIM_SOPT4_FTM0FLT0 (0U) /*!< Bit position for SIM_SOPT4_FTM0FLT0. */
813 #define BM_SIM_SOPT4_FTM0FLT0 (0x00000001U) /*!< Bit mask for SIM_SOPT4_FTM0FLT0. */
814 #define BS_SIM_SOPT4_FTM0FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT0. */
816 /*! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. */
817 #define BR_SIM_SOPT4_FTM0FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0))
819 /*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT0. */
820 #define BF_SIM_SOPT4_FTM0FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT0) & BM_SIM_SOPT4_FTM0FLT0)
822 /*! @brief Set the FTM0FLT0 field to a new value. */
823 #define BW_SIM_SOPT4_FTM0FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0) = (v))
827 * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
829 * Selects the source of FTM0 fault 1. The pin source for fault 1 must be
830 * configured for the FTM module fault function through the appropriate pin control
831 * register in the port control module.
834 * - 0 - FTM0_FLT1 pin
838 #define BP_SIM_SOPT4_FTM0FLT1 (1U) /*!< Bit position for SIM_SOPT4_FTM0FLT1. */
839 #define BM_SIM_SOPT4_FTM0FLT1 (0x00000002U) /*!< Bit mask for SIM_SOPT4_FTM0FLT1. */
840 #define BS_SIM_SOPT4_FTM0FLT1 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT1. */
842 /*! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. */
843 #define BR_SIM_SOPT4_FTM0FLT1(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1))
845 /*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT1. */
846 #define BF_SIM_SOPT4_FTM0FLT1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT1) & BM_SIM_SOPT4_FTM0FLT1)
848 /*! @brief Set the FTM0FLT1 field to a new value. */
849 #define BW_SIM_SOPT4_FTM0FLT1(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1) = (v))
853 * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
855 * Selects the source of FTM0 fault 2. The pin source for fault 2 must be
856 * configured for the FTM module fault function through the appropriate pin control
857 * register in the port control module.
860 * - 0 - FTM0_FLT2 pin
864 #define BP_SIM_SOPT4_FTM0FLT2 (2U) /*!< Bit position for SIM_SOPT4_FTM0FLT2. */
865 #define BM_SIM_SOPT4_FTM0FLT2 (0x00000004U) /*!< Bit mask for SIM_SOPT4_FTM0FLT2. */
866 #define BS_SIM_SOPT4_FTM0FLT2 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT2. */
868 /*! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field. */
869 #define BR_SIM_SOPT4_FTM0FLT2(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT2))
871 /*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT2. */
872 #define BF_SIM_SOPT4_FTM0FLT2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT2) & BM_SIM_SOPT4_FTM0FLT2)
874 /*! @brief Set the FTM0FLT2 field to a new value. */
875 #define BW_SIM_SOPT4_FTM0FLT2(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT2) = (v))
879 * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
881 * Selects the source of FTM1 fault 0. The pin source for fault 0 must be
882 * configured for the FTM module fault function through the appropriate pin control
883 * register in the port control module.
886 * - 0 - FTM1_FLT0 pin
890 #define BP_SIM_SOPT4_FTM1FLT0 (4U) /*!< Bit position for SIM_SOPT4_FTM1FLT0. */
891 #define BM_SIM_SOPT4_FTM1FLT0 (0x00000010U) /*!< Bit mask for SIM_SOPT4_FTM1FLT0. */
892 #define BS_SIM_SOPT4_FTM1FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM1FLT0. */
894 /*! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. */
895 #define BR_SIM_SOPT4_FTM1FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0))
897 /*! @brief Format value for bitfield SIM_SOPT4_FTM1FLT0. */
898 #define BF_SIM_SOPT4_FTM1FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1FLT0) & BM_SIM_SOPT4_FTM1FLT0)
900 /*! @brief Set the FTM1FLT0 field to a new value. */
901 #define BW_SIM_SOPT4_FTM1FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0) = (v))
905 * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
907 * Selects the source of FTM2 fault 0. The pin source for fault 0 must be
908 * configured for the FTM module fault function through the appropriate PORTx pin
912 * - 0 - FTM2_FLT0 pin
916 #define BP_SIM_SOPT4_FTM2FLT0 (8U) /*!< Bit position for SIM_SOPT4_FTM2FLT0. */
917 #define BM_SIM_SOPT4_FTM2FLT0 (0x00000100U) /*!< Bit mask for SIM_SOPT4_FTM2FLT0. */
918 #define BS_SIM_SOPT4_FTM2FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM2FLT0. */
920 /*! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. */
921 #define BR_SIM_SOPT4_FTM2FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0))
923 /*! @brief Format value for bitfield SIM_SOPT4_FTM2FLT0. */
924 #define BF_SIM_SOPT4_FTM2FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2FLT0) & BM_SIM_SOPT4_FTM2FLT0)
926 /*! @brief Set the FTM2FLT0 field to a new value. */
927 #define BW_SIM_SOPT4_FTM2FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0) = (v))
931 * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
933 * Selects the source of FTM3 fault 0. The pin source for fault 0 must be
934 * configured for the FTM module fault function through the appropriate PORTx pin
938 * - 0 - FTM3_FLT0 pin
942 #define BP_SIM_SOPT4_FTM3FLT0 (12U) /*!< Bit position for SIM_SOPT4_FTM3FLT0. */
943 #define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) /*!< Bit mask for SIM_SOPT4_FTM3FLT0. */
944 #define BS_SIM_SOPT4_FTM3FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3FLT0. */
946 /*! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. */
947 #define BR_SIM_SOPT4_FTM3FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0))
949 /*! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0. */
950 #define BF_SIM_SOPT4_FTM3FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3FLT0) & BM_SIM_SOPT4_FTM3FLT0)
952 /*! @brief Set the FTM3FLT0 field to a new value. */
953 #define BW_SIM_SOPT4_FTM3FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0) = (v))
957 * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
959 * Selects the source for FTM1 channel 0 input capture. When the FTM is not in
960 * input capture mode, clear this field.
963 * - 00 - FTM1_CH0 signal
966 * - 11 - USB start of frame pulse
969 #define BP_SIM_SOPT4_FTM1CH0SRC (18U) /*!< Bit position for SIM_SOPT4_FTM1CH0SRC. */
970 #define BM_SIM_SOPT4_FTM1CH0SRC (0x000C0000U) /*!< Bit mask for SIM_SOPT4_FTM1CH0SRC. */
971 #define BS_SIM_SOPT4_FTM1CH0SRC (2U) /*!< Bit field size in bits for SIM_SOPT4_FTM1CH0SRC. */
973 /*! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. */
974 #define BR_SIM_SOPT4_FTM1CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM1CH0SRC)
976 /*! @brief Format value for bitfield SIM_SOPT4_FTM1CH0SRC. */
977 #define BF_SIM_SOPT4_FTM1CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CH0SRC) & BM_SIM_SOPT4_FTM1CH0SRC)
979 /*! @brief Set the FTM1CH0SRC field to a new value. */
980 #define BW_SIM_SOPT4_FTM1CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM1CH0SRC) | BF_SIM_SOPT4_FTM1CH0SRC(v)))
984 * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
986 * Selects the source for FTM2 channel 0 input capture. When the FTM is not in
987 * input capture mode, clear this field.
990 * - 00 - FTM2_CH0 signal
996 #define BP_SIM_SOPT4_FTM2CH0SRC (20U) /*!< Bit position for SIM_SOPT4_FTM2CH0SRC. */
997 #define BM_SIM_SOPT4_FTM2CH0SRC (0x00300000U) /*!< Bit mask for SIM_SOPT4_FTM2CH0SRC. */
998 #define BS_SIM_SOPT4_FTM2CH0SRC (2U) /*!< Bit field size in bits for SIM_SOPT4_FTM2CH0SRC. */
1000 /*! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. */
1001 #define BR_SIM_SOPT4_FTM2CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM2CH0SRC)
1003 /*! @brief Format value for bitfield SIM_SOPT4_FTM2CH0SRC. */
1004 #define BF_SIM_SOPT4_FTM2CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CH0SRC) & BM_SIM_SOPT4_FTM2CH0SRC)
1006 /*! @brief Set the FTM2CH0SRC field to a new value. */
1007 #define BW_SIM_SOPT4_FTM2CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM2CH0SRC) | BF_SIM_SOPT4_FTM2CH0SRC(v)))
1011 * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
1013 * Selects the external pin used to drive the clock to the FTM0 module. The
1014 * selected pin must also be configured for the FTM external clock function through
1015 * the appropriate pin control register in the port control module.
1018 * - 0 - FTM_CLK0 pin
1019 * - 1 - FTM_CLK1 pin
1022 #define BP_SIM_SOPT4_FTM0CLKSEL (24U) /*!< Bit position for SIM_SOPT4_FTM0CLKSEL. */
1023 #define BM_SIM_SOPT4_FTM0CLKSEL (0x01000000U) /*!< Bit mask for SIM_SOPT4_FTM0CLKSEL. */
1024 #define BS_SIM_SOPT4_FTM0CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0CLKSEL. */
1026 /*! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. */
1027 #define BR_SIM_SOPT4_FTM0CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL))
1029 /*! @brief Format value for bitfield SIM_SOPT4_FTM0CLKSEL. */
1030 #define BF_SIM_SOPT4_FTM0CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0CLKSEL) & BM_SIM_SOPT4_FTM0CLKSEL)
1032 /*! @brief Set the FTM0CLKSEL field to a new value. */
1033 #define BW_SIM_SOPT4_FTM0CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL) = (v))
1037 * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
1039 * Selects the external pin used to drive the clock to the FTM1 module. The
1040 * selected pin must also be configured for the FTM external clock function through
1041 * the appropriate pin control register in the port control module.
1044 * - 0 - FTM_CLK0 pin
1045 * - 1 - FTM_CLK1 pin
1048 #define BP_SIM_SOPT4_FTM1CLKSEL (25U) /*!< Bit position for SIM_SOPT4_FTM1CLKSEL. */
1049 #define BM_SIM_SOPT4_FTM1CLKSEL (0x02000000U) /*!< Bit mask for SIM_SOPT4_FTM1CLKSEL. */
1050 #define BS_SIM_SOPT4_FTM1CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM1CLKSEL. */
1052 /*! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. */
1053 #define BR_SIM_SOPT4_FTM1CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL))
1055 /*! @brief Format value for bitfield SIM_SOPT4_FTM1CLKSEL. */
1056 #define BF_SIM_SOPT4_FTM1CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CLKSEL) & BM_SIM_SOPT4_FTM1CLKSEL)
1058 /*! @brief Set the FTM1CLKSEL field to a new value. */
1059 #define BW_SIM_SOPT4_FTM1CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL) = (v))
1063 * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
1065 * Selects the external pin used to drive the clock to the FTM2 module. The
1066 * selected pin must also be configured for the FTM2 module external clock function
1067 * through the appropriate pin control register in the port control module.
1070 * - 0 - FTM2 external clock driven by FTM_CLK0 pin.
1071 * - 1 - FTM2 external clock driven by FTM_CLK1 pin.
1074 #define BP_SIM_SOPT4_FTM2CLKSEL (26U) /*!< Bit position for SIM_SOPT4_FTM2CLKSEL. */
1075 #define BM_SIM_SOPT4_FTM2CLKSEL (0x04000000U) /*!< Bit mask for SIM_SOPT4_FTM2CLKSEL. */
1076 #define BS_SIM_SOPT4_FTM2CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM2CLKSEL. */
1078 /*! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. */
1079 #define BR_SIM_SOPT4_FTM2CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL))
1081 /*! @brief Format value for bitfield SIM_SOPT4_FTM2CLKSEL. */
1082 #define BF_SIM_SOPT4_FTM2CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CLKSEL) & BM_SIM_SOPT4_FTM2CLKSEL)
1084 /*! @brief Set the FTM2CLKSEL field to a new value. */
1085 #define BW_SIM_SOPT4_FTM2CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL) = (v))
1089 * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
1091 * Selects the external pin used to drive the clock to the FTM3 module. The
1092 * selected pin must also be configured for the FTM3 module external clock function
1093 * through the appropriate pin control register in the port control module.
1096 * - 0 - FTM3 external clock driven by FTM_CLK0 pin.
1097 * - 1 - FTM3 external clock driven by FTM_CLK1 pin.
1100 #define BP_SIM_SOPT4_FTM3CLKSEL (27U) /*!< Bit position for SIM_SOPT4_FTM3CLKSEL. */
1101 #define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) /*!< Bit mask for SIM_SOPT4_FTM3CLKSEL. */
1102 #define BS_SIM_SOPT4_FTM3CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL. */
1104 /*! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. */
1105 #define BR_SIM_SOPT4_FTM3CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL))
1107 /*! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL. */
1108 #define BF_SIM_SOPT4_FTM3CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3CLKSEL) & BM_SIM_SOPT4_FTM3CLKSEL)
1110 /*! @brief Set the FTM3CLKSEL field to a new value. */
1111 #define BW_SIM_SOPT4_FTM3CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL) = (v))
1115 * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
1117 * Selects the source of FTM0 hardware trigger 0.
1120 * - 0 - HSCMP0 output drives FTM0 hardware trigger 0
1121 * - 1 - FTM1 channel match drives FTM0 hardware trigger 0
1124 #define BP_SIM_SOPT4_FTM0TRG0SRC (28U) /*!< Bit position for SIM_SOPT4_FTM0TRG0SRC. */
1125 #define BM_SIM_SOPT4_FTM0TRG0SRC (0x10000000U) /*!< Bit mask for SIM_SOPT4_FTM0TRG0SRC. */
1126 #define BS_SIM_SOPT4_FTM0TRG0SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0TRG0SRC. */
1128 /*! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. */
1129 #define BR_SIM_SOPT4_FTM0TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC))
1131 /*! @brief Format value for bitfield SIM_SOPT4_FTM0TRG0SRC. */
1132 #define BF_SIM_SOPT4_FTM0TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG0SRC) & BM_SIM_SOPT4_FTM0TRG0SRC)
1134 /*! @brief Set the FTM0TRG0SRC field to a new value. */
1135 #define BW_SIM_SOPT4_FTM0TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC) = (v))
1139 * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
1141 * Selects the source of FTM0 hardware trigger 1.
1144 * - 0 - PDB output trigger 1 drives FTM0 hardware trigger 1
1145 * - 1 - FTM2 channel match drives FTM0 hardware trigger 1
1148 #define BP_SIM_SOPT4_FTM0TRG1SRC (29U) /*!< Bit position for SIM_SOPT4_FTM0TRG1SRC. */
1149 #define BM_SIM_SOPT4_FTM0TRG1SRC (0x20000000U) /*!< Bit mask for SIM_SOPT4_FTM0TRG1SRC. */
1150 #define BS_SIM_SOPT4_FTM0TRG1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0TRG1SRC. */
1152 /*! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. */
1153 #define BR_SIM_SOPT4_FTM0TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC))
1155 /*! @brief Format value for bitfield SIM_SOPT4_FTM0TRG1SRC. */
1156 #define BF_SIM_SOPT4_FTM0TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG1SRC) & BM_SIM_SOPT4_FTM0TRG1SRC)
1158 /*! @brief Set the FTM0TRG1SRC field to a new value. */
1159 #define BW_SIM_SOPT4_FTM0TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC) = (v))
1163 * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
1165 * Selects the source of FTM3 hardware trigger 0.
1169 * - 1 - FTM1 channel match drives FTM3 hardware trigger 0
1172 #define BP_SIM_SOPT4_FTM3TRG0SRC (30U) /*!< Bit position for SIM_SOPT4_FTM3TRG0SRC. */
1173 #define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG0SRC. */
1174 #define BS_SIM_SOPT4_FTM3TRG0SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC. */
1176 /*! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. */
1177 #define BR_SIM_SOPT4_FTM3TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC))
1179 /*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC. */
1180 #define BF_SIM_SOPT4_FTM3TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG0SRC) & BM_SIM_SOPT4_FTM3TRG0SRC)
1182 /*! @brief Set the FTM3TRG0SRC field to a new value. */
1183 #define BW_SIM_SOPT4_FTM3TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC) = (v))
1187 * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
1189 * Selects the source of FTM3 hardware trigger 1.
1193 * - 1 - FTM2 channel match drives FTM3 hardware trigger 1
1196 #define BP_SIM_SOPT4_FTM3TRG1SRC (31U) /*!< Bit position for SIM_SOPT4_FTM3TRG1SRC. */
1197 #define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG1SRC. */
1198 #define BS_SIM_SOPT4_FTM3TRG1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC. */
1200 /*! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. */
1201 #define BR_SIM_SOPT4_FTM3TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC))
1203 /*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC. */
1204 #define BF_SIM_SOPT4_FTM3TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG1SRC) & BM_SIM_SOPT4_FTM3TRG1SRC)
1206 /*! @brief Set the FTM3TRG1SRC field to a new value. */
1207 #define BW_SIM_SOPT4_FTM3TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC) = (v))
1210 /*******************************************************************************
1211 * HW_SIM_SOPT5 - System Options Register 5
1212 ******************************************************************************/
1215 * @brief HW_SIM_SOPT5 - System Options Register 5 (RW)
1217 * Reset value: 0x00000000U
1219 typedef union _hw_sim_sopt5
1222 struct _hw_sim_sopt5_bitfields
1224 uint32_t UART0TXSRC : 2; /*!< [1:0] UART 0 transmit data source
1226 uint32_t UART0RXSRC : 2; /*!< [3:2] UART 0 receive data source select
1228 uint32_t UART1TXSRC : 2; /*!< [5:4] UART 1 transmit data source
1230 uint32_t UART1RXSRC : 2; /*!< [7:6] UART 1 receive data source select
1232 uint32_t RESERVED0 : 24; /*!< [31:8] */
1237 * @name Constants and macros for entire SIM_SOPT5 register
1240 #define HW_SIM_SOPT5_ADDR(x) ((x) + 0x1010U)
1242 #define HW_SIM_SOPT5(x) (*(__IO hw_sim_sopt5_t *) HW_SIM_SOPT5_ADDR(x))
1243 #define HW_SIM_SOPT5_RD(x) (HW_SIM_SOPT5(x).U)
1244 #define HW_SIM_SOPT5_WR(x, v) (HW_SIM_SOPT5(x).U = (v))
1245 #define HW_SIM_SOPT5_SET(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) | (v)))
1246 #define HW_SIM_SOPT5_CLR(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) & ~(v)))
1247 #define HW_SIM_SOPT5_TOG(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) ^ (v)))
1251 * Constants & macros for individual SIM_SOPT5 bitfields
1255 * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
1257 * Selects the source for the UART 0 transmit data.
1260 * - 00 - UART0_TX pin
1261 * - 01 - UART0_TX pin modulated with FTM1 channel 0 output
1262 * - 10 - UART0_TX pin modulated with FTM2 channel 0 output
1266 #define BP_SIM_SOPT5_UART0TXSRC (0U) /*!< Bit position for SIM_SOPT5_UART0TXSRC. */
1267 #define BM_SIM_SOPT5_UART0TXSRC (0x00000003U) /*!< Bit mask for SIM_SOPT5_UART0TXSRC. */
1268 #define BS_SIM_SOPT5_UART0TXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART0TXSRC. */
1270 /*! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. */
1271 #define BR_SIM_SOPT5_UART0TXSRC(x) (HW_SIM_SOPT5(x).B.UART0TXSRC)
1273 /*! @brief Format value for bitfield SIM_SOPT5_UART0TXSRC. */
1274 #define BF_SIM_SOPT5_UART0TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0TXSRC) & BM_SIM_SOPT5_UART0TXSRC)
1276 /*! @brief Set the UART0TXSRC field to a new value. */
1277 #define BW_SIM_SOPT5_UART0TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0TXSRC) | BF_SIM_SOPT5_UART0TXSRC(v)))
1281 * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
1283 * Selects the source for the UART 0 receive data.
1286 * - 00 - UART0_RX pin
1292 #define BP_SIM_SOPT5_UART0RXSRC (2U) /*!< Bit position for SIM_SOPT5_UART0RXSRC. */
1293 #define BM_SIM_SOPT5_UART0RXSRC (0x0000000CU) /*!< Bit mask for SIM_SOPT5_UART0RXSRC. */
1294 #define BS_SIM_SOPT5_UART0RXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART0RXSRC. */
1296 /*! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. */
1297 #define BR_SIM_SOPT5_UART0RXSRC(x) (HW_SIM_SOPT5(x).B.UART0RXSRC)
1299 /*! @brief Format value for bitfield SIM_SOPT5_UART0RXSRC. */
1300 #define BF_SIM_SOPT5_UART0RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0RXSRC) & BM_SIM_SOPT5_UART0RXSRC)
1302 /*! @brief Set the UART0RXSRC field to a new value. */
1303 #define BW_SIM_SOPT5_UART0RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0RXSRC) | BF_SIM_SOPT5_UART0RXSRC(v)))
1307 * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
1309 * Selects the source for the UART 1 transmit data.
1312 * - 00 - UART1_TX pin
1313 * - 01 - UART1_TX pin modulated with FTM1 channel 0 output
1314 * - 10 - UART1_TX pin modulated with FTM2 channel 0 output
1318 #define BP_SIM_SOPT5_UART1TXSRC (4U) /*!< Bit position for SIM_SOPT5_UART1TXSRC. */
1319 #define BM_SIM_SOPT5_UART1TXSRC (0x00000030U) /*!< Bit mask for SIM_SOPT5_UART1TXSRC. */
1320 #define BS_SIM_SOPT5_UART1TXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART1TXSRC. */
1322 /*! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. */
1323 #define BR_SIM_SOPT5_UART1TXSRC(x) (HW_SIM_SOPT5(x).B.UART1TXSRC)
1325 /*! @brief Format value for bitfield SIM_SOPT5_UART1TXSRC. */
1326 #define BF_SIM_SOPT5_UART1TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1TXSRC) & BM_SIM_SOPT5_UART1TXSRC)
1328 /*! @brief Set the UART1TXSRC field to a new value. */
1329 #define BW_SIM_SOPT5_UART1TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1TXSRC) | BF_SIM_SOPT5_UART1TXSRC(v)))
1333 * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
1335 * Selects the source for the UART 1 receive data.
1338 * - 00 - UART1_RX pin
1344 #define BP_SIM_SOPT5_UART1RXSRC (6U) /*!< Bit position for SIM_SOPT5_UART1RXSRC. */
1345 #define BM_SIM_SOPT5_UART1RXSRC (0x000000C0U) /*!< Bit mask for SIM_SOPT5_UART1RXSRC. */
1346 #define BS_SIM_SOPT5_UART1RXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART1RXSRC. */
1348 /*! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. */
1349 #define BR_SIM_SOPT5_UART1RXSRC(x) (HW_SIM_SOPT5(x).B.UART1RXSRC)
1351 /*! @brief Format value for bitfield SIM_SOPT5_UART1RXSRC. */
1352 #define BF_SIM_SOPT5_UART1RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1RXSRC) & BM_SIM_SOPT5_UART1RXSRC)
1354 /*! @brief Set the UART1RXSRC field to a new value. */
1355 #define BW_SIM_SOPT5_UART1RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1RXSRC) | BF_SIM_SOPT5_UART1RXSRC(v)))
1358 /*******************************************************************************
1359 * HW_SIM_SOPT7 - System Options Register 7
1360 ******************************************************************************/
1363 * @brief HW_SIM_SOPT7 - System Options Register 7 (RW)
1365 * Reset value: 0x00000000U
1367 typedef union _hw_sim_sopt7
1370 struct _hw_sim_sopt7_bitfields
1372 uint32_t ADC0TRGSEL : 4; /*!< [3:0] ADC0 trigger select */
1373 uint32_t ADC0PRETRGSEL : 1; /*!< [4] ADC0 pretrigger select */
1374 uint32_t RESERVED0 : 2; /*!< [6:5] */
1375 uint32_t ADC0ALTTRGEN : 1; /*!< [7] ADC0 alternate trigger enable */
1376 uint32_t ADC1TRGSEL : 4; /*!< [11:8] ADC1 trigger select */
1377 uint32_t ADC1PRETRGSEL : 1; /*!< [12] ADC1 pre-trigger select */
1378 uint32_t RESERVED1 : 2; /*!< [14:13] */
1379 uint32_t ADC1ALTTRGEN : 1; /*!< [15] ADC1 alternate trigger enable */
1380 uint32_t RESERVED2 : 16; /*!< [31:16] */
1385 * @name Constants and macros for entire SIM_SOPT7 register
1388 #define HW_SIM_SOPT7_ADDR(x) ((x) + 0x1018U)
1390 #define HW_SIM_SOPT7(x) (*(__IO hw_sim_sopt7_t *) HW_SIM_SOPT7_ADDR(x))
1391 #define HW_SIM_SOPT7_RD(x) (HW_SIM_SOPT7(x).U)
1392 #define HW_SIM_SOPT7_WR(x, v) (HW_SIM_SOPT7(x).U = (v))
1393 #define HW_SIM_SOPT7_SET(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) | (v)))
1394 #define HW_SIM_SOPT7_CLR(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) & ~(v)))
1395 #define HW_SIM_SOPT7_TOG(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) ^ (v)))
1399 * Constants & macros for individual SIM_SOPT7 bitfields
1403 * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
1405 * Selects the ADC0 trigger source when alternative triggers are functional in
1406 * stop and VLPS modes. .
1409 * - 0000 - PDB external trigger pin input (PDB0_EXTRG)
1410 * - 0001 - High speed comparator 0 output
1411 * - 0010 - High speed comparator 1 output
1412 * - 0011 - High speed comparator 2 output
1413 * - 0100 - PIT trigger 0
1414 * - 0101 - PIT trigger 1
1415 * - 0110 - PIT trigger 2
1416 * - 0111 - PIT trigger 3
1417 * - 1000 - FTM0 trigger
1418 * - 1001 - FTM1 trigger
1419 * - 1010 - FTM2 trigger
1420 * - 1011 - FTM3 trigger
1421 * - 1100 - RTC alarm
1422 * - 1101 - RTC seconds
1423 * - 1110 - Low-power timer (LPTMR) trigger
1427 #define BP_SIM_SOPT7_ADC0TRGSEL (0U) /*!< Bit position for SIM_SOPT7_ADC0TRGSEL. */
1428 #define BM_SIM_SOPT7_ADC0TRGSEL (0x0000000FU) /*!< Bit mask for SIM_SOPT7_ADC0TRGSEL. */
1429 #define BS_SIM_SOPT7_ADC0TRGSEL (4U) /*!< Bit field size in bits for SIM_SOPT7_ADC0TRGSEL. */
1431 /*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */
1432 #define BR_SIM_SOPT7_ADC0TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC0TRGSEL)
1434 /*! @brief Format value for bitfield SIM_SOPT7_ADC0TRGSEL. */
1435 #define BF_SIM_SOPT7_ADC0TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0TRGSEL) & BM_SIM_SOPT7_ADC0TRGSEL)
1437 /*! @brief Set the ADC0TRGSEL field to a new value. */
1438 #define BW_SIM_SOPT7_ADC0TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC0TRGSEL) | BF_SIM_SOPT7_ADC0TRGSEL(v)))
1442 * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
1444 * Selects the ADC0 pre-trigger source when alternative triggers are enabled
1445 * through ADC0ALTTRGEN.
1448 * - 0 - Pre-trigger A
1449 * - 1 - Pre-trigger B
1452 #define BP_SIM_SOPT7_ADC0PRETRGSEL (4U) /*!< Bit position for SIM_SOPT7_ADC0PRETRGSEL. */
1453 #define BM_SIM_SOPT7_ADC0PRETRGSEL (0x00000010U) /*!< Bit mask for SIM_SOPT7_ADC0PRETRGSEL. */
1454 #define BS_SIM_SOPT7_ADC0PRETRGSEL (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC0PRETRGSEL. */
1456 /*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */
1457 #define BR_SIM_SOPT7_ADC0PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL))
1459 /*! @brief Format value for bitfield SIM_SOPT7_ADC0PRETRGSEL. */
1460 #define BF_SIM_SOPT7_ADC0PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0PRETRGSEL) & BM_SIM_SOPT7_ADC0PRETRGSEL)
1462 /*! @brief Set the ADC0PRETRGSEL field to a new value. */
1463 #define BW_SIM_SOPT7_ADC0PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL) = (v))
1467 * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
1469 * Enable alternative conversion triggers for ADC0.
1472 * - 0 - PDB trigger selected for ADC0.
1473 * - 1 - Alternate trigger selected for ADC0.
1476 #define BP_SIM_SOPT7_ADC0ALTTRGEN (7U) /*!< Bit position for SIM_SOPT7_ADC0ALTTRGEN. */
1477 #define BM_SIM_SOPT7_ADC0ALTTRGEN (0x00000080U) /*!< Bit mask for SIM_SOPT7_ADC0ALTTRGEN. */
1478 #define BS_SIM_SOPT7_ADC0ALTTRGEN (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC0ALTTRGEN. */
1480 /*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */
1481 #define BR_SIM_SOPT7_ADC0ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN))
1483 /*! @brief Format value for bitfield SIM_SOPT7_ADC0ALTTRGEN. */
1484 #define BF_SIM_SOPT7_ADC0ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0ALTTRGEN) & BM_SIM_SOPT7_ADC0ALTTRGEN)
1486 /*! @brief Set the ADC0ALTTRGEN field to a new value. */
1487 #define BW_SIM_SOPT7_ADC0ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN) = (v))
1491 * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
1493 * Selects the ADC1 trigger source when alternative triggers are functional in
1494 * stop and VLPS modes.
1497 * - 0000 - PDB external trigger pin input (PDB0_EXTRG)
1498 * - 0001 - High speed comparator 0 output
1499 * - 0010 - High speed comparator 1 output
1500 * - 0011 - High speed comparator 2 output
1501 * - 0100 - PIT trigger 0
1502 * - 0101 - PIT trigger 1
1503 * - 0110 - PIT trigger 2
1504 * - 0111 - PIT trigger 3
1505 * - 1000 - FTM0 trigger
1506 * - 1001 - FTM1 trigger
1507 * - 1010 - FTM2 trigger
1508 * - 1011 - FTM3 trigger
1509 * - 1100 - RTC alarm
1510 * - 1101 - RTC seconds
1511 * - 1110 - Low-power timer (LPTMR) trigger
1515 #define BP_SIM_SOPT7_ADC1TRGSEL (8U) /*!< Bit position for SIM_SOPT7_ADC1TRGSEL. */
1516 #define BM_SIM_SOPT7_ADC1TRGSEL (0x00000F00U) /*!< Bit mask for SIM_SOPT7_ADC1TRGSEL. */
1517 #define BS_SIM_SOPT7_ADC1TRGSEL (4U) /*!< Bit field size in bits for SIM_SOPT7_ADC1TRGSEL. */
1519 /*! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. */
1520 #define BR_SIM_SOPT7_ADC1TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC1TRGSEL)
1522 /*! @brief Format value for bitfield SIM_SOPT7_ADC1TRGSEL. */
1523 #define BF_SIM_SOPT7_ADC1TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1TRGSEL) & BM_SIM_SOPT7_ADC1TRGSEL)
1525 /*! @brief Set the ADC1TRGSEL field to a new value. */
1526 #define BW_SIM_SOPT7_ADC1TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC1TRGSEL) | BF_SIM_SOPT7_ADC1TRGSEL(v)))
1530 * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
1532 * Selects the ADC1 pre-trigger source when alternative triggers are enabled
1533 * through ADC1ALTTRGEN.
1536 * - 0 - Pre-trigger A selected for ADC1.
1537 * - 1 - Pre-trigger B selected for ADC1.
1540 #define BP_SIM_SOPT7_ADC1PRETRGSEL (12U) /*!< Bit position for SIM_SOPT7_ADC1PRETRGSEL. */
1541 #define BM_SIM_SOPT7_ADC1PRETRGSEL (0x00001000U) /*!< Bit mask for SIM_SOPT7_ADC1PRETRGSEL. */
1542 #define BS_SIM_SOPT7_ADC1PRETRGSEL (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC1PRETRGSEL. */
1544 /*! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. */
1545 #define BR_SIM_SOPT7_ADC1PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL))
1547 /*! @brief Format value for bitfield SIM_SOPT7_ADC1PRETRGSEL. */
1548 #define BF_SIM_SOPT7_ADC1PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1PRETRGSEL) & BM_SIM_SOPT7_ADC1PRETRGSEL)
1550 /*! @brief Set the ADC1PRETRGSEL field to a new value. */
1551 #define BW_SIM_SOPT7_ADC1PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL) = (v))
1555 * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
1557 * Enable alternative conversion triggers for ADC1.
1560 * - 0 - PDB trigger selected for ADC1
1561 * - 1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
1564 #define BP_SIM_SOPT7_ADC1ALTTRGEN (15U) /*!< Bit position for SIM_SOPT7_ADC1ALTTRGEN. */
1565 #define BM_SIM_SOPT7_ADC1ALTTRGEN (0x00008000U) /*!< Bit mask for SIM_SOPT7_ADC1ALTTRGEN. */
1566 #define BS_SIM_SOPT7_ADC1ALTTRGEN (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC1ALTTRGEN. */
1568 /*! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. */
1569 #define BR_SIM_SOPT7_ADC1ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN))
1571 /*! @brief Format value for bitfield SIM_SOPT7_ADC1ALTTRGEN. */
1572 #define BF_SIM_SOPT7_ADC1ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1ALTTRGEN) & BM_SIM_SOPT7_ADC1ALTTRGEN)
1574 /*! @brief Set the ADC1ALTTRGEN field to a new value. */
1575 #define BW_SIM_SOPT7_ADC1ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN) = (v))
1578 /*******************************************************************************
1579 * HW_SIM_SDID - System Device Identification Register
1580 ******************************************************************************/
1583 * @brief HW_SIM_SDID - System Device Identification Register (RO)
1585 * Reset value: 0x00000380U
1587 typedef union _hw_sim_sdid
1590 struct _hw_sim_sdid_bitfields
1592 uint32_t PINID : 4; /*!< [3:0] Pincount identification */
1593 uint32_t FAMID : 3; /*!< [6:4] Kinetis family identification */
1594 uint32_t DIEID : 5; /*!< [11:7] Device Die ID */
1595 uint32_t REVID : 4; /*!< [15:12] Device revision number */
1596 uint32_t RESERVED0 : 4; /*!< [19:16] */
1597 uint32_t SERIESID : 4; /*!< [23:20] Kinetis Series ID */
1598 uint32_t SUBFAMID : 4; /*!< [27:24] Kinetis Sub-Family ID */
1599 uint32_t FAMILYID : 4; /*!< [31:28] Kinetis Family ID */
1604 * @name Constants and macros for entire SIM_SDID register
1607 #define HW_SIM_SDID_ADDR(x) ((x) + 0x1024U)
1609 #define HW_SIM_SDID(x) (*(__I hw_sim_sdid_t *) HW_SIM_SDID_ADDR(x))
1610 #define HW_SIM_SDID_RD(x) (HW_SIM_SDID(x).U)
1614 * Constants & macros for individual SIM_SDID bitfields
1618 * @name Register SIM_SDID, field PINID[3:0] (RO)
1620 * Specifies the pincount of the device.
1630 * - 0111 - 81-pin or 121-pin
1634 * - 1011 - Custom pinout (WLCSP)
1641 #define BP_SIM_SDID_PINID (0U) /*!< Bit position for SIM_SDID_PINID. */
1642 #define BM_SIM_SDID_PINID (0x0000000FU) /*!< Bit mask for SIM_SDID_PINID. */
1643 #define BS_SIM_SDID_PINID (4U) /*!< Bit field size in bits for SIM_SDID_PINID. */
1645 /*! @brief Read current value of the SIM_SDID_PINID field. */
1646 #define BR_SIM_SDID_PINID(x) (HW_SIM_SDID(x).B.PINID)
1650 * @name Register SIM_SDID, field FAMID[6:4] (RO)
1652 * This field is maintained for compatibility only, but has been superceded by
1653 * the SERIESID, FAMILYID and SUBFAMID fields in this register.
1656 * - 000 - K1x Family (without tamper)
1657 * - 001 - K2x Family (without tamper)
1658 * - 010 - K3x Family or K1x/K6x Family (with tamper)
1659 * - 011 - K4x Family or K2x Family (with tamper)
1660 * - 100 - K6x Family (without tamper)
1661 * - 101 - K7x Family
1666 #define BP_SIM_SDID_FAMID (4U) /*!< Bit position for SIM_SDID_FAMID. */
1667 #define BM_SIM_SDID_FAMID (0x00000070U) /*!< Bit mask for SIM_SDID_FAMID. */
1668 #define BS_SIM_SDID_FAMID (3U) /*!< Bit field size in bits for SIM_SDID_FAMID. */
1670 /*! @brief Read current value of the SIM_SDID_FAMID field. */
1671 #define BR_SIM_SDID_FAMID(x) (HW_SIM_SDID(x).B.FAMID)
1675 * @name Register SIM_SDID, field DIEID[11:7] (RO)
1677 * Specifies the silicon feature set identication number for the device.
1680 #define BP_SIM_SDID_DIEID (7U) /*!< Bit position for SIM_SDID_DIEID. */
1681 #define BM_SIM_SDID_DIEID (0x00000F80U) /*!< Bit mask for SIM_SDID_DIEID. */
1682 #define BS_SIM_SDID_DIEID (5U) /*!< Bit field size in bits for SIM_SDID_DIEID. */
1684 /*! @brief Read current value of the SIM_SDID_DIEID field. */
1685 #define BR_SIM_SDID_DIEID(x) (HW_SIM_SDID(x).B.DIEID)
1689 * @name Register SIM_SDID, field REVID[15:12] (RO)
1691 * Specifies the silicon implementation number for the device.
1694 #define BP_SIM_SDID_REVID (12U) /*!< Bit position for SIM_SDID_REVID. */
1695 #define BM_SIM_SDID_REVID (0x0000F000U) /*!< Bit mask for SIM_SDID_REVID. */
1696 #define BS_SIM_SDID_REVID (4U) /*!< Bit field size in bits for SIM_SDID_REVID. */
1698 /*! @brief Read current value of the SIM_SDID_REVID field. */
1699 #define BR_SIM_SDID_REVID(x) (HW_SIM_SDID(x).B.REVID)
1703 * @name Register SIM_SDID, field SERIESID[23:20] (RO)
1705 * Specifies the Kinetis series of the device.
1708 * - 0000 - Kinetis K series
1709 * - 0001 - Kinetis L series
1710 * - 0101 - Kinetis W series
1711 * - 0110 - Kinetis V series
1714 #define BP_SIM_SDID_SERIESID (20U) /*!< Bit position for SIM_SDID_SERIESID. */
1715 #define BM_SIM_SDID_SERIESID (0x00F00000U) /*!< Bit mask for SIM_SDID_SERIESID. */
1716 #define BS_SIM_SDID_SERIESID (4U) /*!< Bit field size in bits for SIM_SDID_SERIESID. */
1718 /*! @brief Read current value of the SIM_SDID_SERIESID field. */
1719 #define BR_SIM_SDID_SERIESID(x) (HW_SIM_SDID(x).B.SERIESID)
1723 * @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
1725 * Specifies the Kinetis sub-family of the device.
1728 * - 0000 - Kx0 Subfamily
1729 * - 0001 - Kx1 Subfamily (tamper detect)
1730 * - 0010 - Kx2 Subfamily
1731 * - 0011 - Kx3 Subfamily (tamper detect)
1732 * - 0100 - Kx4 Subfamily
1733 * - 0101 - Kx5 Subfamily (tamper detect)
1734 * - 0110 - Kx6 Subfamily
1737 #define BP_SIM_SDID_SUBFAMID (24U) /*!< Bit position for SIM_SDID_SUBFAMID. */
1738 #define BM_SIM_SDID_SUBFAMID (0x0F000000U) /*!< Bit mask for SIM_SDID_SUBFAMID. */
1739 #define BS_SIM_SDID_SUBFAMID (4U) /*!< Bit field size in bits for SIM_SDID_SUBFAMID. */
1741 /*! @brief Read current value of the SIM_SDID_SUBFAMID field. */
1742 #define BR_SIM_SDID_SUBFAMID(x) (HW_SIM_SDID(x).B.SUBFAMID)
1746 * @name Register SIM_SDID, field FAMILYID[31:28] (RO)
1748 * Specifies the Kinetis family of the device.
1751 * - 0001 - K1x Family
1752 * - 0010 - K2x Family
1753 * - 0011 - K3x Family
1754 * - 0100 - K4x Family
1755 * - 0110 - K6x Family
1756 * - 0111 - K7x Family
1759 #define BP_SIM_SDID_FAMILYID (28U) /*!< Bit position for SIM_SDID_FAMILYID. */
1760 #define BM_SIM_SDID_FAMILYID (0xF0000000U) /*!< Bit mask for SIM_SDID_FAMILYID. */
1761 #define BS_SIM_SDID_FAMILYID (4U) /*!< Bit field size in bits for SIM_SDID_FAMILYID. */
1763 /*! @brief Read current value of the SIM_SDID_FAMILYID field. */
1764 #define BR_SIM_SDID_FAMILYID(x) (HW_SIM_SDID(x).B.FAMILYID)
1767 /*******************************************************************************
1768 * HW_SIM_SCGC1 - System Clock Gating Control Register 1
1769 ******************************************************************************/
1772 * @brief HW_SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
1774 * Reset value: 0x00000000U
1776 typedef union _hw_sim_scgc1
1779 struct _hw_sim_scgc1_bitfields
1781 uint32_t RESERVED0 : 6; /*!< [5:0] */
1782 uint32_t I2C2b : 1; /*!< [6] I2C2 Clock Gate Control */
1783 uint32_t RESERVED1 : 3; /*!< [9:7] */
1784 uint32_t UART4b : 1; /*!< [10] UART4 Clock Gate Control */
1785 uint32_t UART5b : 1; /*!< [11] UART5 Clock Gate Control */
1786 uint32_t RESERVED2 : 20; /*!< [31:12] */
1791 * @name Constants and macros for entire SIM_SCGC1 register
1794 #define HW_SIM_SCGC1_ADDR(x) ((x) + 0x1028U)
1796 #define HW_SIM_SCGC1(x) (*(__IO hw_sim_scgc1_t *) HW_SIM_SCGC1_ADDR(x))
1797 #define HW_SIM_SCGC1_RD(x) (HW_SIM_SCGC1(x).U)
1798 #define HW_SIM_SCGC1_WR(x, v) (HW_SIM_SCGC1(x).U = (v))
1799 #define HW_SIM_SCGC1_SET(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) | (v)))
1800 #define HW_SIM_SCGC1_CLR(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) & ~(v)))
1801 #define HW_SIM_SCGC1_TOG(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) ^ (v)))
1805 * Constants & macros for individual SIM_SCGC1 bitfields
1809 * @name Register SIM_SCGC1, field I2C2[6] (RW)
1811 * This bit controls the clock gate to the I2C2 module.
1814 * - 0 - Clock disabled
1815 * - 1 - Clock enabled
1818 #define BP_SIM_SCGC1_I2C2 (6U) /*!< Bit position for SIM_SCGC1_I2C2. */
1819 #define BM_SIM_SCGC1_I2C2 (0x00000040U) /*!< Bit mask for SIM_SCGC1_I2C2. */
1820 #define BS_SIM_SCGC1_I2C2 (1U) /*!< Bit field size in bits for SIM_SCGC1_I2C2. */
1822 /*! @brief Read current value of the SIM_SCGC1_I2C2 field. */
1823 #define BR_SIM_SCGC1_I2C2(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_I2C2))
1825 /*! @brief Format value for bitfield SIM_SCGC1_I2C2. */
1826 #define BF_SIM_SCGC1_I2C2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_I2C2) & BM_SIM_SCGC1_I2C2)
1828 /*! @brief Set the I2C2 field to a new value. */
1829 #define BW_SIM_SCGC1_I2C2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_I2C2) = (v))
1833 * @name Register SIM_SCGC1, field UART4[10] (RW)
1835 * This bit controls the clock gate to the UART4 module.
1838 * - 0 - Clock disabled
1839 * - 1 - Clock enabled
1842 #define BP_SIM_SCGC1_UART4 (10U) /*!< Bit position for SIM_SCGC1_UART4. */
1843 #define BM_SIM_SCGC1_UART4 (0x00000400U) /*!< Bit mask for SIM_SCGC1_UART4. */
1844 #define BS_SIM_SCGC1_UART4 (1U) /*!< Bit field size in bits for SIM_SCGC1_UART4. */
1846 /*! @brief Read current value of the SIM_SCGC1_UART4 field. */
1847 #define BR_SIM_SCGC1_UART4(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART4))
1849 /*! @brief Format value for bitfield SIM_SCGC1_UART4. */
1850 #define BF_SIM_SCGC1_UART4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_UART4) & BM_SIM_SCGC1_UART4)
1852 /*! @brief Set the UART4 field to a new value. */
1853 #define BW_SIM_SCGC1_UART4(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART4) = (v))
1857 * @name Register SIM_SCGC1, field UART5[11] (RW)
1859 * This bit controls the clock gate to the UART5 module.
1862 * - 0 - Clock disabled
1863 * - 1 - Clock enabled
1866 #define BP_SIM_SCGC1_UART5 (11U) /*!< Bit position for SIM_SCGC1_UART5. */
1867 #define BM_SIM_SCGC1_UART5 (0x00000800U) /*!< Bit mask for SIM_SCGC1_UART5. */
1868 #define BS_SIM_SCGC1_UART5 (1U) /*!< Bit field size in bits for SIM_SCGC1_UART5. */
1870 /*! @brief Read current value of the SIM_SCGC1_UART5 field. */
1871 #define BR_SIM_SCGC1_UART5(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART5))
1873 /*! @brief Format value for bitfield SIM_SCGC1_UART5. */
1874 #define BF_SIM_SCGC1_UART5(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_UART5) & BM_SIM_SCGC1_UART5)
1876 /*! @brief Set the UART5 field to a new value. */
1877 #define BW_SIM_SCGC1_UART5(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART5) = (v))
1880 /*******************************************************************************
1881 * HW_SIM_SCGC2 - System Clock Gating Control Register 2
1882 ******************************************************************************/
1885 * @brief HW_SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
1887 * Reset value: 0x00000000U
1889 * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through
1890 * AIPS1, define the clock gate control bits in the SCGC2. When accessing through
1891 * AIPS0, define the clock gate control bits in SCGC6.
1893 typedef union _hw_sim_scgc2
1896 struct _hw_sim_scgc2_bitfields
1898 uint32_t ENETb : 1; /*!< [0] ENET Clock Gate Control */
1899 uint32_t RESERVED0 : 11; /*!< [11:1] */
1900 uint32_t DAC0b : 1; /*!< [12] DAC0 Clock Gate Control */
1901 uint32_t DAC1b : 1; /*!< [13] DAC1 Clock Gate Control */
1902 uint32_t RESERVED1 : 18; /*!< [31:14] */
1907 * @name Constants and macros for entire SIM_SCGC2 register
1910 #define HW_SIM_SCGC2_ADDR(x) ((x) + 0x102CU)
1912 #define HW_SIM_SCGC2(x) (*(__IO hw_sim_scgc2_t *) HW_SIM_SCGC2_ADDR(x))
1913 #define HW_SIM_SCGC2_RD(x) (HW_SIM_SCGC2(x).U)
1914 #define HW_SIM_SCGC2_WR(x, v) (HW_SIM_SCGC2(x).U = (v))
1915 #define HW_SIM_SCGC2_SET(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) | (v)))
1916 #define HW_SIM_SCGC2_CLR(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) & ~(v)))
1917 #define HW_SIM_SCGC2_TOG(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) ^ (v)))
1921 * Constants & macros for individual SIM_SCGC2 bitfields
1925 * @name Register SIM_SCGC2, field ENET[0] (RW)
1927 * This bit controls the clock gate to the ENET module.
1930 * - 0 - Clock disabled
1931 * - 1 - Clock enabled
1934 #define BP_SIM_SCGC2_ENET (0U) /*!< Bit position for SIM_SCGC2_ENET. */
1935 #define BM_SIM_SCGC2_ENET (0x00000001U) /*!< Bit mask for SIM_SCGC2_ENET. */
1936 #define BS_SIM_SCGC2_ENET (1U) /*!< Bit field size in bits for SIM_SCGC2_ENET. */
1938 /*! @brief Read current value of the SIM_SCGC2_ENET field. */
1939 #define BR_SIM_SCGC2_ENET(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_ENET))
1941 /*! @brief Format value for bitfield SIM_SCGC2_ENET. */
1942 #define BF_SIM_SCGC2_ENET(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_ENET) & BM_SIM_SCGC2_ENET)
1944 /*! @brief Set the ENET field to a new value. */
1945 #define BW_SIM_SCGC2_ENET(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_ENET) = (v))
1949 * @name Register SIM_SCGC2, field DAC0[12] (RW)
1951 * This bit controls the clock gate to the DAC0 module.
1954 * - 0 - Clock disabled
1955 * - 1 - Clock enabled
1958 #define BP_SIM_SCGC2_DAC0 (12U) /*!< Bit position for SIM_SCGC2_DAC0. */
1959 #define BM_SIM_SCGC2_DAC0 (0x00001000U) /*!< Bit mask for SIM_SCGC2_DAC0. */
1960 #define BS_SIM_SCGC2_DAC0 (1U) /*!< Bit field size in bits for SIM_SCGC2_DAC0. */
1962 /*! @brief Read current value of the SIM_SCGC2_DAC0 field. */
1963 #define BR_SIM_SCGC2_DAC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC0))
1965 /*! @brief Format value for bitfield SIM_SCGC2_DAC0. */
1966 #define BF_SIM_SCGC2_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_DAC0) & BM_SIM_SCGC2_DAC0)
1968 /*! @brief Set the DAC0 field to a new value. */
1969 #define BW_SIM_SCGC2_DAC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC0) = (v))
1973 * @name Register SIM_SCGC2, field DAC1[13] (RW)
1975 * This bit controls the clock gate to the DAC1 module.
1978 * - 0 - Clock disabled
1979 * - 1 - Clock enabled
1982 #define BP_SIM_SCGC2_DAC1 (13U) /*!< Bit position for SIM_SCGC2_DAC1. */
1983 #define BM_SIM_SCGC2_DAC1 (0x00002000U) /*!< Bit mask for SIM_SCGC2_DAC1. */
1984 #define BS_SIM_SCGC2_DAC1 (1U) /*!< Bit field size in bits for SIM_SCGC2_DAC1. */
1986 /*! @brief Read current value of the SIM_SCGC2_DAC1 field. */
1987 #define BR_SIM_SCGC2_DAC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC1))
1989 /*! @brief Format value for bitfield SIM_SCGC2_DAC1. */
1990 #define BF_SIM_SCGC2_DAC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_DAC1) & BM_SIM_SCGC2_DAC1)
1992 /*! @brief Set the DAC1 field to a new value. */
1993 #define BW_SIM_SCGC2_DAC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC1) = (v))
1996 /*******************************************************************************
1997 * HW_SIM_SCGC3 - System Clock Gating Control Register 3
1998 ******************************************************************************/
2001 * @brief HW_SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
2003 * Reset value: 0x00000000U
2005 * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing
2006 * through AIPS1, define the clock gate control bits in the SCGC3. When accessing
2007 * through AIPS0, define the clock gate control bits in SCGC6.
2009 typedef union _hw_sim_scgc3
2012 struct _hw_sim_scgc3_bitfields
2014 uint32_t RNGA : 1; /*!< [0] RNGA Clock Gate Control */
2015 uint32_t RESERVED0 : 11; /*!< [11:1] */
2016 uint32_t SPI2b : 1; /*!< [12] SPI2 Clock Gate Control */
2017 uint32_t RESERVED1 : 4; /*!< [16:13] */
2018 uint32_t SDHCb : 1; /*!< [17] SDHC Clock Gate Control */
2019 uint32_t RESERVED2 : 6; /*!< [23:18] */
2020 uint32_t FTM2b : 1; /*!< [24] FTM2 Clock Gate Control */
2021 uint32_t FTM3b : 1; /*!< [25] FTM3 Clock Gate Control */
2022 uint32_t RESERVED3 : 1; /*!< [26] */
2023 uint32_t ADC1b : 1; /*!< [27] ADC1 Clock Gate Control */
2024 uint32_t RESERVED4 : 4; /*!< [31:28] */
2029 * @name Constants and macros for entire SIM_SCGC3 register
2032 #define HW_SIM_SCGC3_ADDR(x) ((x) + 0x1030U)
2034 #define HW_SIM_SCGC3(x) (*(__IO hw_sim_scgc3_t *) HW_SIM_SCGC3_ADDR(x))
2035 #define HW_SIM_SCGC3_RD(x) (HW_SIM_SCGC3(x).U)
2036 #define HW_SIM_SCGC3_WR(x, v) (HW_SIM_SCGC3(x).U = (v))
2037 #define HW_SIM_SCGC3_SET(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) | (v)))
2038 #define HW_SIM_SCGC3_CLR(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) & ~(v)))
2039 #define HW_SIM_SCGC3_TOG(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) ^ (v)))
2043 * Constants & macros for individual SIM_SCGC3 bitfields
2047 * @name Register SIM_SCGC3, field RNGA[0] (RW)
2049 * This bit controls the clock gate to the RNGA module.
2052 * - 0 - Clock disabled
2053 * - 1 - Clock enabled
2056 #define BP_SIM_SCGC3_RNGA (0U) /*!< Bit position for SIM_SCGC3_RNGA. */
2057 #define BM_SIM_SCGC3_RNGA (0x00000001U) /*!< Bit mask for SIM_SCGC3_RNGA. */
2058 #define BS_SIM_SCGC3_RNGA (1U) /*!< Bit field size in bits for SIM_SCGC3_RNGA. */
2060 /*! @brief Read current value of the SIM_SCGC3_RNGA field. */
2061 #define BR_SIM_SCGC3_RNGA(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_RNGA))
2063 /*! @brief Format value for bitfield SIM_SCGC3_RNGA. */
2064 #define BF_SIM_SCGC3_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_RNGA) & BM_SIM_SCGC3_RNGA)
2066 /*! @brief Set the RNGA field to a new value. */
2067 #define BW_SIM_SCGC3_RNGA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_RNGA) = (v))
2071 * @name Register SIM_SCGC3, field SPI2[12] (RW)
2073 * This bit controls the clock gate to the SPI2 module.
2076 * - 0 - Clock disabled
2077 * - 1 - Clock enabled
2080 #define BP_SIM_SCGC3_SPI2 (12U) /*!< Bit position for SIM_SCGC3_SPI2. */
2081 #define BM_SIM_SCGC3_SPI2 (0x00001000U) /*!< Bit mask for SIM_SCGC3_SPI2. */
2082 #define BS_SIM_SCGC3_SPI2 (1U) /*!< Bit field size in bits for SIM_SCGC3_SPI2. */
2084 /*! @brief Read current value of the SIM_SCGC3_SPI2 field. */
2085 #define BR_SIM_SCGC3_SPI2(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SPI2))
2087 /*! @brief Format value for bitfield SIM_SCGC3_SPI2. */
2088 #define BF_SIM_SCGC3_SPI2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_SPI2) & BM_SIM_SCGC3_SPI2)
2090 /*! @brief Set the SPI2 field to a new value. */
2091 #define BW_SIM_SCGC3_SPI2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SPI2) = (v))
2095 * @name Register SIM_SCGC3, field SDHC[17] (RW)
2097 * This bit controls the clock gate to the SDHC module.
2100 * - 0 - Clock disabled
2101 * - 1 - Clock enabled
2104 #define BP_SIM_SCGC3_SDHC (17U) /*!< Bit position for SIM_SCGC3_SDHC. */
2105 #define BM_SIM_SCGC3_SDHC (0x00020000U) /*!< Bit mask for SIM_SCGC3_SDHC. */
2106 #define BS_SIM_SCGC3_SDHC (1U) /*!< Bit field size in bits for SIM_SCGC3_SDHC. */
2108 /*! @brief Read current value of the SIM_SCGC3_SDHC field. */
2109 #define BR_SIM_SCGC3_SDHC(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SDHC))
2111 /*! @brief Format value for bitfield SIM_SCGC3_SDHC. */
2112 #define BF_SIM_SCGC3_SDHC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_SDHC) & BM_SIM_SCGC3_SDHC)
2114 /*! @brief Set the SDHC field to a new value. */
2115 #define BW_SIM_SCGC3_SDHC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SDHC) = (v))
2119 * @name Register SIM_SCGC3, field FTM2[24] (RW)
2121 * This bit controls the clock gate to the FTM2 module.
2124 * - 0 - Clock disabled
2125 * - 1 - Clock enabled
2128 #define BP_SIM_SCGC3_FTM2 (24U) /*!< Bit position for SIM_SCGC3_FTM2. */
2129 #define BM_SIM_SCGC3_FTM2 (0x01000000U) /*!< Bit mask for SIM_SCGC3_FTM2. */
2130 #define BS_SIM_SCGC3_FTM2 (1U) /*!< Bit field size in bits for SIM_SCGC3_FTM2. */
2132 /*! @brief Read current value of the SIM_SCGC3_FTM2 field. */
2133 #define BR_SIM_SCGC3_FTM2(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM2))
2135 /*! @brief Format value for bitfield SIM_SCGC3_FTM2. */
2136 #define BF_SIM_SCGC3_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FTM2) & BM_SIM_SCGC3_FTM2)
2138 /*! @brief Set the FTM2 field to a new value. */
2139 #define BW_SIM_SCGC3_FTM2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM2) = (v))
2143 * @name Register SIM_SCGC3, field FTM3[25] (RW)
2145 * This bit controls the clock gate to the FTM3 module.
2148 * - 0 - Clock disabled
2149 * - 1 - Clock enabled
2152 #define BP_SIM_SCGC3_FTM3 (25U) /*!< Bit position for SIM_SCGC3_FTM3. */
2153 #define BM_SIM_SCGC3_FTM3 (0x02000000U) /*!< Bit mask for SIM_SCGC3_FTM3. */
2154 #define BS_SIM_SCGC3_FTM3 (1U) /*!< Bit field size in bits for SIM_SCGC3_FTM3. */
2156 /*! @brief Read current value of the SIM_SCGC3_FTM3 field. */
2157 #define BR_SIM_SCGC3_FTM3(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM3))
2159 /*! @brief Format value for bitfield SIM_SCGC3_FTM3. */
2160 #define BF_SIM_SCGC3_FTM3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FTM3) & BM_SIM_SCGC3_FTM3)
2162 /*! @brief Set the FTM3 field to a new value. */
2163 #define BW_SIM_SCGC3_FTM3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM3) = (v))
2167 * @name Register SIM_SCGC3, field ADC1[27] (RW)
2169 * This bit controls the clock gate to the ADC1 module.
2172 * - 0 - Clock disabled
2173 * - 1 - Clock enabled
2176 #define BP_SIM_SCGC3_ADC1 (27U) /*!< Bit position for SIM_SCGC3_ADC1. */
2177 #define BM_SIM_SCGC3_ADC1 (0x08000000U) /*!< Bit mask for SIM_SCGC3_ADC1. */
2178 #define BS_SIM_SCGC3_ADC1 (1U) /*!< Bit field size in bits for SIM_SCGC3_ADC1. */
2180 /*! @brief Read current value of the SIM_SCGC3_ADC1 field. */
2181 #define BR_SIM_SCGC3_ADC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC1))
2183 /*! @brief Format value for bitfield SIM_SCGC3_ADC1. */
2184 #define BF_SIM_SCGC3_ADC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_ADC1) & BM_SIM_SCGC3_ADC1)
2186 /*! @brief Set the ADC1 field to a new value. */
2187 #define BW_SIM_SCGC3_ADC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC1) = (v))
2190 /*******************************************************************************
2191 * HW_SIM_SCGC4 - System Clock Gating Control Register 4
2192 ******************************************************************************/
2195 * @brief HW_SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
2197 * Reset value: 0xF0100030U
2199 typedef union _hw_sim_scgc4
2202 struct _hw_sim_scgc4_bitfields
2204 uint32_t RESERVED0 : 1; /*!< [0] */
2205 uint32_t EWMb : 1; /*!< [1] EWM Clock Gate Control */
2206 uint32_t CMTb : 1; /*!< [2] CMT Clock Gate Control */
2207 uint32_t RESERVED1 : 3; /*!< [5:3] */
2208 uint32_t I2C0b : 1; /*!< [6] I2C0 Clock Gate Control */
2209 uint32_t I2C1b : 1; /*!< [7] I2C1 Clock Gate Control */
2210 uint32_t RESERVED2 : 2; /*!< [9:8] */
2211 uint32_t UART0b : 1; /*!< [10] UART0 Clock Gate Control */
2212 uint32_t UART1b : 1; /*!< [11] UART1 Clock Gate Control */
2213 uint32_t UART2b : 1; /*!< [12] UART2 Clock Gate Control */
2214 uint32_t UART3b : 1; /*!< [13] UART3 Clock Gate Control */
2215 uint32_t RESERVED3 : 4; /*!< [17:14] */
2216 uint32_t USBOTG : 1; /*!< [18] USB Clock Gate Control */
2217 uint32_t CMP : 1; /*!< [19] Comparator Clock Gate Control */
2218 uint32_t VREFb : 1; /*!< [20] VREF Clock Gate Control */
2219 uint32_t RESERVED4 : 11; /*!< [31:21] */
2224 * @name Constants and macros for entire SIM_SCGC4 register
2227 #define HW_SIM_SCGC4_ADDR(x) ((x) + 0x1034U)
2229 #define HW_SIM_SCGC4(x) (*(__IO hw_sim_scgc4_t *) HW_SIM_SCGC4_ADDR(x))
2230 #define HW_SIM_SCGC4_RD(x) (HW_SIM_SCGC4(x).U)
2231 #define HW_SIM_SCGC4_WR(x, v) (HW_SIM_SCGC4(x).U = (v))
2232 #define HW_SIM_SCGC4_SET(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) | (v)))
2233 #define HW_SIM_SCGC4_CLR(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) & ~(v)))
2234 #define HW_SIM_SCGC4_TOG(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) ^ (v)))
2238 * Constants & macros for individual SIM_SCGC4 bitfields
2242 * @name Register SIM_SCGC4, field EWM[1] (RW)
2244 * This bit controls the clock gate to the EWM module.
2247 * - 0 - Clock disabled
2248 * - 1 - Clock enabled
2251 #define BP_SIM_SCGC4_EWM (1U) /*!< Bit position for SIM_SCGC4_EWM. */
2252 #define BM_SIM_SCGC4_EWM (0x00000002U) /*!< Bit mask for SIM_SCGC4_EWM. */
2253 #define BS_SIM_SCGC4_EWM (1U) /*!< Bit field size in bits for SIM_SCGC4_EWM. */
2255 /*! @brief Read current value of the SIM_SCGC4_EWM field. */
2256 #define BR_SIM_SCGC4_EWM(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM))
2258 /*! @brief Format value for bitfield SIM_SCGC4_EWM. */
2259 #define BF_SIM_SCGC4_EWM(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_EWM) & BM_SIM_SCGC4_EWM)
2261 /*! @brief Set the EWM field to a new value. */
2262 #define BW_SIM_SCGC4_EWM(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM) = (v))
2266 * @name Register SIM_SCGC4, field CMT[2] (RW)
2268 * This bit controls the clock gate to the CMT module.
2271 * - 0 - Clock disabled
2272 * - 1 - Clock enabled
2275 #define BP_SIM_SCGC4_CMT (2U) /*!< Bit position for SIM_SCGC4_CMT. */
2276 #define BM_SIM_SCGC4_CMT (0x00000004U) /*!< Bit mask for SIM_SCGC4_CMT. */
2277 #define BS_SIM_SCGC4_CMT (1U) /*!< Bit field size in bits for SIM_SCGC4_CMT. */
2279 /*! @brief Read current value of the SIM_SCGC4_CMT field. */
2280 #define BR_SIM_SCGC4_CMT(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMT))
2282 /*! @brief Format value for bitfield SIM_SCGC4_CMT. */
2283 #define BF_SIM_SCGC4_CMT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMT) & BM_SIM_SCGC4_CMT)
2285 /*! @brief Set the CMT field to a new value. */
2286 #define BW_SIM_SCGC4_CMT(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMT) = (v))
2290 * @name Register SIM_SCGC4, field I2C0[6] (RW)
2292 * This bit controls the clock gate to the I 2 C0 module.
2295 * - 0 - Clock disabled
2296 * - 1 - Clock enabled
2299 #define BP_SIM_SCGC4_I2C0 (6U) /*!< Bit position for SIM_SCGC4_I2C0. */
2300 #define BM_SIM_SCGC4_I2C0 (0x00000040U) /*!< Bit mask for SIM_SCGC4_I2C0. */
2301 #define BS_SIM_SCGC4_I2C0 (1U) /*!< Bit field size in bits for SIM_SCGC4_I2C0. */
2303 /*! @brief Read current value of the SIM_SCGC4_I2C0 field. */
2304 #define BR_SIM_SCGC4_I2C0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0))
2306 /*! @brief Format value for bitfield SIM_SCGC4_I2C0. */
2307 #define BF_SIM_SCGC4_I2C0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C0) & BM_SIM_SCGC4_I2C0)
2309 /*! @brief Set the I2C0 field to a new value. */
2310 #define BW_SIM_SCGC4_I2C0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0) = (v))
2314 * @name Register SIM_SCGC4, field I2C1[7] (RW)
2316 * This bit controls the clock gate to the I 2 C1 module.
2319 * - 0 - Clock disabled
2320 * - 1 - Clock enabled
2323 #define BP_SIM_SCGC4_I2C1 (7U) /*!< Bit position for SIM_SCGC4_I2C1. */
2324 #define BM_SIM_SCGC4_I2C1 (0x00000080U) /*!< Bit mask for SIM_SCGC4_I2C1. */
2325 #define BS_SIM_SCGC4_I2C1 (1U) /*!< Bit field size in bits for SIM_SCGC4_I2C1. */
2327 /*! @brief Read current value of the SIM_SCGC4_I2C1 field. */
2328 #define BR_SIM_SCGC4_I2C1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1))
2330 /*! @brief Format value for bitfield SIM_SCGC4_I2C1. */
2331 #define BF_SIM_SCGC4_I2C1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C1) & BM_SIM_SCGC4_I2C1)
2333 /*! @brief Set the I2C1 field to a new value. */
2334 #define BW_SIM_SCGC4_I2C1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1) = (v))
2338 * @name Register SIM_SCGC4, field UART0[10] (RW)
2340 * This bit controls the clock gate to the UART0 module.
2343 * - 0 - Clock disabled
2344 * - 1 - Clock enabled
2347 #define BP_SIM_SCGC4_UART0 (10U) /*!< Bit position for SIM_SCGC4_UART0. */
2348 #define BM_SIM_SCGC4_UART0 (0x00000400U) /*!< Bit mask for SIM_SCGC4_UART0. */
2349 #define BS_SIM_SCGC4_UART0 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART0. */
2351 /*! @brief Read current value of the SIM_SCGC4_UART0 field. */
2352 #define BR_SIM_SCGC4_UART0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0))
2354 /*! @brief Format value for bitfield SIM_SCGC4_UART0. */
2355 #define BF_SIM_SCGC4_UART0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART0) & BM_SIM_SCGC4_UART0)
2357 /*! @brief Set the UART0 field to a new value. */
2358 #define BW_SIM_SCGC4_UART0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0) = (v))
2362 * @name Register SIM_SCGC4, field UART1[11] (RW)
2364 * This bit controls the clock gate to the UART1 module.
2367 * - 0 - Clock disabled
2368 * - 1 - Clock enabled
2371 #define BP_SIM_SCGC4_UART1 (11U) /*!< Bit position for SIM_SCGC4_UART1. */
2372 #define BM_SIM_SCGC4_UART1 (0x00000800U) /*!< Bit mask for SIM_SCGC4_UART1. */
2373 #define BS_SIM_SCGC4_UART1 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART1. */
2375 /*! @brief Read current value of the SIM_SCGC4_UART1 field. */
2376 #define BR_SIM_SCGC4_UART1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1))
2378 /*! @brief Format value for bitfield SIM_SCGC4_UART1. */
2379 #define BF_SIM_SCGC4_UART1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART1) & BM_SIM_SCGC4_UART1)
2381 /*! @brief Set the UART1 field to a new value. */
2382 #define BW_SIM_SCGC4_UART1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1) = (v))
2386 * @name Register SIM_SCGC4, field UART2[12] (RW)
2388 * This bit controls the clock gate to the UART2 module.
2391 * - 0 - Clock disabled
2392 * - 1 - Clock enabled
2395 #define BP_SIM_SCGC4_UART2 (12U) /*!< Bit position for SIM_SCGC4_UART2. */
2396 #define BM_SIM_SCGC4_UART2 (0x00001000U) /*!< Bit mask for SIM_SCGC4_UART2. */
2397 #define BS_SIM_SCGC4_UART2 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART2. */
2399 /*! @brief Read current value of the SIM_SCGC4_UART2 field. */
2400 #define BR_SIM_SCGC4_UART2(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2))
2402 /*! @brief Format value for bitfield SIM_SCGC4_UART2. */
2403 #define BF_SIM_SCGC4_UART2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART2) & BM_SIM_SCGC4_UART2)
2405 /*! @brief Set the UART2 field to a new value. */
2406 #define BW_SIM_SCGC4_UART2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2) = (v))
2410 * @name Register SIM_SCGC4, field UART3[13] (RW)
2412 * This bit controls the clock gate to the UART3 module.
2415 * - 0 - Clock disabled
2416 * - 1 - Clock enabled
2419 #define BP_SIM_SCGC4_UART3 (13U) /*!< Bit position for SIM_SCGC4_UART3. */
2420 #define BM_SIM_SCGC4_UART3 (0x00002000U) /*!< Bit mask for SIM_SCGC4_UART3. */
2421 #define BS_SIM_SCGC4_UART3 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART3. */
2423 /*! @brief Read current value of the SIM_SCGC4_UART3 field. */
2424 #define BR_SIM_SCGC4_UART3(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART3))
2426 /*! @brief Format value for bitfield SIM_SCGC4_UART3. */
2427 #define BF_SIM_SCGC4_UART3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART3) & BM_SIM_SCGC4_UART3)
2429 /*! @brief Set the UART3 field to a new value. */
2430 #define BW_SIM_SCGC4_UART3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART3) = (v))
2434 * @name Register SIM_SCGC4, field USBOTG[18] (RW)
2436 * This bit controls the clock gate to the USB module.
2439 * - 0 - Clock disabled
2440 * - 1 - Clock enabled
2443 #define BP_SIM_SCGC4_USBOTG (18U) /*!< Bit position for SIM_SCGC4_USBOTG. */
2444 #define BM_SIM_SCGC4_USBOTG (0x00040000U) /*!< Bit mask for SIM_SCGC4_USBOTG. */
2445 #define BS_SIM_SCGC4_USBOTG (1U) /*!< Bit field size in bits for SIM_SCGC4_USBOTG. */
2447 /*! @brief Read current value of the SIM_SCGC4_USBOTG field. */
2448 #define BR_SIM_SCGC4_USBOTG(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG))
2450 /*! @brief Format value for bitfield SIM_SCGC4_USBOTG. */
2451 #define BF_SIM_SCGC4_USBOTG(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_USBOTG) & BM_SIM_SCGC4_USBOTG)
2453 /*! @brief Set the USBOTG field to a new value. */
2454 #define BW_SIM_SCGC4_USBOTG(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG) = (v))
2458 * @name Register SIM_SCGC4, field CMP[19] (RW)
2460 * This bit controls the clock gate to the comparator module.
2463 * - 0 - Clock disabled
2464 * - 1 - Clock enabled
2467 #define BP_SIM_SCGC4_CMP (19U) /*!< Bit position for SIM_SCGC4_CMP. */
2468 #define BM_SIM_SCGC4_CMP (0x00080000U) /*!< Bit mask for SIM_SCGC4_CMP. */
2469 #define BS_SIM_SCGC4_CMP (1U) /*!< Bit field size in bits for SIM_SCGC4_CMP. */
2471 /*! @brief Read current value of the SIM_SCGC4_CMP field. */
2472 #define BR_SIM_SCGC4_CMP(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP))
2474 /*! @brief Format value for bitfield SIM_SCGC4_CMP. */
2475 #define BF_SIM_SCGC4_CMP(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMP) & BM_SIM_SCGC4_CMP)
2477 /*! @brief Set the CMP field to a new value. */
2478 #define BW_SIM_SCGC4_CMP(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP) = (v))
2482 * @name Register SIM_SCGC4, field VREF[20] (RW)
2484 * This bit controls the clock gate to the VREF module.
2487 * - 0 - Clock disabled
2488 * - 1 - Clock enabled
2491 #define BP_SIM_SCGC4_VREF (20U) /*!< Bit position for SIM_SCGC4_VREF. */
2492 #define BM_SIM_SCGC4_VREF (0x00100000U) /*!< Bit mask for SIM_SCGC4_VREF. */
2493 #define BS_SIM_SCGC4_VREF (1U) /*!< Bit field size in bits for SIM_SCGC4_VREF. */
2495 /*! @brief Read current value of the SIM_SCGC4_VREF field. */
2496 #define BR_SIM_SCGC4_VREF(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF))
2498 /*! @brief Format value for bitfield SIM_SCGC4_VREF. */
2499 #define BF_SIM_SCGC4_VREF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_VREF) & BM_SIM_SCGC4_VREF)
2501 /*! @brief Set the VREF field to a new value. */
2502 #define BW_SIM_SCGC4_VREF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF) = (v))
2505 /*******************************************************************************
2506 * HW_SIM_SCGC5 - System Clock Gating Control Register 5
2507 ******************************************************************************/
2510 * @brief HW_SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
2512 * Reset value: 0x00040182U
2514 typedef union _hw_sim_scgc5
2517 struct _hw_sim_scgc5_bitfields
2519 uint32_t LPTMR : 1; /*!< [0] Low Power Timer Access Control */
2520 uint32_t RESERVED0 : 8; /*!< [8:1] */
2521 uint32_t PORTAb : 1; /*!< [9] Port A Clock Gate Control */
2522 uint32_t PORTBb : 1; /*!< [10] Port B Clock Gate Control */
2523 uint32_t PORTCb : 1; /*!< [11] Port C Clock Gate Control */
2524 uint32_t PORTDb : 1; /*!< [12] Port D Clock Gate Control */
2525 uint32_t PORTEb : 1; /*!< [13] Port E Clock Gate Control */
2526 uint32_t RESERVED1 : 18; /*!< [31:14] */
2531 * @name Constants and macros for entire SIM_SCGC5 register
2534 #define HW_SIM_SCGC5_ADDR(x) ((x) + 0x1038U)
2536 #define HW_SIM_SCGC5(x) (*(__IO hw_sim_scgc5_t *) HW_SIM_SCGC5_ADDR(x))
2537 #define HW_SIM_SCGC5_RD(x) (HW_SIM_SCGC5(x).U)
2538 #define HW_SIM_SCGC5_WR(x, v) (HW_SIM_SCGC5(x).U = (v))
2539 #define HW_SIM_SCGC5_SET(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) | (v)))
2540 #define HW_SIM_SCGC5_CLR(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) & ~(v)))
2541 #define HW_SIM_SCGC5_TOG(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) ^ (v)))
2545 * Constants & macros for individual SIM_SCGC5 bitfields
2549 * @name Register SIM_SCGC5, field LPTMR[0] (RW)
2551 * This bit controls software access to the Low Power Timer module.
2554 * - 0 - Access disabled
2555 * - 1 - Access enabled
2558 #define BP_SIM_SCGC5_LPTMR (0U) /*!< Bit position for SIM_SCGC5_LPTMR. */
2559 #define BM_SIM_SCGC5_LPTMR (0x00000001U) /*!< Bit mask for SIM_SCGC5_LPTMR. */
2560 #define BS_SIM_SCGC5_LPTMR (1U) /*!< Bit field size in bits for SIM_SCGC5_LPTMR. */
2562 /*! @brief Read current value of the SIM_SCGC5_LPTMR field. */
2563 #define BR_SIM_SCGC5_LPTMR(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR))
2565 /*! @brief Format value for bitfield SIM_SCGC5_LPTMR. */
2566 #define BF_SIM_SCGC5_LPTMR(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_LPTMR) & BM_SIM_SCGC5_LPTMR)
2568 /*! @brief Set the LPTMR field to a new value. */
2569 #define BW_SIM_SCGC5_LPTMR(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR) = (v))
2573 * @name Register SIM_SCGC5, field PORTA[9] (RW)
2575 * This bit controls the clock gate to the Port A module.
2578 * - 0 - Clock disabled
2579 * - 1 - Clock enabled
2582 #define BP_SIM_SCGC5_PORTA (9U) /*!< Bit position for SIM_SCGC5_PORTA. */
2583 #define BM_SIM_SCGC5_PORTA (0x00000200U) /*!< Bit mask for SIM_SCGC5_PORTA. */
2584 #define BS_SIM_SCGC5_PORTA (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTA. */
2586 /*! @brief Read current value of the SIM_SCGC5_PORTA field. */
2587 #define BR_SIM_SCGC5_PORTA(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA))
2589 /*! @brief Format value for bitfield SIM_SCGC5_PORTA. */
2590 #define BF_SIM_SCGC5_PORTA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTA) & BM_SIM_SCGC5_PORTA)
2592 /*! @brief Set the PORTA field to a new value. */
2593 #define BW_SIM_SCGC5_PORTA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA) = (v))
2597 * @name Register SIM_SCGC5, field PORTB[10] (RW)
2599 * This bit controls the clock gate to the Port B module.
2602 * - 0 - Clock disabled
2603 * - 1 - Clock enabled
2606 #define BP_SIM_SCGC5_PORTB (10U) /*!< Bit position for SIM_SCGC5_PORTB. */
2607 #define BM_SIM_SCGC5_PORTB (0x00000400U) /*!< Bit mask for SIM_SCGC5_PORTB. */
2608 #define BS_SIM_SCGC5_PORTB (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTB. */
2610 /*! @brief Read current value of the SIM_SCGC5_PORTB field. */
2611 #define BR_SIM_SCGC5_PORTB(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB))
2613 /*! @brief Format value for bitfield SIM_SCGC5_PORTB. */
2614 #define BF_SIM_SCGC5_PORTB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTB) & BM_SIM_SCGC5_PORTB)
2616 /*! @brief Set the PORTB field to a new value. */
2617 #define BW_SIM_SCGC5_PORTB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB) = (v))
2621 * @name Register SIM_SCGC5, field PORTC[11] (RW)
2623 * This bit controls the clock gate to the Port C module.
2626 * - 0 - Clock disabled
2627 * - 1 - Clock enabled
2630 #define BP_SIM_SCGC5_PORTC (11U) /*!< Bit position for SIM_SCGC5_PORTC. */
2631 #define BM_SIM_SCGC5_PORTC (0x00000800U) /*!< Bit mask for SIM_SCGC5_PORTC. */
2632 #define BS_SIM_SCGC5_PORTC (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTC. */
2634 /*! @brief Read current value of the SIM_SCGC5_PORTC field. */
2635 #define BR_SIM_SCGC5_PORTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC))
2637 /*! @brief Format value for bitfield SIM_SCGC5_PORTC. */
2638 #define BF_SIM_SCGC5_PORTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTC) & BM_SIM_SCGC5_PORTC)
2640 /*! @brief Set the PORTC field to a new value. */
2641 #define BW_SIM_SCGC5_PORTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC) = (v))
2645 * @name Register SIM_SCGC5, field PORTD[12] (RW)
2647 * This bit controls the clock gate to the Port D module.
2650 * - 0 - Clock disabled
2651 * - 1 - Clock enabled
2654 #define BP_SIM_SCGC5_PORTD (12U) /*!< Bit position for SIM_SCGC5_PORTD. */
2655 #define BM_SIM_SCGC5_PORTD (0x00001000U) /*!< Bit mask for SIM_SCGC5_PORTD. */
2656 #define BS_SIM_SCGC5_PORTD (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTD. */
2658 /*! @brief Read current value of the SIM_SCGC5_PORTD field. */
2659 #define BR_SIM_SCGC5_PORTD(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD))
2661 /*! @brief Format value for bitfield SIM_SCGC5_PORTD. */
2662 #define BF_SIM_SCGC5_PORTD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTD) & BM_SIM_SCGC5_PORTD)
2664 /*! @brief Set the PORTD field to a new value. */
2665 #define BW_SIM_SCGC5_PORTD(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD) = (v))
2669 * @name Register SIM_SCGC5, field PORTE[13] (RW)
2671 * This bit controls the clock gate to the Port E module.
2674 * - 0 - Clock disabled
2675 * - 1 - Clock enabled
2678 #define BP_SIM_SCGC5_PORTE (13U) /*!< Bit position for SIM_SCGC5_PORTE. */
2679 #define BM_SIM_SCGC5_PORTE (0x00002000U) /*!< Bit mask for SIM_SCGC5_PORTE. */
2680 #define BS_SIM_SCGC5_PORTE (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTE. */
2682 /*! @brief Read current value of the SIM_SCGC5_PORTE field. */
2683 #define BR_SIM_SCGC5_PORTE(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE))
2685 /*! @brief Format value for bitfield SIM_SCGC5_PORTE. */
2686 #define BF_SIM_SCGC5_PORTE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTE) & BM_SIM_SCGC5_PORTE)
2688 /*! @brief Set the PORTE field to a new value. */
2689 #define BW_SIM_SCGC5_PORTE(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE) = (v))
2692 /*******************************************************************************
2693 * HW_SIM_SCGC6 - System Clock Gating Control Register 6
2694 ******************************************************************************/
2697 * @brief HW_SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
2699 * Reset value: 0x40000001U
2701 * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
2702 * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
2703 * When accessing through AIPS0, define the clock gate control bits in SCGC6.
2705 typedef union _hw_sim_scgc6
2708 struct _hw_sim_scgc6_bitfields
2710 uint32_t FTF : 1; /*!< [0] Flash Memory Clock Gate Control */
2711 uint32_t DMAMUXb : 1; /*!< [1] DMA Mux Clock Gate Control */
2712 uint32_t RESERVED0 : 2; /*!< [3:2] */
2713 uint32_t FLEXCAN0 : 1; /*!< [4] FlexCAN0 Clock Gate Control */
2714 uint32_t RESERVED1 : 4; /*!< [8:5] */
2715 uint32_t RNGA : 1; /*!< [9] RNGA Clock Gate Control */
2716 uint32_t RESERVED2 : 2; /*!< [11:10] */
2717 uint32_t SPI0b : 1; /*!< [12] SPI0 Clock Gate Control */
2718 uint32_t SPI1b : 1; /*!< [13] SPI1 Clock Gate Control */
2719 uint32_t RESERVED3 : 1; /*!< [14] */
2720 uint32_t I2S : 1; /*!< [15] I2S Clock Gate Control */
2721 uint32_t RESERVED4 : 2; /*!< [17:16] */
2722 uint32_t CRC : 1; /*!< [18] CRC Clock Gate Control */
2723 uint32_t RESERVED5 : 2; /*!< [20:19] */
2724 uint32_t USBDCDb : 1; /*!< [21] USB DCD Clock Gate Control */
2725 uint32_t PDB : 1; /*!< [22] PDB Clock Gate Control */
2726 uint32_t PITb : 1; /*!< [23] PIT Clock Gate Control */
2727 uint32_t FTM0b : 1; /*!< [24] FTM0 Clock Gate Control */
2728 uint32_t FTM1b : 1; /*!< [25] FTM1 Clock Gate Control */
2729 uint32_t FTM2b : 1; /*!< [26] FTM2 Clock Gate Control */
2730 uint32_t ADC0b : 1; /*!< [27] ADC0 Clock Gate Control */
2731 uint32_t RESERVED6 : 1; /*!< [28] */
2732 uint32_t RTCb : 1; /*!< [29] RTC Access Control */
2733 uint32_t RESERVED7 : 1; /*!< [30] */
2734 uint32_t DAC0b : 1; /*!< [31] DAC0 Clock Gate Control */
2739 * @name Constants and macros for entire SIM_SCGC6 register
2742 #define HW_SIM_SCGC6_ADDR(x) ((x) + 0x103CU)
2744 #define HW_SIM_SCGC6(x) (*(__IO hw_sim_scgc6_t *) HW_SIM_SCGC6_ADDR(x))
2745 #define HW_SIM_SCGC6_RD(x) (HW_SIM_SCGC6(x).U)
2746 #define HW_SIM_SCGC6_WR(x, v) (HW_SIM_SCGC6(x).U = (v))
2747 #define HW_SIM_SCGC6_SET(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) | (v)))
2748 #define HW_SIM_SCGC6_CLR(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) & ~(v)))
2749 #define HW_SIM_SCGC6_TOG(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) ^ (v)))
2753 * Constants & macros for individual SIM_SCGC6 bitfields
2757 * @name Register SIM_SCGC6, field FTF[0] (RW)
2759 * This bit controls the clock gate to the flash memory. Flash reads are still
2760 * supported while the flash memory is clock gated, but entry into low power modes
2764 * - 0 - Clock disabled
2765 * - 1 - Clock enabled
2768 #define BP_SIM_SCGC6_FTF (0U) /*!< Bit position for SIM_SCGC6_FTF. */
2769 #define BM_SIM_SCGC6_FTF (0x00000001U) /*!< Bit mask for SIM_SCGC6_FTF. */
2770 #define BS_SIM_SCGC6_FTF (1U) /*!< Bit field size in bits for SIM_SCGC6_FTF. */
2772 /*! @brief Read current value of the SIM_SCGC6_FTF field. */
2773 #define BR_SIM_SCGC6_FTF(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF))
2775 /*! @brief Format value for bitfield SIM_SCGC6_FTF. */
2776 #define BF_SIM_SCGC6_FTF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTF) & BM_SIM_SCGC6_FTF)
2778 /*! @brief Set the FTF field to a new value. */
2779 #define BW_SIM_SCGC6_FTF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF) = (v))
2783 * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
2785 * This bit controls the clock gate to the DMA Mux module.
2788 * - 0 - Clock disabled
2789 * - 1 - Clock enabled
2792 #define BP_SIM_SCGC6_DMAMUX (1U) /*!< Bit position for SIM_SCGC6_DMAMUX. */
2793 #define BM_SIM_SCGC6_DMAMUX (0x00000002U) /*!< Bit mask for SIM_SCGC6_DMAMUX. */
2794 #define BS_SIM_SCGC6_DMAMUX (1U) /*!< Bit field size in bits for SIM_SCGC6_DMAMUX. */
2796 /*! @brief Read current value of the SIM_SCGC6_DMAMUX field. */
2797 #define BR_SIM_SCGC6_DMAMUX(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX))
2799 /*! @brief Format value for bitfield SIM_SCGC6_DMAMUX. */
2800 #define BF_SIM_SCGC6_DMAMUX(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DMAMUX) & BM_SIM_SCGC6_DMAMUX)
2802 /*! @brief Set the DMAMUX field to a new value. */
2803 #define BW_SIM_SCGC6_DMAMUX(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX) = (v))
2807 * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
2809 * This bit controls the clock gate to the FlexCAN0 module.
2812 * - 0 - Clock disabled
2813 * - 1 - Clock enabled
2816 #define BP_SIM_SCGC6_FLEXCAN0 (4U) /*!< Bit position for SIM_SCGC6_FLEXCAN0. */
2817 #define BM_SIM_SCGC6_FLEXCAN0 (0x00000010U) /*!< Bit mask for SIM_SCGC6_FLEXCAN0. */
2818 #define BS_SIM_SCGC6_FLEXCAN0 (1U) /*!< Bit field size in bits for SIM_SCGC6_FLEXCAN0. */
2820 /*! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field. */
2821 #define BR_SIM_SCGC6_FLEXCAN0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FLEXCAN0))
2823 /*! @brief Format value for bitfield SIM_SCGC6_FLEXCAN0. */
2824 #define BF_SIM_SCGC6_FLEXCAN0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FLEXCAN0) & BM_SIM_SCGC6_FLEXCAN0)
2826 /*! @brief Set the FLEXCAN0 field to a new value. */
2827 #define BW_SIM_SCGC6_FLEXCAN0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FLEXCAN0) = (v))
2831 * @name Register SIM_SCGC6, field RNGA[9] (RW)
2833 * This bit controls the clock gate to the RNGA module.
2836 #define BP_SIM_SCGC6_RNGA (9U) /*!< Bit position for SIM_SCGC6_RNGA. */
2837 #define BM_SIM_SCGC6_RNGA (0x00000200U) /*!< Bit mask for SIM_SCGC6_RNGA. */
2838 #define BS_SIM_SCGC6_RNGA (1U) /*!< Bit field size in bits for SIM_SCGC6_RNGA. */
2840 /*! @brief Read current value of the SIM_SCGC6_RNGA field. */
2841 #define BR_SIM_SCGC6_RNGA(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA))
2843 /*! @brief Format value for bitfield SIM_SCGC6_RNGA. */
2844 #define BF_SIM_SCGC6_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RNGA) & BM_SIM_SCGC6_RNGA)
2846 /*! @brief Set the RNGA field to a new value. */
2847 #define BW_SIM_SCGC6_RNGA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA) = (v))
2851 * @name Register SIM_SCGC6, field SPI0[12] (RW)
2853 * This bit controls the clock gate to the SPI0 module.
2856 * - 0 - Clock disabled
2857 * - 1 - Clock enabled
2860 #define BP_SIM_SCGC6_SPI0 (12U) /*!< Bit position for SIM_SCGC6_SPI0. */
2861 #define BM_SIM_SCGC6_SPI0 (0x00001000U) /*!< Bit mask for SIM_SCGC6_SPI0. */
2862 #define BS_SIM_SCGC6_SPI0 (1U) /*!< Bit field size in bits for SIM_SCGC6_SPI0. */
2864 /*! @brief Read current value of the SIM_SCGC6_SPI0 field. */
2865 #define BR_SIM_SCGC6_SPI0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0))
2867 /*! @brief Format value for bitfield SIM_SCGC6_SPI0. */
2868 #define BF_SIM_SCGC6_SPI0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI0) & BM_SIM_SCGC6_SPI0)
2870 /*! @brief Set the SPI0 field to a new value. */
2871 #define BW_SIM_SCGC6_SPI0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0) = (v))
2875 * @name Register SIM_SCGC6, field SPI1[13] (RW)
2877 * This bit controls the clock gate to the SPI1 module.
2880 * - 0 - Clock disabled
2881 * - 1 - Clock enabled
2884 #define BP_SIM_SCGC6_SPI1 (13U) /*!< Bit position for SIM_SCGC6_SPI1. */
2885 #define BM_SIM_SCGC6_SPI1 (0x00002000U) /*!< Bit mask for SIM_SCGC6_SPI1. */
2886 #define BS_SIM_SCGC6_SPI1 (1U) /*!< Bit field size in bits for SIM_SCGC6_SPI1. */
2888 /*! @brief Read current value of the SIM_SCGC6_SPI1 field. */
2889 #define BR_SIM_SCGC6_SPI1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1))
2891 /*! @brief Format value for bitfield SIM_SCGC6_SPI1. */
2892 #define BF_SIM_SCGC6_SPI1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI1) & BM_SIM_SCGC6_SPI1)
2894 /*! @brief Set the SPI1 field to a new value. */
2895 #define BW_SIM_SCGC6_SPI1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1) = (v))
2899 * @name Register SIM_SCGC6, field I2S[15] (RW)
2901 * This bit controls the clock gate to the I 2 S module.
2904 * - 0 - Clock disabled
2905 * - 1 - Clock enabled
2908 #define BP_SIM_SCGC6_I2S (15U) /*!< Bit position for SIM_SCGC6_I2S. */
2909 #define BM_SIM_SCGC6_I2S (0x00008000U) /*!< Bit mask for SIM_SCGC6_I2S. */
2910 #define BS_SIM_SCGC6_I2S (1U) /*!< Bit field size in bits for SIM_SCGC6_I2S. */
2912 /*! @brief Read current value of the SIM_SCGC6_I2S field. */
2913 #define BR_SIM_SCGC6_I2S(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S))
2915 /*! @brief Format value for bitfield SIM_SCGC6_I2S. */
2916 #define BF_SIM_SCGC6_I2S(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_I2S) & BM_SIM_SCGC6_I2S)
2918 /*! @brief Set the I2S field to a new value. */
2919 #define BW_SIM_SCGC6_I2S(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S) = (v))
2923 * @name Register SIM_SCGC6, field CRC[18] (RW)
2925 * This bit controls the clock gate to the CRC module.
2928 * - 0 - Clock disabled
2929 * - 1 - Clock enabled
2932 #define BP_SIM_SCGC6_CRC (18U) /*!< Bit position for SIM_SCGC6_CRC. */
2933 #define BM_SIM_SCGC6_CRC (0x00040000U) /*!< Bit mask for SIM_SCGC6_CRC. */
2934 #define BS_SIM_SCGC6_CRC (1U) /*!< Bit field size in bits for SIM_SCGC6_CRC. */
2936 /*! @brief Read current value of the SIM_SCGC6_CRC field. */
2937 #define BR_SIM_SCGC6_CRC(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC))
2939 /*! @brief Format value for bitfield SIM_SCGC6_CRC. */
2940 #define BF_SIM_SCGC6_CRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_CRC) & BM_SIM_SCGC6_CRC)
2942 /*! @brief Set the CRC field to a new value. */
2943 #define BW_SIM_SCGC6_CRC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC) = (v))
2947 * @name Register SIM_SCGC6, field USBDCD[21] (RW)
2949 * This bit controls the clock gate to the USB DCD module.
2952 * - 0 - Clock disabled
2953 * - 1 - Clock enabled
2956 #define BP_SIM_SCGC6_USBDCD (21U) /*!< Bit position for SIM_SCGC6_USBDCD. */
2957 #define BM_SIM_SCGC6_USBDCD (0x00200000U) /*!< Bit mask for SIM_SCGC6_USBDCD. */
2958 #define BS_SIM_SCGC6_USBDCD (1U) /*!< Bit field size in bits for SIM_SCGC6_USBDCD. */
2960 /*! @brief Read current value of the SIM_SCGC6_USBDCD field. */
2961 #define BR_SIM_SCGC6_USBDCD(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBDCD))
2963 /*! @brief Format value for bitfield SIM_SCGC6_USBDCD. */
2964 #define BF_SIM_SCGC6_USBDCD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_USBDCD) & BM_SIM_SCGC6_USBDCD)
2966 /*! @brief Set the USBDCD field to a new value. */
2967 #define BW_SIM_SCGC6_USBDCD(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBDCD) = (v))
2971 * @name Register SIM_SCGC6, field PDB[22] (RW)
2973 * This bit controls the clock gate to the PDB module.
2976 * - 0 - Clock disabled
2977 * - 1 - Clock enabled
2980 #define BP_SIM_SCGC6_PDB (22U) /*!< Bit position for SIM_SCGC6_PDB. */
2981 #define BM_SIM_SCGC6_PDB (0x00400000U) /*!< Bit mask for SIM_SCGC6_PDB. */
2982 #define BS_SIM_SCGC6_PDB (1U) /*!< Bit field size in bits for SIM_SCGC6_PDB. */
2984 /*! @brief Read current value of the SIM_SCGC6_PDB field. */
2985 #define BR_SIM_SCGC6_PDB(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB))
2987 /*! @brief Format value for bitfield SIM_SCGC6_PDB. */
2988 #define BF_SIM_SCGC6_PDB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PDB) & BM_SIM_SCGC6_PDB)
2990 /*! @brief Set the PDB field to a new value. */
2991 #define BW_SIM_SCGC6_PDB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB) = (v))
2995 * @name Register SIM_SCGC6, field PIT[23] (RW)
2997 * This bit controls the clock gate to the PIT module.
3000 * - 0 - Clock disabled
3001 * - 1 - Clock enabled
3004 #define BP_SIM_SCGC6_PIT (23U) /*!< Bit position for SIM_SCGC6_PIT. */
3005 #define BM_SIM_SCGC6_PIT (0x00800000U) /*!< Bit mask for SIM_SCGC6_PIT. */
3006 #define BS_SIM_SCGC6_PIT (1U) /*!< Bit field size in bits for SIM_SCGC6_PIT. */
3008 /*! @brief Read current value of the SIM_SCGC6_PIT field. */
3009 #define BR_SIM_SCGC6_PIT(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT))
3011 /*! @brief Format value for bitfield SIM_SCGC6_PIT. */
3012 #define BF_SIM_SCGC6_PIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PIT) & BM_SIM_SCGC6_PIT)
3014 /*! @brief Set the PIT field to a new value. */
3015 #define BW_SIM_SCGC6_PIT(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT) = (v))
3019 * @name Register SIM_SCGC6, field FTM0[24] (RW)
3021 * This bit controls the clock gate to the FTM0 module.
3024 * - 0 - Clock disabled
3025 * - 1 - Clock enabled
3028 #define BP_SIM_SCGC6_FTM0 (24U) /*!< Bit position for SIM_SCGC6_FTM0. */
3029 #define BM_SIM_SCGC6_FTM0 (0x01000000U) /*!< Bit mask for SIM_SCGC6_FTM0. */
3030 #define BS_SIM_SCGC6_FTM0 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM0. */
3032 /*! @brief Read current value of the SIM_SCGC6_FTM0 field. */
3033 #define BR_SIM_SCGC6_FTM0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0))
3035 /*! @brief Format value for bitfield SIM_SCGC6_FTM0. */
3036 #define BF_SIM_SCGC6_FTM0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM0) & BM_SIM_SCGC6_FTM0)
3038 /*! @brief Set the FTM0 field to a new value. */
3039 #define BW_SIM_SCGC6_FTM0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0) = (v))
3043 * @name Register SIM_SCGC6, field FTM1[25] (RW)
3045 * This bit controls the clock gate to the FTM1 module.
3048 * - 0 - Clock disabled
3049 * - 1 - Clock enabled
3052 #define BP_SIM_SCGC6_FTM1 (25U) /*!< Bit position for SIM_SCGC6_FTM1. */
3053 #define BM_SIM_SCGC6_FTM1 (0x02000000U) /*!< Bit mask for SIM_SCGC6_FTM1. */
3054 #define BS_SIM_SCGC6_FTM1 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM1. */
3056 /*! @brief Read current value of the SIM_SCGC6_FTM1 field. */
3057 #define BR_SIM_SCGC6_FTM1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1))
3059 /*! @brief Format value for bitfield SIM_SCGC6_FTM1. */
3060 #define BF_SIM_SCGC6_FTM1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM1) & BM_SIM_SCGC6_FTM1)
3062 /*! @brief Set the FTM1 field to a new value. */
3063 #define BW_SIM_SCGC6_FTM1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1) = (v))
3067 * @name Register SIM_SCGC6, field FTM2[26] (RW)
3069 * This bit controls the clock gate to the FTM2 module.
3072 * - 0 - Clock disabled
3073 * - 1 - Clock enabled
3076 #define BP_SIM_SCGC6_FTM2 (26U) /*!< Bit position for SIM_SCGC6_FTM2. */
3077 #define BM_SIM_SCGC6_FTM2 (0x04000000U) /*!< Bit mask for SIM_SCGC6_FTM2. */
3078 #define BS_SIM_SCGC6_FTM2 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM2. */
3080 /*! @brief Read current value of the SIM_SCGC6_FTM2 field. */
3081 #define BR_SIM_SCGC6_FTM2(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2))
3083 /*! @brief Format value for bitfield SIM_SCGC6_FTM2. */
3084 #define BF_SIM_SCGC6_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM2) & BM_SIM_SCGC6_FTM2)
3086 /*! @brief Set the FTM2 field to a new value. */
3087 #define BW_SIM_SCGC6_FTM2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2) = (v))
3091 * @name Register SIM_SCGC6, field ADC0[27] (RW)
3093 * This bit controls the clock gate to the ADC0 module.
3096 * - 0 - Clock disabled
3097 * - 1 - Clock enabled
3100 #define BP_SIM_SCGC6_ADC0 (27U) /*!< Bit position for SIM_SCGC6_ADC0. */
3101 #define BM_SIM_SCGC6_ADC0 (0x08000000U) /*!< Bit mask for SIM_SCGC6_ADC0. */
3102 #define BS_SIM_SCGC6_ADC0 (1U) /*!< Bit field size in bits for SIM_SCGC6_ADC0. */
3104 /*! @brief Read current value of the SIM_SCGC6_ADC0 field. */
3105 #define BR_SIM_SCGC6_ADC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0))
3107 /*! @brief Format value for bitfield SIM_SCGC6_ADC0. */
3108 #define BF_SIM_SCGC6_ADC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_ADC0) & BM_SIM_SCGC6_ADC0)
3110 /*! @brief Set the ADC0 field to a new value. */
3111 #define BW_SIM_SCGC6_ADC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0) = (v))
3115 * @name Register SIM_SCGC6, field RTC[29] (RW)
3117 * This bit controls software access and interrupts to the RTC module.
3120 * - 0 - Access and interrupts disabled
3121 * - 1 - Access and interrupts enabled
3124 #define BP_SIM_SCGC6_RTC (29U) /*!< Bit position for SIM_SCGC6_RTC. */
3125 #define BM_SIM_SCGC6_RTC (0x20000000U) /*!< Bit mask for SIM_SCGC6_RTC. */
3126 #define BS_SIM_SCGC6_RTC (1U) /*!< Bit field size in bits for SIM_SCGC6_RTC. */
3128 /*! @brief Read current value of the SIM_SCGC6_RTC field. */
3129 #define BR_SIM_SCGC6_RTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC))
3131 /*! @brief Format value for bitfield SIM_SCGC6_RTC. */
3132 #define BF_SIM_SCGC6_RTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RTC) & BM_SIM_SCGC6_RTC)
3134 /*! @brief Set the RTC field to a new value. */
3135 #define BW_SIM_SCGC6_RTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC) = (v))
3139 * @name Register SIM_SCGC6, field DAC0[31] (RW)
3141 * This bit controls the clock gate to the DAC0 module.
3144 * - 0 - Clock disabled
3145 * - 1 - Clock enabled
3148 #define BP_SIM_SCGC6_DAC0 (31U) /*!< Bit position for SIM_SCGC6_DAC0. */
3149 #define BM_SIM_SCGC6_DAC0 (0x80000000U) /*!< Bit mask for SIM_SCGC6_DAC0. */
3150 #define BS_SIM_SCGC6_DAC0 (1U) /*!< Bit field size in bits for SIM_SCGC6_DAC0. */
3152 /*! @brief Read current value of the SIM_SCGC6_DAC0 field. */
3153 #define BR_SIM_SCGC6_DAC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0))
3155 /*! @brief Format value for bitfield SIM_SCGC6_DAC0. */
3156 #define BF_SIM_SCGC6_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DAC0) & BM_SIM_SCGC6_DAC0)
3158 /*! @brief Set the DAC0 field to a new value. */
3159 #define BW_SIM_SCGC6_DAC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0) = (v))
3162 /*******************************************************************************
3163 * HW_SIM_SCGC7 - System Clock Gating Control Register 7
3164 ******************************************************************************/
3167 * @brief HW_SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
3169 * Reset value: 0x00000006U
3171 typedef union _hw_sim_scgc7
3174 struct _hw_sim_scgc7_bitfields
3176 uint32_t FLEXBUS : 1; /*!< [0] FlexBus Clock Gate Control */
3177 uint32_t DMA : 1; /*!< [1] DMA Clock Gate Control */
3178 uint32_t MPUb : 1; /*!< [2] MPU Clock Gate Control */
3179 uint32_t RESERVED0 : 29; /*!< [31:3] */
3184 * @name Constants and macros for entire SIM_SCGC7 register
3187 #define HW_SIM_SCGC7_ADDR(x) ((x) + 0x1040U)
3189 #define HW_SIM_SCGC7(x) (*(__IO hw_sim_scgc7_t *) HW_SIM_SCGC7_ADDR(x))
3190 #define HW_SIM_SCGC7_RD(x) (HW_SIM_SCGC7(x).U)
3191 #define HW_SIM_SCGC7_WR(x, v) (HW_SIM_SCGC7(x).U = (v))
3192 #define HW_SIM_SCGC7_SET(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) | (v)))
3193 #define HW_SIM_SCGC7_CLR(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) & ~(v)))
3194 #define HW_SIM_SCGC7_TOG(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) ^ (v)))
3198 * Constants & macros for individual SIM_SCGC7 bitfields
3202 * @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
3204 * This bit controls the clock gate to the FlexBus module.
3207 * - 0 - Clock disabled
3208 * - 1 - Clock enabled
3211 #define BP_SIM_SCGC7_FLEXBUS (0U) /*!< Bit position for SIM_SCGC7_FLEXBUS. */
3212 #define BM_SIM_SCGC7_FLEXBUS (0x00000001U) /*!< Bit mask for SIM_SCGC7_FLEXBUS. */
3213 #define BS_SIM_SCGC7_FLEXBUS (1U) /*!< Bit field size in bits for SIM_SCGC7_FLEXBUS. */
3215 /*! @brief Read current value of the SIM_SCGC7_FLEXBUS field. */
3216 #define BR_SIM_SCGC7_FLEXBUS(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS))
3218 /*! @brief Format value for bitfield SIM_SCGC7_FLEXBUS. */
3219 #define BF_SIM_SCGC7_FLEXBUS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_FLEXBUS) & BM_SIM_SCGC7_FLEXBUS)
3221 /*! @brief Set the FLEXBUS field to a new value. */
3222 #define BW_SIM_SCGC7_FLEXBUS(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS) = (v))
3226 * @name Register SIM_SCGC7, field DMA[1] (RW)
3228 * This bit controls the clock gate to the DMA module.
3231 * - 0 - Clock disabled
3232 * - 1 - Clock enabled
3235 #define BP_SIM_SCGC7_DMA (1U) /*!< Bit position for SIM_SCGC7_DMA. */
3236 #define BM_SIM_SCGC7_DMA (0x00000002U) /*!< Bit mask for SIM_SCGC7_DMA. */
3237 #define BS_SIM_SCGC7_DMA (1U) /*!< Bit field size in bits for SIM_SCGC7_DMA. */
3239 /*! @brief Read current value of the SIM_SCGC7_DMA field. */
3240 #define BR_SIM_SCGC7_DMA(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA))
3242 /*! @brief Format value for bitfield SIM_SCGC7_DMA. */
3243 #define BF_SIM_SCGC7_DMA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_DMA) & BM_SIM_SCGC7_DMA)
3245 /*! @brief Set the DMA field to a new value. */
3246 #define BW_SIM_SCGC7_DMA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA) = (v))
3250 * @name Register SIM_SCGC7, field MPU[2] (RW)
3252 * This bit controls the clock gate to the MPU module.
3255 * - 0 - Clock disabled
3256 * - 1 - Clock enabled
3259 #define BP_SIM_SCGC7_MPU (2U) /*!< Bit position for SIM_SCGC7_MPU. */
3260 #define BM_SIM_SCGC7_MPU (0x00000004U) /*!< Bit mask for SIM_SCGC7_MPU. */
3261 #define BS_SIM_SCGC7_MPU (1U) /*!< Bit field size in bits for SIM_SCGC7_MPU. */
3263 /*! @brief Read current value of the SIM_SCGC7_MPU field. */
3264 #define BR_SIM_SCGC7_MPU(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_MPU))
3266 /*! @brief Format value for bitfield SIM_SCGC7_MPU. */
3267 #define BF_SIM_SCGC7_MPU(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_MPU) & BM_SIM_SCGC7_MPU)
3269 /*! @brief Set the MPU field to a new value. */
3270 #define BW_SIM_SCGC7_MPU(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_MPU) = (v))
3273 /*******************************************************************************
3274 * HW_SIM_CLKDIV1 - System Clock Divider Register 1
3275 ******************************************************************************/
3278 * @brief HW_SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
3280 * Reset value: 0x00010000U
3282 * When updating CLKDIV1, update all fields using the one write command.
3283 * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
3284 * write to be ignored. The maximum divide ratio that can be programmed between
3285 * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
3286 * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
3287 * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
3290 typedef union _hw_sim_clkdiv1
3293 struct _hw_sim_clkdiv1_bitfields
3295 uint32_t RESERVED0 : 16; /*!< [15:0] */
3296 uint32_t OUTDIV4 : 4; /*!< [19:16] Clock 4 output divider value */
3297 uint32_t OUTDIV3 : 4; /*!< [23:20] Clock 3 output divider value */
3298 uint32_t OUTDIV2 : 4; /*!< [27:24] Clock 2 output divider value */
3299 uint32_t OUTDIV1 : 4; /*!< [31:28] Clock 1 output divider value */
3304 * @name Constants and macros for entire SIM_CLKDIV1 register
3307 #define HW_SIM_CLKDIV1_ADDR(x) ((x) + 0x1044U)
3309 #define HW_SIM_CLKDIV1(x) (*(__IO hw_sim_clkdiv1_t *) HW_SIM_CLKDIV1_ADDR(x))
3310 #define HW_SIM_CLKDIV1_RD(x) (HW_SIM_CLKDIV1(x).U)
3311 #define HW_SIM_CLKDIV1_WR(x, v) (HW_SIM_CLKDIV1(x).U = (v))
3312 #define HW_SIM_CLKDIV1_SET(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) | (v)))
3313 #define HW_SIM_CLKDIV1_CLR(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) & ~(v)))
3314 #define HW_SIM_CLKDIV1_TOG(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) ^ (v)))
3318 * Constants & macros for individual SIM_CLKDIV1 bitfields
3322 * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
3324 * This field sets the divide value for the flash clock from MCGOUTCLK. At the
3325 * end of reset, it is loaded with either 0001 or 1111 depending on
3326 * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
3330 * - 0000 - Divide-by-1.
3331 * - 0001 - Divide-by-2.
3332 * - 0010 - Divide-by-3.
3333 * - 0011 - Divide-by-4.
3334 * - 0100 - Divide-by-5.
3335 * - 0101 - Divide-by-6.
3336 * - 0110 - Divide-by-7.
3337 * - 0111 - Divide-by-8.
3338 * - 1000 - Divide-by-9.
3339 * - 1001 - Divide-by-10.
3340 * - 1010 - Divide-by-11.
3341 * - 1011 - Divide-by-12.
3342 * - 1100 - Divide-by-13.
3343 * - 1101 - Divide-by-14.
3344 * - 1110 - Divide-by-15.
3345 * - 1111 - Divide-by-16.
3348 #define BP_SIM_CLKDIV1_OUTDIV4 (16U) /*!< Bit position for SIM_CLKDIV1_OUTDIV4. */
3349 #define BM_SIM_CLKDIV1_OUTDIV4 (0x000F0000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV4. */
3350 #define BS_SIM_CLKDIV1_OUTDIV4 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV4. */
3352 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */
3353 #define BR_SIM_CLKDIV1_OUTDIV4(x) (HW_SIM_CLKDIV1(x).B.OUTDIV4)
3355 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV4. */
3356 #define BF_SIM_CLKDIV1_OUTDIV4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV4) & BM_SIM_CLKDIV1_OUTDIV4)
3358 /*! @brief Set the OUTDIV4 field to a new value. */
3359 #define BW_SIM_CLKDIV1_OUTDIV4(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV4) | BF_SIM_CLKDIV1_OUTDIV4(v)))
3363 * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
3365 * This field sets the divide value for the FlexBus clock (external pin FB_CLK)
3366 * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
3367 * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
3368 * divide of the system clock frequency.
3371 * - 0000 - Divide-by-1.
3372 * - 0001 - Divide-by-2.
3373 * - 0010 - Divide-by-3.
3374 * - 0011 - Divide-by-4.
3375 * - 0100 - Divide-by-5.
3376 * - 0101 - Divide-by-6.
3377 * - 0110 - Divide-by-7.
3378 * - 0111 - Divide-by-8.
3379 * - 1000 - Divide-by-9.
3380 * - 1001 - Divide-by-10.
3381 * - 1010 - Divide-by-11.
3382 * - 1011 - Divide-by-12.
3383 * - 1100 - Divide-by-13.
3384 * - 1101 - Divide-by-14.
3385 * - 1110 - Divide-by-15.
3386 * - 1111 - Divide-by-16.
3389 #define BP_SIM_CLKDIV1_OUTDIV3 (20U) /*!< Bit position for SIM_CLKDIV1_OUTDIV3. */
3390 #define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV3. */
3391 #define BS_SIM_CLKDIV1_OUTDIV3 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3. */
3393 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. */
3394 #define BR_SIM_CLKDIV1_OUTDIV3(x) (HW_SIM_CLKDIV1(x).B.OUTDIV3)
3396 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3. */
3397 #define BF_SIM_CLKDIV1_OUTDIV3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV3) & BM_SIM_CLKDIV1_OUTDIV3)
3399 /*! @brief Set the OUTDIV3 field to a new value. */
3400 #define BW_SIM_CLKDIV1_OUTDIV3(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV3) | BF_SIM_CLKDIV1_OUTDIV3(v)))
3404 * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
3406 * This field sets the divide value for the bus clock from MCGOUTCLK. At the end
3407 * of reset, it is loaded with either 0000 or 0111 depending on
3408 * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
3412 * - 0000 - Divide-by-1.
3413 * - 0001 - Divide-by-2.
3414 * - 0010 - Divide-by-3.
3415 * - 0011 - Divide-by-4.
3416 * - 0100 - Divide-by-5.
3417 * - 0101 - Divide-by-6.
3418 * - 0110 - Divide-by-7.
3419 * - 0111 - Divide-by-8.
3420 * - 1000 - Divide-by-9.
3421 * - 1001 - Divide-by-10.
3422 * - 1010 - Divide-by-11.
3423 * - 1011 - Divide-by-12.
3424 * - 1100 - Divide-by-13.
3425 * - 1101 - Divide-by-14.
3426 * - 1110 - Divide-by-15.
3427 * - 1111 - Divide-by-16.
3430 #define BP_SIM_CLKDIV1_OUTDIV2 (24U) /*!< Bit position for SIM_CLKDIV1_OUTDIV2. */
3431 #define BM_SIM_CLKDIV1_OUTDIV2 (0x0F000000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV2. */
3432 #define BS_SIM_CLKDIV1_OUTDIV2 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV2. */
3434 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. */
3435 #define BR_SIM_CLKDIV1_OUTDIV2(x) (HW_SIM_CLKDIV1(x).B.OUTDIV2)
3437 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV2. */
3438 #define BF_SIM_CLKDIV1_OUTDIV2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV2) & BM_SIM_CLKDIV1_OUTDIV2)
3440 /*! @brief Set the OUTDIV2 field to a new value. */
3441 #define BW_SIM_CLKDIV1_OUTDIV2(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV2) | BF_SIM_CLKDIV1_OUTDIV2(v)))
3445 * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
3447 * This field sets the divide value for the core/system clock from MCGOUTCLK. At
3448 * the end of reset, it is loaded with either 0000 or 0111 depending on
3452 * - 0000 - Divide-by-1.
3453 * - 0001 - Divide-by-2.
3454 * - 0010 - Divide-by-3.
3455 * - 0011 - Divide-by-4.
3456 * - 0100 - Divide-by-5.
3457 * - 0101 - Divide-by-6.
3458 * - 0110 - Divide-by-7.
3459 * - 0111 - Divide-by-8.
3460 * - 1000 - Divide-by-9.
3461 * - 1001 - Divide-by-10.
3462 * - 1010 - Divide-by-11.
3463 * - 1011 - Divide-by-12.
3464 * - 1100 - Divide-by-13.
3465 * - 1101 - Divide-by-14.
3466 * - 1110 - Divide-by-15.
3467 * - 1111 - Divide-by-16.
3470 #define BP_SIM_CLKDIV1_OUTDIV1 (28U) /*!< Bit position for SIM_CLKDIV1_OUTDIV1. */
3471 #define BM_SIM_CLKDIV1_OUTDIV1 (0xF0000000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV1. */
3472 #define BS_SIM_CLKDIV1_OUTDIV1 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV1. */
3474 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */
3475 #define BR_SIM_CLKDIV1_OUTDIV1(x) (HW_SIM_CLKDIV1(x).B.OUTDIV1)
3477 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV1. */
3478 #define BF_SIM_CLKDIV1_OUTDIV1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV1) & BM_SIM_CLKDIV1_OUTDIV1)
3480 /*! @brief Set the OUTDIV1 field to a new value. */
3481 #define BW_SIM_CLKDIV1_OUTDIV1(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV1) | BF_SIM_CLKDIV1_OUTDIV1(v)))
3484 /*******************************************************************************
3485 * HW_SIM_CLKDIV2 - System Clock Divider Register 2
3486 ******************************************************************************/
3489 * @brief HW_SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
3491 * Reset value: 0x00000000U
3493 typedef union _hw_sim_clkdiv2
3496 struct _hw_sim_clkdiv2_bitfields
3498 uint32_t USBFRAC : 1; /*!< [0] USB clock divider fraction */
3499 uint32_t USBDIV : 3; /*!< [3:1] USB clock divider divisor */
3500 uint32_t RESERVED0 : 28; /*!< [31:4] */
3505 * @name Constants and macros for entire SIM_CLKDIV2 register
3508 #define HW_SIM_CLKDIV2_ADDR(x) ((x) + 0x1048U)
3510 #define HW_SIM_CLKDIV2(x) (*(__IO hw_sim_clkdiv2_t *) HW_SIM_CLKDIV2_ADDR(x))
3511 #define HW_SIM_CLKDIV2_RD(x) (HW_SIM_CLKDIV2(x).U)
3512 #define HW_SIM_CLKDIV2_WR(x, v) (HW_SIM_CLKDIV2(x).U = (v))
3513 #define HW_SIM_CLKDIV2_SET(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) | (v)))
3514 #define HW_SIM_CLKDIV2_CLR(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) & ~(v)))
3515 #define HW_SIM_CLKDIV2_TOG(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) ^ (v)))
3519 * Constants & macros for individual SIM_CLKDIV2 bitfields
3523 * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
3525 * This field sets the fraction multiply value for the fractional clock divider
3526 * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
3527 * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
3530 #define BP_SIM_CLKDIV2_USBFRAC (0U) /*!< Bit position for SIM_CLKDIV2_USBFRAC. */
3531 #define BM_SIM_CLKDIV2_USBFRAC (0x00000001U) /*!< Bit mask for SIM_CLKDIV2_USBFRAC. */
3532 #define BS_SIM_CLKDIV2_USBFRAC (1U) /*!< Bit field size in bits for SIM_CLKDIV2_USBFRAC. */
3534 /*! @brief Read current value of the SIM_CLKDIV2_USBFRAC field. */
3535 #define BR_SIM_CLKDIV2_USBFRAC(x) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC))
3537 /*! @brief Format value for bitfield SIM_CLKDIV2_USBFRAC. */
3538 #define BF_SIM_CLKDIV2_USBFRAC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBFRAC) & BM_SIM_CLKDIV2_USBFRAC)
3540 /*! @brief Set the USBFRAC field to a new value. */
3541 #define BW_SIM_CLKDIV2_USBFRAC(x, v) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC) = (v))
3545 * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
3547 * This field sets the divide value for the fractional clock divider when the
3548 * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
3549 * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
3552 #define BP_SIM_CLKDIV2_USBDIV (1U) /*!< Bit position for SIM_CLKDIV2_USBDIV. */
3553 #define BM_SIM_CLKDIV2_USBDIV (0x0000000EU) /*!< Bit mask for SIM_CLKDIV2_USBDIV. */
3554 #define BS_SIM_CLKDIV2_USBDIV (3U) /*!< Bit field size in bits for SIM_CLKDIV2_USBDIV. */
3556 /*! @brief Read current value of the SIM_CLKDIV2_USBDIV field. */
3557 #define BR_SIM_CLKDIV2_USBDIV(x) (HW_SIM_CLKDIV2(x).B.USBDIV)
3559 /*! @brief Format value for bitfield SIM_CLKDIV2_USBDIV. */
3560 #define BF_SIM_CLKDIV2_USBDIV(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBDIV) & BM_SIM_CLKDIV2_USBDIV)
3562 /*! @brief Set the USBDIV field to a new value. */
3563 #define BW_SIM_CLKDIV2_USBDIV(x, v) (HW_SIM_CLKDIV2_WR(x, (HW_SIM_CLKDIV2_RD(x) & ~BM_SIM_CLKDIV2_USBDIV) | BF_SIM_CLKDIV2_USBDIV(v)))
3566 /*******************************************************************************
3567 * HW_SIM_FCFG1 - Flash Configuration Register 1
3568 ******************************************************************************/
3571 * @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW)
3573 * Reset value: 0xFF0F0F00U
3575 * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on
3576 * user programming in user IFR via the PGMPART flash command. For devices with
3577 * program flash only:
3579 typedef union _hw_sim_fcfg1
3582 struct _hw_sim_fcfg1_bitfields
3584 uint32_t FLASHDIS : 1; /*!< [0] Flash Disable */
3585 uint32_t FLASHDOZE : 1; /*!< [1] Flash Doze */
3586 uint32_t RESERVED0 : 6; /*!< [7:2] */
3587 uint32_t DEPART : 4; /*!< [11:8] FlexNVM partition */
3588 uint32_t RESERVED1 : 4; /*!< [15:12] */
3589 uint32_t EESIZE : 4; /*!< [19:16] EEPROM size */
3590 uint32_t RESERVED2 : 4; /*!< [23:20] */
3591 uint32_t PFSIZE : 4; /*!< [27:24] Program flash size */
3592 uint32_t NVMSIZE : 4; /*!< [31:28] FlexNVM size */
3597 * @name Constants and macros for entire SIM_FCFG1 register
3600 #define HW_SIM_FCFG1_ADDR(x) ((x) + 0x104CU)
3602 #define HW_SIM_FCFG1(x) (*(__IO hw_sim_fcfg1_t *) HW_SIM_FCFG1_ADDR(x))
3603 #define HW_SIM_FCFG1_RD(x) (HW_SIM_FCFG1(x).U)
3604 #define HW_SIM_FCFG1_WR(x, v) (HW_SIM_FCFG1(x).U = (v))
3605 #define HW_SIM_FCFG1_SET(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) | (v)))
3606 #define HW_SIM_FCFG1_CLR(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) & ~(v)))
3607 #define HW_SIM_FCFG1_TOG(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) ^ (v)))
3611 * Constants & macros for individual SIM_FCFG1 bitfields
3615 * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
3617 * Flash accesses are disabled (and generate a bus error) and the Flash memory
3618 * is placed in a low power state. This bit should not be changed during VLP
3619 * modes. Relocate the interrupt vectors out of Flash memory before disabling the
3623 * - 0 - Flash is enabled
3624 * - 1 - Flash is disabled
3627 #define BP_SIM_FCFG1_FLASHDIS (0U) /*!< Bit position for SIM_FCFG1_FLASHDIS. */
3628 #define BM_SIM_FCFG1_FLASHDIS (0x00000001U) /*!< Bit mask for SIM_FCFG1_FLASHDIS. */
3629 #define BS_SIM_FCFG1_FLASHDIS (1U) /*!< Bit field size in bits for SIM_FCFG1_FLASHDIS. */
3631 /*! @brief Read current value of the SIM_FCFG1_FLASHDIS field. */
3632 #define BR_SIM_FCFG1_FLASHDIS(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS))
3634 /*! @brief Format value for bitfield SIM_FCFG1_FLASHDIS. */
3635 #define BF_SIM_FCFG1_FLASHDIS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDIS) & BM_SIM_FCFG1_FLASHDIS)
3637 /*! @brief Set the FLASHDIS field to a new value. */
3638 #define BW_SIM_FCFG1_FLASHDIS(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS) = (v))
3642 * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
3644 * When set, Flash memory is disabled for the duration of Wait mode. An attempt
3645 * by the DMA or other bus master to access the Flash when the Flash is disabled
3646 * will result in a bus error. This bit should be clear during VLP modes. The
3647 * Flash will be automatically enabled again at the end of Wait mode so interrupt
3648 * vectors do not need to be relocated out of Flash memory. The wakeup time from
3649 * Wait mode is extended when this bit is set.
3652 * - 0 - Flash remains enabled during Wait mode
3653 * - 1 - Flash is disabled for the duration of Wait mode
3656 #define BP_SIM_FCFG1_FLASHDOZE (1U) /*!< Bit position for SIM_FCFG1_FLASHDOZE. */
3657 #define BM_SIM_FCFG1_FLASHDOZE (0x00000002U) /*!< Bit mask for SIM_FCFG1_FLASHDOZE. */
3658 #define BS_SIM_FCFG1_FLASHDOZE (1U) /*!< Bit field size in bits for SIM_FCFG1_FLASHDOZE. */
3660 /*! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. */
3661 #define BR_SIM_FCFG1_FLASHDOZE(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE))
3663 /*! @brief Format value for bitfield SIM_FCFG1_FLASHDOZE. */
3664 #define BF_SIM_FCFG1_FLASHDOZE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDOZE) & BM_SIM_FCFG1_FLASHDOZE)
3666 /*! @brief Set the FLASHDOZE field to a new value. */
3667 #define BW_SIM_FCFG1_FLASHDOZE(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE) = (v))
3671 * @name Register SIM_FCFG1, field DEPART[11:8] (RO)
3673 * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
3674 * description in FTFE chapter. For devices without FlexNVM: Reserved
3677 #define BP_SIM_FCFG1_DEPART (8U) /*!< Bit position for SIM_FCFG1_DEPART. */
3678 #define BM_SIM_FCFG1_DEPART (0x00000F00U) /*!< Bit mask for SIM_FCFG1_DEPART. */
3679 #define BS_SIM_FCFG1_DEPART (4U) /*!< Bit field size in bits for SIM_FCFG1_DEPART. */
3681 /*! @brief Read current value of the SIM_FCFG1_DEPART field. */
3682 #define BR_SIM_FCFG1_DEPART(x) (HW_SIM_FCFG1(x).B.DEPART)
3686 * @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
3688 * EEPROM data size .
3696 * - 0101 - 512 Bytes
3697 * - 0110 - 256 Bytes
3698 * - 0111 - 128 Bytes
3704 #define BP_SIM_FCFG1_EESIZE (16U) /*!< Bit position for SIM_FCFG1_EESIZE. */
3705 #define BM_SIM_FCFG1_EESIZE (0x000F0000U) /*!< Bit mask for SIM_FCFG1_EESIZE. */
3706 #define BS_SIM_FCFG1_EESIZE (4U) /*!< Bit field size in bits for SIM_FCFG1_EESIZE. */
3708 /*! @brief Read current value of the SIM_FCFG1_EESIZE field. */
3709 #define BR_SIM_FCFG1_EESIZE(x) (HW_SIM_FCFG1(x).B.EESIZE)
3713 * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
3715 * This field specifies the amount of program flash memory available on the
3716 * device . Undefined values are reserved.
3719 * - 0011 - 32 KB of program flash memory
3720 * - 0101 - 64 KB of program flash memory
3721 * - 0111 - 128 KB of program flash memory
3722 * - 1001 - 256 KB of program flash memory
3723 * - 1011 - 512 KB of program flash memory
3724 * - 1101 - 1024 KB of program flash memory
3725 * - 1111 - 1024 KB of program flash memory
3728 #define BP_SIM_FCFG1_PFSIZE (24U) /*!< Bit position for SIM_FCFG1_PFSIZE. */
3729 #define BM_SIM_FCFG1_PFSIZE (0x0F000000U) /*!< Bit mask for SIM_FCFG1_PFSIZE. */
3730 #define BS_SIM_FCFG1_PFSIZE (4U) /*!< Bit field size in bits for SIM_FCFG1_PFSIZE. */
3732 /*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */
3733 #define BR_SIM_FCFG1_PFSIZE(x) (HW_SIM_FCFG1(x).B.PFSIZE)
3737 * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
3739 * This field specifies the amount of FlexNVM memory available on the device .
3740 * Undefined values are reserved.
3743 * - 0000 - 0 KB of FlexNVM
3744 * - 0011 - 32 KB of FlexNVM
3745 * - 0101 - 64 KB of FlexNVM
3746 * - 0111 - 128 KB of FlexNVM
3747 * - 1001 - 256 KB of FlexNVM
3748 * - 1011 - 512 KB of FlexNVM
3749 * - 1111 - 512 KB of FlexNVM
3752 #define BP_SIM_FCFG1_NVMSIZE (28U) /*!< Bit position for SIM_FCFG1_NVMSIZE. */
3753 #define BM_SIM_FCFG1_NVMSIZE (0xF0000000U) /*!< Bit mask for SIM_FCFG1_NVMSIZE. */
3754 #define BS_SIM_FCFG1_NVMSIZE (4U) /*!< Bit field size in bits for SIM_FCFG1_NVMSIZE. */
3756 /*! @brief Read current value of the SIM_FCFG1_NVMSIZE field. */
3757 #define BR_SIM_FCFG1_NVMSIZE(x) (HW_SIM_FCFG1(x).B.NVMSIZE)
3760 /*******************************************************************************
3761 * HW_SIM_FCFG2 - Flash Configuration Register 2
3762 ******************************************************************************/
3765 * @brief HW_SIM_FCFG2 - Flash Configuration Register 2 (RO)
3767 * Reset value: 0x7F7F0000U
3769 typedef union _hw_sim_fcfg2
3772 struct _hw_sim_fcfg2_bitfields
3774 uint32_t RESERVED0 : 16; /*!< [15:0] */
3775 uint32_t MAXADDR1 : 7; /*!< [22:16] Max address block 1 */
3776 uint32_t PFLSH : 1; /*!< [23] Program flash only */
3777 uint32_t MAXADDR0 : 7; /*!< [30:24] Max address block 0 */
3778 uint32_t RESERVED1 : 1; /*!< [31] */
3783 * @name Constants and macros for entire SIM_FCFG2 register
3786 #define HW_SIM_FCFG2_ADDR(x) ((x) + 0x1050U)
3788 #define HW_SIM_FCFG2(x) (*(__I hw_sim_fcfg2_t *) HW_SIM_FCFG2_ADDR(x))
3789 #define HW_SIM_FCFG2_RD(x) (HW_SIM_FCFG2(x).U)
3793 * Constants & macros for individual SIM_FCFG2 bitfields
3797 * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
3799 * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus
3800 * the FlexNVM base address indicates the first invalid address of the FlexNVM
3801 * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of
3802 * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value
3803 * for a device with 256 KB FlexNVM. For devices with program flash only: This
3804 * field equals zero if there is only one program flash block, otherwise it equals
3805 * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20
3806 * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be
3807 * the MAXADDR1 value for a device with 512 KB program flash memory across two
3808 * flash blocks and no FlexNVM.
3811 #define BP_SIM_FCFG2_MAXADDR1 (16U) /*!< Bit position for SIM_FCFG2_MAXADDR1. */
3812 #define BM_SIM_FCFG2_MAXADDR1 (0x007F0000U) /*!< Bit mask for SIM_FCFG2_MAXADDR1. */
3813 #define BS_SIM_FCFG2_MAXADDR1 (7U) /*!< Bit field size in bits for SIM_FCFG2_MAXADDR1. */
3815 /*! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. */
3816 #define BR_SIM_FCFG2_MAXADDR1(x) (HW_SIM_FCFG2(x).B.MAXADDR1)
3820 * @name Register SIM_FCFG2, field PFLSH[23] (RO)
3822 * For devices with FlexNVM, this bit is always clear. For devices without
3823 * FlexNVM, this bit is always set.
3826 * - 0 - Device supports FlexNVM
3827 * - 1 - Program Flash only, device does not support FlexNVM
3830 #define BP_SIM_FCFG2_PFLSH (23U) /*!< Bit position for SIM_FCFG2_PFLSH. */
3831 #define BM_SIM_FCFG2_PFLSH (0x00800000U) /*!< Bit mask for SIM_FCFG2_PFLSH. */
3832 #define BS_SIM_FCFG2_PFLSH (1U) /*!< Bit field size in bits for SIM_FCFG2_PFLSH. */
3834 /*! @brief Read current value of the SIM_FCFG2_PFLSH field. */
3835 #define BR_SIM_FCFG2_PFLSH(x) (BITBAND_ACCESS32(HW_SIM_FCFG2_ADDR(x), BP_SIM_FCFG2_PFLSH))
3839 * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
3841 * This field concatenated with 13 trailing zeros indicates the first invalid
3842 * address of each program flash block. For example, if MAXADDR0 = 0x20 the first
3843 * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
3844 * value for a device with 256 KB program flash in flash block 0.
3847 #define BP_SIM_FCFG2_MAXADDR0 (24U) /*!< Bit position for SIM_FCFG2_MAXADDR0. */
3848 #define BM_SIM_FCFG2_MAXADDR0 (0x7F000000U) /*!< Bit mask for SIM_FCFG2_MAXADDR0. */
3849 #define BS_SIM_FCFG2_MAXADDR0 (7U) /*!< Bit field size in bits for SIM_FCFG2_MAXADDR0. */
3851 /*! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. */
3852 #define BR_SIM_FCFG2_MAXADDR0(x) (HW_SIM_FCFG2(x).B.MAXADDR0)
3855 /*******************************************************************************
3856 * HW_SIM_UIDH - Unique Identification Register High
3857 ******************************************************************************/
3860 * @brief HW_SIM_UIDH - Unique Identification Register High (RO)
3862 * Reset value: 0x00000000U
3864 typedef union _hw_sim_uidh
3867 struct _hw_sim_uidh_bitfields
3869 uint32_t UID : 32; /*!< [31:0] Unique Identification */
3874 * @name Constants and macros for entire SIM_UIDH register
3877 #define HW_SIM_UIDH_ADDR(x) ((x) + 0x1054U)
3879 #define HW_SIM_UIDH(x) (*(__I hw_sim_uidh_t *) HW_SIM_UIDH_ADDR(x))
3880 #define HW_SIM_UIDH_RD(x) (HW_SIM_UIDH(x).U)
3884 * Constants & macros for individual SIM_UIDH bitfields
3888 * @name Register SIM_UIDH, field UID[31:0] (RO)
3890 * Unique identification for the device.
3893 #define BP_SIM_UIDH_UID (0U) /*!< Bit position for SIM_UIDH_UID. */
3894 #define BM_SIM_UIDH_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDH_UID. */
3895 #define BS_SIM_UIDH_UID (32U) /*!< Bit field size in bits for SIM_UIDH_UID. */
3897 /*! @brief Read current value of the SIM_UIDH_UID field. */
3898 #define BR_SIM_UIDH_UID(x) (HW_SIM_UIDH(x).U)
3901 /*******************************************************************************
3902 * HW_SIM_UIDMH - Unique Identification Register Mid-High
3903 ******************************************************************************/
3906 * @brief HW_SIM_UIDMH - Unique Identification Register Mid-High (RO)
3908 * Reset value: 0x00000000U
3910 typedef union _hw_sim_uidmh
3913 struct _hw_sim_uidmh_bitfields
3915 uint32_t UID : 32; /*!< [31:0] Unique Identification */
3920 * @name Constants and macros for entire SIM_UIDMH register
3923 #define HW_SIM_UIDMH_ADDR(x) ((x) + 0x1058U)
3925 #define HW_SIM_UIDMH(x) (*(__I hw_sim_uidmh_t *) HW_SIM_UIDMH_ADDR(x))
3926 #define HW_SIM_UIDMH_RD(x) (HW_SIM_UIDMH(x).U)
3930 * Constants & macros for individual SIM_UIDMH bitfields
3934 * @name Register SIM_UIDMH, field UID[31:0] (RO)
3936 * Unique identification for the device.
3939 #define BP_SIM_UIDMH_UID (0U) /*!< Bit position for SIM_UIDMH_UID. */
3940 #define BM_SIM_UIDMH_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDMH_UID. */
3941 #define BS_SIM_UIDMH_UID (32U) /*!< Bit field size in bits for SIM_UIDMH_UID. */
3943 /*! @brief Read current value of the SIM_UIDMH_UID field. */
3944 #define BR_SIM_UIDMH_UID(x) (HW_SIM_UIDMH(x).U)
3947 /*******************************************************************************
3948 * HW_SIM_UIDML - Unique Identification Register Mid Low
3949 ******************************************************************************/
3952 * @brief HW_SIM_UIDML - Unique Identification Register Mid Low (RO)
3954 * Reset value: 0x00000000U
3956 typedef union _hw_sim_uidml
3959 struct _hw_sim_uidml_bitfields
3961 uint32_t UID : 32; /*!< [31:0] Unique Identification */
3966 * @name Constants and macros for entire SIM_UIDML register
3969 #define HW_SIM_UIDML_ADDR(x) ((x) + 0x105CU)
3971 #define HW_SIM_UIDML(x) (*(__I hw_sim_uidml_t *) HW_SIM_UIDML_ADDR(x))
3972 #define HW_SIM_UIDML_RD(x) (HW_SIM_UIDML(x).U)
3976 * Constants & macros for individual SIM_UIDML bitfields
3980 * @name Register SIM_UIDML, field UID[31:0] (RO)
3982 * Unique identification for the device.
3985 #define BP_SIM_UIDML_UID (0U) /*!< Bit position for SIM_UIDML_UID. */
3986 #define BM_SIM_UIDML_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDML_UID. */
3987 #define BS_SIM_UIDML_UID (32U) /*!< Bit field size in bits for SIM_UIDML_UID. */
3989 /*! @brief Read current value of the SIM_UIDML_UID field. */
3990 #define BR_SIM_UIDML_UID(x) (HW_SIM_UIDML(x).U)
3993 /*******************************************************************************
3994 * HW_SIM_UIDL - Unique Identification Register Low
3995 ******************************************************************************/
3998 * @brief HW_SIM_UIDL - Unique Identification Register Low (RO)
4000 * Reset value: 0x00000000U
4002 typedef union _hw_sim_uidl
4005 struct _hw_sim_uidl_bitfields
4007 uint32_t UID : 32; /*!< [31:0] Unique Identification */
4012 * @name Constants and macros for entire SIM_UIDL register
4015 #define HW_SIM_UIDL_ADDR(x) ((x) + 0x1060U)
4017 #define HW_SIM_UIDL(x) (*(__I hw_sim_uidl_t *) HW_SIM_UIDL_ADDR(x))
4018 #define HW_SIM_UIDL_RD(x) (HW_SIM_UIDL(x).U)
4022 * Constants & macros for individual SIM_UIDL bitfields
4026 * @name Register SIM_UIDL, field UID[31:0] (RO)
4028 * Unique identification for the device.
4031 #define BP_SIM_UIDL_UID (0U) /*!< Bit position for SIM_UIDL_UID. */
4032 #define BM_SIM_UIDL_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDL_UID. */
4033 #define BS_SIM_UIDL_UID (32U) /*!< Bit field size in bits for SIM_UIDL_UID. */
4035 /*! @brief Read current value of the SIM_UIDL_UID field. */
4036 #define BR_SIM_UIDL_UID(x) (HW_SIM_UIDL(x).U)
4039 /*******************************************************************************
4040 * hw_sim_t - module struct
4041 ******************************************************************************/
4043 * @brief All SIM module registers.
4046 typedef struct _hw_sim
4048 __IO hw_sim_sopt1_t SOPT1; /*!< [0x0] System Options Register 1 */
4049 __IO hw_sim_sopt1cfg_t SOPT1CFG; /*!< [0x4] SOPT1 Configuration Register */
4050 uint8_t _reserved0[4092];
4051 __IO hw_sim_sopt2_t SOPT2; /*!< [0x1004] System Options Register 2 */
4052 uint8_t _reserved1[4];
4053 __IO hw_sim_sopt4_t SOPT4; /*!< [0x100C] System Options Register 4 */
4054 __IO hw_sim_sopt5_t SOPT5; /*!< [0x1010] System Options Register 5 */
4055 uint8_t _reserved2[4];
4056 __IO hw_sim_sopt7_t SOPT7; /*!< [0x1018] System Options Register 7 */
4057 uint8_t _reserved3[8];
4058 __I hw_sim_sdid_t SDID; /*!< [0x1024] System Device Identification Register */
4059 __IO hw_sim_scgc1_t SCGC1; /*!< [0x1028] System Clock Gating Control Register 1 */
4060 __IO hw_sim_scgc2_t SCGC2; /*!< [0x102C] System Clock Gating Control Register 2 */
4061 __IO hw_sim_scgc3_t SCGC3; /*!< [0x1030] System Clock Gating Control Register 3 */
4062 __IO hw_sim_scgc4_t SCGC4; /*!< [0x1034] System Clock Gating Control Register 4 */
4063 __IO hw_sim_scgc5_t SCGC5; /*!< [0x1038] System Clock Gating Control Register 5 */
4064 __IO hw_sim_scgc6_t SCGC6; /*!< [0x103C] System Clock Gating Control Register 6 */
4065 __IO hw_sim_scgc7_t SCGC7; /*!< [0x1040] System Clock Gating Control Register 7 */
4066 __IO hw_sim_clkdiv1_t CLKDIV1; /*!< [0x1044] System Clock Divider Register 1 */
4067 __IO hw_sim_clkdiv2_t CLKDIV2; /*!< [0x1048] System Clock Divider Register 2 */
4068 __IO hw_sim_fcfg1_t FCFG1; /*!< [0x104C] Flash Configuration Register 1 */
4069 __I hw_sim_fcfg2_t FCFG2; /*!< [0x1050] Flash Configuration Register 2 */
4070 __I hw_sim_uidh_t UIDH; /*!< [0x1054] Unique Identification Register High */
4071 __I hw_sim_uidmh_t UIDMH; /*!< [0x1058] Unique Identification Register Mid-High */
4072 __I hw_sim_uidml_t UIDML; /*!< [0x105C] Unique Identification Register Mid Low */
4073 __I hw_sim_uidl_t UIDL; /*!< [0x1060] Unique Identification Register Low */
4077 /*! @brief Macro to access all SIM registers. */
4078 /*! @param x SIM module instance base address. */
4079 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
4080 * use the '&' operator, like <code>&HW_SIM(SIM_BASE)</code>. */
4081 #define HW_SIM(x) (*(hw_sim_t *)(x))
4083 #endif /* __HW_SIM_REGISTERS_H__ */