2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_EWM_REGISTERS_H__
81 #define __HW_EWM_REGISTERS_H__
84 #include "fsl_bitaccess.h"
89 * External Watchdog Monitor
91 * Registers defined in this header file:
92 * - HW_EWM_CTRL - Control Register
93 * - HW_EWM_SERV - Service Register
94 * - HW_EWM_CMPL - Compare Low Register
95 * - HW_EWM_CMPH - Compare High Register
97 * - hw_ewm_t - Struct containing all module registers.
100 #define HW_EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */
102 /*******************************************************************************
103 * HW_EWM_CTRL - Control Register
104 ******************************************************************************/
107 * @brief HW_EWM_CTRL - Control Register (RW)
111 * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
112 * written once after a CPU reset. Modifying these bits more than once, generates
113 * a bus transfer error.
115 typedef union _hw_ewm_ctrl
118 struct _hw_ewm_ctrl_bitfields
120 uint8_t EWMEN : 1; /*!< [0] EWM enable. */
121 uint8_t ASSIN : 1; /*!< [1] EWM_in's Assertion State Select. */
122 uint8_t INEN : 1; /*!< [2] Input Enable. */
123 uint8_t INTEN : 1; /*!< [3] Interrupt Enable. */
124 uint8_t RESERVED0 : 4; /*!< [7:4] */
129 * @name Constants and macros for entire EWM_CTRL register
132 #define HW_EWM_CTRL_ADDR(x) ((x) + 0x0U)
134 #define HW_EWM_CTRL(x) (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR(x))
135 #define HW_EWM_CTRL_RD(x) (HW_EWM_CTRL(x).U)
136 #define HW_EWM_CTRL_WR(x, v) (HW_EWM_CTRL(x).U = (v))
137 #define HW_EWM_CTRL_SET(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) | (v)))
138 #define HW_EWM_CTRL_CLR(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) & ~(v)))
139 #define HW_EWM_CTRL_TOG(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) ^ (v)))
143 * Constants & macros for individual EWM_CTRL bitfields
147 * @name Register EWM_CTRL, field EWMEN[0] (RW)
149 * This bit when set, enables the EWM module. This resets the EWM counter to
150 * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
151 * therefore it cannot be enabled until a reset occurs, due to the write-once
152 * nature of this bit.
155 #define BP_EWM_CTRL_EWMEN (0U) /*!< Bit position for EWM_CTRL_EWMEN. */
156 #define BM_EWM_CTRL_EWMEN (0x01U) /*!< Bit mask for EWM_CTRL_EWMEN. */
157 #define BS_EWM_CTRL_EWMEN (1U) /*!< Bit field size in bits for EWM_CTRL_EWMEN. */
159 /*! @brief Read current value of the EWM_CTRL_EWMEN field. */
160 #define BR_EWM_CTRL_EWMEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN))
162 /*! @brief Format value for bitfield EWM_CTRL_EWMEN. */
163 #define BF_EWM_CTRL_EWMEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_EWMEN) & BM_EWM_CTRL_EWMEN)
165 /*! @brief Set the EWMEN field to a new value. */
166 #define BW_EWM_CTRL_EWMEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN) = (v))
170 * @name Register EWM_CTRL, field ASSIN[1] (RW)
172 * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
173 * inverts the assert state to a logic one.
176 #define BP_EWM_CTRL_ASSIN (1U) /*!< Bit position for EWM_CTRL_ASSIN. */
177 #define BM_EWM_CTRL_ASSIN (0x02U) /*!< Bit mask for EWM_CTRL_ASSIN. */
178 #define BS_EWM_CTRL_ASSIN (1U) /*!< Bit field size in bits for EWM_CTRL_ASSIN. */
180 /*! @brief Read current value of the EWM_CTRL_ASSIN field. */
181 #define BR_EWM_CTRL_ASSIN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN))
183 /*! @brief Format value for bitfield EWM_CTRL_ASSIN. */
184 #define BF_EWM_CTRL_ASSIN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_ASSIN) & BM_EWM_CTRL_ASSIN)
186 /*! @brief Set the ASSIN field to a new value. */
187 #define BW_EWM_CTRL_ASSIN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN) = (v))
191 * @name Register EWM_CTRL, field INEN[2] (RW)
193 * This bit when set, enables the EWM_in port.
196 #define BP_EWM_CTRL_INEN (2U) /*!< Bit position for EWM_CTRL_INEN. */
197 #define BM_EWM_CTRL_INEN (0x04U) /*!< Bit mask for EWM_CTRL_INEN. */
198 #define BS_EWM_CTRL_INEN (1U) /*!< Bit field size in bits for EWM_CTRL_INEN. */
200 /*! @brief Read current value of the EWM_CTRL_INEN field. */
201 #define BR_EWM_CTRL_INEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN))
203 /*! @brief Format value for bitfield EWM_CTRL_INEN. */
204 #define BF_EWM_CTRL_INEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INEN) & BM_EWM_CTRL_INEN)
206 /*! @brief Set the INEN field to a new value. */
207 #define BW_EWM_CTRL_INEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN) = (v))
211 * @name Register EWM_CTRL, field INTEN[3] (RW)
213 * This bit when set and EWM_out is asserted, an interrupt request is generated.
214 * To de-assert interrupt request, user should clear this bit by writing 0.
217 #define BP_EWM_CTRL_INTEN (3U) /*!< Bit position for EWM_CTRL_INTEN. */
218 #define BM_EWM_CTRL_INTEN (0x08U) /*!< Bit mask for EWM_CTRL_INTEN. */
219 #define BS_EWM_CTRL_INTEN (1U) /*!< Bit field size in bits for EWM_CTRL_INTEN. */
221 /*! @brief Read current value of the EWM_CTRL_INTEN field. */
222 #define BR_EWM_CTRL_INTEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN))
224 /*! @brief Format value for bitfield EWM_CTRL_INTEN. */
225 #define BF_EWM_CTRL_INTEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INTEN) & BM_EWM_CTRL_INTEN)
227 /*! @brief Set the INTEN field to a new value. */
228 #define BW_EWM_CTRL_INTEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN) = (v))
231 /*******************************************************************************
232 * HW_EWM_SERV - Service Register
233 ******************************************************************************/
236 * @brief HW_EWM_SERV - Service Register (WORZ)
240 * The SERV register provides the interface from the CPU to the EWM module. It
241 * is write-only and reads of this register return zero.
243 typedef union _hw_ewm_serv
246 struct _hw_ewm_serv_bitfields
248 uint8_t SERVICE : 8; /*!< [7:0] */
253 * @name Constants and macros for entire EWM_SERV register
256 #define HW_EWM_SERV_ADDR(x) ((x) + 0x1U)
258 #define HW_EWM_SERV(x) (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR(x))
259 #define HW_EWM_SERV_RD(x) (HW_EWM_SERV(x).U)
260 #define HW_EWM_SERV_WR(x, v) (HW_EWM_SERV(x).U = (v))
264 * Constants & macros for individual EWM_SERV bitfields
268 * @name Register EWM_SERV, field SERVICE[7:0] (WORZ)
270 * The EWM service mechanism requires the CPU to write two values to the SERV
271 * register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The
272 * EWM service is illegal if either of the following conditions is true. The
273 * first or second data byte is not written correctly. The second data byte is not
274 * written within a fixed number of peripheral bus cycles of the first data byte.
275 * This fixed number of cycles is called EWM_service_time.
278 #define BP_EWM_SERV_SERVICE (0U) /*!< Bit position for EWM_SERV_SERVICE. */
279 #define BM_EWM_SERV_SERVICE (0xFFU) /*!< Bit mask for EWM_SERV_SERVICE. */
280 #define BS_EWM_SERV_SERVICE (8U) /*!< Bit field size in bits for EWM_SERV_SERVICE. */
282 /*! @brief Format value for bitfield EWM_SERV_SERVICE. */
283 #define BF_EWM_SERV_SERVICE(v) ((uint8_t)((uint8_t)(v) << BP_EWM_SERV_SERVICE) & BM_EWM_SERV_SERVICE)
285 /*! @brief Set the SERVICE field to a new value. */
286 #define BW_EWM_SERV_SERVICE(x, v) (HW_EWM_SERV_WR(x, v))
289 /*******************************************************************************
290 * HW_EWM_CMPL - Compare Low Register
291 ******************************************************************************/
294 * @brief HW_EWM_CMPL - Compare Low Register (RW)
298 * The CMPL register is reset to zero after a CPU reset. This provides no
299 * minimum time for the CPU to service the EWM counter. This register can be written
300 * only once after a CPU reset. Writing this register more than once generates a
301 * bus transfer error.
303 typedef union _hw_ewm_cmpl
306 struct _hw_ewm_cmpl_bitfields
308 uint8_t COMPAREL : 8; /*!< [7:0] */
313 * @name Constants and macros for entire EWM_CMPL register
316 #define HW_EWM_CMPL_ADDR(x) ((x) + 0x2U)
318 #define HW_EWM_CMPL(x) (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR(x))
319 #define HW_EWM_CMPL_RD(x) (HW_EWM_CMPL(x).U)
320 #define HW_EWM_CMPL_WR(x, v) (HW_EWM_CMPL(x).U = (v))
321 #define HW_EWM_CMPL_SET(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) | (v)))
322 #define HW_EWM_CMPL_CLR(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) & ~(v)))
323 #define HW_EWM_CMPL_TOG(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) ^ (v)))
327 * Constants & macros for individual EWM_CMPL bitfields
331 * @name Register EWM_CMPL, field COMPAREL[7:0] (RW)
333 * To prevent runaway code from changing this field, software should write to
334 * this field after a CPU reset even if the (default) minimum service time is
338 #define BP_EWM_CMPL_COMPAREL (0U) /*!< Bit position for EWM_CMPL_COMPAREL. */
339 #define BM_EWM_CMPL_COMPAREL (0xFFU) /*!< Bit mask for EWM_CMPL_COMPAREL. */
340 #define BS_EWM_CMPL_COMPAREL (8U) /*!< Bit field size in bits for EWM_CMPL_COMPAREL. */
342 /*! @brief Read current value of the EWM_CMPL_COMPAREL field. */
343 #define BR_EWM_CMPL_COMPAREL(x) (HW_EWM_CMPL(x).U)
345 /*! @brief Format value for bitfield EWM_CMPL_COMPAREL. */
346 #define BF_EWM_CMPL_COMPAREL(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPL_COMPAREL) & BM_EWM_CMPL_COMPAREL)
348 /*! @brief Set the COMPAREL field to a new value. */
349 #define BW_EWM_CMPL_COMPAREL(x, v) (HW_EWM_CMPL_WR(x, v))
352 /*******************************************************************************
353 * HW_EWM_CMPH - Compare High Register
354 ******************************************************************************/
357 * @brief HW_EWM_CMPH - Compare High Register (RW)
361 * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
362 * of 256 clocks time, for the CPU to service the EWM counter. This register can
363 * be written only once after a CPU reset. Writing this register more than once
364 * generates a bus transfer error. The valid values for CMPH are up to 0xFE
365 * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
366 * if EWM counter is greater than CMPH.
368 typedef union _hw_ewm_cmph
371 struct _hw_ewm_cmph_bitfields
373 uint8_t COMPAREH : 8; /*!< [7:0] */
378 * @name Constants and macros for entire EWM_CMPH register
381 #define HW_EWM_CMPH_ADDR(x) ((x) + 0x3U)
383 #define HW_EWM_CMPH(x) (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR(x))
384 #define HW_EWM_CMPH_RD(x) (HW_EWM_CMPH(x).U)
385 #define HW_EWM_CMPH_WR(x, v) (HW_EWM_CMPH(x).U = (v))
386 #define HW_EWM_CMPH_SET(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) | (v)))
387 #define HW_EWM_CMPH_CLR(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) & ~(v)))
388 #define HW_EWM_CMPH_TOG(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) ^ (v)))
392 * Constants & macros for individual EWM_CMPH bitfields
396 * @name Register EWM_CMPH, field COMPAREH[7:0] (RW)
398 * To prevent runaway code from changing this field, software should write to
399 * this field after a CPU reset even if the (default) maximum service time is
403 #define BP_EWM_CMPH_COMPAREH (0U) /*!< Bit position for EWM_CMPH_COMPAREH. */
404 #define BM_EWM_CMPH_COMPAREH (0xFFU) /*!< Bit mask for EWM_CMPH_COMPAREH. */
405 #define BS_EWM_CMPH_COMPAREH (8U) /*!< Bit field size in bits for EWM_CMPH_COMPAREH. */
407 /*! @brief Read current value of the EWM_CMPH_COMPAREH field. */
408 #define BR_EWM_CMPH_COMPAREH(x) (HW_EWM_CMPH(x).U)
410 /*! @brief Format value for bitfield EWM_CMPH_COMPAREH. */
411 #define BF_EWM_CMPH_COMPAREH(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPH_COMPAREH) & BM_EWM_CMPH_COMPAREH)
413 /*! @brief Set the COMPAREH field to a new value. */
414 #define BW_EWM_CMPH_COMPAREH(x, v) (HW_EWM_CMPH_WR(x, v))
417 /*******************************************************************************
418 * hw_ewm_t - module struct
419 ******************************************************************************/
421 * @brief All EWM module registers.
424 typedef struct _hw_ewm
426 __IO hw_ewm_ctrl_t CTRL; /*!< [0x0] Control Register */
427 __O hw_ewm_serv_t SERV; /*!< [0x1] Service Register */
428 __IO hw_ewm_cmpl_t CMPL; /*!< [0x2] Compare Low Register */
429 __IO hw_ewm_cmph_t CMPH; /*!< [0x3] Compare High Register */
433 /*! @brief Macro to access all EWM registers. */
434 /*! @param x EWM module instance base address. */
435 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
436 * use the '&' operator, like <code>&HW_EWM(EWM_BASE)</code>. */
437 #define HW_EWM(x) (*(hw_ewm_t *)(x))
439 #endif /* __HW_EWM_REGISTERS_H__ */