2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_ENET_REGISTERS_H__
81 #define __HW_ENET_REGISTERS_H__
84 #include "fsl_bitaccess.h"
89 * Ethernet MAC-NET Core
91 * Registers defined in this header file:
92 * - HW_ENET_EIR - Interrupt Event Register
93 * - HW_ENET_EIMR - Interrupt Mask Register
94 * - HW_ENET_RDAR - Receive Descriptor Active Register
95 * - HW_ENET_TDAR - Transmit Descriptor Active Register
96 * - HW_ENET_ECR - Ethernet Control Register
97 * - HW_ENET_MMFR - MII Management Frame Register
98 * - HW_ENET_MSCR - MII Speed Control Register
99 * - HW_ENET_MIBC - MIB Control Register
100 * - HW_ENET_RCR - Receive Control Register
101 * - HW_ENET_TCR - Transmit Control Register
102 * - HW_ENET_PALR - Physical Address Lower Register
103 * - HW_ENET_PAUR - Physical Address Upper Register
104 * - HW_ENET_OPD - Opcode/Pause Duration Register
105 * - HW_ENET_IAUR - Descriptor Individual Upper Address Register
106 * - HW_ENET_IALR - Descriptor Individual Lower Address Register
107 * - HW_ENET_GAUR - Descriptor Group Upper Address Register
108 * - HW_ENET_GALR - Descriptor Group Lower Address Register
109 * - HW_ENET_TFWR - Transmit FIFO Watermark Register
110 * - HW_ENET_RDSR - Receive Descriptor Ring Start Register
111 * - HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
112 * - HW_ENET_MRBR - Maximum Receive Buffer Size Register
113 * - HW_ENET_RSFL - Receive FIFO Section Full Threshold
114 * - HW_ENET_RSEM - Receive FIFO Section Empty Threshold
115 * - HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
116 * - HW_ENET_RAFL - Receive FIFO Almost Full Threshold
117 * - HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
118 * - HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
119 * - HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
120 * - HW_ENET_TIPG - Transmit Inter-Packet Gap
121 * - HW_ENET_FTRL - Frame Truncation Length
122 * - HW_ENET_TACC - Transmit Accelerator Function Configuration
123 * - HW_ENET_RACC - Receive Accelerator Function Configuration
124 * - HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
125 * - HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
126 * - HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
127 * - HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
128 * - HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
129 * - HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
130 * - HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
131 * - HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
132 * - HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
133 * - HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
134 * - HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
135 * - HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
136 * - HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
137 * - HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
138 * - HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
139 * - HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
140 * - HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
141 * - HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
142 * - HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
143 * - HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
144 * - HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
145 * - HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
146 * - HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
147 * - HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
148 * - HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
149 * - HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
150 * - HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
151 * - HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
152 * - HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
153 * - HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
154 * - HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
155 * - HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
156 * - HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
157 * - HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
158 * - HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
159 * - HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
160 * - HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
161 * - HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
162 * - HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
163 * - HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
164 * - HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
165 * - HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
166 * - HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
167 * - HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
168 * - HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
169 * - HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
170 * - HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
171 * - HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
172 * - HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
173 * - HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
174 * - HW_ENET_ATCR - Adjustable Timer Control Register
175 * - HW_ENET_ATVR - Timer Value Register
176 * - HW_ENET_ATOFF - Timer Offset Register
177 * - HW_ENET_ATPER - Timer Period Register
178 * - HW_ENET_ATCOR - Timer Correction Register
179 * - HW_ENET_ATINC - Time-Stamping Clock Period Register
180 * - HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
181 * - HW_ENET_TGSR - Timer Global Status Register
182 * - HW_ENET_TCSRn - Timer Control Status Register
183 * - HW_ENET_TCCRn - Timer Compare Capture Register
185 * - hw_enet_t - Struct containing all module registers.
188 #define HW_ENET_INSTANCE_COUNT (1U) /*!< Number of instances of the ENET module. */
190 /*******************************************************************************
191 * HW_ENET_EIR - Interrupt Event Register
192 ******************************************************************************/
195 * @brief HW_ENET_EIR - Interrupt Event Register (RW)
197 * Reset value: 0x00000000U
199 * When an event occurs that sets a bit in EIR, an interrupt occurs if the
200 * corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
201 * an EIR bit clears it; writing 0 has no effect. This register is cleared upon
202 * hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
203 * corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
204 * Legacy mode does not require these flags to be enabled.
206 typedef union _hw_enet_eir
209 struct _hw_enet_eir_bitfields
211 uint32_t RESERVED0 : 15; /*!< [14:0] */
212 uint32_t TS_TIMER : 1; /*!< [15] Timestamp Timer */
213 uint32_t TS_AVAIL : 1; /*!< [16] Transmit Timestamp Available */
214 uint32_t WAKEUP : 1; /*!< [17] Node Wakeup Request Indication */
215 uint32_t PLR : 1; /*!< [18] Payload Receive Error */
216 uint32_t UN : 1; /*!< [19] Transmit FIFO Underrun */
217 uint32_t RL : 1; /*!< [20] Collision Retry Limit */
218 uint32_t LC : 1; /*!< [21] Late Collision */
219 uint32_t EBERR : 1; /*!< [22] Ethernet Bus Error */
220 uint32_t MII : 1; /*!< [23] MII Interrupt. */
221 uint32_t RXB : 1; /*!< [24] Receive Buffer Interrupt */
222 uint32_t RXF : 1; /*!< [25] Receive Frame Interrupt */
223 uint32_t TXB : 1; /*!< [26] Transmit Buffer Interrupt */
224 uint32_t TXF : 1; /*!< [27] Transmit Frame Interrupt */
225 uint32_t GRA : 1; /*!< [28] Graceful Stop Complete */
226 uint32_t BABT : 1; /*!< [29] Babbling Transmit Error */
227 uint32_t BABR : 1; /*!< [30] Babbling Receive Error */
228 uint32_t RESERVED1 : 1; /*!< [31] */
233 * @name Constants and macros for entire ENET_EIR register
236 #define HW_ENET_EIR_ADDR(x) ((x) + 0x4U)
238 #define HW_ENET_EIR(x) (*(__IO hw_enet_eir_t *) HW_ENET_EIR_ADDR(x))
239 #define HW_ENET_EIR_RD(x) (HW_ENET_EIR(x).U)
240 #define HW_ENET_EIR_WR(x, v) (HW_ENET_EIR(x).U = (v))
241 #define HW_ENET_EIR_SET(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) | (v)))
242 #define HW_ENET_EIR_CLR(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) & ~(v)))
243 #define HW_ENET_EIR_TOG(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) ^ (v)))
247 * Constants & macros for individual ENET_EIR bitfields
251 * @name Register ENET_EIR, field TS_TIMER[15] (W1C)
253 * The adjustable timer reached the period event. A period event interrupt can
254 * be generated if ATCR[PEREN] is set and the timer wraps according to the
255 * periodic setting in the ATPER register. Set the timer period value before setting
259 #define BP_ENET_EIR_TS_TIMER (15U) /*!< Bit position for ENET_EIR_TS_TIMER. */
260 #define BM_ENET_EIR_TS_TIMER (0x00008000U) /*!< Bit mask for ENET_EIR_TS_TIMER. */
261 #define BS_ENET_EIR_TS_TIMER (1U) /*!< Bit field size in bits for ENET_EIR_TS_TIMER. */
263 /*! @brief Read current value of the ENET_EIR_TS_TIMER field. */
264 #define BR_ENET_EIR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER))
266 /*! @brief Format value for bitfield ENET_EIR_TS_TIMER. */
267 #define BF_ENET_EIR_TS_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TS_TIMER) & BM_ENET_EIR_TS_TIMER)
269 /*! @brief Set the TS_TIMER field to a new value. */
270 #define BW_ENET_EIR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER) = (v))
274 * @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
276 * Indicates that the timestamp of the last transmitted timing frame is
277 * available in the ATSTMP register.
280 #define BP_ENET_EIR_TS_AVAIL (16U) /*!< Bit position for ENET_EIR_TS_AVAIL. */
281 #define BM_ENET_EIR_TS_AVAIL (0x00010000U) /*!< Bit mask for ENET_EIR_TS_AVAIL. */
282 #define BS_ENET_EIR_TS_AVAIL (1U) /*!< Bit field size in bits for ENET_EIR_TS_AVAIL. */
284 /*! @brief Read current value of the ENET_EIR_TS_AVAIL field. */
285 #define BR_ENET_EIR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL))
287 /*! @brief Format value for bitfield ENET_EIR_TS_AVAIL. */
288 #define BF_ENET_EIR_TS_AVAIL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TS_AVAIL) & BM_ENET_EIR_TS_AVAIL)
290 /*! @brief Set the TS_AVAIL field to a new value. */
291 #define BW_ENET_EIR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL) = (v))
295 * @name Register ENET_EIR, field WAKEUP[17] (W1C)
297 * Read-only status bit to indicate that a magic packet has been detected. Will
298 * act only if ECR[MAGICEN] is set.
301 #define BP_ENET_EIR_WAKEUP (17U) /*!< Bit position for ENET_EIR_WAKEUP. */
302 #define BM_ENET_EIR_WAKEUP (0x00020000U) /*!< Bit mask for ENET_EIR_WAKEUP. */
303 #define BS_ENET_EIR_WAKEUP (1U) /*!< Bit field size in bits for ENET_EIR_WAKEUP. */
305 /*! @brief Read current value of the ENET_EIR_WAKEUP field. */
306 #define BR_ENET_EIR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP))
308 /*! @brief Format value for bitfield ENET_EIR_WAKEUP. */
309 #define BF_ENET_EIR_WAKEUP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_WAKEUP) & BM_ENET_EIR_WAKEUP)
311 /*! @brief Set the WAKEUP field to a new value. */
312 #define BW_ENET_EIR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP) = (v))
316 * @name Register ENET_EIR, field PLR[18] (W1C)
318 * Indicates a frame was received with a payload length error. See Frame
319 * Length/Type Verification: Payload Length Check for more information.
322 #define BP_ENET_EIR_PLR (18U) /*!< Bit position for ENET_EIR_PLR. */
323 #define BM_ENET_EIR_PLR (0x00040000U) /*!< Bit mask for ENET_EIR_PLR. */
324 #define BS_ENET_EIR_PLR (1U) /*!< Bit field size in bits for ENET_EIR_PLR. */
326 /*! @brief Read current value of the ENET_EIR_PLR field. */
327 #define BR_ENET_EIR_PLR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR))
329 /*! @brief Format value for bitfield ENET_EIR_PLR. */
330 #define BF_ENET_EIR_PLR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_PLR) & BM_ENET_EIR_PLR)
332 /*! @brief Set the PLR field to a new value. */
333 #define BW_ENET_EIR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR) = (v))
337 * @name Register ENET_EIR, field UN[19] (W1C)
339 * Indicates the transmit FIFO became empty before the complete frame was
340 * transmitted. A bad CRC is appended to the frame fragment and the remainder of the
341 * frame is discarded.
344 #define BP_ENET_EIR_UN (19U) /*!< Bit position for ENET_EIR_UN. */
345 #define BM_ENET_EIR_UN (0x00080000U) /*!< Bit mask for ENET_EIR_UN. */
346 #define BS_ENET_EIR_UN (1U) /*!< Bit field size in bits for ENET_EIR_UN. */
348 /*! @brief Read current value of the ENET_EIR_UN field. */
349 #define BR_ENET_EIR_UN(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN))
351 /*! @brief Format value for bitfield ENET_EIR_UN. */
352 #define BF_ENET_EIR_UN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_UN) & BM_ENET_EIR_UN)
354 /*! @brief Set the UN field to a new value. */
355 #define BW_ENET_EIR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN) = (v))
359 * @name Register ENET_EIR, field RL[20] (W1C)
361 * Indicates a collision occurred on each of 16 successive attempts to transmit
362 * the frame. The frame is discarded without being transmitted and transmission
363 * of the next frame commences. This error can only occur in half-duplex mode.
366 #define BP_ENET_EIR_RL (20U) /*!< Bit position for ENET_EIR_RL. */
367 #define BM_ENET_EIR_RL (0x00100000U) /*!< Bit mask for ENET_EIR_RL. */
368 #define BS_ENET_EIR_RL (1U) /*!< Bit field size in bits for ENET_EIR_RL. */
370 /*! @brief Read current value of the ENET_EIR_RL field. */
371 #define BR_ENET_EIR_RL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL))
373 /*! @brief Format value for bitfield ENET_EIR_RL. */
374 #define BF_ENET_EIR_RL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RL) & BM_ENET_EIR_RL)
376 /*! @brief Set the RL field to a new value. */
377 #define BW_ENET_EIR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL) = (v))
381 * @name Register ENET_EIR, field LC[21] (W1C)
383 * Indicates a collision occurred beyond the collision window (slot time) in
384 * half-duplex mode. The frame truncates with a bad CRC and the remainder of the
385 * frame is discarded.
388 #define BP_ENET_EIR_LC (21U) /*!< Bit position for ENET_EIR_LC. */
389 #define BM_ENET_EIR_LC (0x00200000U) /*!< Bit mask for ENET_EIR_LC. */
390 #define BS_ENET_EIR_LC (1U) /*!< Bit field size in bits for ENET_EIR_LC. */
392 /*! @brief Read current value of the ENET_EIR_LC field. */
393 #define BR_ENET_EIR_LC(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC))
395 /*! @brief Format value for bitfield ENET_EIR_LC. */
396 #define BF_ENET_EIR_LC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_LC) & BM_ENET_EIR_LC)
398 /*! @brief Set the LC field to a new value. */
399 #define BW_ENET_EIR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC) = (v))
403 * @name Register ENET_EIR, field EBERR[22] (W1C)
405 * Indicates a system bus error occurred when a uDMA transaction is underway.
406 * When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
407 * MAC. When this occurs, software must ensure proper actions, possibly resetting
408 * the system, to resume normal operation.
411 #define BP_ENET_EIR_EBERR (22U) /*!< Bit position for ENET_EIR_EBERR. */
412 #define BM_ENET_EIR_EBERR (0x00400000U) /*!< Bit mask for ENET_EIR_EBERR. */
413 #define BS_ENET_EIR_EBERR (1U) /*!< Bit field size in bits for ENET_EIR_EBERR. */
415 /*! @brief Read current value of the ENET_EIR_EBERR field. */
416 #define BR_ENET_EIR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR))
418 /*! @brief Format value for bitfield ENET_EIR_EBERR. */
419 #define BF_ENET_EIR_EBERR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_EBERR) & BM_ENET_EIR_EBERR)
421 /*! @brief Set the EBERR field to a new value. */
422 #define BW_ENET_EIR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR) = (v))
426 * @name Register ENET_EIR, field MII[23] (W1C)
428 * Indicates that the MII has completed the data transfer requested.
431 #define BP_ENET_EIR_MII (23U) /*!< Bit position for ENET_EIR_MII. */
432 #define BM_ENET_EIR_MII (0x00800000U) /*!< Bit mask for ENET_EIR_MII. */
433 #define BS_ENET_EIR_MII (1U) /*!< Bit field size in bits for ENET_EIR_MII. */
435 /*! @brief Read current value of the ENET_EIR_MII field. */
436 #define BR_ENET_EIR_MII(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII))
438 /*! @brief Format value for bitfield ENET_EIR_MII. */
439 #define BF_ENET_EIR_MII(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_MII) & BM_ENET_EIR_MII)
441 /*! @brief Set the MII field to a new value. */
442 #define BW_ENET_EIR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII) = (v))
446 * @name Register ENET_EIR, field RXB[24] (W1C)
448 * Indicates a receive buffer descriptor is not the last in the frame has been
452 #define BP_ENET_EIR_RXB (24U) /*!< Bit position for ENET_EIR_RXB. */
453 #define BM_ENET_EIR_RXB (0x01000000U) /*!< Bit mask for ENET_EIR_RXB. */
454 #define BS_ENET_EIR_RXB (1U) /*!< Bit field size in bits for ENET_EIR_RXB. */
456 /*! @brief Read current value of the ENET_EIR_RXB field. */
457 #define BR_ENET_EIR_RXB(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB))
459 /*! @brief Format value for bitfield ENET_EIR_RXB. */
460 #define BF_ENET_EIR_RXB(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RXB) & BM_ENET_EIR_RXB)
462 /*! @brief Set the RXB field to a new value. */
463 #define BW_ENET_EIR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB) = (v))
467 * @name Register ENET_EIR, field RXF[25] (W1C)
469 * Indicates a frame has been received and the last corresponding buffer
470 * descriptor has been updated.
473 #define BP_ENET_EIR_RXF (25U) /*!< Bit position for ENET_EIR_RXF. */
474 #define BM_ENET_EIR_RXF (0x02000000U) /*!< Bit mask for ENET_EIR_RXF. */
475 #define BS_ENET_EIR_RXF (1U) /*!< Bit field size in bits for ENET_EIR_RXF. */
477 /*! @brief Read current value of the ENET_EIR_RXF field. */
478 #define BR_ENET_EIR_RXF(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF))
480 /*! @brief Format value for bitfield ENET_EIR_RXF. */
481 #define BF_ENET_EIR_RXF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RXF) & BM_ENET_EIR_RXF)
483 /*! @brief Set the RXF field to a new value. */
484 #define BW_ENET_EIR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF) = (v))
488 * @name Register ENET_EIR, field TXB[26] (W1C)
490 * Indicates a transmit buffer descriptor has been updated.
493 #define BP_ENET_EIR_TXB (26U) /*!< Bit position for ENET_EIR_TXB. */
494 #define BM_ENET_EIR_TXB (0x04000000U) /*!< Bit mask for ENET_EIR_TXB. */
495 #define BS_ENET_EIR_TXB (1U) /*!< Bit field size in bits for ENET_EIR_TXB. */
497 /*! @brief Read current value of the ENET_EIR_TXB field. */
498 #define BR_ENET_EIR_TXB(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB))
500 /*! @brief Format value for bitfield ENET_EIR_TXB. */
501 #define BF_ENET_EIR_TXB(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TXB) & BM_ENET_EIR_TXB)
503 /*! @brief Set the TXB field to a new value. */
504 #define BW_ENET_EIR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB) = (v))
508 * @name Register ENET_EIR, field TXF[27] (W1C)
510 * Indicates a frame has been transmitted and the last corresponding buffer
511 * descriptor has been updated.
514 #define BP_ENET_EIR_TXF (27U) /*!< Bit position for ENET_EIR_TXF. */
515 #define BM_ENET_EIR_TXF (0x08000000U) /*!< Bit mask for ENET_EIR_TXF. */
516 #define BS_ENET_EIR_TXF (1U) /*!< Bit field size in bits for ENET_EIR_TXF. */
518 /*! @brief Read current value of the ENET_EIR_TXF field. */
519 #define BR_ENET_EIR_TXF(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF))
521 /*! @brief Format value for bitfield ENET_EIR_TXF. */
522 #define BF_ENET_EIR_TXF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TXF) & BM_ENET_EIR_TXF)
524 /*! @brief Set the TXF field to a new value. */
525 #define BW_ENET_EIR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF) = (v))
529 * @name Register ENET_EIR, field GRA[28] (W1C)
531 * This interrupt is asserted after the transmitter is put into a pause state
532 * after completion of the frame currently being transmitted. See Graceful Transmit
533 * Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
534 * asserted only when the TX transitions into the stopped state. If this bit is
535 * cleared by writing 1 and the TX is still stopped, the bit is not set again.
538 #define BP_ENET_EIR_GRA (28U) /*!< Bit position for ENET_EIR_GRA. */
539 #define BM_ENET_EIR_GRA (0x10000000U) /*!< Bit mask for ENET_EIR_GRA. */
540 #define BS_ENET_EIR_GRA (1U) /*!< Bit field size in bits for ENET_EIR_GRA. */
542 /*! @brief Read current value of the ENET_EIR_GRA field. */
543 #define BR_ENET_EIR_GRA(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA))
545 /*! @brief Format value for bitfield ENET_EIR_GRA. */
546 #define BF_ENET_EIR_GRA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_GRA) & BM_ENET_EIR_GRA)
548 /*! @brief Set the GRA field to a new value. */
549 #define BW_ENET_EIR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA) = (v))
553 * @name Register ENET_EIR, field BABT[29] (W1C)
555 * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
556 * this condition is caused when a frame that is too long is placed into the
557 * transmit data buffer(s). Truncation does not occur.
560 #define BP_ENET_EIR_BABT (29U) /*!< Bit position for ENET_EIR_BABT. */
561 #define BM_ENET_EIR_BABT (0x20000000U) /*!< Bit mask for ENET_EIR_BABT. */
562 #define BS_ENET_EIR_BABT (1U) /*!< Bit field size in bits for ENET_EIR_BABT. */
564 /*! @brief Read current value of the ENET_EIR_BABT field. */
565 #define BR_ENET_EIR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT))
567 /*! @brief Format value for bitfield ENET_EIR_BABT. */
568 #define BF_ENET_EIR_BABT(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_BABT) & BM_ENET_EIR_BABT)
570 /*! @brief Set the BABT field to a new value. */
571 #define BW_ENET_EIR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT) = (v))
575 * @name Register ENET_EIR, field BABR[30] (W1C)
577 * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
580 #define BP_ENET_EIR_BABR (30U) /*!< Bit position for ENET_EIR_BABR. */
581 #define BM_ENET_EIR_BABR (0x40000000U) /*!< Bit mask for ENET_EIR_BABR. */
582 #define BS_ENET_EIR_BABR (1U) /*!< Bit field size in bits for ENET_EIR_BABR. */
584 /*! @brief Read current value of the ENET_EIR_BABR field. */
585 #define BR_ENET_EIR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR))
587 /*! @brief Format value for bitfield ENET_EIR_BABR. */
588 #define BF_ENET_EIR_BABR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_BABR) & BM_ENET_EIR_BABR)
590 /*! @brief Set the BABR field to a new value. */
591 #define BW_ENET_EIR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR) = (v))
594 /*******************************************************************************
595 * HW_ENET_EIMR - Interrupt Mask Register
596 ******************************************************************************/
599 * @brief HW_ENET_EIMR - Interrupt Mask Register (RW)
601 * Reset value: 0x00000000U
603 * EIMR controls which interrupt events are allowed to generate actual
604 * interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
605 * and EIMR registers are set, an interrupt is generated. The interrupt signal
606 * remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
607 * 0 is written to the EIMR field.
609 typedef union _hw_enet_eimr
612 struct _hw_enet_eimr_bitfields
614 uint32_t RESERVED0 : 15; /*!< [14:0] */
615 uint32_t TS_TIMER : 1; /*!< [15] TS_TIMER Interrupt Mask */
616 uint32_t TS_AVAIL : 1; /*!< [16] TS_AVAIL Interrupt Mask */
617 uint32_t WAKEUP : 1; /*!< [17] WAKEUP Interrupt Mask */
618 uint32_t PLR : 1; /*!< [18] PLR Interrupt Mask */
619 uint32_t UN : 1; /*!< [19] UN Interrupt Mask */
620 uint32_t RL : 1; /*!< [20] RL Interrupt Mask */
621 uint32_t LC : 1; /*!< [21] LC Interrupt Mask */
622 uint32_t EBERR : 1; /*!< [22] EBERR Interrupt Mask */
623 uint32_t MII : 1; /*!< [23] MII Interrupt Mask */
624 uint32_t RXB : 1; /*!< [24] RXB Interrupt Mask */
625 uint32_t RXF : 1; /*!< [25] RXF Interrupt Mask */
626 uint32_t TXB : 1; /*!< [26] TXB Interrupt Mask */
627 uint32_t TXF : 1; /*!< [27] TXF Interrupt Mask */
628 uint32_t GRA : 1; /*!< [28] GRA Interrupt Mask */
629 uint32_t BABT : 1; /*!< [29] BABT Interrupt Mask */
630 uint32_t BABR : 1; /*!< [30] BABR Interrupt Mask */
631 uint32_t RESERVED1 : 1; /*!< [31] */
636 * @name Constants and macros for entire ENET_EIMR register
639 #define HW_ENET_EIMR_ADDR(x) ((x) + 0x8U)
641 #define HW_ENET_EIMR(x) (*(__IO hw_enet_eimr_t *) HW_ENET_EIMR_ADDR(x))
642 #define HW_ENET_EIMR_RD(x) (HW_ENET_EIMR(x).U)
643 #define HW_ENET_EIMR_WR(x, v) (HW_ENET_EIMR(x).U = (v))
644 #define HW_ENET_EIMR_SET(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) | (v)))
645 #define HW_ENET_EIMR_CLR(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) & ~(v)))
646 #define HW_ENET_EIMR_TOG(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) ^ (v)))
650 * Constants & macros for individual ENET_EIMR bitfields
654 * @name Register ENET_EIMR, field TS_TIMER[15] (RW)
656 * Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
657 * an interrupt condition can generate an interrupt. At every module clock, the
658 * EIR samples the signal generated by the interrupting source. The corresponding
659 * EIR TS_TIMER field reflects the state of the interrupt signal even if the
660 * corresponding EIMR field is cleared.
663 #define BP_ENET_EIMR_TS_TIMER (15U) /*!< Bit position for ENET_EIMR_TS_TIMER. */
664 #define BM_ENET_EIMR_TS_TIMER (0x00008000U) /*!< Bit mask for ENET_EIMR_TS_TIMER. */
665 #define BS_ENET_EIMR_TS_TIMER (1U) /*!< Bit field size in bits for ENET_EIMR_TS_TIMER. */
667 /*! @brief Read current value of the ENET_EIMR_TS_TIMER field. */
668 #define BR_ENET_EIMR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER))
670 /*! @brief Format value for bitfield ENET_EIMR_TS_TIMER. */
671 #define BF_ENET_EIMR_TS_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TS_TIMER) & BM_ENET_EIMR_TS_TIMER)
673 /*! @brief Set the TS_TIMER field to a new value. */
674 #define BW_ENET_EIMR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER) = (v))
678 * @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
680 * Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
681 * an interrupt condition can generate an interrupt. At every module clock, the
682 * EIR samples the signal generated by the interrupting source. The corresponding
683 * EIR TS_AVAIL field reflects the state of the interrupt signal even if the
684 * corresponding EIMR field is cleared.
687 #define BP_ENET_EIMR_TS_AVAIL (16U) /*!< Bit position for ENET_EIMR_TS_AVAIL. */
688 #define BM_ENET_EIMR_TS_AVAIL (0x00010000U) /*!< Bit mask for ENET_EIMR_TS_AVAIL. */
689 #define BS_ENET_EIMR_TS_AVAIL (1U) /*!< Bit field size in bits for ENET_EIMR_TS_AVAIL. */
691 /*! @brief Read current value of the ENET_EIMR_TS_AVAIL field. */
692 #define BR_ENET_EIMR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL))
694 /*! @brief Format value for bitfield ENET_EIMR_TS_AVAIL. */
695 #define BF_ENET_EIMR_TS_AVAIL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TS_AVAIL) & BM_ENET_EIMR_TS_AVAIL)
697 /*! @brief Set the TS_AVAIL field to a new value. */
698 #define BW_ENET_EIMR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL) = (v))
702 * @name Register ENET_EIMR, field WAKEUP[17] (RW)
704 * Corresponds to interrupt source EIR[WAKEUP] register and determines whether
705 * an interrupt condition can generate an interrupt. At every module clock, the
706 * EIR samples the signal generated by the interrupting source. The corresponding
707 * EIR WAKEUP field reflects the state of the interrupt signal even if the
708 * corresponding EIMR field is cleared.
711 #define BP_ENET_EIMR_WAKEUP (17U) /*!< Bit position for ENET_EIMR_WAKEUP. */
712 #define BM_ENET_EIMR_WAKEUP (0x00020000U) /*!< Bit mask for ENET_EIMR_WAKEUP. */
713 #define BS_ENET_EIMR_WAKEUP (1U) /*!< Bit field size in bits for ENET_EIMR_WAKEUP. */
715 /*! @brief Read current value of the ENET_EIMR_WAKEUP field. */
716 #define BR_ENET_EIMR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP))
718 /*! @brief Format value for bitfield ENET_EIMR_WAKEUP. */
719 #define BF_ENET_EIMR_WAKEUP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_WAKEUP) & BM_ENET_EIMR_WAKEUP)
721 /*! @brief Set the WAKEUP field to a new value. */
722 #define BW_ENET_EIMR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP) = (v))
726 * @name Register ENET_EIMR, field PLR[18] (RW)
728 * Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
729 * condition can generate an interrupt. At every module clock, the EIR samples
730 * the signal generated by the interrupting source. The corresponding EIR PLR field
731 * reflects the state of the interrupt signal even if the corresponding EIMR
735 #define BP_ENET_EIMR_PLR (18U) /*!< Bit position for ENET_EIMR_PLR. */
736 #define BM_ENET_EIMR_PLR (0x00040000U) /*!< Bit mask for ENET_EIMR_PLR. */
737 #define BS_ENET_EIMR_PLR (1U) /*!< Bit field size in bits for ENET_EIMR_PLR. */
739 /*! @brief Read current value of the ENET_EIMR_PLR field. */
740 #define BR_ENET_EIMR_PLR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR))
742 /*! @brief Format value for bitfield ENET_EIMR_PLR. */
743 #define BF_ENET_EIMR_PLR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_PLR) & BM_ENET_EIMR_PLR)
745 /*! @brief Set the PLR field to a new value. */
746 #define BW_ENET_EIMR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR) = (v))
750 * @name Register ENET_EIMR, field UN[19] (RW)
752 * Corresponds to interrupt source EIR[UN] and determines whether an interrupt
753 * condition can generate an interrupt. At every module clock, the EIR samples the
754 * signal generated by the interrupting source. The corresponding EIR UN field
755 * reflects the state of the interrupt signal even if the corresponding EIMR field
759 #define BP_ENET_EIMR_UN (19U) /*!< Bit position for ENET_EIMR_UN. */
760 #define BM_ENET_EIMR_UN (0x00080000U) /*!< Bit mask for ENET_EIMR_UN. */
761 #define BS_ENET_EIMR_UN (1U) /*!< Bit field size in bits for ENET_EIMR_UN. */
763 /*! @brief Read current value of the ENET_EIMR_UN field. */
764 #define BR_ENET_EIMR_UN(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN))
766 /*! @brief Format value for bitfield ENET_EIMR_UN. */
767 #define BF_ENET_EIMR_UN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_UN) & BM_ENET_EIMR_UN)
769 /*! @brief Set the UN field to a new value. */
770 #define BW_ENET_EIMR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN) = (v))
774 * @name Register ENET_EIMR, field RL[20] (RW)
776 * Corresponds to interrupt source EIR[RL] and determines whether an interrupt
777 * condition can generate an interrupt. At every module clock, the EIR samples the
778 * signal generated by the interrupting source. The corresponding EIR RL field
779 * reflects the state of the interrupt signal even if the corresponding EIMR field
783 #define BP_ENET_EIMR_RL (20U) /*!< Bit position for ENET_EIMR_RL. */
784 #define BM_ENET_EIMR_RL (0x00100000U) /*!< Bit mask for ENET_EIMR_RL. */
785 #define BS_ENET_EIMR_RL (1U) /*!< Bit field size in bits for ENET_EIMR_RL. */
787 /*! @brief Read current value of the ENET_EIMR_RL field. */
788 #define BR_ENET_EIMR_RL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL))
790 /*! @brief Format value for bitfield ENET_EIMR_RL. */
791 #define BF_ENET_EIMR_RL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RL) & BM_ENET_EIMR_RL)
793 /*! @brief Set the RL field to a new value. */
794 #define BW_ENET_EIMR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL) = (v))
798 * @name Register ENET_EIMR, field LC[21] (RW)
800 * Corresponds to interrupt source EIR[LC] and determines whether an interrupt
801 * condition can generate an interrupt. At every module clock, the EIR samples the
802 * signal generated by the interrupting source. The corresponding EIR LC field
803 * reflects the state of the interrupt signal even if the corresponding EIMR field
807 #define BP_ENET_EIMR_LC (21U) /*!< Bit position for ENET_EIMR_LC. */
808 #define BM_ENET_EIMR_LC (0x00200000U) /*!< Bit mask for ENET_EIMR_LC. */
809 #define BS_ENET_EIMR_LC (1U) /*!< Bit field size in bits for ENET_EIMR_LC. */
811 /*! @brief Read current value of the ENET_EIMR_LC field. */
812 #define BR_ENET_EIMR_LC(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC))
814 /*! @brief Format value for bitfield ENET_EIMR_LC. */
815 #define BF_ENET_EIMR_LC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_LC) & BM_ENET_EIMR_LC)
817 /*! @brief Set the LC field to a new value. */
818 #define BW_ENET_EIMR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC) = (v))
822 * @name Register ENET_EIMR, field EBERR[22] (RW)
824 * Corresponds to interrupt source EIR[EBERR] and determines whether an
825 * interrupt condition can generate an interrupt. At every module clock, the EIR samples
826 * the signal generated by the interrupting source. The corresponding EIR EBERR
827 * field reflects the state of the interrupt signal even if the corresponding EIMR
831 #define BP_ENET_EIMR_EBERR (22U) /*!< Bit position for ENET_EIMR_EBERR. */
832 #define BM_ENET_EIMR_EBERR (0x00400000U) /*!< Bit mask for ENET_EIMR_EBERR. */
833 #define BS_ENET_EIMR_EBERR (1U) /*!< Bit field size in bits for ENET_EIMR_EBERR. */
835 /*! @brief Read current value of the ENET_EIMR_EBERR field. */
836 #define BR_ENET_EIMR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR))
838 /*! @brief Format value for bitfield ENET_EIMR_EBERR. */
839 #define BF_ENET_EIMR_EBERR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_EBERR) & BM_ENET_EIMR_EBERR)
841 /*! @brief Set the EBERR field to a new value. */
842 #define BW_ENET_EIMR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR) = (v))
846 * @name Register ENET_EIMR, field MII[23] (RW)
848 * Corresponds to interrupt source EIR[MII] and determines whether an interrupt
849 * condition can generate an interrupt. At every module clock, the EIR samples
850 * the signal generated by the interrupting source. The corresponding EIR MII field
851 * reflects the state of the interrupt signal even if the corresponding EIMR
855 #define BP_ENET_EIMR_MII (23U) /*!< Bit position for ENET_EIMR_MII. */
856 #define BM_ENET_EIMR_MII (0x00800000U) /*!< Bit mask for ENET_EIMR_MII. */
857 #define BS_ENET_EIMR_MII (1U) /*!< Bit field size in bits for ENET_EIMR_MII. */
859 /*! @brief Read current value of the ENET_EIMR_MII field. */
860 #define BR_ENET_EIMR_MII(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII))
862 /*! @brief Format value for bitfield ENET_EIMR_MII. */
863 #define BF_ENET_EIMR_MII(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_MII) & BM_ENET_EIMR_MII)
865 /*! @brief Set the MII field to a new value. */
866 #define BW_ENET_EIMR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII) = (v))
870 * @name Register ENET_EIMR, field RXB[24] (RW)
872 * Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
873 * condition can generate an interrupt. At every module clock, the EIR samples
874 * the signal generated by the interrupting source. The corresponding EIR RXB field
875 * reflects the state of the interrupt signal even if the corresponding EIMR
879 #define BP_ENET_EIMR_RXB (24U) /*!< Bit position for ENET_EIMR_RXB. */
880 #define BM_ENET_EIMR_RXB (0x01000000U) /*!< Bit mask for ENET_EIMR_RXB. */
881 #define BS_ENET_EIMR_RXB (1U) /*!< Bit field size in bits for ENET_EIMR_RXB. */
883 /*! @brief Read current value of the ENET_EIMR_RXB field. */
884 #define BR_ENET_EIMR_RXB(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB))
886 /*! @brief Format value for bitfield ENET_EIMR_RXB. */
887 #define BF_ENET_EIMR_RXB(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RXB) & BM_ENET_EIMR_RXB)
889 /*! @brief Set the RXB field to a new value. */
890 #define BW_ENET_EIMR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB) = (v))
894 * @name Register ENET_EIMR, field RXF[25] (RW)
896 * Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
897 * condition can generate an interrupt. At every module clock, the EIR samples
898 * the signal generated by the interrupting source. The corresponding EIR RXF field
899 * reflects the state of the interrupt signal even if the corresponding EIMR
903 #define BP_ENET_EIMR_RXF (25U) /*!< Bit position for ENET_EIMR_RXF. */
904 #define BM_ENET_EIMR_RXF (0x02000000U) /*!< Bit mask for ENET_EIMR_RXF. */
905 #define BS_ENET_EIMR_RXF (1U) /*!< Bit field size in bits for ENET_EIMR_RXF. */
907 /*! @brief Read current value of the ENET_EIMR_RXF field. */
908 #define BR_ENET_EIMR_RXF(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF))
910 /*! @brief Format value for bitfield ENET_EIMR_RXF. */
911 #define BF_ENET_EIMR_RXF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RXF) & BM_ENET_EIMR_RXF)
913 /*! @brief Set the RXF field to a new value. */
914 #define BW_ENET_EIMR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF) = (v))
918 * @name Register ENET_EIMR, field TXB[26] (RW)
920 * Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
921 * condition can generate an interrupt. At every module clock, the EIR samples
922 * the signal generated by the interrupting source. The corresponding EIR TXF field
923 * reflects the state of the interrupt signal even if the corresponding EIMR
927 * - 0 - The corresponding interrupt source is masked.
928 * - 1 - The corresponding interrupt source is not masked.
931 #define BP_ENET_EIMR_TXB (26U) /*!< Bit position for ENET_EIMR_TXB. */
932 #define BM_ENET_EIMR_TXB (0x04000000U) /*!< Bit mask for ENET_EIMR_TXB. */
933 #define BS_ENET_EIMR_TXB (1U) /*!< Bit field size in bits for ENET_EIMR_TXB. */
935 /*! @brief Read current value of the ENET_EIMR_TXB field. */
936 #define BR_ENET_EIMR_TXB(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB))
938 /*! @brief Format value for bitfield ENET_EIMR_TXB. */
939 #define BF_ENET_EIMR_TXB(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TXB) & BM_ENET_EIMR_TXB)
941 /*! @brief Set the TXB field to a new value. */
942 #define BW_ENET_EIMR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB) = (v))
946 * @name Register ENET_EIMR, field TXF[27] (RW)
948 * Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
949 * condition can generate an interrupt. At every module clock, the EIR samples
950 * the signal generated by the interrupting source. The corresponding EIR TXF field
951 * reflects the state of the interrupt signal even if the corresponding EIMR
955 * - 0 - The corresponding interrupt source is masked.
956 * - 1 - The corresponding interrupt source is not masked.
959 #define BP_ENET_EIMR_TXF (27U) /*!< Bit position for ENET_EIMR_TXF. */
960 #define BM_ENET_EIMR_TXF (0x08000000U) /*!< Bit mask for ENET_EIMR_TXF. */
961 #define BS_ENET_EIMR_TXF (1U) /*!< Bit field size in bits for ENET_EIMR_TXF. */
963 /*! @brief Read current value of the ENET_EIMR_TXF field. */
964 #define BR_ENET_EIMR_TXF(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF))
966 /*! @brief Format value for bitfield ENET_EIMR_TXF. */
967 #define BF_ENET_EIMR_TXF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TXF) & BM_ENET_EIMR_TXF)
969 /*! @brief Set the TXF field to a new value. */
970 #define BW_ENET_EIMR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF) = (v))
974 * @name Register ENET_EIMR, field GRA[28] (RW)
976 * Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
977 * condition can generate an interrupt. At every module clock, the EIR samples
978 * the signal generated by the interrupting source. The corresponding EIR GRA field
979 * reflects the state of the interrupt signal even if the corresponding EIMR
983 * - 0 - The corresponding interrupt source is masked.
984 * - 1 - The corresponding interrupt source is not masked.
987 #define BP_ENET_EIMR_GRA (28U) /*!< Bit position for ENET_EIMR_GRA. */
988 #define BM_ENET_EIMR_GRA (0x10000000U) /*!< Bit mask for ENET_EIMR_GRA. */
989 #define BS_ENET_EIMR_GRA (1U) /*!< Bit field size in bits for ENET_EIMR_GRA. */
991 /*! @brief Read current value of the ENET_EIMR_GRA field. */
992 #define BR_ENET_EIMR_GRA(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA))
994 /*! @brief Format value for bitfield ENET_EIMR_GRA. */
995 #define BF_ENET_EIMR_GRA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_GRA) & BM_ENET_EIMR_GRA)
997 /*! @brief Set the GRA field to a new value. */
998 #define BW_ENET_EIMR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA) = (v))
1002 * @name Register ENET_EIMR, field BABT[29] (RW)
1004 * Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
1005 * condition can generate an interrupt. At every module clock, the EIR samples
1006 * the signal generated by the interrupting source. The corresponding EIR BABT
1007 * field reflects the state of the interrupt signal even if the corresponding EIMR
1011 * - 0 - The corresponding interrupt source is masked.
1012 * - 1 - The corresponding interrupt source is not masked.
1015 #define BP_ENET_EIMR_BABT (29U) /*!< Bit position for ENET_EIMR_BABT. */
1016 #define BM_ENET_EIMR_BABT (0x20000000U) /*!< Bit mask for ENET_EIMR_BABT. */
1017 #define BS_ENET_EIMR_BABT (1U) /*!< Bit field size in bits for ENET_EIMR_BABT. */
1019 /*! @brief Read current value of the ENET_EIMR_BABT field. */
1020 #define BR_ENET_EIMR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT))
1022 /*! @brief Format value for bitfield ENET_EIMR_BABT. */
1023 #define BF_ENET_EIMR_BABT(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_BABT) & BM_ENET_EIMR_BABT)
1025 /*! @brief Set the BABT field to a new value. */
1026 #define BW_ENET_EIMR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT) = (v))
1030 * @name Register ENET_EIMR, field BABR[30] (RW)
1032 * Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
1033 * condition can generate an interrupt. At every module clock, the EIR samples
1034 * the signal generated by the interrupting source. The corresponding EIR BABR
1035 * field reflects the state of the interrupt signal even if the corresponding EIMR
1039 * - 0 - The corresponding interrupt source is masked.
1040 * - 1 - The corresponding interrupt source is not masked.
1043 #define BP_ENET_EIMR_BABR (30U) /*!< Bit position for ENET_EIMR_BABR. */
1044 #define BM_ENET_EIMR_BABR (0x40000000U) /*!< Bit mask for ENET_EIMR_BABR. */
1045 #define BS_ENET_EIMR_BABR (1U) /*!< Bit field size in bits for ENET_EIMR_BABR. */
1047 /*! @brief Read current value of the ENET_EIMR_BABR field. */
1048 #define BR_ENET_EIMR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR))
1050 /*! @brief Format value for bitfield ENET_EIMR_BABR. */
1051 #define BF_ENET_EIMR_BABR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_BABR) & BM_ENET_EIMR_BABR)
1053 /*! @brief Set the BABR field to a new value. */
1054 #define BW_ENET_EIMR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR) = (v))
1057 /*******************************************************************************
1058 * HW_ENET_RDAR - Receive Descriptor Active Register
1059 ******************************************************************************/
1062 * @brief HW_ENET_RDAR - Receive Descriptor Active Register (RW)
1064 * Reset value: 0x00000000U
1066 * RDAR is a command register, written by the user, to indicate that the receive
1067 * descriptor ring has been updated, that is, that the driver produced empty
1068 * receive buffers with the empty bit set.
1070 typedef union _hw_enet_rdar
1073 struct _hw_enet_rdar_bitfields
1075 uint32_t RESERVED0 : 24; /*!< [23:0] */
1076 uint32_t RDAR : 1; /*!< [24] Receive Descriptor Active */
1077 uint32_t RESERVED1 : 7; /*!< [31:25] */
1082 * @name Constants and macros for entire ENET_RDAR register
1085 #define HW_ENET_RDAR_ADDR(x) ((x) + 0x10U)
1087 #define HW_ENET_RDAR(x) (*(__IO hw_enet_rdar_t *) HW_ENET_RDAR_ADDR(x))
1088 #define HW_ENET_RDAR_RD(x) (HW_ENET_RDAR(x).U)
1089 #define HW_ENET_RDAR_WR(x, v) (HW_ENET_RDAR(x).U = (v))
1090 #define HW_ENET_RDAR_SET(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) | (v)))
1091 #define HW_ENET_RDAR_CLR(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) & ~(v)))
1092 #define HW_ENET_RDAR_TOG(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) ^ (v)))
1096 * Constants & macros for individual ENET_RDAR bitfields
1100 * @name Register ENET_RDAR, field RDAR[24] (RW)
1102 * Always set to 1 when this register is written, regardless of the value
1103 * written. This field is cleared by the MAC device when no additional empty
1104 * descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
1105 * from set to cleared or when ECR[RESET] is set.
1108 #define BP_ENET_RDAR_RDAR (24U) /*!< Bit position for ENET_RDAR_RDAR. */
1109 #define BM_ENET_RDAR_RDAR (0x01000000U) /*!< Bit mask for ENET_RDAR_RDAR. */
1110 #define BS_ENET_RDAR_RDAR (1U) /*!< Bit field size in bits for ENET_RDAR_RDAR. */
1112 /*! @brief Read current value of the ENET_RDAR_RDAR field. */
1113 #define BR_ENET_RDAR_RDAR(x) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR))
1115 /*! @brief Format value for bitfield ENET_RDAR_RDAR. */
1116 #define BF_ENET_RDAR_RDAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RDAR_RDAR) & BM_ENET_RDAR_RDAR)
1118 /*! @brief Set the RDAR field to a new value. */
1119 #define BW_ENET_RDAR_RDAR(x, v) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR) = (v))
1122 /*******************************************************************************
1123 * HW_ENET_TDAR - Transmit Descriptor Active Register
1124 ******************************************************************************/
1127 * @brief HW_ENET_TDAR - Transmit Descriptor Active Register (RW)
1129 * Reset value: 0x00000000U
1131 * The TDAR is a command register that the user writes to indicate that the
1132 * transmit descriptor ring has been updated, that is, that transmit buffers have
1133 * been produced by the driver with the ready bit set in the buffer descriptor. The
1134 * TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
1135 * cleared, or when ECR[RESET] is set.
1137 typedef union _hw_enet_tdar
1140 struct _hw_enet_tdar_bitfields
1142 uint32_t RESERVED0 : 24; /*!< [23:0] */
1143 uint32_t TDAR : 1; /*!< [24] Transmit Descriptor Active */
1144 uint32_t RESERVED1 : 7; /*!< [31:25] */
1149 * @name Constants and macros for entire ENET_TDAR register
1152 #define HW_ENET_TDAR_ADDR(x) ((x) + 0x14U)
1154 #define HW_ENET_TDAR(x) (*(__IO hw_enet_tdar_t *) HW_ENET_TDAR_ADDR(x))
1155 #define HW_ENET_TDAR_RD(x) (HW_ENET_TDAR(x).U)
1156 #define HW_ENET_TDAR_WR(x, v) (HW_ENET_TDAR(x).U = (v))
1157 #define HW_ENET_TDAR_SET(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) | (v)))
1158 #define HW_ENET_TDAR_CLR(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) & ~(v)))
1159 #define HW_ENET_TDAR_TOG(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) ^ (v)))
1163 * Constants & macros for individual ENET_TDAR bitfields
1167 * @name Register ENET_TDAR, field TDAR[24] (RW)
1169 * Always set to 1 when this register is written, regardless of the value
1170 * written. This bit is cleared by the MAC device when no additional ready descriptors
1171 * remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
1172 * set to cleared or when ECR[RESET] is set.
1175 #define BP_ENET_TDAR_TDAR (24U) /*!< Bit position for ENET_TDAR_TDAR. */
1176 #define BM_ENET_TDAR_TDAR (0x01000000U) /*!< Bit mask for ENET_TDAR_TDAR. */
1177 #define BS_ENET_TDAR_TDAR (1U) /*!< Bit field size in bits for ENET_TDAR_TDAR. */
1179 /*! @brief Read current value of the ENET_TDAR_TDAR field. */
1180 #define BR_ENET_TDAR_TDAR(x) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR))
1182 /*! @brief Format value for bitfield ENET_TDAR_TDAR. */
1183 #define BF_ENET_TDAR_TDAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TDAR_TDAR) & BM_ENET_TDAR_TDAR)
1185 /*! @brief Set the TDAR field to a new value. */
1186 #define BW_ENET_TDAR_TDAR(x, v) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR) = (v))
1189 /*******************************************************************************
1190 * HW_ENET_ECR - Ethernet Control Register
1191 ******************************************************************************/
1194 * @brief HW_ENET_ECR - Ethernet Control Register (RW)
1196 * Reset value: 0xF0000000U
1198 * ECR is a read/write user register, though hardware may also alter fields in
1199 * this register. It controls many of the high level features of the Ethernet MAC,
1200 * including legacy FEC support through the EN1588 field.
1202 typedef union _hw_enet_ecr
1205 struct _hw_enet_ecr_bitfields
1207 uint32_t RESET : 1; /*!< [0] Ethernet MAC Reset */
1208 uint32_t ETHEREN : 1; /*!< [1] Ethernet Enable */
1209 uint32_t MAGICEN : 1; /*!< [2] Magic Packet Detection Enable */
1210 uint32_t SLEEP : 1; /*!< [3] Sleep Mode Enable */
1211 uint32_t EN1588 : 1; /*!< [4] EN1588 Enable */
1212 uint32_t RESERVED0 : 1; /*!< [5] */
1213 uint32_t DBGEN : 1; /*!< [6] Debug Enable */
1214 uint32_t STOPEN : 1; /*!< [7] STOPEN Signal Control */
1215 uint32_t DBSWP : 1; /*!< [8] Descriptor Byte Swapping Enable */
1216 uint32_t RESERVED1 : 23; /*!< [31:9] */
1221 * @name Constants and macros for entire ENET_ECR register
1224 #define HW_ENET_ECR_ADDR(x) ((x) + 0x24U)
1226 #define HW_ENET_ECR(x) (*(__IO hw_enet_ecr_t *) HW_ENET_ECR_ADDR(x))
1227 #define HW_ENET_ECR_RD(x) (HW_ENET_ECR(x).U)
1228 #define HW_ENET_ECR_WR(x, v) (HW_ENET_ECR(x).U = (v))
1229 #define HW_ENET_ECR_SET(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) | (v)))
1230 #define HW_ENET_ECR_CLR(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) & ~(v)))
1231 #define HW_ENET_ECR_TOG(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) ^ (v)))
1235 * Constants & macros for individual ENET_ECR bitfields
1239 * @name Register ENET_ECR, field RESET[0] (RW)
1241 * When this field is set, it clears the ETHEREN field.
1244 #define BP_ENET_ECR_RESET (0U) /*!< Bit position for ENET_ECR_RESET. */
1245 #define BM_ENET_ECR_RESET (0x00000001U) /*!< Bit mask for ENET_ECR_RESET. */
1246 #define BS_ENET_ECR_RESET (1U) /*!< Bit field size in bits for ENET_ECR_RESET. */
1248 /*! @brief Read current value of the ENET_ECR_RESET field. */
1249 #define BR_ENET_ECR_RESET(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET))
1251 /*! @brief Format value for bitfield ENET_ECR_RESET. */
1252 #define BF_ENET_ECR_RESET(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_RESET) & BM_ENET_ECR_RESET)
1254 /*! @brief Set the RESET field to a new value. */
1255 #define BW_ENET_ECR_RESET(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET) = (v))
1259 * @name Register ENET_ECR, field ETHEREN[1] (RW)
1261 * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
1262 * descriptors for an aborted transmit frame are not updated. The uDMA, buffer
1263 * descriptor, and FIFO control logic are reset, including the buffer descriptor and
1264 * FIFO pointers. Hardware clears this field under the following conditions: RESET
1265 * is set by software An error condition causes the EBERR field to set. ETHEREN
1266 * must be set at the very last step during ENET
1267 * configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
1268 * is cleared to 0 by software then then next time ETHEREN is set, the EIR
1269 * interrupts must cleared to 0 due to previous pending interrupts.
1272 * - 0 - Reception immediately stops and transmission stops after a bad CRC is
1273 * appended to any currently transmitted frame.
1274 * - 1 - MAC is enabled, and reception and transmission are possible.
1277 #define BP_ENET_ECR_ETHEREN (1U) /*!< Bit position for ENET_ECR_ETHEREN. */
1278 #define BM_ENET_ECR_ETHEREN (0x00000002U) /*!< Bit mask for ENET_ECR_ETHEREN. */
1279 #define BS_ENET_ECR_ETHEREN (1U) /*!< Bit field size in bits for ENET_ECR_ETHEREN. */
1281 /*! @brief Read current value of the ENET_ECR_ETHEREN field. */
1282 #define BR_ENET_ECR_ETHEREN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN))
1284 /*! @brief Format value for bitfield ENET_ECR_ETHEREN. */
1285 #define BF_ENET_ECR_ETHEREN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_ETHEREN) & BM_ENET_ECR_ETHEREN)
1287 /*! @brief Set the ETHEREN field to a new value. */
1288 #define BW_ENET_ECR_ETHEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN) = (v))
1292 * @name Register ENET_ECR, field MAGICEN[2] (RW)
1294 * Enables/disables magic packet detection. MAGICEN is relevant only if the
1295 * SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
1296 * sleep mode and magic packet detection.
1299 * - 0 - Magic detection logic disabled.
1300 * - 1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame
1304 #define BP_ENET_ECR_MAGICEN (2U) /*!< Bit position for ENET_ECR_MAGICEN. */
1305 #define BM_ENET_ECR_MAGICEN (0x00000004U) /*!< Bit mask for ENET_ECR_MAGICEN. */
1306 #define BS_ENET_ECR_MAGICEN (1U) /*!< Bit field size in bits for ENET_ECR_MAGICEN. */
1308 /*! @brief Read current value of the ENET_ECR_MAGICEN field. */
1309 #define BR_ENET_ECR_MAGICEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN))
1311 /*! @brief Format value for bitfield ENET_ECR_MAGICEN. */
1312 #define BF_ENET_ECR_MAGICEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_MAGICEN) & BM_ENET_ECR_MAGICEN)
1314 /*! @brief Set the MAGICEN field to a new value. */
1315 #define BW_ENET_ECR_MAGICEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN) = (v))
1319 * @name Register ENET_ECR, field SLEEP[3] (RW)
1322 * - 0 - Normal operating mode.
1326 #define BP_ENET_ECR_SLEEP (3U) /*!< Bit position for ENET_ECR_SLEEP. */
1327 #define BM_ENET_ECR_SLEEP (0x00000008U) /*!< Bit mask for ENET_ECR_SLEEP. */
1328 #define BS_ENET_ECR_SLEEP (1U) /*!< Bit field size in bits for ENET_ECR_SLEEP. */
1330 /*! @brief Read current value of the ENET_ECR_SLEEP field. */
1331 #define BR_ENET_ECR_SLEEP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP))
1333 /*! @brief Format value for bitfield ENET_ECR_SLEEP. */
1334 #define BF_ENET_ECR_SLEEP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_SLEEP) & BM_ENET_ECR_SLEEP)
1336 /*! @brief Set the SLEEP field to a new value. */
1337 #define BW_ENET_ECR_SLEEP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP) = (v))
1341 * @name Register ENET_ECR, field EN1588[4] (RW)
1343 * Enables enhanced functionality of the MAC.
1346 * - 0 - Legacy FEC buffer descriptors and functions enabled.
1347 * - 1 - Enhanced frame time-stamping functions enabled.
1350 #define BP_ENET_ECR_EN1588 (4U) /*!< Bit position for ENET_ECR_EN1588. */
1351 #define BM_ENET_ECR_EN1588 (0x00000010U) /*!< Bit mask for ENET_ECR_EN1588. */
1352 #define BS_ENET_ECR_EN1588 (1U) /*!< Bit field size in bits for ENET_ECR_EN1588. */
1354 /*! @brief Read current value of the ENET_ECR_EN1588 field. */
1355 #define BR_ENET_ECR_EN1588(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588))
1357 /*! @brief Format value for bitfield ENET_ECR_EN1588. */
1358 #define BF_ENET_ECR_EN1588(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_EN1588) & BM_ENET_ECR_EN1588)
1360 /*! @brief Set the EN1588 field to a new value. */
1361 #define BW_ENET_ECR_EN1588(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588) = (v))
1365 * @name Register ENET_ECR, field DBGEN[6] (RW)
1367 * Enables the MAC to enter hardware freeze mode when the device enters debug
1371 * - 0 - MAC continues operation in debug mode.
1372 * - 1 - MAC enters hardware freeze mode when the processor is in debug mode.
1375 #define BP_ENET_ECR_DBGEN (6U) /*!< Bit position for ENET_ECR_DBGEN. */
1376 #define BM_ENET_ECR_DBGEN (0x00000040U) /*!< Bit mask for ENET_ECR_DBGEN. */
1377 #define BS_ENET_ECR_DBGEN (1U) /*!< Bit field size in bits for ENET_ECR_DBGEN. */
1379 /*! @brief Read current value of the ENET_ECR_DBGEN field. */
1380 #define BR_ENET_ECR_DBGEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN))
1382 /*! @brief Format value for bitfield ENET_ECR_DBGEN. */
1383 #define BF_ENET_ECR_DBGEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_DBGEN) & BM_ENET_ECR_DBGEN)
1385 /*! @brief Set the DBGEN field to a new value. */
1386 #define BW_ENET_ECR_DBGEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN) = (v))
1390 * @name Register ENET_ECR, field STOPEN[7] (RW)
1392 * Controls device behavior in doze mode. In doze mode, if this field is set
1393 * then all the clocks of the ENET assembly are disabled, except the RMII /MII
1394 * clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
1395 * depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
1396 * can still wake the system after receiving a magic packet in stop mode. MAGICEN
1397 * must be set prior to entering sleep/stop mode.
1400 #define BP_ENET_ECR_STOPEN (7U) /*!< Bit position for ENET_ECR_STOPEN. */
1401 #define BM_ENET_ECR_STOPEN (0x00000080U) /*!< Bit mask for ENET_ECR_STOPEN. */
1402 #define BS_ENET_ECR_STOPEN (1U) /*!< Bit field size in bits for ENET_ECR_STOPEN. */
1404 /*! @brief Read current value of the ENET_ECR_STOPEN field. */
1405 #define BR_ENET_ECR_STOPEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN))
1407 /*! @brief Format value for bitfield ENET_ECR_STOPEN. */
1408 #define BF_ENET_ECR_STOPEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_STOPEN) & BM_ENET_ECR_STOPEN)
1410 /*! @brief Set the STOPEN field to a new value. */
1411 #define BW_ENET_ECR_STOPEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN) = (v))
1415 * @name Register ENET_ECR, field DBSWP[8] (RW)
1417 * Swaps the byte locations of the buffer descriptors. This field must be
1418 * written to 1 after reset.
1421 * - 0 - The buffer descriptor bytes are not swapped to support big-endian
1423 * - 1 - The buffer descriptor bytes are swapped to support little-endian
1427 #define BP_ENET_ECR_DBSWP (8U) /*!< Bit position for ENET_ECR_DBSWP. */
1428 #define BM_ENET_ECR_DBSWP (0x00000100U) /*!< Bit mask for ENET_ECR_DBSWP. */
1429 #define BS_ENET_ECR_DBSWP (1U) /*!< Bit field size in bits for ENET_ECR_DBSWP. */
1431 /*! @brief Read current value of the ENET_ECR_DBSWP field. */
1432 #define BR_ENET_ECR_DBSWP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP))
1434 /*! @brief Format value for bitfield ENET_ECR_DBSWP. */
1435 #define BF_ENET_ECR_DBSWP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_DBSWP) & BM_ENET_ECR_DBSWP)
1437 /*! @brief Set the DBSWP field to a new value. */
1438 #define BW_ENET_ECR_DBSWP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP) = (v))
1441 /*******************************************************************************
1442 * HW_ENET_MMFR - MII Management Frame Register
1443 ******************************************************************************/
1446 * @brief HW_ENET_MMFR - MII Management Frame Register (RW)
1448 * Reset value: 0x00000000U
1450 * Writing to MMFR triggers a management frame transaction to the PHY device
1451 * unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
1452 * during a write to MMFR, an MII frame is generated with the data previously written
1453 * to the MMFR. This allows MMFR and MSCR to be programmed in either order if
1454 * MSCR is currently zero. If the MMFR register is written while frame generation is
1455 * in progress, the frame contents are altered. Software must use the EIR[MII]
1456 * interrupt indication to avoid writing to the MMFR register while frame
1457 * generation is in progress.
1459 typedef union _hw_enet_mmfr
1462 struct _hw_enet_mmfr_bitfields
1464 uint32_t DATA : 16; /*!< [15:0] Management Frame Data */
1465 uint32_t TA : 2; /*!< [17:16] Turn Around */
1466 uint32_t RA : 5; /*!< [22:18] Register Address */
1467 uint32_t PA : 5; /*!< [27:23] PHY Address */
1468 uint32_t OP : 2; /*!< [29:28] Operation Code */
1469 uint32_t ST : 2; /*!< [31:30] Start Of Frame Delimiter */
1474 * @name Constants and macros for entire ENET_MMFR register
1477 #define HW_ENET_MMFR_ADDR(x) ((x) + 0x40U)
1479 #define HW_ENET_MMFR(x) (*(__IO hw_enet_mmfr_t *) HW_ENET_MMFR_ADDR(x))
1480 #define HW_ENET_MMFR_RD(x) (HW_ENET_MMFR(x).U)
1481 #define HW_ENET_MMFR_WR(x, v) (HW_ENET_MMFR(x).U = (v))
1482 #define HW_ENET_MMFR_SET(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) | (v)))
1483 #define HW_ENET_MMFR_CLR(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) & ~(v)))
1484 #define HW_ENET_MMFR_TOG(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) ^ (v)))
1488 * Constants & macros for individual ENET_MMFR bitfields
1492 * @name Register ENET_MMFR, field DATA[15:0] (RW)
1494 * This is the field for data to be written to or read from the PHY register.
1497 #define BP_ENET_MMFR_DATA (0U) /*!< Bit position for ENET_MMFR_DATA. */
1498 #define BM_ENET_MMFR_DATA (0x0000FFFFU) /*!< Bit mask for ENET_MMFR_DATA. */
1499 #define BS_ENET_MMFR_DATA (16U) /*!< Bit field size in bits for ENET_MMFR_DATA. */
1501 /*! @brief Read current value of the ENET_MMFR_DATA field. */
1502 #define BR_ENET_MMFR_DATA(x) (HW_ENET_MMFR(x).B.DATA)
1504 /*! @brief Format value for bitfield ENET_MMFR_DATA. */
1505 #define BF_ENET_MMFR_DATA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_DATA) & BM_ENET_MMFR_DATA)
1507 /*! @brief Set the DATA field to a new value. */
1508 #define BW_ENET_MMFR_DATA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_DATA) | BF_ENET_MMFR_DATA(v)))
1512 * @name Register ENET_MMFR, field TA[17:16] (RW)
1514 * This field must be programmed to 10 to generate a valid MII management frame.
1517 #define BP_ENET_MMFR_TA (16U) /*!< Bit position for ENET_MMFR_TA. */
1518 #define BM_ENET_MMFR_TA (0x00030000U) /*!< Bit mask for ENET_MMFR_TA. */
1519 #define BS_ENET_MMFR_TA (2U) /*!< Bit field size in bits for ENET_MMFR_TA. */
1521 /*! @brief Read current value of the ENET_MMFR_TA field. */
1522 #define BR_ENET_MMFR_TA(x) (HW_ENET_MMFR(x).B.TA)
1524 /*! @brief Format value for bitfield ENET_MMFR_TA. */
1525 #define BF_ENET_MMFR_TA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_TA) & BM_ENET_MMFR_TA)
1527 /*! @brief Set the TA field to a new value. */
1528 #define BW_ENET_MMFR_TA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_TA) | BF_ENET_MMFR_TA(v)))
1532 * @name Register ENET_MMFR, field RA[22:18] (RW)
1534 * Specifies one of up to 32 registers within the specified PHY device.
1537 #define BP_ENET_MMFR_RA (18U) /*!< Bit position for ENET_MMFR_RA. */
1538 #define BM_ENET_MMFR_RA (0x007C0000U) /*!< Bit mask for ENET_MMFR_RA. */
1539 #define BS_ENET_MMFR_RA (5U) /*!< Bit field size in bits for ENET_MMFR_RA. */
1541 /*! @brief Read current value of the ENET_MMFR_RA field. */
1542 #define BR_ENET_MMFR_RA(x) (HW_ENET_MMFR(x).B.RA)
1544 /*! @brief Format value for bitfield ENET_MMFR_RA. */
1545 #define BF_ENET_MMFR_RA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_RA) & BM_ENET_MMFR_RA)
1547 /*! @brief Set the RA field to a new value. */
1548 #define BW_ENET_MMFR_RA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_RA) | BF_ENET_MMFR_RA(v)))
1552 * @name Register ENET_MMFR, field PA[27:23] (RW)
1554 * Specifies one of up to 32 attached PHY devices.
1557 #define BP_ENET_MMFR_PA (23U) /*!< Bit position for ENET_MMFR_PA. */
1558 #define BM_ENET_MMFR_PA (0x0F800000U) /*!< Bit mask for ENET_MMFR_PA. */
1559 #define BS_ENET_MMFR_PA (5U) /*!< Bit field size in bits for ENET_MMFR_PA. */
1561 /*! @brief Read current value of the ENET_MMFR_PA field. */
1562 #define BR_ENET_MMFR_PA(x) (HW_ENET_MMFR(x).B.PA)
1564 /*! @brief Format value for bitfield ENET_MMFR_PA. */
1565 #define BF_ENET_MMFR_PA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_PA) & BM_ENET_MMFR_PA)
1567 /*! @brief Set the PA field to a new value. */
1568 #define BW_ENET_MMFR_PA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_PA) | BF_ENET_MMFR_PA(v)))
1572 * @name Register ENET_MMFR, field OP[29:28] (RW)
1574 * Determines the frame operation.
1577 * - 00 - Write frame operation, but not MII compliant.
1578 * - 01 - Write frame operation for a valid MII management frame.
1579 * - 10 - Read frame operation for a valid MII management frame.
1580 * - 11 - Read frame operation, but not MII compliant.
1583 #define BP_ENET_MMFR_OP (28U) /*!< Bit position for ENET_MMFR_OP. */
1584 #define BM_ENET_MMFR_OP (0x30000000U) /*!< Bit mask for ENET_MMFR_OP. */
1585 #define BS_ENET_MMFR_OP (2U) /*!< Bit field size in bits for ENET_MMFR_OP. */
1587 /*! @brief Read current value of the ENET_MMFR_OP field. */
1588 #define BR_ENET_MMFR_OP(x) (HW_ENET_MMFR(x).B.OP)
1590 /*! @brief Format value for bitfield ENET_MMFR_OP. */
1591 #define BF_ENET_MMFR_OP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_OP) & BM_ENET_MMFR_OP)
1593 /*! @brief Set the OP field to a new value. */
1594 #define BW_ENET_MMFR_OP(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_OP) | BF_ENET_MMFR_OP(v)))
1598 * @name Register ENET_MMFR, field ST[31:30] (RW)
1600 * These fields must be programmed to 01 for a valid MII management frame.
1603 #define BP_ENET_MMFR_ST (30U) /*!< Bit position for ENET_MMFR_ST. */
1604 #define BM_ENET_MMFR_ST (0xC0000000U) /*!< Bit mask for ENET_MMFR_ST. */
1605 #define BS_ENET_MMFR_ST (2U) /*!< Bit field size in bits for ENET_MMFR_ST. */
1607 /*! @brief Read current value of the ENET_MMFR_ST field. */
1608 #define BR_ENET_MMFR_ST(x) (HW_ENET_MMFR(x).B.ST)
1610 /*! @brief Format value for bitfield ENET_MMFR_ST. */
1611 #define BF_ENET_MMFR_ST(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_ST) & BM_ENET_MMFR_ST)
1613 /*! @brief Set the ST field to a new value. */
1614 #define BW_ENET_MMFR_ST(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_ST) | BF_ENET_MMFR_ST(v)))
1617 /*******************************************************************************
1618 * HW_ENET_MSCR - MII Speed Control Register
1619 ******************************************************************************/
1622 * @brief HW_ENET_MSCR - MII Speed Control Register (RW)
1624 * Reset value: 0x00000000U
1626 * MSCR provides control of the MII clock (MDC pin) frequency and allows a
1627 * preamble drop on the MII management frame. The MII_SPEED field must be programmed
1628 * with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
1629 * compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
1630 * a non-zero value to source a read or write management frame. After the
1631 * management frame is complete, the MSCR register may optionally be cleared to turn
1632 * off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
1633 * changes during operation. This change takes effect following a rising or falling
1634 * edge of MDC. If the internal module clock is 25 MHz, programming this register
1635 * to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
1636 * / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
1637 * MII_SPEED as a function of internal module clock frequency. Programming Examples
1638 * for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
1639 * 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
1642 typedef union _hw_enet_mscr
1645 struct _hw_enet_mscr_bitfields
1647 uint32_t RESERVED0 : 1; /*!< [0] */
1648 uint32_t MII_SPEED : 6; /*!< [6:1] MII Speed */
1649 uint32_t DIS_PRE : 1; /*!< [7] Disable Preamble */
1650 uint32_t HOLDTIME : 3; /*!< [10:8] Hold time On MDIO Output */
1651 uint32_t RESERVED1 : 21; /*!< [31:11] */
1656 * @name Constants and macros for entire ENET_MSCR register
1659 #define HW_ENET_MSCR_ADDR(x) ((x) + 0x44U)
1661 #define HW_ENET_MSCR(x) (*(__IO hw_enet_mscr_t *) HW_ENET_MSCR_ADDR(x))
1662 #define HW_ENET_MSCR_RD(x) (HW_ENET_MSCR(x).U)
1663 #define HW_ENET_MSCR_WR(x, v) (HW_ENET_MSCR(x).U = (v))
1664 #define HW_ENET_MSCR_SET(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) | (v)))
1665 #define HW_ENET_MSCR_CLR(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) & ~(v)))
1666 #define HW_ENET_MSCR_TOG(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) ^ (v)))
1670 * Constants & macros for individual ENET_MSCR bitfields
1674 * @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
1676 * Controls the frequency of the MII management interface clock (MDC) relative
1677 * to the internal module clock. A value of 0 in this field turns off MDC and
1678 * leaves it in low voltage state. Any non-zero value results in the MDC frequency
1679 * of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
1682 #define BP_ENET_MSCR_MII_SPEED (1U) /*!< Bit position for ENET_MSCR_MII_SPEED. */
1683 #define BM_ENET_MSCR_MII_SPEED (0x0000007EU) /*!< Bit mask for ENET_MSCR_MII_SPEED. */
1684 #define BS_ENET_MSCR_MII_SPEED (6U) /*!< Bit field size in bits for ENET_MSCR_MII_SPEED. */
1686 /*! @brief Read current value of the ENET_MSCR_MII_SPEED field. */
1687 #define BR_ENET_MSCR_MII_SPEED(x) (HW_ENET_MSCR(x).B.MII_SPEED)
1689 /*! @brief Format value for bitfield ENET_MSCR_MII_SPEED. */
1690 #define BF_ENET_MSCR_MII_SPEED(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_MII_SPEED) & BM_ENET_MSCR_MII_SPEED)
1692 /*! @brief Set the MII_SPEED field to a new value. */
1693 #define BW_ENET_MSCR_MII_SPEED(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_MII_SPEED) | BF_ENET_MSCR_MII_SPEED(v)))
1697 * @name Register ENET_MSCR, field DIS_PRE[7] (RW)
1699 * Enables/disables prepending a preamble to the MII management frame. The MII
1700 * standard allows the preamble to be dropped if the attached PHY devices do not
1704 * - 0 - Preamble enabled.
1705 * - 1 - Preamble (32 ones) is not prepended to the MII management frame.
1708 #define BP_ENET_MSCR_DIS_PRE (7U) /*!< Bit position for ENET_MSCR_DIS_PRE. */
1709 #define BM_ENET_MSCR_DIS_PRE (0x00000080U) /*!< Bit mask for ENET_MSCR_DIS_PRE. */
1710 #define BS_ENET_MSCR_DIS_PRE (1U) /*!< Bit field size in bits for ENET_MSCR_DIS_PRE. */
1712 /*! @brief Read current value of the ENET_MSCR_DIS_PRE field. */
1713 #define BR_ENET_MSCR_DIS_PRE(x) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE))
1715 /*! @brief Format value for bitfield ENET_MSCR_DIS_PRE. */
1716 #define BF_ENET_MSCR_DIS_PRE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_DIS_PRE) & BM_ENET_MSCR_DIS_PRE)
1718 /*! @brief Set the DIS_PRE field to a new value. */
1719 #define BW_ENET_MSCR_DIS_PRE(x, v) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE) = (v))
1723 * @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
1725 * IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
1726 * output. Depending on the host bus frequency, the setting may need to be
1730 * - 000 - 1 internal module clock cycle
1731 * - 001 - 2 internal module clock cycles
1732 * - 010 - 3 internal module clock cycles
1733 * - 111 - 8 internal module clock cycles
1736 #define BP_ENET_MSCR_HOLDTIME (8U) /*!< Bit position for ENET_MSCR_HOLDTIME. */
1737 #define BM_ENET_MSCR_HOLDTIME (0x00000700U) /*!< Bit mask for ENET_MSCR_HOLDTIME. */
1738 #define BS_ENET_MSCR_HOLDTIME (3U) /*!< Bit field size in bits for ENET_MSCR_HOLDTIME. */
1740 /*! @brief Read current value of the ENET_MSCR_HOLDTIME field. */
1741 #define BR_ENET_MSCR_HOLDTIME(x) (HW_ENET_MSCR(x).B.HOLDTIME)
1743 /*! @brief Format value for bitfield ENET_MSCR_HOLDTIME. */
1744 #define BF_ENET_MSCR_HOLDTIME(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_HOLDTIME) & BM_ENET_MSCR_HOLDTIME)
1746 /*! @brief Set the HOLDTIME field to a new value. */
1747 #define BW_ENET_MSCR_HOLDTIME(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_HOLDTIME) | BF_ENET_MSCR_HOLDTIME(v)))
1750 /*******************************************************************************
1751 * HW_ENET_MIBC - MIB Control Register
1752 ******************************************************************************/
1755 * @brief HW_ENET_MIBC - MIB Control Register (RW)
1757 * Reset value: 0xC0000000U
1759 * MIBC is a read/write register controlling and observing the state of the MIB
1760 * block. Access this register to disable the MIB block operation or clear the
1761 * MIB counters. The MIB_DIS field resets to 1.
1763 typedef union _hw_enet_mibc
1766 struct _hw_enet_mibc_bitfields
1768 uint32_t RESERVED0 : 29; /*!< [28:0] */
1769 uint32_t MIB_CLEAR : 1; /*!< [29] MIB Clear */
1770 uint32_t MIB_IDLE : 1; /*!< [30] MIB Idle */
1771 uint32_t MIB_DIS : 1; /*!< [31] Disable MIB Logic */
1776 * @name Constants and macros for entire ENET_MIBC register
1779 #define HW_ENET_MIBC_ADDR(x) ((x) + 0x64U)
1781 #define HW_ENET_MIBC(x) (*(__IO hw_enet_mibc_t *) HW_ENET_MIBC_ADDR(x))
1782 #define HW_ENET_MIBC_RD(x) (HW_ENET_MIBC(x).U)
1783 #define HW_ENET_MIBC_WR(x, v) (HW_ENET_MIBC(x).U = (v))
1784 #define HW_ENET_MIBC_SET(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) | (v)))
1785 #define HW_ENET_MIBC_CLR(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) & ~(v)))
1786 #define HW_ENET_MIBC_TOG(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) ^ (v)))
1790 * Constants & macros for individual ENET_MIBC bitfields
1794 * @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
1796 * If set, all statistics counters are reset to 0. This field is not
1797 * self-clearing. To clear the MIB counters set and then clear the field.
1800 #define BP_ENET_MIBC_MIB_CLEAR (29U) /*!< Bit position for ENET_MIBC_MIB_CLEAR. */
1801 #define BM_ENET_MIBC_MIB_CLEAR (0x20000000U) /*!< Bit mask for ENET_MIBC_MIB_CLEAR. */
1802 #define BS_ENET_MIBC_MIB_CLEAR (1U) /*!< Bit field size in bits for ENET_MIBC_MIB_CLEAR. */
1804 /*! @brief Read current value of the ENET_MIBC_MIB_CLEAR field. */
1805 #define BR_ENET_MIBC_MIB_CLEAR(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR))
1807 /*! @brief Format value for bitfield ENET_MIBC_MIB_CLEAR. */
1808 #define BF_ENET_MIBC_MIB_CLEAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MIBC_MIB_CLEAR) & BM_ENET_MIBC_MIB_CLEAR)
1810 /*! @brief Set the MIB_CLEAR field to a new value. */
1811 #define BW_ENET_MIBC_MIB_CLEAR(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR) = (v))
1815 * @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
1817 * If this status field is set, the MIB block is not currently updating any MIB
1821 #define BP_ENET_MIBC_MIB_IDLE (30U) /*!< Bit position for ENET_MIBC_MIB_IDLE. */
1822 #define BM_ENET_MIBC_MIB_IDLE (0x40000000U) /*!< Bit mask for ENET_MIBC_MIB_IDLE. */
1823 #define BS_ENET_MIBC_MIB_IDLE (1U) /*!< Bit field size in bits for ENET_MIBC_MIB_IDLE. */
1825 /*! @brief Read current value of the ENET_MIBC_MIB_IDLE field. */
1826 #define BR_ENET_MIBC_MIB_IDLE(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_IDLE))
1830 * @name Register ENET_MIBC, field MIB_DIS[31] (RW)
1832 * If this control field is set, the MIB logic halts and does not update any MIB
1836 #define BP_ENET_MIBC_MIB_DIS (31U) /*!< Bit position for ENET_MIBC_MIB_DIS. */
1837 #define BM_ENET_MIBC_MIB_DIS (0x80000000U) /*!< Bit mask for ENET_MIBC_MIB_DIS. */
1838 #define BS_ENET_MIBC_MIB_DIS (1U) /*!< Bit field size in bits for ENET_MIBC_MIB_DIS. */
1840 /*! @brief Read current value of the ENET_MIBC_MIB_DIS field. */
1841 #define BR_ENET_MIBC_MIB_DIS(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS))
1843 /*! @brief Format value for bitfield ENET_MIBC_MIB_DIS. */
1844 #define BF_ENET_MIBC_MIB_DIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MIBC_MIB_DIS) & BM_ENET_MIBC_MIB_DIS)
1846 /*! @brief Set the MIB_DIS field to a new value. */
1847 #define BW_ENET_MIBC_MIB_DIS(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS) = (v))
1850 /*******************************************************************************
1851 * HW_ENET_RCR - Receive Control Register
1852 ******************************************************************************/
1855 * @brief HW_ENET_RCR - Receive Control Register (RW)
1857 * Reset value: 0x05EE0001U
1859 typedef union _hw_enet_rcr
1862 struct _hw_enet_rcr_bitfields
1864 uint32_t LOOP : 1; /*!< [0] Internal Loopback */
1865 uint32_t DRT : 1; /*!< [1] Disable Receive On Transmit */
1866 uint32_t MII_MODE : 1; /*!< [2] Media Independent Interface Mode */
1867 uint32_t PROM : 1; /*!< [3] Promiscuous Mode */
1868 uint32_t BC_REJ : 1; /*!< [4] Broadcast Frame Reject */
1869 uint32_t FCE : 1; /*!< [5] Flow Control Enable */
1870 uint32_t RESERVED0 : 2; /*!< [7:6] */
1871 uint32_t RMII_MODE : 1; /*!< [8] RMII Mode Enable */
1872 uint32_t RMII_10T : 1; /*!< [9] */
1873 uint32_t RESERVED1 : 2; /*!< [11:10] */
1874 uint32_t PADEN : 1; /*!< [12] Enable Frame Padding Remove On Receive
1876 uint32_t PAUFWD : 1; /*!< [13] Terminate/Forward Pause Frames */
1877 uint32_t CRCFWD : 1; /*!< [14] Terminate/Forward Received CRC */
1878 uint32_t CFEN : 1; /*!< [15] MAC Control Frame Enable */
1879 uint32_t MAX_FL : 14; /*!< [29:16] Maximum Frame Length */
1880 uint32_t NLC : 1; /*!< [30] Payload Length Check Disable */
1881 uint32_t GRS : 1; /*!< [31] Graceful Receive Stopped */
1886 * @name Constants and macros for entire ENET_RCR register
1889 #define HW_ENET_RCR_ADDR(x) ((x) + 0x84U)
1891 #define HW_ENET_RCR(x) (*(__IO hw_enet_rcr_t *) HW_ENET_RCR_ADDR(x))
1892 #define HW_ENET_RCR_RD(x) (HW_ENET_RCR(x).U)
1893 #define HW_ENET_RCR_WR(x, v) (HW_ENET_RCR(x).U = (v))
1894 #define HW_ENET_RCR_SET(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) | (v)))
1895 #define HW_ENET_RCR_CLR(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) & ~(v)))
1896 #define HW_ENET_RCR_TOG(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) ^ (v)))
1900 * Constants & macros for individual ENET_RCR bitfields
1904 * @name Register ENET_RCR, field LOOP[0] (RW)
1906 * This is an MII internal loopback, therefore MII_MODE must be written to 1 and
1907 * RMII_MODE must be written to 0.
1910 * - 0 - Loopback disabled.
1911 * - 1 - Transmitted frames are looped back internal to the device and transmit
1912 * MII output signals are not asserted. DRT must be cleared.
1915 #define BP_ENET_RCR_LOOP (0U) /*!< Bit position for ENET_RCR_LOOP. */
1916 #define BM_ENET_RCR_LOOP (0x00000001U) /*!< Bit mask for ENET_RCR_LOOP. */
1917 #define BS_ENET_RCR_LOOP (1U) /*!< Bit field size in bits for ENET_RCR_LOOP. */
1919 /*! @brief Read current value of the ENET_RCR_LOOP field. */
1920 #define BR_ENET_RCR_LOOP(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP))
1922 /*! @brief Format value for bitfield ENET_RCR_LOOP. */
1923 #define BF_ENET_RCR_LOOP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_LOOP) & BM_ENET_RCR_LOOP)
1925 /*! @brief Set the LOOP field to a new value. */
1926 #define BW_ENET_RCR_LOOP(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP) = (v))
1930 * @name Register ENET_RCR, field DRT[1] (RW)
1933 * - 0 - Receive path operates independently of transmit. Used for full-duplex
1934 * or to monitor transmit activity in half-duplex mode.
1935 * - 1 - Disable reception of frames while transmitting. Normally used for
1939 #define BP_ENET_RCR_DRT (1U) /*!< Bit position for ENET_RCR_DRT. */
1940 #define BM_ENET_RCR_DRT (0x00000002U) /*!< Bit mask for ENET_RCR_DRT. */
1941 #define BS_ENET_RCR_DRT (1U) /*!< Bit field size in bits for ENET_RCR_DRT. */
1943 /*! @brief Read current value of the ENET_RCR_DRT field. */
1944 #define BR_ENET_RCR_DRT(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT))
1946 /*! @brief Format value for bitfield ENET_RCR_DRT. */
1947 #define BF_ENET_RCR_DRT(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_DRT) & BM_ENET_RCR_DRT)
1949 /*! @brief Set the DRT field to a new value. */
1950 #define BW_ENET_RCR_DRT(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT) = (v))
1954 * @name Register ENET_RCR, field MII_MODE[2] (RW)
1956 * This field must always be set.
1960 * - 1 - MII or RMII mode, as indicated by the RMII_MODE field.
1963 #define BP_ENET_RCR_MII_MODE (2U) /*!< Bit position for ENET_RCR_MII_MODE. */
1964 #define BM_ENET_RCR_MII_MODE (0x00000004U) /*!< Bit mask for ENET_RCR_MII_MODE. */
1965 #define BS_ENET_RCR_MII_MODE (1U) /*!< Bit field size in bits for ENET_RCR_MII_MODE. */
1967 /*! @brief Read current value of the ENET_RCR_MII_MODE field. */
1968 #define BR_ENET_RCR_MII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE))
1970 /*! @brief Format value for bitfield ENET_RCR_MII_MODE. */
1971 #define BF_ENET_RCR_MII_MODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_MII_MODE) & BM_ENET_RCR_MII_MODE)
1973 /*! @brief Set the MII_MODE field to a new value. */
1974 #define BW_ENET_RCR_MII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE) = (v))
1978 * @name Register ENET_RCR, field PROM[3] (RW)
1980 * All frames are accepted regardless of address matching.
1987 #define BP_ENET_RCR_PROM (3U) /*!< Bit position for ENET_RCR_PROM. */
1988 #define BM_ENET_RCR_PROM (0x00000008U) /*!< Bit mask for ENET_RCR_PROM. */
1989 #define BS_ENET_RCR_PROM (1U) /*!< Bit field size in bits for ENET_RCR_PROM. */
1991 /*! @brief Read current value of the ENET_RCR_PROM field. */
1992 #define BR_ENET_RCR_PROM(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM))
1994 /*! @brief Format value for bitfield ENET_RCR_PROM. */
1995 #define BF_ENET_RCR_PROM(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PROM) & BM_ENET_RCR_PROM)
1997 /*! @brief Set the PROM field to a new value. */
1998 #define BW_ENET_RCR_PROM(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM) = (v))
2002 * @name Register ENET_RCR, field BC_REJ[4] (RW)
2004 * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
2005 * rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
2006 * broadcast DA are accepted and the MISS (M) is set in the receive buffer
2010 #define BP_ENET_RCR_BC_REJ (4U) /*!< Bit position for ENET_RCR_BC_REJ. */
2011 #define BM_ENET_RCR_BC_REJ (0x00000010U) /*!< Bit mask for ENET_RCR_BC_REJ. */
2012 #define BS_ENET_RCR_BC_REJ (1U) /*!< Bit field size in bits for ENET_RCR_BC_REJ. */
2014 /*! @brief Read current value of the ENET_RCR_BC_REJ field. */
2015 #define BR_ENET_RCR_BC_REJ(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ))
2017 /*! @brief Format value for bitfield ENET_RCR_BC_REJ. */
2018 #define BF_ENET_RCR_BC_REJ(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_BC_REJ) & BM_ENET_RCR_BC_REJ)
2020 /*! @brief Set the BC_REJ field to a new value. */
2021 #define BW_ENET_RCR_BC_REJ(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ) = (v))
2025 * @name Register ENET_RCR, field FCE[5] (RW)
2027 * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
2028 * transmitter stops transmitting data frames for a given duration.
2031 #define BP_ENET_RCR_FCE (5U) /*!< Bit position for ENET_RCR_FCE. */
2032 #define BM_ENET_RCR_FCE (0x00000020U) /*!< Bit mask for ENET_RCR_FCE. */
2033 #define BS_ENET_RCR_FCE (1U) /*!< Bit field size in bits for ENET_RCR_FCE. */
2035 /*! @brief Read current value of the ENET_RCR_FCE field. */
2036 #define BR_ENET_RCR_FCE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE))
2038 /*! @brief Format value for bitfield ENET_RCR_FCE. */
2039 #define BF_ENET_RCR_FCE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_FCE) & BM_ENET_RCR_FCE)
2041 /*! @brief Set the FCE field to a new value. */
2042 #define BW_ENET_RCR_FCE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE) = (v))
2046 * @name Register ENET_RCR, field RMII_MODE[8] (RW)
2048 * Specifies whether the MAC is configured for MII mode or RMII operation .
2051 * - 0 - MAC configured for MII mode.
2052 * - 1 - MAC configured for RMII operation.
2055 #define BP_ENET_RCR_RMII_MODE (8U) /*!< Bit position for ENET_RCR_RMII_MODE. */
2056 #define BM_ENET_RCR_RMII_MODE (0x00000100U) /*!< Bit mask for ENET_RCR_RMII_MODE. */
2057 #define BS_ENET_RCR_RMII_MODE (1U) /*!< Bit field size in bits for ENET_RCR_RMII_MODE. */
2059 /*! @brief Read current value of the ENET_RCR_RMII_MODE field. */
2060 #define BR_ENET_RCR_RMII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE))
2062 /*! @brief Format value for bitfield ENET_RCR_RMII_MODE. */
2063 #define BF_ENET_RCR_RMII_MODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_RMII_MODE) & BM_ENET_RCR_RMII_MODE)
2065 /*! @brief Set the RMII_MODE field to a new value. */
2066 #define BW_ENET_RCR_RMII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE) = (v))
2070 * @name Register ENET_RCR, field RMII_10T[9] (RW)
2072 * Enables 10-Mbps mode of the RMII .
2075 * - 0 - 100 Mbps operation.
2076 * - 1 - 10 Mbps operation.
2079 #define BP_ENET_RCR_RMII_10T (9U) /*!< Bit position for ENET_RCR_RMII_10T. */
2080 #define BM_ENET_RCR_RMII_10T (0x00000200U) /*!< Bit mask for ENET_RCR_RMII_10T. */
2081 #define BS_ENET_RCR_RMII_10T (1U) /*!< Bit field size in bits for ENET_RCR_RMII_10T. */
2083 /*! @brief Read current value of the ENET_RCR_RMII_10T field. */
2084 #define BR_ENET_RCR_RMII_10T(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T))
2086 /*! @brief Format value for bitfield ENET_RCR_RMII_10T. */
2087 #define BF_ENET_RCR_RMII_10T(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_RMII_10T) & BM_ENET_RCR_RMII_10T)
2089 /*! @brief Set the RMII_10T field to a new value. */
2090 #define BW_ENET_RCR_RMII_10T(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T) = (v))
2094 * @name Register ENET_RCR, field PADEN[12] (RW)
2096 * Specifies whether the MAC removes padding from received frames.
2099 * - 0 - No padding is removed on receive by the MAC.
2100 * - 1 - Padding is removed from received frames.
2103 #define BP_ENET_RCR_PADEN (12U) /*!< Bit position for ENET_RCR_PADEN. */
2104 #define BM_ENET_RCR_PADEN (0x00001000U) /*!< Bit mask for ENET_RCR_PADEN. */
2105 #define BS_ENET_RCR_PADEN (1U) /*!< Bit field size in bits for ENET_RCR_PADEN. */
2107 /*! @brief Read current value of the ENET_RCR_PADEN field. */
2108 #define BR_ENET_RCR_PADEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN))
2110 /*! @brief Format value for bitfield ENET_RCR_PADEN. */
2111 #define BF_ENET_RCR_PADEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PADEN) & BM_ENET_RCR_PADEN)
2113 /*! @brief Set the PADEN field to a new value. */
2114 #define BW_ENET_RCR_PADEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN) = (v))
2118 * @name Register ENET_RCR, field PAUFWD[13] (RW)
2120 * Specifies whether pause frames are terminated or forwarded.
2123 * - 0 - Pause frames are terminated and discarded in the MAC.
2124 * - 1 - Pause frames are forwarded to the user application.
2127 #define BP_ENET_RCR_PAUFWD (13U) /*!< Bit position for ENET_RCR_PAUFWD. */
2128 #define BM_ENET_RCR_PAUFWD (0x00002000U) /*!< Bit mask for ENET_RCR_PAUFWD. */
2129 #define BS_ENET_RCR_PAUFWD (1U) /*!< Bit field size in bits for ENET_RCR_PAUFWD. */
2131 /*! @brief Read current value of the ENET_RCR_PAUFWD field. */
2132 #define BR_ENET_RCR_PAUFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD))
2134 /*! @brief Format value for bitfield ENET_RCR_PAUFWD. */
2135 #define BF_ENET_RCR_PAUFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PAUFWD) & BM_ENET_RCR_PAUFWD)
2137 /*! @brief Set the PAUFWD field to a new value. */
2138 #define BW_ENET_RCR_PAUFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD) = (v))
2142 * @name Register ENET_RCR, field CRCFWD[14] (RW)
2144 * Specifies whether the CRC field of received frames is transmitted or
2145 * stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
2146 * field is checked and always terminated and removed.
2149 * - 0 - The CRC field of received frames is transmitted to the user application.
2150 * - 1 - The CRC field is stripped from the frame.
2153 #define BP_ENET_RCR_CRCFWD (14U) /*!< Bit position for ENET_RCR_CRCFWD. */
2154 #define BM_ENET_RCR_CRCFWD (0x00004000U) /*!< Bit mask for ENET_RCR_CRCFWD. */
2155 #define BS_ENET_RCR_CRCFWD (1U) /*!< Bit field size in bits for ENET_RCR_CRCFWD. */
2157 /*! @brief Read current value of the ENET_RCR_CRCFWD field. */
2158 #define BR_ENET_RCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD))
2160 /*! @brief Format value for bitfield ENET_RCR_CRCFWD. */
2161 #define BF_ENET_RCR_CRCFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_CRCFWD) & BM_ENET_RCR_CRCFWD)
2163 /*! @brief Set the CRCFWD field to a new value. */
2164 #define BW_ENET_RCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD) = (v))
2168 * @name Register ENET_RCR, field CFEN[15] (RW)
2170 * Enables/disables the MAC control frame.
2173 * - 0 - MAC control frames with any opcode other than 0x0001 (pause frame) are
2174 * accepted and forwarded to the client interface.
2175 * - 1 - MAC control frames with any opcode other than 0x0001 (pause frame) are
2176 * silently discarded.
2179 #define BP_ENET_RCR_CFEN (15U) /*!< Bit position for ENET_RCR_CFEN. */
2180 #define BM_ENET_RCR_CFEN (0x00008000U) /*!< Bit mask for ENET_RCR_CFEN. */
2181 #define BS_ENET_RCR_CFEN (1U) /*!< Bit field size in bits for ENET_RCR_CFEN. */
2183 /*! @brief Read current value of the ENET_RCR_CFEN field. */
2184 #define BR_ENET_RCR_CFEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN))
2186 /*! @brief Format value for bitfield ENET_RCR_CFEN. */
2187 #define BF_ENET_RCR_CFEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_CFEN) & BM_ENET_RCR_CFEN)
2189 /*! @brief Set the CFEN field to a new value. */
2190 #define BW_ENET_RCR_CFEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN) = (v))
2194 * @name Register ENET_RCR, field MAX_FL[29:16] (RW)
2196 * Resets to decimal 1518. Length is measured starting at DA and includes the
2197 * CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
2198 * interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
2199 * to occur and set the LG field in the end of frame receive buffer descriptor.
2200 * The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
2204 #define BP_ENET_RCR_MAX_FL (16U) /*!< Bit position for ENET_RCR_MAX_FL. */
2205 #define BM_ENET_RCR_MAX_FL (0x3FFF0000U) /*!< Bit mask for ENET_RCR_MAX_FL. */
2206 #define BS_ENET_RCR_MAX_FL (14U) /*!< Bit field size in bits for ENET_RCR_MAX_FL. */
2208 /*! @brief Read current value of the ENET_RCR_MAX_FL field. */
2209 #define BR_ENET_RCR_MAX_FL(x) (HW_ENET_RCR(x).B.MAX_FL)
2211 /*! @brief Format value for bitfield ENET_RCR_MAX_FL. */
2212 #define BF_ENET_RCR_MAX_FL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_MAX_FL) & BM_ENET_RCR_MAX_FL)
2214 /*! @brief Set the MAX_FL field to a new value. */
2215 #define BW_ENET_RCR_MAX_FL(x, v) (HW_ENET_RCR_WR(x, (HW_ENET_RCR_RD(x) & ~BM_ENET_RCR_MAX_FL) | BF_ENET_RCR_MAX_FL(v)))
2219 * @name Register ENET_RCR, field NLC[30] (RW)
2221 * Enables/disables a payload length check.
2224 * - 0 - The payload length check is disabled.
2225 * - 1 - The core checks the frame's payload length with the frame length/type
2226 * field. Errors are indicated in the EIR[PLC] field.
2229 #define BP_ENET_RCR_NLC (30U) /*!< Bit position for ENET_RCR_NLC. */
2230 #define BM_ENET_RCR_NLC (0x40000000U) /*!< Bit mask for ENET_RCR_NLC. */
2231 #define BS_ENET_RCR_NLC (1U) /*!< Bit field size in bits for ENET_RCR_NLC. */
2233 /*! @brief Read current value of the ENET_RCR_NLC field. */
2234 #define BR_ENET_RCR_NLC(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC))
2236 /*! @brief Format value for bitfield ENET_RCR_NLC. */
2237 #define BF_ENET_RCR_NLC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_NLC) & BM_ENET_RCR_NLC)
2239 /*! @brief Set the NLC field to a new value. */
2240 #define BW_ENET_RCR_NLC(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC) = (v))
2244 * @name Register ENET_RCR, field GRS[31] (RO)
2246 * Read-only status indicating that the MAC receive datapath is stopped.
2249 #define BP_ENET_RCR_GRS (31U) /*!< Bit position for ENET_RCR_GRS. */
2250 #define BM_ENET_RCR_GRS (0x80000000U) /*!< Bit mask for ENET_RCR_GRS. */
2251 #define BS_ENET_RCR_GRS (1U) /*!< Bit field size in bits for ENET_RCR_GRS. */
2253 /*! @brief Read current value of the ENET_RCR_GRS field. */
2254 #define BR_ENET_RCR_GRS(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_GRS))
2257 /*******************************************************************************
2258 * HW_ENET_TCR - Transmit Control Register
2259 ******************************************************************************/
2262 * @brief HW_ENET_TCR - Transmit Control Register (RW)
2264 * Reset value: 0x00000000U
2266 * TCR is read/write and configures the transmit block. This register is cleared
2267 * at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
2269 typedef union _hw_enet_tcr
2272 struct _hw_enet_tcr_bitfields
2274 uint32_t GTS : 1; /*!< [0] Graceful Transmit Stop */
2275 uint32_t RESERVED0 : 1; /*!< [1] */
2276 uint32_t FDEN : 1; /*!< [2] Full-Duplex Enable */
2277 uint32_t TFC_PAUSE : 1; /*!< [3] Transmit Frame Control Pause */
2278 uint32_t RFC_PAUSE : 1; /*!< [4] Receive Frame Control Pause */
2279 uint32_t ADDSEL : 3; /*!< [7:5] Source MAC Address Select On Transmit
2281 uint32_t ADDINS : 1; /*!< [8] Set MAC Address On Transmit */
2282 uint32_t CRCFWD : 1; /*!< [9] Forward Frame From Application With CRC
2284 uint32_t RESERVED1 : 22; /*!< [31:10] */
2289 * @name Constants and macros for entire ENET_TCR register
2292 #define HW_ENET_TCR_ADDR(x) ((x) + 0xC4U)
2294 #define HW_ENET_TCR(x) (*(__IO hw_enet_tcr_t *) HW_ENET_TCR_ADDR(x))
2295 #define HW_ENET_TCR_RD(x) (HW_ENET_TCR(x).U)
2296 #define HW_ENET_TCR_WR(x, v) (HW_ENET_TCR(x).U = (v))
2297 #define HW_ENET_TCR_SET(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) | (v)))
2298 #define HW_ENET_TCR_CLR(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) & ~(v)))
2299 #define HW_ENET_TCR_TOG(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) ^ (v)))
2303 * Constants & macros for individual ENET_TCR bitfields
2307 * @name Register ENET_TCR, field GTS[0] (RW)
2309 * When this field is set, MAC stops transmission after any frame currently
2310 * transmitted is complete and EIR[GRA] is set. If frame transmission is not
2311 * currently underway, the GRA interrupt is asserted immediately. After transmission
2312 * finishes, clear GTS to restart. The next frame in the transmit FIFO is then
2313 * transmitted. If an early collision occurs during transmission when GTS is set,
2314 * transmission stops after the collision. The frame is transmitted again after GTS is
2315 * cleared. There may be old frames in the transmit FIFO that transmit when GTS
2316 * is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
2319 #define BP_ENET_TCR_GTS (0U) /*!< Bit position for ENET_TCR_GTS. */
2320 #define BM_ENET_TCR_GTS (0x00000001U) /*!< Bit mask for ENET_TCR_GTS. */
2321 #define BS_ENET_TCR_GTS (1U) /*!< Bit field size in bits for ENET_TCR_GTS. */
2323 /*! @brief Read current value of the ENET_TCR_GTS field. */
2324 #define BR_ENET_TCR_GTS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS))
2326 /*! @brief Format value for bitfield ENET_TCR_GTS. */
2327 #define BF_ENET_TCR_GTS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_GTS) & BM_ENET_TCR_GTS)
2329 /*! @brief Set the GTS field to a new value. */
2330 #define BW_ENET_TCR_GTS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS) = (v))
2334 * @name Register ENET_TCR, field FDEN[2] (RW)
2336 * If this field is set, frames transmit independent of carrier sense and
2337 * collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
2340 #define BP_ENET_TCR_FDEN (2U) /*!< Bit position for ENET_TCR_FDEN. */
2341 #define BM_ENET_TCR_FDEN (0x00000004U) /*!< Bit mask for ENET_TCR_FDEN. */
2342 #define BS_ENET_TCR_FDEN (1U) /*!< Bit field size in bits for ENET_TCR_FDEN. */
2344 /*! @brief Read current value of the ENET_TCR_FDEN field. */
2345 #define BR_ENET_TCR_FDEN(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN))
2347 /*! @brief Format value for bitfield ENET_TCR_FDEN. */
2348 #define BF_ENET_TCR_FDEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_FDEN) & BM_ENET_TCR_FDEN)
2350 /*! @brief Set the FDEN field to a new value. */
2351 #define BW_ENET_TCR_FDEN(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN) = (v))
2355 * @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
2357 * Pauses frame transmission. When this field is set, EIR[GRA] is set. With
2358 * transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
2359 * Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
2360 * transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
2361 * the MAC may continue transmitting a MAC control PAUSE frame.
2364 * - 0 - No PAUSE frame transmitted.
2365 * - 1 - The MAC stops transmission of data frames after the current
2366 * transmission is complete.
2369 #define BP_ENET_TCR_TFC_PAUSE (3U) /*!< Bit position for ENET_TCR_TFC_PAUSE. */
2370 #define BM_ENET_TCR_TFC_PAUSE (0x00000008U) /*!< Bit mask for ENET_TCR_TFC_PAUSE. */
2371 #define BS_ENET_TCR_TFC_PAUSE (1U) /*!< Bit field size in bits for ENET_TCR_TFC_PAUSE. */
2373 /*! @brief Read current value of the ENET_TCR_TFC_PAUSE field. */
2374 #define BR_ENET_TCR_TFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE))
2376 /*! @brief Format value for bitfield ENET_TCR_TFC_PAUSE. */
2377 #define BF_ENET_TCR_TFC_PAUSE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_TFC_PAUSE) & BM_ENET_TCR_TFC_PAUSE)
2379 /*! @brief Set the TFC_PAUSE field to a new value. */
2380 #define BW_ENET_TCR_TFC_PAUSE(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE) = (v))
2384 * @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
2386 * This status field is set when a full-duplex flow control pause frame is
2387 * received and the transmitter pauses for the duration defined in this pause frame.
2388 * This field automatically clears when the pause duration is complete.
2391 #define BP_ENET_TCR_RFC_PAUSE (4U) /*!< Bit position for ENET_TCR_RFC_PAUSE. */
2392 #define BM_ENET_TCR_RFC_PAUSE (0x00000010U) /*!< Bit mask for ENET_TCR_RFC_PAUSE. */
2393 #define BS_ENET_TCR_RFC_PAUSE (1U) /*!< Bit field size in bits for ENET_TCR_RFC_PAUSE. */
2395 /*! @brief Read current value of the ENET_TCR_RFC_PAUSE field. */
2396 #define BR_ENET_TCR_RFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_RFC_PAUSE))
2400 * @name Register ENET_TCR, field ADDSEL[7:5] (RW)
2402 * If ADDINS is set, indicates the MAC address that overwrites the source MAC
2406 * - 000 - Node MAC address programmed on PADDR1/2 registers.
2412 #define BP_ENET_TCR_ADDSEL (5U) /*!< Bit position for ENET_TCR_ADDSEL. */
2413 #define BM_ENET_TCR_ADDSEL (0x000000E0U) /*!< Bit mask for ENET_TCR_ADDSEL. */
2414 #define BS_ENET_TCR_ADDSEL (3U) /*!< Bit field size in bits for ENET_TCR_ADDSEL. */
2416 /*! @brief Read current value of the ENET_TCR_ADDSEL field. */
2417 #define BR_ENET_TCR_ADDSEL(x) (HW_ENET_TCR(x).B.ADDSEL)
2419 /*! @brief Format value for bitfield ENET_TCR_ADDSEL. */
2420 #define BF_ENET_TCR_ADDSEL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_ADDSEL) & BM_ENET_TCR_ADDSEL)
2422 /*! @brief Set the ADDSEL field to a new value. */
2423 #define BW_ENET_TCR_ADDSEL(x, v) (HW_ENET_TCR_WR(x, (HW_ENET_TCR_RD(x) & ~BM_ENET_TCR_ADDSEL) | BF_ENET_TCR_ADDSEL(v)))
2427 * @name Register ENET_TCR, field ADDINS[8] (RW)
2430 * - 0 - The source MAC address is not modified by the MAC.
2431 * - 1 - The MAC overwrites the source MAC address with the programmed MAC
2432 * address according to ADDSEL.
2435 #define BP_ENET_TCR_ADDINS (8U) /*!< Bit position for ENET_TCR_ADDINS. */
2436 #define BM_ENET_TCR_ADDINS (0x00000100U) /*!< Bit mask for ENET_TCR_ADDINS. */
2437 #define BS_ENET_TCR_ADDINS (1U) /*!< Bit field size in bits for ENET_TCR_ADDINS. */
2439 /*! @brief Read current value of the ENET_TCR_ADDINS field. */
2440 #define BR_ENET_TCR_ADDINS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS))
2442 /*! @brief Format value for bitfield ENET_TCR_ADDINS. */
2443 #define BF_ENET_TCR_ADDINS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_ADDINS) & BM_ENET_TCR_ADDINS)
2445 /*! @brief Set the ADDINS field to a new value. */
2446 #define BW_ENET_TCR_ADDINS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS) = (v))
2450 * @name Register ENET_TCR, field CRCFWD[9] (RW)
2453 * - 0 - TxBD[TC] controls whether the frame has a CRC from the application.
2454 * - 1 - The transmitter does not append any CRC to transmitted frames, as it is
2455 * expecting a frame with CRC from the application.
2458 #define BP_ENET_TCR_CRCFWD (9U) /*!< Bit position for ENET_TCR_CRCFWD. */
2459 #define BM_ENET_TCR_CRCFWD (0x00000200U) /*!< Bit mask for ENET_TCR_CRCFWD. */
2460 #define BS_ENET_TCR_CRCFWD (1U) /*!< Bit field size in bits for ENET_TCR_CRCFWD. */
2462 /*! @brief Read current value of the ENET_TCR_CRCFWD field. */
2463 #define BR_ENET_TCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD))
2465 /*! @brief Format value for bitfield ENET_TCR_CRCFWD. */
2466 #define BF_ENET_TCR_CRCFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_CRCFWD) & BM_ENET_TCR_CRCFWD)
2468 /*! @brief Set the CRCFWD field to a new value. */
2469 #define BW_ENET_TCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD) = (v))
2472 /*******************************************************************************
2473 * HW_ENET_PALR - Physical Address Lower Register
2474 ******************************************************************************/
2477 * @brief HW_ENET_PALR - Physical Address Lower Register (RW)
2479 * Reset value: 0x00000000U
2481 * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
2482 * in the address recognition process to compare with the destination address
2483 * (DA) field of receive frames with an individual DA. In addition, this register
2484 * is used in bytes 0 through 3 of the six-byte source address field when
2485 * transmitting PAUSE frames. This register is not reset and you must initialize it.
2487 typedef union _hw_enet_palr
2490 struct _hw_enet_palr_bitfields
2492 uint32_t PADDR1 : 32; /*!< [31:0] Pause Address */
2497 * @name Constants and macros for entire ENET_PALR register
2500 #define HW_ENET_PALR_ADDR(x) ((x) + 0xE4U)
2502 #define HW_ENET_PALR(x) (*(__IO hw_enet_palr_t *) HW_ENET_PALR_ADDR(x))
2503 #define HW_ENET_PALR_RD(x) (HW_ENET_PALR(x).U)
2504 #define HW_ENET_PALR_WR(x, v) (HW_ENET_PALR(x).U = (v))
2505 #define HW_ENET_PALR_SET(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) | (v)))
2506 #define HW_ENET_PALR_CLR(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) & ~(v)))
2507 #define HW_ENET_PALR_TOG(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) ^ (v)))
2511 * Constants & macros for individual ENET_PALR bitfields
2515 * @name Register ENET_PALR, field PADDR1[31:0] (RW)
2517 * Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the
2518 * 6-byte individual address are used for exact match and the source address
2519 * field in PAUSE frames.
2522 #define BP_ENET_PALR_PADDR1 (0U) /*!< Bit position for ENET_PALR_PADDR1. */
2523 #define BM_ENET_PALR_PADDR1 (0xFFFFFFFFU) /*!< Bit mask for ENET_PALR_PADDR1. */
2524 #define BS_ENET_PALR_PADDR1 (32U) /*!< Bit field size in bits for ENET_PALR_PADDR1. */
2526 /*! @brief Read current value of the ENET_PALR_PADDR1 field. */
2527 #define BR_ENET_PALR_PADDR1(x) (HW_ENET_PALR(x).U)
2529 /*! @brief Format value for bitfield ENET_PALR_PADDR1. */
2530 #define BF_ENET_PALR_PADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_PALR_PADDR1) & BM_ENET_PALR_PADDR1)
2532 /*! @brief Set the PADDR1 field to a new value. */
2533 #define BW_ENET_PALR_PADDR1(x, v) (HW_ENET_PALR_WR(x, v))
2536 /*******************************************************************************
2537 * HW_ENET_PAUR - Physical Address Upper Register
2538 ******************************************************************************/
2541 * @brief HW_ENET_PAUR - Physical Address Upper Register (RW)
2543 * Reset value: 0x00008808U
2545 * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
2546 * the address recognition process to compare with the destination address (DA)
2547 * field of receive frames with an individual DA. In addition, this register is
2548 * used in bytes 4 and 5 of the six-byte source address field when transmitting
2549 * PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
2550 * transmission of PAUSE frames. The upper 16 bits of this register are not reset and
2551 * you must initialize it.
2553 typedef union _hw_enet_paur
2556 struct _hw_enet_paur_bitfields
2558 uint32_t TYPE : 16; /*!< [15:0] Type Field In PAUSE Frames */
2559 uint32_t PADDR2 : 16; /*!< [31:16] */
2564 * @name Constants and macros for entire ENET_PAUR register
2567 #define HW_ENET_PAUR_ADDR(x) ((x) + 0xE8U)
2569 #define HW_ENET_PAUR(x) (*(__IO hw_enet_paur_t *) HW_ENET_PAUR_ADDR(x))
2570 #define HW_ENET_PAUR_RD(x) (HW_ENET_PAUR(x).U)
2571 #define HW_ENET_PAUR_WR(x, v) (HW_ENET_PAUR(x).U = (v))
2572 #define HW_ENET_PAUR_SET(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) | (v)))
2573 #define HW_ENET_PAUR_CLR(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) & ~(v)))
2574 #define HW_ENET_PAUR_TOG(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) ^ (v)))
2578 * Constants & macros for individual ENET_PAUR bitfields
2582 * @name Register ENET_PAUR, field TYPE[15:0] (RO)
2584 * These fields have a constant value of 0x8808.
2587 #define BP_ENET_PAUR_TYPE (0U) /*!< Bit position for ENET_PAUR_TYPE. */
2588 #define BM_ENET_PAUR_TYPE (0x0000FFFFU) /*!< Bit mask for ENET_PAUR_TYPE. */
2589 #define BS_ENET_PAUR_TYPE (16U) /*!< Bit field size in bits for ENET_PAUR_TYPE. */
2591 /*! @brief Read current value of the ENET_PAUR_TYPE field. */
2592 #define BR_ENET_PAUR_TYPE(x) (HW_ENET_PAUR(x).B.TYPE)
2596 * @name Register ENET_PAUR, field PADDR2[31:16] (RW)
2598 * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
2599 * for exact match, and the source address field in PAUSE frames.
2602 #define BP_ENET_PAUR_PADDR2 (16U) /*!< Bit position for ENET_PAUR_PADDR2. */
2603 #define BM_ENET_PAUR_PADDR2 (0xFFFF0000U) /*!< Bit mask for ENET_PAUR_PADDR2. */
2604 #define BS_ENET_PAUR_PADDR2 (16U) /*!< Bit field size in bits for ENET_PAUR_PADDR2. */
2606 /*! @brief Read current value of the ENET_PAUR_PADDR2 field. */
2607 #define BR_ENET_PAUR_PADDR2(x) (HW_ENET_PAUR(x).B.PADDR2)
2609 /*! @brief Format value for bitfield ENET_PAUR_PADDR2. */
2610 #define BF_ENET_PAUR_PADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_PAUR_PADDR2) & BM_ENET_PAUR_PADDR2)
2612 /*! @brief Set the PADDR2 field to a new value. */
2613 #define BW_ENET_PAUR_PADDR2(x, v) (HW_ENET_PAUR_WR(x, (HW_ENET_PAUR_RD(x) & ~BM_ENET_PAUR_PADDR2) | BF_ENET_PAUR_PADDR2(v)))
2616 /*******************************************************************************
2617 * HW_ENET_OPD - Opcode/Pause Duration Register
2618 ******************************************************************************/
2621 * @brief HW_ENET_OPD - Opcode/Pause Duration Register (RW)
2623 * Reset value: 0x00010000U
2625 * OPD is read/write accessible. This register contains the 16-bit opcode and
2626 * 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
2627 * field is a constant value, 0x0001. When another node detects a PAUSE frame,
2628 * that node pauses transmission for the duration specified in the pause duration
2629 * field. The lower 16 bits of this register are not reset and you must initialize
2632 typedef union _hw_enet_opd
2635 struct _hw_enet_opd_bitfields
2637 uint32_t PAUSE_DUR : 16; /*!< [15:0] Pause Duration */
2638 uint32_t OPCODE : 16; /*!< [31:16] Opcode Field In PAUSE Frames */
2643 * @name Constants and macros for entire ENET_OPD register
2646 #define HW_ENET_OPD_ADDR(x) ((x) + 0xECU)
2648 #define HW_ENET_OPD(x) (*(__IO hw_enet_opd_t *) HW_ENET_OPD_ADDR(x))
2649 #define HW_ENET_OPD_RD(x) (HW_ENET_OPD(x).U)
2650 #define HW_ENET_OPD_WR(x, v) (HW_ENET_OPD(x).U = (v))
2651 #define HW_ENET_OPD_SET(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) | (v)))
2652 #define HW_ENET_OPD_CLR(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) & ~(v)))
2653 #define HW_ENET_OPD_TOG(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) ^ (v)))
2657 * Constants & macros for individual ENET_OPD bitfields
2661 * @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
2663 * Pause duration field used in PAUSE frames.
2666 #define BP_ENET_OPD_PAUSE_DUR (0U) /*!< Bit position for ENET_OPD_PAUSE_DUR. */
2667 #define BM_ENET_OPD_PAUSE_DUR (0x0000FFFFU) /*!< Bit mask for ENET_OPD_PAUSE_DUR. */
2668 #define BS_ENET_OPD_PAUSE_DUR (16U) /*!< Bit field size in bits for ENET_OPD_PAUSE_DUR. */
2670 /*! @brief Read current value of the ENET_OPD_PAUSE_DUR field. */
2671 #define BR_ENET_OPD_PAUSE_DUR(x) (HW_ENET_OPD(x).B.PAUSE_DUR)
2673 /*! @brief Format value for bitfield ENET_OPD_PAUSE_DUR. */
2674 #define BF_ENET_OPD_PAUSE_DUR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_OPD_PAUSE_DUR) & BM_ENET_OPD_PAUSE_DUR)
2676 /*! @brief Set the PAUSE_DUR field to a new value. */
2677 #define BW_ENET_OPD_PAUSE_DUR(x, v) (HW_ENET_OPD_WR(x, (HW_ENET_OPD_RD(x) & ~BM_ENET_OPD_PAUSE_DUR) | BF_ENET_OPD_PAUSE_DUR(v)))
2681 * @name Register ENET_OPD, field OPCODE[31:16] (RO)
2683 * These fields have a constant value of 0x0001.
2686 #define BP_ENET_OPD_OPCODE (16U) /*!< Bit position for ENET_OPD_OPCODE. */
2687 #define BM_ENET_OPD_OPCODE (0xFFFF0000U) /*!< Bit mask for ENET_OPD_OPCODE. */
2688 #define BS_ENET_OPD_OPCODE (16U) /*!< Bit field size in bits for ENET_OPD_OPCODE. */
2690 /*! @brief Read current value of the ENET_OPD_OPCODE field. */
2691 #define BR_ENET_OPD_OPCODE(x) (HW_ENET_OPD(x).B.OPCODE)
2694 /*******************************************************************************
2695 * HW_ENET_IAUR - Descriptor Individual Upper Address Register
2696 ******************************************************************************/
2699 * @brief HW_ENET_IAUR - Descriptor Individual Upper Address Register (RW)
2701 * Reset value: 0x00000000U
2703 * IAUR contains the upper 32 bits of the 64-bit individual address hash table.
2704 * The address recognition process uses this table to check for a possible match
2705 * with the destination address (DA) field of receive frames with an individual
2706 * DA. This register is not reset and you must initialize it.
2708 typedef union _hw_enet_iaur
2711 struct _hw_enet_iaur_bitfields
2713 uint32_t IADDR1 : 32; /*!< [31:0] */
2718 * @name Constants and macros for entire ENET_IAUR register
2721 #define HW_ENET_IAUR_ADDR(x) ((x) + 0x118U)
2723 #define HW_ENET_IAUR(x) (*(__IO hw_enet_iaur_t *) HW_ENET_IAUR_ADDR(x))
2724 #define HW_ENET_IAUR_RD(x) (HW_ENET_IAUR(x).U)
2725 #define HW_ENET_IAUR_WR(x, v) (HW_ENET_IAUR(x).U = (v))
2726 #define HW_ENET_IAUR_SET(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) | (v)))
2727 #define HW_ENET_IAUR_CLR(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) & ~(v)))
2728 #define HW_ENET_IAUR_TOG(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) ^ (v)))
2732 * Constants & macros for individual ENET_IAUR bitfields
2736 * @name Register ENET_IAUR, field IADDR1[31:0] (RW)
2738 * Contains the upper 32 bits of the 64-bit hash table used in the address
2739 * recognition process for receive frames with a unicast address. Bit 31 of IADDR1
2740 * contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
2743 #define BP_ENET_IAUR_IADDR1 (0U) /*!< Bit position for ENET_IAUR_IADDR1. */
2744 #define BM_ENET_IAUR_IADDR1 (0xFFFFFFFFU) /*!< Bit mask for ENET_IAUR_IADDR1. */
2745 #define BS_ENET_IAUR_IADDR1 (32U) /*!< Bit field size in bits for ENET_IAUR_IADDR1. */
2747 /*! @brief Read current value of the ENET_IAUR_IADDR1 field. */
2748 #define BR_ENET_IAUR_IADDR1(x) (HW_ENET_IAUR(x).U)
2750 /*! @brief Format value for bitfield ENET_IAUR_IADDR1. */
2751 #define BF_ENET_IAUR_IADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_IAUR_IADDR1) & BM_ENET_IAUR_IADDR1)
2753 /*! @brief Set the IADDR1 field to a new value. */
2754 #define BW_ENET_IAUR_IADDR1(x, v) (HW_ENET_IAUR_WR(x, v))
2757 /*******************************************************************************
2758 * HW_ENET_IALR - Descriptor Individual Lower Address Register
2759 ******************************************************************************/
2762 * @brief HW_ENET_IALR - Descriptor Individual Lower Address Register (RW)
2764 * Reset value: 0x00000000U
2766 * IALR contains the lower 32 bits of the 64-bit individual address hash table.
2767 * The address recognition process uses this table to check for a possible match
2768 * with the DA field of receive frames with an individual DA. This register is
2769 * not reset and you must initialize it.
2771 typedef union _hw_enet_ialr
2774 struct _hw_enet_ialr_bitfields
2776 uint32_t IADDR2 : 32; /*!< [31:0] */
2781 * @name Constants and macros for entire ENET_IALR register
2784 #define HW_ENET_IALR_ADDR(x) ((x) + 0x11CU)
2786 #define HW_ENET_IALR(x) (*(__IO hw_enet_ialr_t *) HW_ENET_IALR_ADDR(x))
2787 #define HW_ENET_IALR_RD(x) (HW_ENET_IALR(x).U)
2788 #define HW_ENET_IALR_WR(x, v) (HW_ENET_IALR(x).U = (v))
2789 #define HW_ENET_IALR_SET(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) | (v)))
2790 #define HW_ENET_IALR_CLR(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) & ~(v)))
2791 #define HW_ENET_IALR_TOG(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) ^ (v)))
2795 * Constants & macros for individual ENET_IALR bitfields
2799 * @name Register ENET_IALR, field IADDR2[31:0] (RW)
2801 * Contains the lower 32 bits of the 64-bit hash table used in the address
2802 * recognition process for receive frames with a unicast address. Bit 31 of IADDR2
2803 * contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
2806 #define BP_ENET_IALR_IADDR2 (0U) /*!< Bit position for ENET_IALR_IADDR2. */
2807 #define BM_ENET_IALR_IADDR2 (0xFFFFFFFFU) /*!< Bit mask for ENET_IALR_IADDR2. */
2808 #define BS_ENET_IALR_IADDR2 (32U) /*!< Bit field size in bits for ENET_IALR_IADDR2. */
2810 /*! @brief Read current value of the ENET_IALR_IADDR2 field. */
2811 #define BR_ENET_IALR_IADDR2(x) (HW_ENET_IALR(x).U)
2813 /*! @brief Format value for bitfield ENET_IALR_IADDR2. */
2814 #define BF_ENET_IALR_IADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_IALR_IADDR2) & BM_ENET_IALR_IADDR2)
2816 /*! @brief Set the IADDR2 field to a new value. */
2817 #define BW_ENET_IALR_IADDR2(x, v) (HW_ENET_IALR_WR(x, v))
2820 /*******************************************************************************
2821 * HW_ENET_GAUR - Descriptor Group Upper Address Register
2822 ******************************************************************************/
2825 * @brief HW_ENET_GAUR - Descriptor Group Upper Address Register (RW)
2827 * Reset value: 0x00000000U
2829 * GAUR contains the upper 32 bits of the 64-bit hash table used in the address
2830 * recognition process for receive frames with a multicast address. You must
2831 * initialize this register.
2833 typedef union _hw_enet_gaur
2836 struct _hw_enet_gaur_bitfields
2838 uint32_t GADDR1 : 32; /*!< [31:0] */
2843 * @name Constants and macros for entire ENET_GAUR register
2846 #define HW_ENET_GAUR_ADDR(x) ((x) + 0x120U)
2848 #define HW_ENET_GAUR(x) (*(__IO hw_enet_gaur_t *) HW_ENET_GAUR_ADDR(x))
2849 #define HW_ENET_GAUR_RD(x) (HW_ENET_GAUR(x).U)
2850 #define HW_ENET_GAUR_WR(x, v) (HW_ENET_GAUR(x).U = (v))
2851 #define HW_ENET_GAUR_SET(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) | (v)))
2852 #define HW_ENET_GAUR_CLR(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) & ~(v)))
2853 #define HW_ENET_GAUR_TOG(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) ^ (v)))
2857 * Constants & macros for individual ENET_GAUR bitfields
2861 * @name Register ENET_GAUR, field GADDR1[31:0] (RW)
2863 * Contains the upper 32 bits of the 64-bit hash table used in the address
2864 * recognition process for receive frames with a multicast address. Bit 31 of GADDR1
2865 * contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
2868 #define BP_ENET_GAUR_GADDR1 (0U) /*!< Bit position for ENET_GAUR_GADDR1. */
2869 #define BM_ENET_GAUR_GADDR1 (0xFFFFFFFFU) /*!< Bit mask for ENET_GAUR_GADDR1. */
2870 #define BS_ENET_GAUR_GADDR1 (32U) /*!< Bit field size in bits for ENET_GAUR_GADDR1. */
2872 /*! @brief Read current value of the ENET_GAUR_GADDR1 field. */
2873 #define BR_ENET_GAUR_GADDR1(x) (HW_ENET_GAUR(x).U)
2875 /*! @brief Format value for bitfield ENET_GAUR_GADDR1. */
2876 #define BF_ENET_GAUR_GADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_GAUR_GADDR1) & BM_ENET_GAUR_GADDR1)
2878 /*! @brief Set the GADDR1 field to a new value. */
2879 #define BW_ENET_GAUR_GADDR1(x, v) (HW_ENET_GAUR_WR(x, v))
2882 /*******************************************************************************
2883 * HW_ENET_GALR - Descriptor Group Lower Address Register
2884 ******************************************************************************/
2887 * @brief HW_ENET_GALR - Descriptor Group Lower Address Register (RW)
2889 * Reset value: 0x00000000U
2891 * GALR contains the lower 32 bits of the 64-bit hash table used in the address
2892 * recognition process for receive frames with a multicast address. You must
2893 * initialize this register.
2895 typedef union _hw_enet_galr
2898 struct _hw_enet_galr_bitfields
2900 uint32_t GADDR2 : 32; /*!< [31:0] */
2905 * @name Constants and macros for entire ENET_GALR register
2908 #define HW_ENET_GALR_ADDR(x) ((x) + 0x124U)
2910 #define HW_ENET_GALR(x) (*(__IO hw_enet_galr_t *) HW_ENET_GALR_ADDR(x))
2911 #define HW_ENET_GALR_RD(x) (HW_ENET_GALR(x).U)
2912 #define HW_ENET_GALR_WR(x, v) (HW_ENET_GALR(x).U = (v))
2913 #define HW_ENET_GALR_SET(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) | (v)))
2914 #define HW_ENET_GALR_CLR(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) & ~(v)))
2915 #define HW_ENET_GALR_TOG(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) ^ (v)))
2919 * Constants & macros for individual ENET_GALR bitfields
2923 * @name Register ENET_GALR, field GADDR2[31:0] (RW)
2925 * Contains the lower 32 bits of the 64-bit hash table used in the address
2926 * recognition process for receive frames with a multicast address. Bit 31 of GADDR2
2927 * contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
2930 #define BP_ENET_GALR_GADDR2 (0U) /*!< Bit position for ENET_GALR_GADDR2. */
2931 #define BM_ENET_GALR_GADDR2 (0xFFFFFFFFU) /*!< Bit mask for ENET_GALR_GADDR2. */
2932 #define BS_ENET_GALR_GADDR2 (32U) /*!< Bit field size in bits for ENET_GALR_GADDR2. */
2934 /*! @brief Read current value of the ENET_GALR_GADDR2 field. */
2935 #define BR_ENET_GALR_GADDR2(x) (HW_ENET_GALR(x).U)
2937 /*! @brief Format value for bitfield ENET_GALR_GADDR2. */
2938 #define BF_ENET_GALR_GADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_GALR_GADDR2) & BM_ENET_GALR_GADDR2)
2940 /*! @brief Set the GADDR2 field to a new value. */
2941 #define BW_ENET_GALR_GADDR2(x, v) (HW_ENET_GALR_WR(x, v))
2944 /*******************************************************************************
2945 * HW_ENET_TFWR - Transmit FIFO Watermark Register
2946 ******************************************************************************/
2949 * @brief HW_ENET_TFWR - Transmit FIFO Watermark Register (RW)
2951 * Reset value: 0x00000000U
2953 * If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
2954 * in the transmit FIFO before transmission of a frame can begin. This allows you
2955 * to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
2956 * latency (TFWR = 11) due to contention for the system bus. Setting the
2957 * watermark to a high value minimizes the risk of transmit FIFO underrun due to
2958 * contention for the system bus. The byte counts associated with the TFWR field may need
2959 * to be modified to match a given system requirement. For example, worst case
2960 * bus access latency by the transmit data DMA channel. When the FIFO level
2961 * reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
2962 * transmit control logic starts frame transmission even before the end-of-frame is
2963 * available in the FIFO (cut-through operation). If a complete frame has a size
2964 * smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
2965 * to the line. To enable store and forward on the Transmit path, set STR_FWD to
2966 * '1'. In this case, the MAC starts to transmit data only when a complete frame
2967 * is stored in the Transmit FIFO.
2969 typedef union _hw_enet_tfwr
2972 struct _hw_enet_tfwr_bitfields
2974 uint32_t TFWR : 6; /*!< [5:0] Transmit FIFO Write */
2975 uint32_t RESERVED0 : 2; /*!< [7:6] */
2976 uint32_t STRFWD : 1; /*!< [8] Store And Forward Enable */
2977 uint32_t RESERVED1 : 23; /*!< [31:9] */
2982 * @name Constants and macros for entire ENET_TFWR register
2985 #define HW_ENET_TFWR_ADDR(x) ((x) + 0x144U)
2987 #define HW_ENET_TFWR(x) (*(__IO hw_enet_tfwr_t *) HW_ENET_TFWR_ADDR(x))
2988 #define HW_ENET_TFWR_RD(x) (HW_ENET_TFWR(x).U)
2989 #define HW_ENET_TFWR_WR(x, v) (HW_ENET_TFWR(x).U = (v))
2990 #define HW_ENET_TFWR_SET(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) | (v)))
2991 #define HW_ENET_TFWR_CLR(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) & ~(v)))
2992 #define HW_ENET_TFWR_TOG(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) ^ (v)))
2996 * Constants & macros for individual ENET_TFWR bitfields
3000 * @name Register ENET_TFWR, field TFWR[5:0] (RW)
3002 * If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
3003 * steps of 64 bytes, written to the transmit FIFO before transmission of a frame
3004 * begins. If a frame with less than the threshold is written, it is still sent
3005 * independently of this threshold setting. The threshold is relevant only if the
3006 * frame is larger than the threshold given. This chip may not support the maximum
3007 * number of bytes written shown below. See the chip-specific information for the
3008 * ENET module for this value.
3011 * - 000000 - 64 bytes written.
3012 * - 000001 - 64 bytes written.
3013 * - 000010 - 128 bytes written.
3014 * - 000011 - 192 bytes written.
3015 * - 111110 - 3968 bytes written.
3016 * - 111111 - 4032 bytes written.
3019 #define BP_ENET_TFWR_TFWR (0U) /*!< Bit position for ENET_TFWR_TFWR. */
3020 #define BM_ENET_TFWR_TFWR (0x0000003FU) /*!< Bit mask for ENET_TFWR_TFWR. */
3021 #define BS_ENET_TFWR_TFWR (6U) /*!< Bit field size in bits for ENET_TFWR_TFWR. */
3023 /*! @brief Read current value of the ENET_TFWR_TFWR field. */
3024 #define BR_ENET_TFWR_TFWR(x) (HW_ENET_TFWR(x).B.TFWR)
3026 /*! @brief Format value for bitfield ENET_TFWR_TFWR. */
3027 #define BF_ENET_TFWR_TFWR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TFWR_TFWR) & BM_ENET_TFWR_TFWR)
3029 /*! @brief Set the TFWR field to a new value. */
3030 #define BW_ENET_TFWR_TFWR(x, v) (HW_ENET_TFWR_WR(x, (HW_ENET_TFWR_RD(x) & ~BM_ENET_TFWR_TFWR) | BF_ENET_TFWR_TFWR(v)))
3034 * @name Register ENET_TFWR, field STRFWD[8] (RW)
3037 * - 0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
3041 #define BP_ENET_TFWR_STRFWD (8U) /*!< Bit position for ENET_TFWR_STRFWD. */
3042 #define BM_ENET_TFWR_STRFWD (0x00000100U) /*!< Bit mask for ENET_TFWR_STRFWD. */
3043 #define BS_ENET_TFWR_STRFWD (1U) /*!< Bit field size in bits for ENET_TFWR_STRFWD. */
3045 /*! @brief Read current value of the ENET_TFWR_STRFWD field. */
3046 #define BR_ENET_TFWR_STRFWD(x) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD))
3048 /*! @brief Format value for bitfield ENET_TFWR_STRFWD. */
3049 #define BF_ENET_TFWR_STRFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TFWR_STRFWD) & BM_ENET_TFWR_STRFWD)
3051 /*! @brief Set the STRFWD field to a new value. */
3052 #define BW_ENET_TFWR_STRFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD) = (v))
3055 /*******************************************************************************
3056 * HW_ENET_RDSR - Receive Descriptor Ring Start Register
3057 ******************************************************************************/
3060 * @brief HW_ENET_RDSR - Receive Descriptor Ring Start Register (RW)
3062 * Reset value: 0x00000000U
3064 * RDSR points to the beginning of the circular receive buffer descriptor queue
3065 * in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
3066 * zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
3067 * by 16. This register must be initialized prior to operation
3069 typedef union _hw_enet_rdsr
3072 struct _hw_enet_rdsr_bitfields
3074 uint32_t RESERVED0 : 3; /*!< [2:0] */
3075 uint32_t R_DES_START : 29; /*!< [31:3] */
3080 * @name Constants and macros for entire ENET_RDSR register
3083 #define HW_ENET_RDSR_ADDR(x) ((x) + 0x180U)
3085 #define HW_ENET_RDSR(x) (*(__IO hw_enet_rdsr_t *) HW_ENET_RDSR_ADDR(x))
3086 #define HW_ENET_RDSR_RD(x) (HW_ENET_RDSR(x).U)
3087 #define HW_ENET_RDSR_WR(x, v) (HW_ENET_RDSR(x).U = (v))
3088 #define HW_ENET_RDSR_SET(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) | (v)))
3089 #define HW_ENET_RDSR_CLR(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) & ~(v)))
3090 #define HW_ENET_RDSR_TOG(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) ^ (v)))
3094 * Constants & macros for individual ENET_RDSR bitfields
3098 * @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
3100 * Pointer to the beginning of the receive buffer descriptor queue.
3103 #define BP_ENET_RDSR_R_DES_START (3U) /*!< Bit position for ENET_RDSR_R_DES_START. */
3104 #define BM_ENET_RDSR_R_DES_START (0xFFFFFFF8U) /*!< Bit mask for ENET_RDSR_R_DES_START. */
3105 #define BS_ENET_RDSR_R_DES_START (29U) /*!< Bit field size in bits for ENET_RDSR_R_DES_START. */
3107 /*! @brief Read current value of the ENET_RDSR_R_DES_START field. */
3108 #define BR_ENET_RDSR_R_DES_START(x) (HW_ENET_RDSR(x).B.R_DES_START)
3110 /*! @brief Format value for bitfield ENET_RDSR_R_DES_START. */
3111 #define BF_ENET_RDSR_R_DES_START(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RDSR_R_DES_START) & BM_ENET_RDSR_R_DES_START)
3113 /*! @brief Set the R_DES_START field to a new value. */
3114 #define BW_ENET_RDSR_R_DES_START(x, v) (HW_ENET_RDSR_WR(x, (HW_ENET_RDSR_RD(x) & ~BM_ENET_RDSR_R_DES_START) | BF_ENET_RDSR_R_DES_START(v)))
3117 /*******************************************************************************
3118 * HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
3119 ******************************************************************************/
3122 * @brief HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
3124 * Reset value: 0x00000000U
3126 * TDSR provides a pointer to the beginning of the circular transmit buffer
3127 * descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
3128 * must be zero); however, it is recommended to be 128-bit aligned, that is,
3129 * evenly divisible by 16. This register must be initialized prior to operation.
3131 typedef union _hw_enet_tdsr
3134 struct _hw_enet_tdsr_bitfields
3136 uint32_t RESERVED0 : 3; /*!< [2:0] */
3137 uint32_t X_DES_START : 29; /*!< [31:3] */
3142 * @name Constants and macros for entire ENET_TDSR register
3145 #define HW_ENET_TDSR_ADDR(x) ((x) + 0x184U)
3147 #define HW_ENET_TDSR(x) (*(__IO hw_enet_tdsr_t *) HW_ENET_TDSR_ADDR(x))
3148 #define HW_ENET_TDSR_RD(x) (HW_ENET_TDSR(x).U)
3149 #define HW_ENET_TDSR_WR(x, v) (HW_ENET_TDSR(x).U = (v))
3150 #define HW_ENET_TDSR_SET(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) | (v)))
3151 #define HW_ENET_TDSR_CLR(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) & ~(v)))
3152 #define HW_ENET_TDSR_TOG(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) ^ (v)))
3156 * Constants & macros for individual ENET_TDSR bitfields
3160 * @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
3162 * Pointer to the beginning of the transmit buffer descriptor queue.
3165 #define BP_ENET_TDSR_X_DES_START (3U) /*!< Bit position for ENET_TDSR_X_DES_START. */
3166 #define BM_ENET_TDSR_X_DES_START (0xFFFFFFF8U) /*!< Bit mask for ENET_TDSR_X_DES_START. */
3167 #define BS_ENET_TDSR_X_DES_START (29U) /*!< Bit field size in bits for ENET_TDSR_X_DES_START. */
3169 /*! @brief Read current value of the ENET_TDSR_X_DES_START field. */
3170 #define BR_ENET_TDSR_X_DES_START(x) (HW_ENET_TDSR(x).B.X_DES_START)
3172 /*! @brief Format value for bitfield ENET_TDSR_X_DES_START. */
3173 #define BF_ENET_TDSR_X_DES_START(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TDSR_X_DES_START) & BM_ENET_TDSR_X_DES_START)
3175 /*! @brief Set the X_DES_START field to a new value. */
3176 #define BW_ENET_TDSR_X_DES_START(x, v) (HW_ENET_TDSR_WR(x, (HW_ENET_TDSR_RD(x) & ~BM_ENET_TDSR_X_DES_START) | BF_ENET_TDSR_X_DES_START(v)))
3179 /*******************************************************************************
3180 * HW_ENET_MRBR - Maximum Receive Buffer Size Register
3181 ******************************************************************************/
3184 * @brief HW_ENET_MRBR - Maximum Receive Buffer Size Register (RW)
3186 * Reset value: 0x00000000U
3188 * The MRBR is a user-programmable register that dictates the maximum size of
3189 * all receive buffers. This value should take into consideration that the receive
3190 * CRC is always written into the last receive buffer. To allow one maximum size
3191 * frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
3192 * the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
3193 * set to zero by the device. To minimize bus usage (descriptor fetches), set
3194 * MRBR greater than or equal to 256 bytes. This register must be initialized
3197 typedef union _hw_enet_mrbr
3200 struct _hw_enet_mrbr_bitfields
3202 uint32_t RESERVED0 : 4; /*!< [3:0] */
3203 uint32_t R_BUF_SIZE : 10; /*!< [13:4] */
3204 uint32_t RESERVED1 : 18; /*!< [31:14] */
3209 * @name Constants and macros for entire ENET_MRBR register
3212 #define HW_ENET_MRBR_ADDR(x) ((x) + 0x188U)
3214 #define HW_ENET_MRBR(x) (*(__IO hw_enet_mrbr_t *) HW_ENET_MRBR_ADDR(x))
3215 #define HW_ENET_MRBR_RD(x) (HW_ENET_MRBR(x).U)
3216 #define HW_ENET_MRBR_WR(x, v) (HW_ENET_MRBR(x).U = (v))
3217 #define HW_ENET_MRBR_SET(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) | (v)))
3218 #define HW_ENET_MRBR_CLR(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) & ~(v)))
3219 #define HW_ENET_MRBR_TOG(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) ^ (v)))
3223 * Constants & macros for individual ENET_MRBR bitfields
3227 * @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
3229 * Receive buffer size in bytes.
3232 #define BP_ENET_MRBR_R_BUF_SIZE (4U) /*!< Bit position for ENET_MRBR_R_BUF_SIZE. */
3233 #define BM_ENET_MRBR_R_BUF_SIZE (0x00003FF0U) /*!< Bit mask for ENET_MRBR_R_BUF_SIZE. */
3234 #define BS_ENET_MRBR_R_BUF_SIZE (10U) /*!< Bit field size in bits for ENET_MRBR_R_BUF_SIZE. */
3236 /*! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field. */
3237 #define BR_ENET_MRBR_R_BUF_SIZE(x) (HW_ENET_MRBR(x).B.R_BUF_SIZE)
3239 /*! @brief Format value for bitfield ENET_MRBR_R_BUF_SIZE. */
3240 #define BF_ENET_MRBR_R_BUF_SIZE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MRBR_R_BUF_SIZE) & BM_ENET_MRBR_R_BUF_SIZE)
3242 /*! @brief Set the R_BUF_SIZE field to a new value. */
3243 #define BW_ENET_MRBR_R_BUF_SIZE(x, v) (HW_ENET_MRBR_WR(x, (HW_ENET_MRBR_RD(x) & ~BM_ENET_MRBR_R_BUF_SIZE) | BF_ENET_MRBR_R_BUF_SIZE(v)))
3246 /*******************************************************************************
3247 * HW_ENET_RSFL - Receive FIFO Section Full Threshold
3248 ******************************************************************************/
3251 * @brief HW_ENET_RSFL - Receive FIFO Section Full Threshold (RW)
3253 * Reset value: 0x00000000U
3255 typedef union _hw_enet_rsfl
3258 struct _hw_enet_rsfl_bitfields
3260 uint32_t RX_SECTION_FULL : 8; /*!< [7:0] Value Of Receive FIFO
3261 * Section Full Threshold */
3262 uint32_t RESERVED0 : 24; /*!< [31:8] */
3267 * @name Constants and macros for entire ENET_RSFL register
3270 #define HW_ENET_RSFL_ADDR(x) ((x) + 0x190U)
3272 #define HW_ENET_RSFL(x) (*(__IO hw_enet_rsfl_t *) HW_ENET_RSFL_ADDR(x))
3273 #define HW_ENET_RSFL_RD(x) (HW_ENET_RSFL(x).U)
3274 #define HW_ENET_RSFL_WR(x, v) (HW_ENET_RSFL(x).U = (v))
3275 #define HW_ENET_RSFL_SET(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) | (v)))
3276 #define HW_ENET_RSFL_CLR(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) & ~(v)))
3277 #define HW_ENET_RSFL_TOG(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) ^ (v)))
3281 * Constants & macros for individual ENET_RSFL bitfields
3285 * @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
3287 * Value, in 64-bit words, of the receive FIFO section full threshold. Clear
3288 * this field to enable store and forward on the RX FIFO. When programming a value
3289 * greater than 0 (cut-through operation), it must be greater than
3290 * RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
3291 * in the Receive FIFO (cut-through operation).
3294 #define BP_ENET_RSFL_RX_SECTION_FULL (0U) /*!< Bit position for ENET_RSFL_RX_SECTION_FULL. */
3295 #define BM_ENET_RSFL_RX_SECTION_FULL (0x000000FFU) /*!< Bit mask for ENET_RSFL_RX_SECTION_FULL. */
3296 #define BS_ENET_RSFL_RX_SECTION_FULL (8U) /*!< Bit field size in bits for ENET_RSFL_RX_SECTION_FULL. */
3298 /*! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field. */
3299 #define BR_ENET_RSFL_RX_SECTION_FULL(x) (HW_ENET_RSFL(x).B.RX_SECTION_FULL)
3301 /*! @brief Format value for bitfield ENET_RSFL_RX_SECTION_FULL. */
3302 #define BF_ENET_RSFL_RX_SECTION_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSFL_RX_SECTION_FULL) & BM_ENET_RSFL_RX_SECTION_FULL)
3304 /*! @brief Set the RX_SECTION_FULL field to a new value. */
3305 #define BW_ENET_RSFL_RX_SECTION_FULL(x, v) (HW_ENET_RSFL_WR(x, (HW_ENET_RSFL_RD(x) & ~BM_ENET_RSFL_RX_SECTION_FULL) | BF_ENET_RSFL_RX_SECTION_FULL(v)))
3308 /*******************************************************************************
3309 * HW_ENET_RSEM - Receive FIFO Section Empty Threshold
3310 ******************************************************************************/
3313 * @brief HW_ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
3315 * Reset value: 0x00000000U
3317 typedef union _hw_enet_rsem
3320 struct _hw_enet_rsem_bitfields
3322 uint32_t RX_SECTION_EMPTY : 8; /*!< [7:0] Value Of The Receive FIFO
3323 * Section Empty Threshold */
3324 uint32_t RESERVED0 : 8; /*!< [15:8] */
3325 uint32_t STAT_SECTION_EMPTY : 5; /*!< [20:16] RX Status FIFO Section
3326 * Empty Threshold */
3327 uint32_t RESERVED1 : 11; /*!< [31:21] */
3332 * @name Constants and macros for entire ENET_RSEM register
3335 #define HW_ENET_RSEM_ADDR(x) ((x) + 0x194U)
3337 #define HW_ENET_RSEM(x) (*(__IO hw_enet_rsem_t *) HW_ENET_RSEM_ADDR(x))
3338 #define HW_ENET_RSEM_RD(x) (HW_ENET_RSEM(x).U)
3339 #define HW_ENET_RSEM_WR(x, v) (HW_ENET_RSEM(x).U = (v))
3340 #define HW_ENET_RSEM_SET(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) | (v)))
3341 #define HW_ENET_RSEM_CLR(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) & ~(v)))
3342 #define HW_ENET_RSEM_TOG(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) ^ (v)))
3346 * Constants & macros for individual ENET_RSEM bitfields
3350 * @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
3352 * Value, in 64-bit words, of the receive FIFO section empty threshold. When the
3353 * FIFO has reached this level, a pause frame will be issued. A value of 0
3354 * disables automatic pause frame generation. When the FIFO level goes below the value
3355 * programmed in this field, an XON pause frame is issued to indicate the FIFO
3356 * congestion is cleared to the remote Ethernet client. The section-empty
3357 * threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
3360 #define BP_ENET_RSEM_RX_SECTION_EMPTY (0U) /*!< Bit position for ENET_RSEM_RX_SECTION_EMPTY. */
3361 #define BM_ENET_RSEM_RX_SECTION_EMPTY (0x000000FFU) /*!< Bit mask for ENET_RSEM_RX_SECTION_EMPTY. */
3362 #define BS_ENET_RSEM_RX_SECTION_EMPTY (8U) /*!< Bit field size in bits for ENET_RSEM_RX_SECTION_EMPTY. */
3364 /*! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field. */
3365 #define BR_ENET_RSEM_RX_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.RX_SECTION_EMPTY)
3367 /*! @brief Format value for bitfield ENET_RSEM_RX_SECTION_EMPTY. */
3368 #define BF_ENET_RSEM_RX_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSEM_RX_SECTION_EMPTY) & BM_ENET_RSEM_RX_SECTION_EMPTY)
3370 /*! @brief Set the RX_SECTION_EMPTY field to a new value. */
3371 #define BW_ENET_RSEM_RX_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_RX_SECTION_EMPTY) | BF_ENET_RSEM_RX_SECTION_EMPTY(v)))
3375 * @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
3377 * Defines number of frames in the receive FIFO, independent of its size, that
3378 * can be accepted. If the limit is reached, reception will continue normally,
3379 * however a pause frame will be triggered to indicate a possible congestion to the
3380 * remote device to avoid FIFO overflow. A value of 0 disables automatic pause
3384 #define BP_ENET_RSEM_STAT_SECTION_EMPTY (16U) /*!< Bit position for ENET_RSEM_STAT_SECTION_EMPTY. */
3385 #define BM_ENET_RSEM_STAT_SECTION_EMPTY (0x001F0000U) /*!< Bit mask for ENET_RSEM_STAT_SECTION_EMPTY. */
3386 #define BS_ENET_RSEM_STAT_SECTION_EMPTY (5U) /*!< Bit field size in bits for ENET_RSEM_STAT_SECTION_EMPTY. */
3388 /*! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field. */
3389 #define BR_ENET_RSEM_STAT_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.STAT_SECTION_EMPTY)
3391 /*! @brief Format value for bitfield ENET_RSEM_STAT_SECTION_EMPTY. */
3392 #define BF_ENET_RSEM_STAT_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSEM_STAT_SECTION_EMPTY) & BM_ENET_RSEM_STAT_SECTION_EMPTY)
3394 /*! @brief Set the STAT_SECTION_EMPTY field to a new value. */
3395 #define BW_ENET_RSEM_STAT_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_STAT_SECTION_EMPTY) | BF_ENET_RSEM_STAT_SECTION_EMPTY(v)))
3398 /*******************************************************************************
3399 * HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
3400 ******************************************************************************/
3403 * @brief HW_ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
3405 * Reset value: 0x00000004U
3407 typedef union _hw_enet_raem
3410 struct _hw_enet_raem_bitfields
3412 uint32_t RX_ALMOST_EMPTY : 8; /*!< [7:0] Value Of The Receive FIFO
3413 * Almost Empty Threshold */
3414 uint32_t RESERVED0 : 24; /*!< [31:8] */
3419 * @name Constants and macros for entire ENET_RAEM register
3422 #define HW_ENET_RAEM_ADDR(x) ((x) + 0x198U)
3424 #define HW_ENET_RAEM(x) (*(__IO hw_enet_raem_t *) HW_ENET_RAEM_ADDR(x))
3425 #define HW_ENET_RAEM_RD(x) (HW_ENET_RAEM(x).U)
3426 #define HW_ENET_RAEM_WR(x, v) (HW_ENET_RAEM(x).U = (v))
3427 #define HW_ENET_RAEM_SET(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) | (v)))
3428 #define HW_ENET_RAEM_CLR(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) & ~(v)))
3429 #define HW_ENET_RAEM_TOG(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) ^ (v)))
3433 * Constants & macros for individual ENET_RAEM bitfields
3437 * @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
3439 * Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
3440 * FIFO level reaches the value programmed in this field and the end-of-frame has
3441 * not been received for the frame yet, the core receive read control stops FIFO
3442 * read (and subsequently stops transferring data to the MAC client
3443 * application). It continues to deliver the frame, if again more data than the threshold or
3444 * the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
3447 #define BP_ENET_RAEM_RX_ALMOST_EMPTY (0U) /*!< Bit position for ENET_RAEM_RX_ALMOST_EMPTY. */
3448 #define BM_ENET_RAEM_RX_ALMOST_EMPTY (0x000000FFU) /*!< Bit mask for ENET_RAEM_RX_ALMOST_EMPTY. */
3449 #define BS_ENET_RAEM_RX_ALMOST_EMPTY (8U) /*!< Bit field size in bits for ENET_RAEM_RX_ALMOST_EMPTY. */
3451 /*! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field. */
3452 #define BR_ENET_RAEM_RX_ALMOST_EMPTY(x) (HW_ENET_RAEM(x).B.RX_ALMOST_EMPTY)
3454 /*! @brief Format value for bitfield ENET_RAEM_RX_ALMOST_EMPTY. */
3455 #define BF_ENET_RAEM_RX_ALMOST_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RAEM_RX_ALMOST_EMPTY) & BM_ENET_RAEM_RX_ALMOST_EMPTY)
3457 /*! @brief Set the RX_ALMOST_EMPTY field to a new value. */
3458 #define BW_ENET_RAEM_RX_ALMOST_EMPTY(x, v) (HW_ENET_RAEM_WR(x, (HW_ENET_RAEM_RD(x) & ~BM_ENET_RAEM_RX_ALMOST_EMPTY) | BF_ENET_RAEM_RX_ALMOST_EMPTY(v)))
3461 /*******************************************************************************
3462 * HW_ENET_RAFL - Receive FIFO Almost Full Threshold
3463 ******************************************************************************/
3466 * @brief HW_ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
3468 * Reset value: 0x00000004U
3470 typedef union _hw_enet_rafl
3473 struct _hw_enet_rafl_bitfields
3475 uint32_t RX_ALMOST_FULL : 8; /*!< [7:0] Value Of The Receive FIFO
3476 * Almost Full Threshold */
3477 uint32_t RESERVED0 : 24; /*!< [31:8] */
3482 * @name Constants and macros for entire ENET_RAFL register
3485 #define HW_ENET_RAFL_ADDR(x) ((x) + 0x19CU)
3487 #define HW_ENET_RAFL(x) (*(__IO hw_enet_rafl_t *) HW_ENET_RAFL_ADDR(x))
3488 #define HW_ENET_RAFL_RD(x) (HW_ENET_RAFL(x).U)
3489 #define HW_ENET_RAFL_WR(x, v) (HW_ENET_RAFL(x).U = (v))
3490 #define HW_ENET_RAFL_SET(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) | (v)))
3491 #define HW_ENET_RAFL_CLR(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) & ~(v)))
3492 #define HW_ENET_RAFL_TOG(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) ^ (v)))
3496 * Constants & macros for individual ENET_RAFL bitfields
3500 * @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
3502 * Value, in 64-bit words, of the receive FIFO almost full threshold. When the
3503 * FIFO level comes close to the maximum, so that there is no more space for at
3504 * least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
3505 * truncates the received frame to avoid FIFO overflow. The corresponding error
3506 * status will be set when the frame is delivered to the application. A minimum
3507 * value of 4 should be set.
3510 #define BP_ENET_RAFL_RX_ALMOST_FULL (0U) /*!< Bit position for ENET_RAFL_RX_ALMOST_FULL. */
3511 #define BM_ENET_RAFL_RX_ALMOST_FULL (0x000000FFU) /*!< Bit mask for ENET_RAFL_RX_ALMOST_FULL. */
3512 #define BS_ENET_RAFL_RX_ALMOST_FULL (8U) /*!< Bit field size in bits for ENET_RAFL_RX_ALMOST_FULL. */
3514 /*! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field. */
3515 #define BR_ENET_RAFL_RX_ALMOST_FULL(x) (HW_ENET_RAFL(x).B.RX_ALMOST_FULL)
3517 /*! @brief Format value for bitfield ENET_RAFL_RX_ALMOST_FULL. */
3518 #define BF_ENET_RAFL_RX_ALMOST_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RAFL_RX_ALMOST_FULL) & BM_ENET_RAFL_RX_ALMOST_FULL)
3520 /*! @brief Set the RX_ALMOST_FULL field to a new value. */
3521 #define BW_ENET_RAFL_RX_ALMOST_FULL(x, v) (HW_ENET_RAFL_WR(x, (HW_ENET_RAFL_RD(x) & ~BM_ENET_RAFL_RX_ALMOST_FULL) | BF_ENET_RAFL_RX_ALMOST_FULL(v)))
3524 /*******************************************************************************
3525 * HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
3526 ******************************************************************************/
3529 * @brief HW_ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
3531 * Reset value: 0x00000000U
3533 typedef union _hw_enet_tsem
3536 struct _hw_enet_tsem_bitfields
3538 uint32_t TX_SECTION_EMPTY : 8; /*!< [7:0] Value Of The Transmit FIFO
3539 * Section Empty Threshold */
3540 uint32_t RESERVED0 : 24; /*!< [31:8] */
3545 * @name Constants and macros for entire ENET_TSEM register
3548 #define HW_ENET_TSEM_ADDR(x) ((x) + 0x1A0U)
3550 #define HW_ENET_TSEM(x) (*(__IO hw_enet_tsem_t *) HW_ENET_TSEM_ADDR(x))
3551 #define HW_ENET_TSEM_RD(x) (HW_ENET_TSEM(x).U)
3552 #define HW_ENET_TSEM_WR(x, v) (HW_ENET_TSEM(x).U = (v))
3553 #define HW_ENET_TSEM_SET(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) | (v)))
3554 #define HW_ENET_TSEM_CLR(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) & ~(v)))
3555 #define HW_ENET_TSEM_TOG(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) ^ (v)))
3559 * Constants & macros for individual ENET_TSEM bitfields
3563 * @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
3565 * Value, in 64-bit words, of the transmit FIFO section empty threshold. See
3566 * Transmit FIFOFour programmable thresholds are available which control the core
3567 * operation. for more information.
3570 #define BP_ENET_TSEM_TX_SECTION_EMPTY (0U) /*!< Bit position for ENET_TSEM_TX_SECTION_EMPTY. */
3571 #define BM_ENET_TSEM_TX_SECTION_EMPTY (0x000000FFU) /*!< Bit mask for ENET_TSEM_TX_SECTION_EMPTY. */
3572 #define BS_ENET_TSEM_TX_SECTION_EMPTY (8U) /*!< Bit field size in bits for ENET_TSEM_TX_SECTION_EMPTY. */
3574 /*! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field. */
3575 #define BR_ENET_TSEM_TX_SECTION_EMPTY(x) (HW_ENET_TSEM(x).B.TX_SECTION_EMPTY)
3577 /*! @brief Format value for bitfield ENET_TSEM_TX_SECTION_EMPTY. */
3578 #define BF_ENET_TSEM_TX_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TSEM_TX_SECTION_EMPTY) & BM_ENET_TSEM_TX_SECTION_EMPTY)
3580 /*! @brief Set the TX_SECTION_EMPTY field to a new value. */
3581 #define BW_ENET_TSEM_TX_SECTION_EMPTY(x, v) (HW_ENET_TSEM_WR(x, (HW_ENET_TSEM_RD(x) & ~BM_ENET_TSEM_TX_SECTION_EMPTY) | BF_ENET_TSEM_TX_SECTION_EMPTY(v)))
3584 /*******************************************************************************
3585 * HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
3586 ******************************************************************************/
3589 * @brief HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
3591 * Reset value: 0x00000004U
3593 typedef union _hw_enet_taem
3596 struct _hw_enet_taem_bitfields
3598 uint32_t TX_ALMOST_EMPTY : 8; /*!< [7:0] Value of Transmit FIFO
3599 * Almost Empty Threshold */
3600 uint32_t RESERVED0 : 24; /*!< [31:8] */
3605 * @name Constants and macros for entire ENET_TAEM register
3608 #define HW_ENET_TAEM_ADDR(x) ((x) + 0x1A4U)
3610 #define HW_ENET_TAEM(x) (*(__IO hw_enet_taem_t *) HW_ENET_TAEM_ADDR(x))
3611 #define HW_ENET_TAEM_RD(x) (HW_ENET_TAEM(x).U)
3612 #define HW_ENET_TAEM_WR(x, v) (HW_ENET_TAEM(x).U = (v))
3613 #define HW_ENET_TAEM_SET(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) | (v)))
3614 #define HW_ENET_TAEM_CLR(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) & ~(v)))
3615 #define HW_ENET_TAEM_TOG(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) ^ (v)))
3619 * Constants & macros for individual ENET_TAEM bitfields
3623 * @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
3625 * Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
3626 * FIFO level reaches the value programmed in this field, and no end-of-frame is
3627 * available for the frame, the MAC transmit logic, to avoid FIFO underflow,
3628 * stops reading the FIFO and transmits a frame with an MII error indication. See
3629 * Transmit FIFOFour programmable thresholds are available which control the core
3630 * operation. for more information. A minimum value of 4 should be set.
3633 #define BP_ENET_TAEM_TX_ALMOST_EMPTY (0U) /*!< Bit position for ENET_TAEM_TX_ALMOST_EMPTY. */
3634 #define BM_ENET_TAEM_TX_ALMOST_EMPTY (0x000000FFU) /*!< Bit mask for ENET_TAEM_TX_ALMOST_EMPTY. */
3635 #define BS_ENET_TAEM_TX_ALMOST_EMPTY (8U) /*!< Bit field size in bits for ENET_TAEM_TX_ALMOST_EMPTY. */
3637 /*! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field. */
3638 #define BR_ENET_TAEM_TX_ALMOST_EMPTY(x) (HW_ENET_TAEM(x).B.TX_ALMOST_EMPTY)
3640 /*! @brief Format value for bitfield ENET_TAEM_TX_ALMOST_EMPTY. */
3641 #define BF_ENET_TAEM_TX_ALMOST_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TAEM_TX_ALMOST_EMPTY) & BM_ENET_TAEM_TX_ALMOST_EMPTY)
3643 /*! @brief Set the TX_ALMOST_EMPTY field to a new value. */
3644 #define BW_ENET_TAEM_TX_ALMOST_EMPTY(x, v) (HW_ENET_TAEM_WR(x, (HW_ENET_TAEM_RD(x) & ~BM_ENET_TAEM_TX_ALMOST_EMPTY) | BF_ENET_TAEM_TX_ALMOST_EMPTY(v)))
3647 /*******************************************************************************
3648 * HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
3649 ******************************************************************************/
3652 * @brief HW_ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
3654 * Reset value: 0x00000008U
3656 typedef union _hw_enet_tafl
3659 struct _hw_enet_tafl_bitfields
3661 uint32_t TX_ALMOST_FULL : 8; /*!< [7:0] Value Of The Transmit FIFO
3662 * Almost Full Threshold */
3663 uint32_t RESERVED0 : 24; /*!< [31:8] */
3668 * @name Constants and macros for entire ENET_TAFL register
3671 #define HW_ENET_TAFL_ADDR(x) ((x) + 0x1A8U)
3673 #define HW_ENET_TAFL(x) (*(__IO hw_enet_tafl_t *) HW_ENET_TAFL_ADDR(x))
3674 #define HW_ENET_TAFL_RD(x) (HW_ENET_TAFL(x).U)
3675 #define HW_ENET_TAFL_WR(x, v) (HW_ENET_TAFL(x).U = (v))
3676 #define HW_ENET_TAFL_SET(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) | (v)))
3677 #define HW_ENET_TAFL_CLR(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) & ~(v)))
3678 #define HW_ENET_TAFL_TOG(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) ^ (v)))
3682 * Constants & macros for individual ENET_TAFL bitfields
3686 * @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
3688 * Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
3689 * value of six is required . A recommended value of at least 8 should be set
3690 * allowing a latency of two clock cycles to the application. If more latency is
3691 * required the value can be increased as necessary (latency = TAFL - 5). When the
3692 * FIFO level comes close to the maximum, so that there is no more space for at
3693 * least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
3694 * application does not react on this signal, the FIFO write control logic, to
3695 * avoid FIFO overflow, truncates the current frame and sets the error status. As a
3696 * result, the frame will be transmitted with an GMII/MII error indication. See
3697 * Transmit FIFOFour programmable thresholds are available which control the core
3698 * operation. for more information. A FIFO overflow is a fatal error and requires
3699 * a global reset on the transmit datapath or at least deassertion of ETHEREN.
3702 #define BP_ENET_TAFL_TX_ALMOST_FULL (0U) /*!< Bit position for ENET_TAFL_TX_ALMOST_FULL. */
3703 #define BM_ENET_TAFL_TX_ALMOST_FULL (0x000000FFU) /*!< Bit mask for ENET_TAFL_TX_ALMOST_FULL. */
3704 #define BS_ENET_TAFL_TX_ALMOST_FULL (8U) /*!< Bit field size in bits for ENET_TAFL_TX_ALMOST_FULL. */
3706 /*! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field. */
3707 #define BR_ENET_TAFL_TX_ALMOST_FULL(x) (HW_ENET_TAFL(x).B.TX_ALMOST_FULL)
3709 /*! @brief Format value for bitfield ENET_TAFL_TX_ALMOST_FULL. */
3710 #define BF_ENET_TAFL_TX_ALMOST_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TAFL_TX_ALMOST_FULL) & BM_ENET_TAFL_TX_ALMOST_FULL)
3712 /*! @brief Set the TX_ALMOST_FULL field to a new value. */
3713 #define BW_ENET_TAFL_TX_ALMOST_FULL(x, v) (HW_ENET_TAFL_WR(x, (HW_ENET_TAFL_RD(x) & ~BM_ENET_TAFL_TX_ALMOST_FULL) | BF_ENET_TAFL_TX_ALMOST_FULL(v)))
3716 /*******************************************************************************
3717 * HW_ENET_TIPG - Transmit Inter-Packet Gap
3718 ******************************************************************************/
3721 * @brief HW_ENET_TIPG - Transmit Inter-Packet Gap (RW)
3723 * Reset value: 0x0000000CU
3725 typedef union _hw_enet_tipg
3728 struct _hw_enet_tipg_bitfields
3730 uint32_t IPG : 5; /*!< [4:0] Transmit Inter-Packet Gap */
3731 uint32_t RESERVED0 : 27; /*!< [31:5] */
3736 * @name Constants and macros for entire ENET_TIPG register
3739 #define HW_ENET_TIPG_ADDR(x) ((x) + 0x1ACU)
3741 #define HW_ENET_TIPG(x) (*(__IO hw_enet_tipg_t *) HW_ENET_TIPG_ADDR(x))
3742 #define HW_ENET_TIPG_RD(x) (HW_ENET_TIPG(x).U)
3743 #define HW_ENET_TIPG_WR(x, v) (HW_ENET_TIPG(x).U = (v))
3744 #define HW_ENET_TIPG_SET(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) | (v)))
3745 #define HW_ENET_TIPG_CLR(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) & ~(v)))
3746 #define HW_ENET_TIPG_TOG(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) ^ (v)))
3750 * Constants & macros for individual ENET_TIPG bitfields
3754 * @name Register ENET_TIPG, field IPG[4:0] (RW)
3756 * Indicates the IPG, in bytes, between transmitted frames. Valid values range
3757 * from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
3758 * 27, the IPG is 27.
3761 #define BP_ENET_TIPG_IPG (0U) /*!< Bit position for ENET_TIPG_IPG. */
3762 #define BM_ENET_TIPG_IPG (0x0000001FU) /*!< Bit mask for ENET_TIPG_IPG. */
3763 #define BS_ENET_TIPG_IPG (5U) /*!< Bit field size in bits for ENET_TIPG_IPG. */
3765 /*! @brief Read current value of the ENET_TIPG_IPG field. */
3766 #define BR_ENET_TIPG_IPG(x) (HW_ENET_TIPG(x).B.IPG)
3768 /*! @brief Format value for bitfield ENET_TIPG_IPG. */
3769 #define BF_ENET_TIPG_IPG(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TIPG_IPG) & BM_ENET_TIPG_IPG)
3771 /*! @brief Set the IPG field to a new value. */
3772 #define BW_ENET_TIPG_IPG(x, v) (HW_ENET_TIPG_WR(x, (HW_ENET_TIPG_RD(x) & ~BM_ENET_TIPG_IPG) | BF_ENET_TIPG_IPG(v)))
3775 /*******************************************************************************
3776 * HW_ENET_FTRL - Frame Truncation Length
3777 ******************************************************************************/
3780 * @brief HW_ENET_FTRL - Frame Truncation Length (RW)
3782 * Reset value: 0x000007FFU
3784 typedef union _hw_enet_ftrl
3787 struct _hw_enet_ftrl_bitfields
3789 uint32_t TRUNC_FL : 14; /*!< [13:0] Frame Truncation Length */
3790 uint32_t RESERVED0 : 18; /*!< [31:14] */
3795 * @name Constants and macros for entire ENET_FTRL register
3798 #define HW_ENET_FTRL_ADDR(x) ((x) + 0x1B0U)
3800 #define HW_ENET_FTRL(x) (*(__IO hw_enet_ftrl_t *) HW_ENET_FTRL_ADDR(x))
3801 #define HW_ENET_FTRL_RD(x) (HW_ENET_FTRL(x).U)
3802 #define HW_ENET_FTRL_WR(x, v) (HW_ENET_FTRL(x).U = (v))
3803 #define HW_ENET_FTRL_SET(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) | (v)))
3804 #define HW_ENET_FTRL_CLR(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) & ~(v)))
3805 #define HW_ENET_FTRL_TOG(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) ^ (v)))
3809 * Constants & macros for individual ENET_FTRL bitfields
3813 * @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
3815 * Indicates the value a receive frame is truncated, if it is greater than this
3816 * value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
3817 * TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
3818 * less data, guaranteeing that it never receives more than the set limit.
3821 #define BP_ENET_FTRL_TRUNC_FL (0U) /*!< Bit position for ENET_FTRL_TRUNC_FL. */
3822 #define BM_ENET_FTRL_TRUNC_FL (0x00003FFFU) /*!< Bit mask for ENET_FTRL_TRUNC_FL. */
3823 #define BS_ENET_FTRL_TRUNC_FL (14U) /*!< Bit field size in bits for ENET_FTRL_TRUNC_FL. */
3825 /*! @brief Read current value of the ENET_FTRL_TRUNC_FL field. */
3826 #define BR_ENET_FTRL_TRUNC_FL(x) (HW_ENET_FTRL(x).B.TRUNC_FL)
3828 /*! @brief Format value for bitfield ENET_FTRL_TRUNC_FL. */
3829 #define BF_ENET_FTRL_TRUNC_FL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_FTRL_TRUNC_FL) & BM_ENET_FTRL_TRUNC_FL)
3831 /*! @brief Set the TRUNC_FL field to a new value. */
3832 #define BW_ENET_FTRL_TRUNC_FL(x, v) (HW_ENET_FTRL_WR(x, (HW_ENET_FTRL_RD(x) & ~BM_ENET_FTRL_TRUNC_FL) | BF_ENET_FTRL_TRUNC_FL(v)))
3835 /*******************************************************************************
3836 * HW_ENET_TACC - Transmit Accelerator Function Configuration
3837 ******************************************************************************/
3840 * @brief HW_ENET_TACC - Transmit Accelerator Function Configuration (RW)
3842 * Reset value: 0x00000000U
3844 * TACC controls accelerator actions when sending frames. The register can be
3845 * changed before or after each frame, but it must remain unmodified during frame
3846 * writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
3849 typedef union _hw_enet_tacc
3852 struct _hw_enet_tacc_bitfields
3854 uint32_t SHIFT16 : 1; /*!< [0] TX FIFO Shift-16 */
3855 uint32_t RESERVED0 : 2; /*!< [2:1] */
3856 uint32_t IPCHK : 1; /*!< [3] */
3857 uint32_t PROCHK : 1; /*!< [4] */
3858 uint32_t RESERVED1 : 27; /*!< [31:5] */
3863 * @name Constants and macros for entire ENET_TACC register
3866 #define HW_ENET_TACC_ADDR(x) ((x) + 0x1C0U)
3868 #define HW_ENET_TACC(x) (*(__IO hw_enet_tacc_t *) HW_ENET_TACC_ADDR(x))
3869 #define HW_ENET_TACC_RD(x) (HW_ENET_TACC(x).U)
3870 #define HW_ENET_TACC_WR(x, v) (HW_ENET_TACC(x).U = (v))
3871 #define HW_ENET_TACC_SET(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) | (v)))
3872 #define HW_ENET_TACC_CLR(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) & ~(v)))
3873 #define HW_ENET_TACC_TOG(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) ^ (v)))
3877 * Constants & macros for individual ENET_TACC bitfields
3881 * @name Register ENET_TACC, field SHIFT16[0] (RW)
3885 * - 1 - Indicates to the transmit data FIFO that the written frames contain two
3886 * additional octets before the frame data. This means the actual frame
3887 * begins at bit 16 of the first word written into the FIFO. This function allows
3888 * putting the frame payload on a 32-bit boundary in memory, as the 14-byte
3889 * Ethernet header is extended to a 16-byte header.
3892 #define BP_ENET_TACC_SHIFT16 (0U) /*!< Bit position for ENET_TACC_SHIFT16. */
3893 #define BM_ENET_TACC_SHIFT16 (0x00000001U) /*!< Bit mask for ENET_TACC_SHIFT16. */
3894 #define BS_ENET_TACC_SHIFT16 (1U) /*!< Bit field size in bits for ENET_TACC_SHIFT16. */
3896 /*! @brief Read current value of the ENET_TACC_SHIFT16 field. */
3897 #define BR_ENET_TACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16))
3899 /*! @brief Format value for bitfield ENET_TACC_SHIFT16. */
3900 #define BF_ENET_TACC_SHIFT16(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_SHIFT16) & BM_ENET_TACC_SHIFT16)
3902 /*! @brief Set the SHIFT16 field to a new value. */
3903 #define BW_ENET_TACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16) = (v))
3907 * @name Register ENET_TACC, field IPCHK[3] (RW)
3909 * Enables insertion of IP header checksum.
3912 * - 0 - Checksum is not inserted.
3913 * - 1 - If an IP frame is transmitted, the checksum is inserted automatically.
3914 * The IP header checksum field must be cleared. If a non-IP frame is
3915 * transmitted the frame is not modified.
3918 #define BP_ENET_TACC_IPCHK (3U) /*!< Bit position for ENET_TACC_IPCHK. */
3919 #define BM_ENET_TACC_IPCHK (0x00000008U) /*!< Bit mask for ENET_TACC_IPCHK. */
3920 #define BS_ENET_TACC_IPCHK (1U) /*!< Bit field size in bits for ENET_TACC_IPCHK. */
3922 /*! @brief Read current value of the ENET_TACC_IPCHK field. */
3923 #define BR_ENET_TACC_IPCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK))
3925 /*! @brief Format value for bitfield ENET_TACC_IPCHK. */
3926 #define BF_ENET_TACC_IPCHK(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_IPCHK) & BM_ENET_TACC_IPCHK)
3928 /*! @brief Set the IPCHK field to a new value. */
3929 #define BW_ENET_TACC_IPCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK) = (v))
3933 * @name Register ENET_TACC, field PROCHK[4] (RW)
3935 * Enables insertion of protocol checksum.
3938 * - 0 - Checksum not inserted.
3939 * - 1 - If an IP frame with a known protocol is transmitted, the checksum is
3940 * inserted automatically into the frame. The checksum field must be cleared.
3941 * The other frames are not modified.
3944 #define BP_ENET_TACC_PROCHK (4U) /*!< Bit position for ENET_TACC_PROCHK. */
3945 #define BM_ENET_TACC_PROCHK (0x00000010U) /*!< Bit mask for ENET_TACC_PROCHK. */
3946 #define BS_ENET_TACC_PROCHK (1U) /*!< Bit field size in bits for ENET_TACC_PROCHK. */
3948 /*! @brief Read current value of the ENET_TACC_PROCHK field. */
3949 #define BR_ENET_TACC_PROCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK))
3951 /*! @brief Format value for bitfield ENET_TACC_PROCHK. */
3952 #define BF_ENET_TACC_PROCHK(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_PROCHK) & BM_ENET_TACC_PROCHK)
3954 /*! @brief Set the PROCHK field to a new value. */
3955 #define BW_ENET_TACC_PROCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK) = (v))
3958 /*******************************************************************************
3959 * HW_ENET_RACC - Receive Accelerator Function Configuration
3960 ******************************************************************************/
3963 * @brief HW_ENET_RACC - Receive Accelerator Function Configuration (RW)
3965 * Reset value: 0x00000000U
3967 typedef union _hw_enet_racc
3970 struct _hw_enet_racc_bitfields
3972 uint32_t PADREM : 1; /*!< [0] Enable Padding Removal For Short IP
3974 uint32_t IPDIS : 1; /*!< [1] Enable Discard Of Frames With Wrong IPv4
3975 * Header Checksum */
3976 uint32_t PRODIS : 1; /*!< [2] Enable Discard Of Frames With Wrong
3977 * Protocol Checksum */
3978 uint32_t RESERVED0 : 3; /*!< [5:3] */
3979 uint32_t LINEDIS : 1; /*!< [6] Enable Discard Of Frames With MAC
3981 uint32_t SHIFT16 : 1; /*!< [7] RX FIFO Shift-16 */
3982 uint32_t RESERVED1 : 24; /*!< [31:8] */
3987 * @name Constants and macros for entire ENET_RACC register
3990 #define HW_ENET_RACC_ADDR(x) ((x) + 0x1C4U)
3992 #define HW_ENET_RACC(x) (*(__IO hw_enet_racc_t *) HW_ENET_RACC_ADDR(x))
3993 #define HW_ENET_RACC_RD(x) (HW_ENET_RACC(x).U)
3994 #define HW_ENET_RACC_WR(x, v) (HW_ENET_RACC(x).U = (v))
3995 #define HW_ENET_RACC_SET(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) | (v)))
3996 #define HW_ENET_RACC_CLR(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) & ~(v)))
3997 #define HW_ENET_RACC_TOG(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) ^ (v)))
4001 * Constants & macros for individual ENET_RACC bitfields
4005 * @name Register ENET_RACC, field PADREM[0] (RW)
4008 * - 0 - Padding not removed.
4009 * - 1 - Any bytes following the IP payload section of the frame are removed
4013 #define BP_ENET_RACC_PADREM (0U) /*!< Bit position for ENET_RACC_PADREM. */
4014 #define BM_ENET_RACC_PADREM (0x00000001U) /*!< Bit mask for ENET_RACC_PADREM. */
4015 #define BS_ENET_RACC_PADREM (1U) /*!< Bit field size in bits for ENET_RACC_PADREM. */
4017 /*! @brief Read current value of the ENET_RACC_PADREM field. */
4018 #define BR_ENET_RACC_PADREM(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM))
4020 /*! @brief Format value for bitfield ENET_RACC_PADREM. */
4021 #define BF_ENET_RACC_PADREM(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_PADREM) & BM_ENET_RACC_PADREM)
4023 /*! @brief Set the PADREM field to a new value. */
4024 #define BW_ENET_RACC_PADREM(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM) = (v))
4028 * @name Register ENET_RACC, field IPDIS[1] (RW)
4031 * - 0 - Frames with wrong IPv4 header checksum are not discarded.
4032 * - 1 - If an IPv4 frame is received with a mismatching header checksum, the
4033 * frame is discarded. IPv6 has no header checksum and is not affected by this
4034 * setting. Discarding is only available when the RX FIFO operates in store
4035 * and forward mode (RSFL cleared).
4038 #define BP_ENET_RACC_IPDIS (1U) /*!< Bit position for ENET_RACC_IPDIS. */
4039 #define BM_ENET_RACC_IPDIS (0x00000002U) /*!< Bit mask for ENET_RACC_IPDIS. */
4040 #define BS_ENET_RACC_IPDIS (1U) /*!< Bit field size in bits for ENET_RACC_IPDIS. */
4042 /*! @brief Read current value of the ENET_RACC_IPDIS field. */
4043 #define BR_ENET_RACC_IPDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS))
4045 /*! @brief Format value for bitfield ENET_RACC_IPDIS. */
4046 #define BF_ENET_RACC_IPDIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_IPDIS) & BM_ENET_RACC_IPDIS)
4048 /*! @brief Set the IPDIS field to a new value. */
4049 #define BW_ENET_RACC_IPDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS) = (v))
4053 * @name Register ENET_RACC, field PRODIS[2] (RW)
4056 * - 0 - Frames with wrong checksum are not discarded.
4057 * - 1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP,
4058 * UDP, or ICMP checksum, the frame is discarded. Discarding is only
4059 * available when the RX FIFO operates in store and forward mode (RSFL cleared).
4062 #define BP_ENET_RACC_PRODIS (2U) /*!< Bit position for ENET_RACC_PRODIS. */
4063 #define BM_ENET_RACC_PRODIS (0x00000004U) /*!< Bit mask for ENET_RACC_PRODIS. */
4064 #define BS_ENET_RACC_PRODIS (1U) /*!< Bit field size in bits for ENET_RACC_PRODIS. */
4066 /*! @brief Read current value of the ENET_RACC_PRODIS field. */
4067 #define BR_ENET_RACC_PRODIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS))
4069 /*! @brief Format value for bitfield ENET_RACC_PRODIS. */
4070 #define BF_ENET_RACC_PRODIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_PRODIS) & BM_ENET_RACC_PRODIS)
4072 /*! @brief Set the PRODIS field to a new value. */
4073 #define BW_ENET_RACC_PRODIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS) = (v))
4077 * @name Register ENET_RACC, field LINEDIS[6] (RW)
4080 * - 0 - Frames with errors are not discarded.
4081 * - 1 - Any frame received with a CRC, length, or PHY error is automatically
4082 * discarded and not forwarded to the user application interface.
4085 #define BP_ENET_RACC_LINEDIS (6U) /*!< Bit position for ENET_RACC_LINEDIS. */
4086 #define BM_ENET_RACC_LINEDIS (0x00000040U) /*!< Bit mask for ENET_RACC_LINEDIS. */
4087 #define BS_ENET_RACC_LINEDIS (1U) /*!< Bit field size in bits for ENET_RACC_LINEDIS. */
4089 /*! @brief Read current value of the ENET_RACC_LINEDIS field. */
4090 #define BR_ENET_RACC_LINEDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS))
4092 /*! @brief Format value for bitfield ENET_RACC_LINEDIS. */
4093 #define BF_ENET_RACC_LINEDIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_LINEDIS) & BM_ENET_RACC_LINEDIS)
4095 /*! @brief Set the LINEDIS field to a new value. */
4096 #define BW_ENET_RACC_LINEDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS) = (v))
4100 * @name Register ENET_RACC, field SHIFT16[7] (RW)
4102 * When this field is set, the actual frame data starts at bit 16 of the first
4103 * word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
4104 * This function only affects the FIFO storage and has no influence on the
4105 * statistics, which use the actual length of the frame received.
4109 * - 1 - Instructs the MAC to write two additional bytes in front of each frame
4110 * received into the RX FIFO.
4113 #define BP_ENET_RACC_SHIFT16 (7U) /*!< Bit position for ENET_RACC_SHIFT16. */
4114 #define BM_ENET_RACC_SHIFT16 (0x00000080U) /*!< Bit mask for ENET_RACC_SHIFT16. */
4115 #define BS_ENET_RACC_SHIFT16 (1U) /*!< Bit field size in bits for ENET_RACC_SHIFT16. */
4117 /*! @brief Read current value of the ENET_RACC_SHIFT16 field. */
4118 #define BR_ENET_RACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16))
4120 /*! @brief Format value for bitfield ENET_RACC_SHIFT16. */
4121 #define BF_ENET_RACC_SHIFT16(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_SHIFT16) & BM_ENET_RACC_SHIFT16)
4123 /*! @brief Set the SHIFT16 field to a new value. */
4124 #define BW_ENET_RACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16) = (v))
4127 /*******************************************************************************
4128 * HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
4129 ******************************************************************************/
4132 * @brief HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
4134 * Reset value: 0x00000000U
4136 typedef union _hw_enet_rmon_t_packets
4139 struct _hw_enet_rmon_t_packets_bitfields
4141 uint32_t TXPKTS : 16; /*!< [15:0] Packet count */
4142 uint32_t RESERVED0 : 16; /*!< [31:16] */
4144 } hw_enet_rmon_t_packets_t;
4147 * @name Constants and macros for entire ENET_RMON_T_PACKETS register
4150 #define HW_ENET_RMON_T_PACKETS_ADDR(x) ((x) + 0x204U)
4152 #define HW_ENET_RMON_T_PACKETS(x) (*(__I hw_enet_rmon_t_packets_t *) HW_ENET_RMON_T_PACKETS_ADDR(x))
4153 #define HW_ENET_RMON_T_PACKETS_RD(x) (HW_ENET_RMON_T_PACKETS(x).U)
4157 * Constants & macros for individual ENET_RMON_T_PACKETS bitfields
4161 * @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
4164 #define BP_ENET_RMON_T_PACKETS_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_PACKETS_TXPKTS. */
4165 #define BM_ENET_RMON_T_PACKETS_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_PACKETS_TXPKTS. */
4166 #define BS_ENET_RMON_T_PACKETS_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_PACKETS_TXPKTS. */
4168 /*! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field. */
4169 #define BR_ENET_RMON_T_PACKETS_TXPKTS(x) (HW_ENET_RMON_T_PACKETS(x).B.TXPKTS)
4172 /*******************************************************************************
4173 * HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
4174 ******************************************************************************/
4177 * @brief HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
4179 * Reset value: 0x00000000U
4181 * RMON Tx Broadcast Packets
4183 typedef union _hw_enet_rmon_t_bc_pkt
4186 struct _hw_enet_rmon_t_bc_pkt_bitfields
4188 uint32_t TXPKTS : 16; /*!< [15:0] Broadcast packets */
4189 uint32_t RESERVED0 : 16; /*!< [31:16] */
4191 } hw_enet_rmon_t_bc_pkt_t;
4194 * @name Constants and macros for entire ENET_RMON_T_BC_PKT register
4197 #define HW_ENET_RMON_T_BC_PKT_ADDR(x) ((x) + 0x208U)
4199 #define HW_ENET_RMON_T_BC_PKT(x) (*(__I hw_enet_rmon_t_bc_pkt_t *) HW_ENET_RMON_T_BC_PKT_ADDR(x))
4200 #define HW_ENET_RMON_T_BC_PKT_RD(x) (HW_ENET_RMON_T_BC_PKT(x).U)
4204 * Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
4208 * @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
4211 #define BP_ENET_RMON_T_BC_PKT_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_BC_PKT_TXPKTS. */
4212 #define BM_ENET_RMON_T_BC_PKT_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_BC_PKT_TXPKTS. */
4213 #define BS_ENET_RMON_T_BC_PKT_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_BC_PKT_TXPKTS. */
4215 /*! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field. */
4216 #define BR_ENET_RMON_T_BC_PKT_TXPKTS(x) (HW_ENET_RMON_T_BC_PKT(x).B.TXPKTS)
4219 /*******************************************************************************
4220 * HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
4221 ******************************************************************************/
4224 * @brief HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
4226 * Reset value: 0x00000000U
4228 typedef union _hw_enet_rmon_t_mc_pkt
4231 struct _hw_enet_rmon_t_mc_pkt_bitfields
4233 uint32_t TXPKTS : 16; /*!< [15:0] Multicast packets */
4234 uint32_t RESERVED0 : 16; /*!< [31:16] */
4236 } hw_enet_rmon_t_mc_pkt_t;
4239 * @name Constants and macros for entire ENET_RMON_T_MC_PKT register
4242 #define HW_ENET_RMON_T_MC_PKT_ADDR(x) ((x) + 0x20CU)
4244 #define HW_ENET_RMON_T_MC_PKT(x) (*(__I hw_enet_rmon_t_mc_pkt_t *) HW_ENET_RMON_T_MC_PKT_ADDR(x))
4245 #define HW_ENET_RMON_T_MC_PKT_RD(x) (HW_ENET_RMON_T_MC_PKT(x).U)
4249 * Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
4253 * @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
4256 #define BP_ENET_RMON_T_MC_PKT_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_MC_PKT_TXPKTS. */
4257 #define BM_ENET_RMON_T_MC_PKT_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_MC_PKT_TXPKTS. */
4258 #define BS_ENET_RMON_T_MC_PKT_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_MC_PKT_TXPKTS. */
4260 /*! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field. */
4261 #define BR_ENET_RMON_T_MC_PKT_TXPKTS(x) (HW_ENET_RMON_T_MC_PKT(x).B.TXPKTS)
4264 /*******************************************************************************
4265 * HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
4266 ******************************************************************************/
4269 * @brief HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
4271 * Reset value: 0x00000000U
4273 typedef union _hw_enet_rmon_t_crc_align
4276 struct _hw_enet_rmon_t_crc_align_bitfields
4278 uint32_t TXPKTS : 16; /*!< [15:0] Packets with CRC/align error */
4279 uint32_t RESERVED0 : 16; /*!< [31:16] */
4281 } hw_enet_rmon_t_crc_align_t;
4284 * @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
4287 #define HW_ENET_RMON_T_CRC_ALIGN_ADDR(x) ((x) + 0x210U)
4289 #define HW_ENET_RMON_T_CRC_ALIGN(x) (*(__I hw_enet_rmon_t_crc_align_t *) HW_ENET_RMON_T_CRC_ALIGN_ADDR(x))
4290 #define HW_ENET_RMON_T_CRC_ALIGN_RD(x) (HW_ENET_RMON_T_CRC_ALIGN(x).U)
4294 * Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
4298 * @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
4301 #define BP_ENET_RMON_T_CRC_ALIGN_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_CRC_ALIGN_TXPKTS. */
4302 #define BM_ENET_RMON_T_CRC_ALIGN_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_CRC_ALIGN_TXPKTS. */
4303 #define BS_ENET_RMON_T_CRC_ALIGN_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_CRC_ALIGN_TXPKTS. */
4305 /*! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field. */
4306 #define BR_ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (HW_ENET_RMON_T_CRC_ALIGN(x).B.TXPKTS)
4309 /*******************************************************************************
4310 * HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
4311 ******************************************************************************/
4314 * @brief HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
4316 * Reset value: 0x00000000U
4318 typedef union _hw_enet_rmon_t_undersize
4321 struct _hw_enet_rmon_t_undersize_bitfields
4323 uint32_t TXPKTS : 16; /*!< [15:0] Packet count */
4324 uint32_t RESERVED0 : 16; /*!< [31:16] */
4326 } hw_enet_rmon_t_undersize_t;
4329 * @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
4332 #define HW_ENET_RMON_T_UNDERSIZE_ADDR(x) ((x) + 0x214U)
4334 #define HW_ENET_RMON_T_UNDERSIZE(x) (*(__I hw_enet_rmon_t_undersize_t *) HW_ENET_RMON_T_UNDERSIZE_ADDR(x))
4335 #define HW_ENET_RMON_T_UNDERSIZE_RD(x) (HW_ENET_RMON_T_UNDERSIZE(x).U)
4339 * Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
4343 * @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
4346 #define BP_ENET_RMON_T_UNDERSIZE_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_UNDERSIZE_TXPKTS. */
4347 #define BM_ENET_RMON_T_UNDERSIZE_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_UNDERSIZE_TXPKTS. */
4348 #define BS_ENET_RMON_T_UNDERSIZE_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_UNDERSIZE_TXPKTS. */
4350 /*! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field. */
4351 #define BR_ENET_RMON_T_UNDERSIZE_TXPKTS(x) (HW_ENET_RMON_T_UNDERSIZE(x).B.TXPKTS)
4354 /*******************************************************************************
4355 * HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
4356 ******************************************************************************/
4359 * @brief HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
4361 * Reset value: 0x00000000U
4363 typedef union _hw_enet_rmon_t_oversize
4366 struct _hw_enet_rmon_t_oversize_bitfields
4368 uint32_t TXPKTS : 16; /*!< [15:0] Packet count */
4369 uint32_t RESERVED0 : 16; /*!< [31:16] */
4371 } hw_enet_rmon_t_oversize_t;
4374 * @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
4377 #define HW_ENET_RMON_T_OVERSIZE_ADDR(x) ((x) + 0x218U)
4379 #define HW_ENET_RMON_T_OVERSIZE(x) (*(__I hw_enet_rmon_t_oversize_t *) HW_ENET_RMON_T_OVERSIZE_ADDR(x))
4380 #define HW_ENET_RMON_T_OVERSIZE_RD(x) (HW_ENET_RMON_T_OVERSIZE(x).U)
4384 * Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
4388 * @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
4391 #define BP_ENET_RMON_T_OVERSIZE_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_OVERSIZE_TXPKTS. */
4392 #define BM_ENET_RMON_T_OVERSIZE_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_OVERSIZE_TXPKTS. */
4393 #define BS_ENET_RMON_T_OVERSIZE_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_OVERSIZE_TXPKTS. */
4395 /*! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field. */
4396 #define BR_ENET_RMON_T_OVERSIZE_TXPKTS(x) (HW_ENET_RMON_T_OVERSIZE(x).B.TXPKTS)
4399 /*******************************************************************************
4400 * HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
4401 ******************************************************************************/
4404 * @brief HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
4406 * Reset value: 0x00000000U
4410 typedef union _hw_enet_rmon_t_frag
4413 struct _hw_enet_rmon_t_frag_bitfields
4415 uint32_t TXPKTS : 16; /*!< [15:0] Packet count */
4416 uint32_t RESERVED0 : 16; /*!< [31:16] */
4418 } hw_enet_rmon_t_frag_t;
4421 * @name Constants and macros for entire ENET_RMON_T_FRAG register
4424 #define HW_ENET_RMON_T_FRAG_ADDR(x) ((x) + 0x21CU)
4426 #define HW_ENET_RMON_T_FRAG(x) (*(__I hw_enet_rmon_t_frag_t *) HW_ENET_RMON_T_FRAG_ADDR(x))
4427 #define HW_ENET_RMON_T_FRAG_RD(x) (HW_ENET_RMON_T_FRAG(x).U)
4431 * Constants & macros for individual ENET_RMON_T_FRAG bitfields
4435 * @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
4438 #define BP_ENET_RMON_T_FRAG_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_FRAG_TXPKTS. */
4439 #define BM_ENET_RMON_T_FRAG_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_FRAG_TXPKTS. */
4440 #define BS_ENET_RMON_T_FRAG_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_FRAG_TXPKTS. */
4442 /*! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field. */
4443 #define BR_ENET_RMON_T_FRAG_TXPKTS(x) (HW_ENET_RMON_T_FRAG(x).B.TXPKTS)
4446 /*******************************************************************************
4447 * HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
4448 ******************************************************************************/
4451 * @brief HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
4453 * Reset value: 0x00000000U
4455 typedef union _hw_enet_rmon_t_jab
4458 struct _hw_enet_rmon_t_jab_bitfields
4460 uint32_t TXPKTS : 16; /*!< [15:0] Packet count */
4461 uint32_t RESERVED0 : 16; /*!< [31:16] */
4463 } hw_enet_rmon_t_jab_t;
4466 * @name Constants and macros for entire ENET_RMON_T_JAB register
4469 #define HW_ENET_RMON_T_JAB_ADDR(x) ((x) + 0x220U)
4471 #define HW_ENET_RMON_T_JAB(x) (*(__I hw_enet_rmon_t_jab_t *) HW_ENET_RMON_T_JAB_ADDR(x))
4472 #define HW_ENET_RMON_T_JAB_RD(x) (HW_ENET_RMON_T_JAB(x).U)
4476 * Constants & macros for individual ENET_RMON_T_JAB bitfields
4480 * @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
4483 #define BP_ENET_RMON_T_JAB_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_JAB_TXPKTS. */
4484 #define BM_ENET_RMON_T_JAB_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_JAB_TXPKTS. */
4485 #define BS_ENET_RMON_T_JAB_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_JAB_TXPKTS. */
4487 /*! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field. */
4488 #define BR_ENET_RMON_T_JAB_TXPKTS(x) (HW_ENET_RMON_T_JAB(x).B.TXPKTS)
4491 /*******************************************************************************
4492 * HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
4493 ******************************************************************************/
4496 * @brief HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
4498 * Reset value: 0x00000000U
4500 typedef union _hw_enet_rmon_t_col
4503 struct _hw_enet_rmon_t_col_bitfields
4505 uint32_t TXPKTS : 16; /*!< [15:0] Packet count */
4506 uint32_t RESERVED0 : 16; /*!< [31:16] */
4508 } hw_enet_rmon_t_col_t;
4511 * @name Constants and macros for entire ENET_RMON_T_COL register
4514 #define HW_ENET_RMON_T_COL_ADDR(x) ((x) + 0x224U)
4516 #define HW_ENET_RMON_T_COL(x) (*(__I hw_enet_rmon_t_col_t *) HW_ENET_RMON_T_COL_ADDR(x))
4517 #define HW_ENET_RMON_T_COL_RD(x) (HW_ENET_RMON_T_COL(x).U)
4521 * Constants & macros for individual ENET_RMON_T_COL bitfields
4525 * @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
4528 #define BP_ENET_RMON_T_COL_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_COL_TXPKTS. */
4529 #define BM_ENET_RMON_T_COL_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_COL_TXPKTS. */
4530 #define BS_ENET_RMON_T_COL_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_COL_TXPKTS. */
4532 /*! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field. */
4533 #define BR_ENET_RMON_T_COL_TXPKTS(x) (HW_ENET_RMON_T_COL(x).B.TXPKTS)
4536 /*******************************************************************************
4537 * HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
4538 ******************************************************************************/
4541 * @brief HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
4543 * Reset value: 0x00000000U
4547 typedef union _hw_enet_rmon_t_p64
4550 struct _hw_enet_rmon_t_p64_bitfields
4552 uint32_t TXPKTS : 16; /*!< [15:0] Packet count */
4553 uint32_t RESERVED0 : 16; /*!< [31:16] */
4555 } hw_enet_rmon_t_p64_t;
4558 * @name Constants and macros for entire ENET_RMON_T_P64 register
4561 #define HW_ENET_RMON_T_P64_ADDR(x) ((x) + 0x228U)
4563 #define HW_ENET_RMON_T_P64(x) (*(__I hw_enet_rmon_t_p64_t *) HW_ENET_RMON_T_P64_ADDR(x))
4564 #define HW_ENET_RMON_T_P64_RD(x) (HW_ENET_RMON_T_P64(x).U)
4568 * Constants & macros for individual ENET_RMON_T_P64 bitfields
4572 * @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
4575 #define BP_ENET_RMON_T_P64_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P64_TXPKTS. */
4576 #define BM_ENET_RMON_T_P64_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P64_TXPKTS. */
4577 #define BS_ENET_RMON_T_P64_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P64_TXPKTS. */
4579 /*! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field. */
4580 #define BR_ENET_RMON_T_P64_TXPKTS(x) (HW_ENET_RMON_T_P64(x).B.TXPKTS)
4583 /*******************************************************************************
4584 * HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
4585 ******************************************************************************/
4588 * @brief HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
4590 * Reset value: 0x00000000U
4592 typedef union _hw_enet_rmon_t_p65to127
4595 struct _hw_enet_rmon_t_p65to127_bitfields
4597 uint32_t TXPKTS : 16; /*!< [15:0] Packet count */
4598 uint32_t RESERVED0 : 16; /*!< [31:16] */
4600 } hw_enet_rmon_t_p65to127_t;
4603 * @name Constants and macros for entire ENET_RMON_T_P65TO127 register
4606 #define HW_ENET_RMON_T_P65TO127_ADDR(x) ((x) + 0x22CU)
4608 #define HW_ENET_RMON_T_P65TO127(x) (*(__I hw_enet_rmon_t_p65to127_t *) HW_ENET_RMON_T_P65TO127_ADDR(x))
4609 #define HW_ENET_RMON_T_P65TO127_RD(x) (HW_ENET_RMON_T_P65TO127(x).U)
4613 * Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
4617 * @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
4620 #define BP_ENET_RMON_T_P65TO127_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P65TO127_TXPKTS. */
4621 #define BM_ENET_RMON_T_P65TO127_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P65TO127_TXPKTS. */
4622 #define BS_ENET_RMON_T_P65TO127_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P65TO127_TXPKTS. */
4624 /*! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field. */
4625 #define BR_ENET_RMON_T_P65TO127_TXPKTS(x) (HW_ENET_RMON_T_P65TO127(x).B.TXPKTS)
4628 /*******************************************************************************
4629 * HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
4630 ******************************************************************************/
4633 * @brief HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
4635 * Reset value: 0x00000000U
4637 typedef union _hw_enet_rmon_t_p128to255
4640 struct _hw_enet_rmon_t_p128to255_bitfields
4642 uint32_t TXPKTS : 16; /*!< [15:0] Packet count */
4643 uint32_t RESERVED0 : 16; /*!< [31:16] */
4645 } hw_enet_rmon_t_p128to255_t;
4648 * @name Constants and macros for entire ENET_RMON_T_P128TO255 register
4651 #define HW_ENET_RMON_T_P128TO255_ADDR(x) ((x) + 0x230U)
4653 #define HW_ENET_RMON_T_P128TO255(x) (*(__I hw_enet_rmon_t_p128to255_t *) HW_ENET_RMON_T_P128TO255_ADDR(x))
4654 #define HW_ENET_RMON_T_P128TO255_RD(x) (HW_ENET_RMON_T_P128TO255(x).U)
4658 * Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
4662 * @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
4665 #define BP_ENET_RMON_T_P128TO255_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P128TO255_TXPKTS. */
4666 #define BM_ENET_RMON_T_P128TO255_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P128TO255_TXPKTS. */
4667 #define BS_ENET_RMON_T_P128TO255_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P128TO255_TXPKTS. */
4669 /*! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field. */
4670 #define BR_ENET_RMON_T_P128TO255_TXPKTS(x) (HW_ENET_RMON_T_P128TO255(x).B.TXPKTS)
4673 /*******************************************************************************
4674 * HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
4675 ******************************************************************************/
4678 * @brief HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
4680 * Reset value: 0x00000000U
4682 typedef union _hw_enet_rmon_t_p256to511
4685 struct _hw_enet_rmon_t_p256to511_bitfields
4687 uint32_t TXPKTS : 16; /*!< [15:0] Packet count */
4688 uint32_t RESERVED0 : 16; /*!< [31:16] */
4690 } hw_enet_rmon_t_p256to511_t;
4693 * @name Constants and macros for entire ENET_RMON_T_P256TO511 register
4696 #define HW_ENET_RMON_T_P256TO511_ADDR(x) ((x) + 0x234U)
4698 #define HW_ENET_RMON_T_P256TO511(x) (*(__I hw_enet_rmon_t_p256to511_t *) HW_ENET_RMON_T_P256TO511_ADDR(x))
4699 #define HW_ENET_RMON_T_P256TO511_RD(x) (HW_ENET_RMON_T_P256TO511(x).U)
4703 * Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
4707 * @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
4710 #define BP_ENET_RMON_T_P256TO511_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P256TO511_TXPKTS. */
4711 #define BM_ENET_RMON_T_P256TO511_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P256TO511_TXPKTS. */
4712 #define BS_ENET_RMON_T_P256TO511_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P256TO511_TXPKTS. */
4714 /*! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field. */
4715 #define BR_ENET_RMON_T_P256TO511_TXPKTS(x) (HW_ENET_RMON_T_P256TO511(x).B.TXPKTS)
4718 /*******************************************************************************
4719 * HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
4720 ******************************************************************************/
4723 * @brief HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
4725 * Reset value: 0x00000000U
4729 typedef union _hw_enet_rmon_t_p512to1023
4732 struct _hw_enet_rmon_t_p512to1023_bitfields
4734 uint32_t TXPKTS : 16; /*!< [15:0] Packet count */
4735 uint32_t RESERVED0 : 16; /*!< [31:16] */
4737 } hw_enet_rmon_t_p512to1023_t;
4740 * @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
4743 #define HW_ENET_RMON_T_P512TO1023_ADDR(x) ((x) + 0x238U)
4745 #define HW_ENET_RMON_T_P512TO1023(x) (*(__I hw_enet_rmon_t_p512to1023_t *) HW_ENET_RMON_T_P512TO1023_ADDR(x))
4746 #define HW_ENET_RMON_T_P512TO1023_RD(x) (HW_ENET_RMON_T_P512TO1023(x).U)
4750 * Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
4754 * @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
4757 #define BP_ENET_RMON_T_P512TO1023_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P512TO1023_TXPKTS. */
4758 #define BM_ENET_RMON_T_P512TO1023_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P512TO1023_TXPKTS. */
4759 #define BS_ENET_RMON_T_P512TO1023_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P512TO1023_TXPKTS. */
4761 /*! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field. */
4762 #define BR_ENET_RMON_T_P512TO1023_TXPKTS(x) (HW_ENET_RMON_T_P512TO1023(x).B.TXPKTS)
4765 /*******************************************************************************
4766 * HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
4767 ******************************************************************************/
4770 * @brief HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
4772 * Reset value: 0x00000000U
4774 typedef union _hw_enet_rmon_t_p1024to2047
4777 struct _hw_enet_rmon_t_p1024to2047_bitfields
4779 uint32_t TXPKTS : 16; /*!< [15:0] Packet count */
4780 uint32_t RESERVED0 : 16; /*!< [31:16] */
4782 } hw_enet_rmon_t_p1024to2047_t;
4785 * @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
4788 #define HW_ENET_RMON_T_P1024TO2047_ADDR(x) ((x) + 0x23CU)
4790 #define HW_ENET_RMON_T_P1024TO2047(x) (*(__I hw_enet_rmon_t_p1024to2047_t *) HW_ENET_RMON_T_P1024TO2047_ADDR(x))
4791 #define HW_ENET_RMON_T_P1024TO2047_RD(x) (HW_ENET_RMON_T_P1024TO2047(x).U)
4795 * Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
4799 * @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
4802 #define BP_ENET_RMON_T_P1024TO2047_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P1024TO2047_TXPKTS. */
4803 #define BM_ENET_RMON_T_P1024TO2047_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P1024TO2047_TXPKTS. */
4804 #define BS_ENET_RMON_T_P1024TO2047_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P1024TO2047_TXPKTS. */
4806 /*! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field. */
4807 #define BR_ENET_RMON_T_P1024TO2047_TXPKTS(x) (HW_ENET_RMON_T_P1024TO2047(x).B.TXPKTS)
4810 /*******************************************************************************
4811 * HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
4812 ******************************************************************************/
4815 * @brief HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
4817 * Reset value: 0x00000000U
4819 typedef union _hw_enet_rmon_t_p_gte2048
4822 struct _hw_enet_rmon_t_p_gte2048_bitfields
4824 uint32_t TXPKTS : 16; /*!< [15:0] Packet count */
4825 uint32_t RESERVED0 : 16; /*!< [31:16] */
4827 } hw_enet_rmon_t_p_gte2048_t;
4830 * @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
4833 #define HW_ENET_RMON_T_P_GTE2048_ADDR(x) ((x) + 0x240U)
4835 #define HW_ENET_RMON_T_P_GTE2048(x) (*(__I hw_enet_rmon_t_p_gte2048_t *) HW_ENET_RMON_T_P_GTE2048_ADDR(x))
4836 #define HW_ENET_RMON_T_P_GTE2048_RD(x) (HW_ENET_RMON_T_P_GTE2048(x).U)
4840 * Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
4844 * @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
4847 #define BP_ENET_RMON_T_P_GTE2048_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P_GTE2048_TXPKTS. */
4848 #define BM_ENET_RMON_T_P_GTE2048_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P_GTE2048_TXPKTS. */
4849 #define BS_ENET_RMON_T_P_GTE2048_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P_GTE2048_TXPKTS. */
4851 /*! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field. */
4852 #define BR_ENET_RMON_T_P_GTE2048_TXPKTS(x) (HW_ENET_RMON_T_P_GTE2048(x).B.TXPKTS)
4855 /*******************************************************************************
4856 * HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
4857 ******************************************************************************/
4860 * @brief HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
4862 * Reset value: 0x00000000U
4864 typedef union _hw_enet_rmon_t_octets
4867 struct _hw_enet_rmon_t_octets_bitfields
4869 uint32_t TXOCTS : 32; /*!< [31:0] Octet count */
4871 } hw_enet_rmon_t_octets_t;
4874 * @name Constants and macros for entire ENET_RMON_T_OCTETS register
4877 #define HW_ENET_RMON_T_OCTETS_ADDR(x) ((x) + 0x244U)
4879 #define HW_ENET_RMON_T_OCTETS(x) (*(__I hw_enet_rmon_t_octets_t *) HW_ENET_RMON_T_OCTETS_ADDR(x))
4880 #define HW_ENET_RMON_T_OCTETS_RD(x) (HW_ENET_RMON_T_OCTETS(x).U)
4884 * Constants & macros for individual ENET_RMON_T_OCTETS bitfields
4888 * @name Register ENET_RMON_T_OCTETS, field TXOCTS[31:0] (RO)
4891 #define BP_ENET_RMON_T_OCTETS_TXOCTS (0U) /*!< Bit position for ENET_RMON_T_OCTETS_TXOCTS. */
4892 #define BM_ENET_RMON_T_OCTETS_TXOCTS (0xFFFFFFFFU) /*!< Bit mask for ENET_RMON_T_OCTETS_TXOCTS. */
4893 #define BS_ENET_RMON_T_OCTETS_TXOCTS (32U) /*!< Bit field size in bits for ENET_RMON_T_OCTETS_TXOCTS. */
4895 /*! @brief Read current value of the ENET_RMON_T_OCTETS_TXOCTS field. */
4896 #define BR_ENET_RMON_T_OCTETS_TXOCTS(x) (HW_ENET_RMON_T_OCTETS(x).U)
4899 /*******************************************************************************
4900 * HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
4901 ******************************************************************************/
4904 * @brief HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
4906 * Reset value: 0x00000000U
4908 typedef union _hw_enet_ieee_t_frame_ok
4911 struct _hw_enet_ieee_t_frame_ok_bitfields
4913 uint32_t COUNT : 16; /*!< [15:0] Frame count */
4914 uint32_t RESERVED0 : 16; /*!< [31:16] */
4916 } hw_enet_ieee_t_frame_ok_t;
4919 * @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
4922 #define HW_ENET_IEEE_T_FRAME_OK_ADDR(x) ((x) + 0x24CU)
4924 #define HW_ENET_IEEE_T_FRAME_OK(x) (*(__I hw_enet_ieee_t_frame_ok_t *) HW_ENET_IEEE_T_FRAME_OK_ADDR(x))
4925 #define HW_ENET_IEEE_T_FRAME_OK_RD(x) (HW_ENET_IEEE_T_FRAME_OK(x).U)
4929 * Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
4933 * @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
4936 #define BP_ENET_IEEE_T_FRAME_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_T_FRAME_OK_COUNT. */
4937 #define BM_ENET_IEEE_T_FRAME_OK_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_FRAME_OK_COUNT. */
4938 #define BS_ENET_IEEE_T_FRAME_OK_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_FRAME_OK_COUNT. */
4940 /*! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field. */
4941 #define BR_ENET_IEEE_T_FRAME_OK_COUNT(x) (HW_ENET_IEEE_T_FRAME_OK(x).B.COUNT)
4944 /*******************************************************************************
4945 * HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
4946 ******************************************************************************/
4949 * @brief HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
4951 * Reset value: 0x00000000U
4953 typedef union _hw_enet_ieee_t_1col
4956 struct _hw_enet_ieee_t_1col_bitfields
4958 uint32_t COUNT : 16; /*!< [15:0] Frame count */
4959 uint32_t RESERVED0 : 16; /*!< [31:16] */
4961 } hw_enet_ieee_t_1col_t;
4964 * @name Constants and macros for entire ENET_IEEE_T_1COL register
4967 #define HW_ENET_IEEE_T_1COL_ADDR(x) ((x) + 0x250U)
4969 #define HW_ENET_IEEE_T_1COL(x) (*(__I hw_enet_ieee_t_1col_t *) HW_ENET_IEEE_T_1COL_ADDR(x))
4970 #define HW_ENET_IEEE_T_1COL_RD(x) (HW_ENET_IEEE_T_1COL(x).U)
4974 * Constants & macros for individual ENET_IEEE_T_1COL bitfields
4978 * @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
4981 #define BP_ENET_IEEE_T_1COL_COUNT (0U) /*!< Bit position for ENET_IEEE_T_1COL_COUNT. */
4982 #define BM_ENET_IEEE_T_1COL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_1COL_COUNT. */
4983 #define BS_ENET_IEEE_T_1COL_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_1COL_COUNT. */
4985 /*! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field. */
4986 #define BR_ENET_IEEE_T_1COL_COUNT(x) (HW_ENET_IEEE_T_1COL(x).B.COUNT)
4989 /*******************************************************************************
4990 * HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
4991 ******************************************************************************/
4994 * @brief HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
4996 * Reset value: 0x00000000U
4998 typedef union _hw_enet_ieee_t_mcol
5001 struct _hw_enet_ieee_t_mcol_bitfields
5003 uint32_t COUNT : 16; /*!< [15:0] Frame count */
5004 uint32_t RESERVED0 : 16; /*!< [31:16] */
5006 } hw_enet_ieee_t_mcol_t;
5009 * @name Constants and macros for entire ENET_IEEE_T_MCOL register
5012 #define HW_ENET_IEEE_T_MCOL_ADDR(x) ((x) + 0x254U)
5014 #define HW_ENET_IEEE_T_MCOL(x) (*(__I hw_enet_ieee_t_mcol_t *) HW_ENET_IEEE_T_MCOL_ADDR(x))
5015 #define HW_ENET_IEEE_T_MCOL_RD(x) (HW_ENET_IEEE_T_MCOL(x).U)
5019 * Constants & macros for individual ENET_IEEE_T_MCOL bitfields
5023 * @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
5026 #define BP_ENET_IEEE_T_MCOL_COUNT (0U) /*!< Bit position for ENET_IEEE_T_MCOL_COUNT. */
5027 #define BM_ENET_IEEE_T_MCOL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_MCOL_COUNT. */
5028 #define BS_ENET_IEEE_T_MCOL_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_MCOL_COUNT. */
5030 /*! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field. */
5031 #define BR_ENET_IEEE_T_MCOL_COUNT(x) (HW_ENET_IEEE_T_MCOL(x).B.COUNT)
5034 /*******************************************************************************
5035 * HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
5036 ******************************************************************************/
5039 * @brief HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
5041 * Reset value: 0x00000000U
5043 typedef union _hw_enet_ieee_t_def
5046 struct _hw_enet_ieee_t_def_bitfields
5048 uint32_t COUNT : 16; /*!< [15:0] Frame count */
5049 uint32_t RESERVED0 : 16; /*!< [31:16] */
5051 } hw_enet_ieee_t_def_t;
5054 * @name Constants and macros for entire ENET_IEEE_T_DEF register
5057 #define HW_ENET_IEEE_T_DEF_ADDR(x) ((x) + 0x258U)
5059 #define HW_ENET_IEEE_T_DEF(x) (*(__I hw_enet_ieee_t_def_t *) HW_ENET_IEEE_T_DEF_ADDR(x))
5060 #define HW_ENET_IEEE_T_DEF_RD(x) (HW_ENET_IEEE_T_DEF(x).U)
5064 * Constants & macros for individual ENET_IEEE_T_DEF bitfields
5068 * @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
5071 #define BP_ENET_IEEE_T_DEF_COUNT (0U) /*!< Bit position for ENET_IEEE_T_DEF_COUNT. */
5072 #define BM_ENET_IEEE_T_DEF_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_DEF_COUNT. */
5073 #define BS_ENET_IEEE_T_DEF_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_DEF_COUNT. */
5075 /*! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field. */
5076 #define BR_ENET_IEEE_T_DEF_COUNT(x) (HW_ENET_IEEE_T_DEF(x).B.COUNT)
5079 /*******************************************************************************
5080 * HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
5081 ******************************************************************************/
5084 * @brief HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
5086 * Reset value: 0x00000000U
5088 typedef union _hw_enet_ieee_t_lcol
5091 struct _hw_enet_ieee_t_lcol_bitfields
5093 uint32_t COUNT : 16; /*!< [15:0] Frame count */
5094 uint32_t RESERVED0 : 16; /*!< [31:16] */
5096 } hw_enet_ieee_t_lcol_t;
5099 * @name Constants and macros for entire ENET_IEEE_T_LCOL register
5102 #define HW_ENET_IEEE_T_LCOL_ADDR(x) ((x) + 0x25CU)
5104 #define HW_ENET_IEEE_T_LCOL(x) (*(__I hw_enet_ieee_t_lcol_t *) HW_ENET_IEEE_T_LCOL_ADDR(x))
5105 #define HW_ENET_IEEE_T_LCOL_RD(x) (HW_ENET_IEEE_T_LCOL(x).U)
5109 * Constants & macros for individual ENET_IEEE_T_LCOL bitfields
5113 * @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
5116 #define BP_ENET_IEEE_T_LCOL_COUNT (0U) /*!< Bit position for ENET_IEEE_T_LCOL_COUNT. */
5117 #define BM_ENET_IEEE_T_LCOL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_LCOL_COUNT. */
5118 #define BS_ENET_IEEE_T_LCOL_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_LCOL_COUNT. */
5120 /*! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field. */
5121 #define BR_ENET_IEEE_T_LCOL_COUNT(x) (HW_ENET_IEEE_T_LCOL(x).B.COUNT)
5124 /*******************************************************************************
5125 * HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
5126 ******************************************************************************/
5129 * @brief HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
5131 * Reset value: 0x00000000U
5133 typedef union _hw_enet_ieee_t_excol
5136 struct _hw_enet_ieee_t_excol_bitfields
5138 uint32_t COUNT : 16; /*!< [15:0] Frame count */
5139 uint32_t RESERVED0 : 16; /*!< [31:16] */
5141 } hw_enet_ieee_t_excol_t;
5144 * @name Constants and macros for entire ENET_IEEE_T_EXCOL register
5147 #define HW_ENET_IEEE_T_EXCOL_ADDR(x) ((x) + 0x260U)
5149 #define HW_ENET_IEEE_T_EXCOL(x) (*(__I hw_enet_ieee_t_excol_t *) HW_ENET_IEEE_T_EXCOL_ADDR(x))
5150 #define HW_ENET_IEEE_T_EXCOL_RD(x) (HW_ENET_IEEE_T_EXCOL(x).U)
5154 * Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
5158 * @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
5161 #define BP_ENET_IEEE_T_EXCOL_COUNT (0U) /*!< Bit position for ENET_IEEE_T_EXCOL_COUNT. */
5162 #define BM_ENET_IEEE_T_EXCOL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_EXCOL_COUNT. */
5163 #define BS_ENET_IEEE_T_EXCOL_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_EXCOL_COUNT. */
5165 /*! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field. */
5166 #define BR_ENET_IEEE_T_EXCOL_COUNT(x) (HW_ENET_IEEE_T_EXCOL(x).B.COUNT)
5169 /*******************************************************************************
5170 * HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
5171 ******************************************************************************/
5174 * @brief HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
5176 * Reset value: 0x00000000U
5178 typedef union _hw_enet_ieee_t_macerr
5181 struct _hw_enet_ieee_t_macerr_bitfields
5183 uint32_t COUNT : 16; /*!< [15:0] Frame count */
5184 uint32_t RESERVED0 : 16; /*!< [31:16] */
5186 } hw_enet_ieee_t_macerr_t;
5189 * @name Constants and macros for entire ENET_IEEE_T_MACERR register
5192 #define HW_ENET_IEEE_T_MACERR_ADDR(x) ((x) + 0x264U)
5194 #define HW_ENET_IEEE_T_MACERR(x) (*(__I hw_enet_ieee_t_macerr_t *) HW_ENET_IEEE_T_MACERR_ADDR(x))
5195 #define HW_ENET_IEEE_T_MACERR_RD(x) (HW_ENET_IEEE_T_MACERR(x).U)
5199 * Constants & macros for individual ENET_IEEE_T_MACERR bitfields
5203 * @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
5206 #define BP_ENET_IEEE_T_MACERR_COUNT (0U) /*!< Bit position for ENET_IEEE_T_MACERR_COUNT. */
5207 #define BM_ENET_IEEE_T_MACERR_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_MACERR_COUNT. */
5208 #define BS_ENET_IEEE_T_MACERR_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_MACERR_COUNT. */
5210 /*! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field. */
5211 #define BR_ENET_IEEE_T_MACERR_COUNT(x) (HW_ENET_IEEE_T_MACERR(x).B.COUNT)
5214 /*******************************************************************************
5215 * HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
5216 ******************************************************************************/
5219 * @brief HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
5221 * Reset value: 0x00000000U
5223 typedef union _hw_enet_ieee_t_cserr
5226 struct _hw_enet_ieee_t_cserr_bitfields
5228 uint32_t COUNT : 16; /*!< [15:0] Frame count */
5229 uint32_t RESERVED0 : 16; /*!< [31:16] */
5231 } hw_enet_ieee_t_cserr_t;
5234 * @name Constants and macros for entire ENET_IEEE_T_CSERR register
5237 #define HW_ENET_IEEE_T_CSERR_ADDR(x) ((x) + 0x268U)
5239 #define HW_ENET_IEEE_T_CSERR(x) (*(__I hw_enet_ieee_t_cserr_t *) HW_ENET_IEEE_T_CSERR_ADDR(x))
5240 #define HW_ENET_IEEE_T_CSERR_RD(x) (HW_ENET_IEEE_T_CSERR(x).U)
5244 * Constants & macros for individual ENET_IEEE_T_CSERR bitfields
5248 * @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
5251 #define BP_ENET_IEEE_T_CSERR_COUNT (0U) /*!< Bit position for ENET_IEEE_T_CSERR_COUNT. */
5252 #define BM_ENET_IEEE_T_CSERR_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_CSERR_COUNT. */
5253 #define BS_ENET_IEEE_T_CSERR_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_CSERR_COUNT. */
5255 /*! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field. */
5256 #define BR_ENET_IEEE_T_CSERR_COUNT(x) (HW_ENET_IEEE_T_CSERR(x).B.COUNT)
5259 /*******************************************************************************
5260 * HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
5261 ******************************************************************************/
5264 * @brief HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
5266 * Reset value: 0x00000000U
5268 typedef union _hw_enet_ieee_t_fdxfc
5271 struct _hw_enet_ieee_t_fdxfc_bitfields
5273 uint32_t COUNT : 16; /*!< [15:0] Frame count */
5274 uint32_t RESERVED0 : 16; /*!< [31:16] */
5276 } hw_enet_ieee_t_fdxfc_t;
5279 * @name Constants and macros for entire ENET_IEEE_T_FDXFC register
5282 #define HW_ENET_IEEE_T_FDXFC_ADDR(x) ((x) + 0x270U)
5284 #define HW_ENET_IEEE_T_FDXFC(x) (*(__I hw_enet_ieee_t_fdxfc_t *) HW_ENET_IEEE_T_FDXFC_ADDR(x))
5285 #define HW_ENET_IEEE_T_FDXFC_RD(x) (HW_ENET_IEEE_T_FDXFC(x).U)
5289 * Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
5293 * @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
5296 #define BP_ENET_IEEE_T_FDXFC_COUNT (0U) /*!< Bit position for ENET_IEEE_T_FDXFC_COUNT. */
5297 #define BM_ENET_IEEE_T_FDXFC_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_FDXFC_COUNT. */
5298 #define BS_ENET_IEEE_T_FDXFC_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_FDXFC_COUNT. */
5300 /*! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field. */
5301 #define BR_ENET_IEEE_T_FDXFC_COUNT(x) (HW_ENET_IEEE_T_FDXFC(x).B.COUNT)
5304 /*******************************************************************************
5305 * HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
5306 ******************************************************************************/
5309 * @brief HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
5311 * Reset value: 0x00000000U
5313 * Counts total octets (includes header and FCS fields).
5315 typedef union _hw_enet_ieee_t_octets_ok
5318 struct _hw_enet_ieee_t_octets_ok_bitfields
5320 uint32_t COUNT : 32; /*!< [31:0] Octet count */
5322 } hw_enet_ieee_t_octets_ok_t;
5325 * @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
5328 #define HW_ENET_IEEE_T_OCTETS_OK_ADDR(x) ((x) + 0x274U)
5330 #define HW_ENET_IEEE_T_OCTETS_OK(x) (*(__I hw_enet_ieee_t_octets_ok_t *) HW_ENET_IEEE_T_OCTETS_OK_ADDR(x))
5331 #define HW_ENET_IEEE_T_OCTETS_OK_RD(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
5335 * Constants & macros for individual ENET_IEEE_T_OCTETS_OK bitfields
5339 * @name Register ENET_IEEE_T_OCTETS_OK, field COUNT[31:0] (RO)
5342 #define BP_ENET_IEEE_T_OCTETS_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_T_OCTETS_OK_COUNT. */
5343 #define BM_ENET_IEEE_T_OCTETS_OK_COUNT (0xFFFFFFFFU) /*!< Bit mask for ENET_IEEE_T_OCTETS_OK_COUNT. */
5344 #define BS_ENET_IEEE_T_OCTETS_OK_COUNT (32U) /*!< Bit field size in bits for ENET_IEEE_T_OCTETS_OK_COUNT. */
5346 /*! @brief Read current value of the ENET_IEEE_T_OCTETS_OK_COUNT field. */
5347 #define BR_ENET_IEEE_T_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
5350 /*******************************************************************************
5351 * HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
5352 ******************************************************************************/
5355 * @brief HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
5357 * Reset value: 0x00000000U
5359 typedef union _hw_enet_rmon_r_packets
5362 struct _hw_enet_rmon_r_packets_bitfields
5364 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5365 uint32_t RESERVED0 : 16; /*!< [31:16] */
5367 } hw_enet_rmon_r_packets_t;
5370 * @name Constants and macros for entire ENET_RMON_R_PACKETS register
5373 #define HW_ENET_RMON_R_PACKETS_ADDR(x) ((x) + 0x284U)
5375 #define HW_ENET_RMON_R_PACKETS(x) (*(__I hw_enet_rmon_r_packets_t *) HW_ENET_RMON_R_PACKETS_ADDR(x))
5376 #define HW_ENET_RMON_R_PACKETS_RD(x) (HW_ENET_RMON_R_PACKETS(x).U)
5380 * Constants & macros for individual ENET_RMON_R_PACKETS bitfields
5384 * @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
5387 #define BP_ENET_RMON_R_PACKETS_COUNT (0U) /*!< Bit position for ENET_RMON_R_PACKETS_COUNT. */
5388 #define BM_ENET_RMON_R_PACKETS_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_PACKETS_COUNT. */
5389 #define BS_ENET_RMON_R_PACKETS_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_PACKETS_COUNT. */
5391 /*! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field. */
5392 #define BR_ENET_RMON_R_PACKETS_COUNT(x) (HW_ENET_RMON_R_PACKETS(x).B.COUNT)
5395 /*******************************************************************************
5396 * HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
5397 ******************************************************************************/
5400 * @brief HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
5402 * Reset value: 0x00000000U
5404 typedef union _hw_enet_rmon_r_bc_pkt
5407 struct _hw_enet_rmon_r_bc_pkt_bitfields
5409 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5410 uint32_t RESERVED0 : 16; /*!< [31:16] */
5412 } hw_enet_rmon_r_bc_pkt_t;
5415 * @name Constants and macros for entire ENET_RMON_R_BC_PKT register
5418 #define HW_ENET_RMON_R_BC_PKT_ADDR(x) ((x) + 0x288U)
5420 #define HW_ENET_RMON_R_BC_PKT(x) (*(__I hw_enet_rmon_r_bc_pkt_t *) HW_ENET_RMON_R_BC_PKT_ADDR(x))
5421 #define HW_ENET_RMON_R_BC_PKT_RD(x) (HW_ENET_RMON_R_BC_PKT(x).U)
5425 * Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
5429 * @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
5432 #define BP_ENET_RMON_R_BC_PKT_COUNT (0U) /*!< Bit position for ENET_RMON_R_BC_PKT_COUNT. */
5433 #define BM_ENET_RMON_R_BC_PKT_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_BC_PKT_COUNT. */
5434 #define BS_ENET_RMON_R_BC_PKT_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_BC_PKT_COUNT. */
5436 /*! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field. */
5437 #define BR_ENET_RMON_R_BC_PKT_COUNT(x) (HW_ENET_RMON_R_BC_PKT(x).B.COUNT)
5440 /*******************************************************************************
5441 * HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
5442 ******************************************************************************/
5445 * @brief HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
5447 * Reset value: 0x00000000U
5449 typedef union _hw_enet_rmon_r_mc_pkt
5452 struct _hw_enet_rmon_r_mc_pkt_bitfields
5454 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5455 uint32_t RESERVED0 : 16; /*!< [31:16] */
5457 } hw_enet_rmon_r_mc_pkt_t;
5460 * @name Constants and macros for entire ENET_RMON_R_MC_PKT register
5463 #define HW_ENET_RMON_R_MC_PKT_ADDR(x) ((x) + 0x28CU)
5465 #define HW_ENET_RMON_R_MC_PKT(x) (*(__I hw_enet_rmon_r_mc_pkt_t *) HW_ENET_RMON_R_MC_PKT_ADDR(x))
5466 #define HW_ENET_RMON_R_MC_PKT_RD(x) (HW_ENET_RMON_R_MC_PKT(x).U)
5470 * Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
5474 * @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
5477 #define BP_ENET_RMON_R_MC_PKT_COUNT (0U) /*!< Bit position for ENET_RMON_R_MC_PKT_COUNT. */
5478 #define BM_ENET_RMON_R_MC_PKT_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_MC_PKT_COUNT. */
5479 #define BS_ENET_RMON_R_MC_PKT_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_MC_PKT_COUNT. */
5481 /*! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field. */
5482 #define BR_ENET_RMON_R_MC_PKT_COUNT(x) (HW_ENET_RMON_R_MC_PKT(x).B.COUNT)
5485 /*******************************************************************************
5486 * HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
5487 ******************************************************************************/
5490 * @brief HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
5492 * Reset value: 0x00000000U
5494 typedef union _hw_enet_rmon_r_crc_align
5497 struct _hw_enet_rmon_r_crc_align_bitfields
5499 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5500 uint32_t RESERVED0 : 16; /*!< [31:16] */
5502 } hw_enet_rmon_r_crc_align_t;
5505 * @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
5508 #define HW_ENET_RMON_R_CRC_ALIGN_ADDR(x) ((x) + 0x290U)
5510 #define HW_ENET_RMON_R_CRC_ALIGN(x) (*(__I hw_enet_rmon_r_crc_align_t *) HW_ENET_RMON_R_CRC_ALIGN_ADDR(x))
5511 #define HW_ENET_RMON_R_CRC_ALIGN_RD(x) (HW_ENET_RMON_R_CRC_ALIGN(x).U)
5515 * Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
5519 * @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
5522 #define BP_ENET_RMON_R_CRC_ALIGN_COUNT (0U) /*!< Bit position for ENET_RMON_R_CRC_ALIGN_COUNT. */
5523 #define BM_ENET_RMON_R_CRC_ALIGN_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_CRC_ALIGN_COUNT. */
5524 #define BS_ENET_RMON_R_CRC_ALIGN_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_CRC_ALIGN_COUNT. */
5526 /*! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field. */
5527 #define BR_ENET_RMON_R_CRC_ALIGN_COUNT(x) (HW_ENET_RMON_R_CRC_ALIGN(x).B.COUNT)
5530 /*******************************************************************************
5531 * HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
5532 ******************************************************************************/
5535 * @brief HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
5537 * Reset value: 0x00000000U
5539 typedef union _hw_enet_rmon_r_undersize
5542 struct _hw_enet_rmon_r_undersize_bitfields
5544 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5545 uint32_t RESERVED0 : 16; /*!< [31:16] */
5547 } hw_enet_rmon_r_undersize_t;
5550 * @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
5553 #define HW_ENET_RMON_R_UNDERSIZE_ADDR(x) ((x) + 0x294U)
5555 #define HW_ENET_RMON_R_UNDERSIZE(x) (*(__I hw_enet_rmon_r_undersize_t *) HW_ENET_RMON_R_UNDERSIZE_ADDR(x))
5556 #define HW_ENET_RMON_R_UNDERSIZE_RD(x) (HW_ENET_RMON_R_UNDERSIZE(x).U)
5560 * Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
5564 * @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
5567 #define BP_ENET_RMON_R_UNDERSIZE_COUNT (0U) /*!< Bit position for ENET_RMON_R_UNDERSIZE_COUNT. */
5568 #define BM_ENET_RMON_R_UNDERSIZE_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_UNDERSIZE_COUNT. */
5569 #define BS_ENET_RMON_R_UNDERSIZE_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_UNDERSIZE_COUNT. */
5571 /*! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field. */
5572 #define BR_ENET_RMON_R_UNDERSIZE_COUNT(x) (HW_ENET_RMON_R_UNDERSIZE(x).B.COUNT)
5575 /*******************************************************************************
5576 * HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
5577 ******************************************************************************/
5580 * @brief HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
5582 * Reset value: 0x00000000U
5584 typedef union _hw_enet_rmon_r_oversize
5587 struct _hw_enet_rmon_r_oversize_bitfields
5589 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5590 uint32_t RESERVED0 : 16; /*!< [31:16] */
5592 } hw_enet_rmon_r_oversize_t;
5595 * @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
5598 #define HW_ENET_RMON_R_OVERSIZE_ADDR(x) ((x) + 0x298U)
5600 #define HW_ENET_RMON_R_OVERSIZE(x) (*(__I hw_enet_rmon_r_oversize_t *) HW_ENET_RMON_R_OVERSIZE_ADDR(x))
5601 #define HW_ENET_RMON_R_OVERSIZE_RD(x) (HW_ENET_RMON_R_OVERSIZE(x).U)
5605 * Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
5609 * @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
5612 #define BP_ENET_RMON_R_OVERSIZE_COUNT (0U) /*!< Bit position for ENET_RMON_R_OVERSIZE_COUNT. */
5613 #define BM_ENET_RMON_R_OVERSIZE_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_OVERSIZE_COUNT. */
5614 #define BS_ENET_RMON_R_OVERSIZE_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_OVERSIZE_COUNT. */
5616 /*! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field. */
5617 #define BR_ENET_RMON_R_OVERSIZE_COUNT(x) (HW_ENET_RMON_R_OVERSIZE(x).B.COUNT)
5620 /*******************************************************************************
5621 * HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
5622 ******************************************************************************/
5625 * @brief HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
5627 * Reset value: 0x00000000U
5629 typedef union _hw_enet_rmon_r_frag
5632 struct _hw_enet_rmon_r_frag_bitfields
5634 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5635 uint32_t RESERVED0 : 16; /*!< [31:16] */
5637 } hw_enet_rmon_r_frag_t;
5640 * @name Constants and macros for entire ENET_RMON_R_FRAG register
5643 #define HW_ENET_RMON_R_FRAG_ADDR(x) ((x) + 0x29CU)
5645 #define HW_ENET_RMON_R_FRAG(x) (*(__I hw_enet_rmon_r_frag_t *) HW_ENET_RMON_R_FRAG_ADDR(x))
5646 #define HW_ENET_RMON_R_FRAG_RD(x) (HW_ENET_RMON_R_FRAG(x).U)
5650 * Constants & macros for individual ENET_RMON_R_FRAG bitfields
5654 * @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
5657 #define BP_ENET_RMON_R_FRAG_COUNT (0U) /*!< Bit position for ENET_RMON_R_FRAG_COUNT. */
5658 #define BM_ENET_RMON_R_FRAG_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_FRAG_COUNT. */
5659 #define BS_ENET_RMON_R_FRAG_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_FRAG_COUNT. */
5661 /*! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field. */
5662 #define BR_ENET_RMON_R_FRAG_COUNT(x) (HW_ENET_RMON_R_FRAG(x).B.COUNT)
5665 /*******************************************************************************
5666 * HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
5667 ******************************************************************************/
5670 * @brief HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
5672 * Reset value: 0x00000000U
5674 typedef union _hw_enet_rmon_r_jab
5677 struct _hw_enet_rmon_r_jab_bitfields
5679 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5680 uint32_t RESERVED0 : 16; /*!< [31:16] */
5682 } hw_enet_rmon_r_jab_t;
5685 * @name Constants and macros for entire ENET_RMON_R_JAB register
5688 #define HW_ENET_RMON_R_JAB_ADDR(x) ((x) + 0x2A0U)
5690 #define HW_ENET_RMON_R_JAB(x) (*(__I hw_enet_rmon_r_jab_t *) HW_ENET_RMON_R_JAB_ADDR(x))
5691 #define HW_ENET_RMON_R_JAB_RD(x) (HW_ENET_RMON_R_JAB(x).U)
5695 * Constants & macros for individual ENET_RMON_R_JAB bitfields
5699 * @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
5702 #define BP_ENET_RMON_R_JAB_COUNT (0U) /*!< Bit position for ENET_RMON_R_JAB_COUNT. */
5703 #define BM_ENET_RMON_R_JAB_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_JAB_COUNT. */
5704 #define BS_ENET_RMON_R_JAB_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_JAB_COUNT. */
5706 /*! @brief Read current value of the ENET_RMON_R_JAB_COUNT field. */
5707 #define BR_ENET_RMON_R_JAB_COUNT(x) (HW_ENET_RMON_R_JAB(x).B.COUNT)
5710 /*******************************************************************************
5711 * HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
5712 ******************************************************************************/
5715 * @brief HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
5717 * Reset value: 0x00000000U
5719 typedef union _hw_enet_rmon_r_p64
5722 struct _hw_enet_rmon_r_p64_bitfields
5724 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5725 uint32_t RESERVED0 : 16; /*!< [31:16] */
5727 } hw_enet_rmon_r_p64_t;
5730 * @name Constants and macros for entire ENET_RMON_R_P64 register
5733 #define HW_ENET_RMON_R_P64_ADDR(x) ((x) + 0x2A8U)
5735 #define HW_ENET_RMON_R_P64(x) (*(__I hw_enet_rmon_r_p64_t *) HW_ENET_RMON_R_P64_ADDR(x))
5736 #define HW_ENET_RMON_R_P64_RD(x) (HW_ENET_RMON_R_P64(x).U)
5740 * Constants & macros for individual ENET_RMON_R_P64 bitfields
5744 * @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
5747 #define BP_ENET_RMON_R_P64_COUNT (0U) /*!< Bit position for ENET_RMON_R_P64_COUNT. */
5748 #define BM_ENET_RMON_R_P64_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P64_COUNT. */
5749 #define BS_ENET_RMON_R_P64_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P64_COUNT. */
5751 /*! @brief Read current value of the ENET_RMON_R_P64_COUNT field. */
5752 #define BR_ENET_RMON_R_P64_COUNT(x) (HW_ENET_RMON_R_P64(x).B.COUNT)
5755 /*******************************************************************************
5756 * HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
5757 ******************************************************************************/
5760 * @brief HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
5762 * Reset value: 0x00000000U
5764 typedef union _hw_enet_rmon_r_p65to127
5767 struct _hw_enet_rmon_r_p65to127_bitfields
5769 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5770 uint32_t RESERVED0 : 16; /*!< [31:16] */
5772 } hw_enet_rmon_r_p65to127_t;
5775 * @name Constants and macros for entire ENET_RMON_R_P65TO127 register
5778 #define HW_ENET_RMON_R_P65TO127_ADDR(x) ((x) + 0x2ACU)
5780 #define HW_ENET_RMON_R_P65TO127(x) (*(__I hw_enet_rmon_r_p65to127_t *) HW_ENET_RMON_R_P65TO127_ADDR(x))
5781 #define HW_ENET_RMON_R_P65TO127_RD(x) (HW_ENET_RMON_R_P65TO127(x).U)
5785 * Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
5789 * @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
5792 #define BP_ENET_RMON_R_P65TO127_COUNT (0U) /*!< Bit position for ENET_RMON_R_P65TO127_COUNT. */
5793 #define BM_ENET_RMON_R_P65TO127_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P65TO127_COUNT. */
5794 #define BS_ENET_RMON_R_P65TO127_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P65TO127_COUNT. */
5796 /*! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field. */
5797 #define BR_ENET_RMON_R_P65TO127_COUNT(x) (HW_ENET_RMON_R_P65TO127(x).B.COUNT)
5800 /*******************************************************************************
5801 * HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
5802 ******************************************************************************/
5805 * @brief HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
5807 * Reset value: 0x00000000U
5809 typedef union _hw_enet_rmon_r_p128to255
5812 struct _hw_enet_rmon_r_p128to255_bitfields
5814 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5815 uint32_t RESERVED0 : 16; /*!< [31:16] */
5817 } hw_enet_rmon_r_p128to255_t;
5820 * @name Constants and macros for entire ENET_RMON_R_P128TO255 register
5823 #define HW_ENET_RMON_R_P128TO255_ADDR(x) ((x) + 0x2B0U)
5825 #define HW_ENET_RMON_R_P128TO255(x) (*(__I hw_enet_rmon_r_p128to255_t *) HW_ENET_RMON_R_P128TO255_ADDR(x))
5826 #define HW_ENET_RMON_R_P128TO255_RD(x) (HW_ENET_RMON_R_P128TO255(x).U)
5830 * Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
5834 * @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
5837 #define BP_ENET_RMON_R_P128TO255_COUNT (0U) /*!< Bit position for ENET_RMON_R_P128TO255_COUNT. */
5838 #define BM_ENET_RMON_R_P128TO255_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P128TO255_COUNT. */
5839 #define BS_ENET_RMON_R_P128TO255_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P128TO255_COUNT. */
5841 /*! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field. */
5842 #define BR_ENET_RMON_R_P128TO255_COUNT(x) (HW_ENET_RMON_R_P128TO255(x).B.COUNT)
5845 /*******************************************************************************
5846 * HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
5847 ******************************************************************************/
5850 * @brief HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
5852 * Reset value: 0x00000000U
5854 typedef union _hw_enet_rmon_r_p256to511
5857 struct _hw_enet_rmon_r_p256to511_bitfields
5859 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5860 uint32_t RESERVED0 : 16; /*!< [31:16] */
5862 } hw_enet_rmon_r_p256to511_t;
5865 * @name Constants and macros for entire ENET_RMON_R_P256TO511 register
5868 #define HW_ENET_RMON_R_P256TO511_ADDR(x) ((x) + 0x2B4U)
5870 #define HW_ENET_RMON_R_P256TO511(x) (*(__I hw_enet_rmon_r_p256to511_t *) HW_ENET_RMON_R_P256TO511_ADDR(x))
5871 #define HW_ENET_RMON_R_P256TO511_RD(x) (HW_ENET_RMON_R_P256TO511(x).U)
5875 * Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
5879 * @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
5882 #define BP_ENET_RMON_R_P256TO511_COUNT (0U) /*!< Bit position for ENET_RMON_R_P256TO511_COUNT. */
5883 #define BM_ENET_RMON_R_P256TO511_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P256TO511_COUNT. */
5884 #define BS_ENET_RMON_R_P256TO511_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P256TO511_COUNT. */
5886 /*! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field. */
5887 #define BR_ENET_RMON_R_P256TO511_COUNT(x) (HW_ENET_RMON_R_P256TO511(x).B.COUNT)
5890 /*******************************************************************************
5891 * HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
5892 ******************************************************************************/
5895 * @brief HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
5897 * Reset value: 0x00000000U
5899 typedef union _hw_enet_rmon_r_p512to1023
5902 struct _hw_enet_rmon_r_p512to1023_bitfields
5904 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5905 uint32_t RESERVED0 : 16; /*!< [31:16] */
5907 } hw_enet_rmon_r_p512to1023_t;
5910 * @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
5913 #define HW_ENET_RMON_R_P512TO1023_ADDR(x) ((x) + 0x2B8U)
5915 #define HW_ENET_RMON_R_P512TO1023(x) (*(__I hw_enet_rmon_r_p512to1023_t *) HW_ENET_RMON_R_P512TO1023_ADDR(x))
5916 #define HW_ENET_RMON_R_P512TO1023_RD(x) (HW_ENET_RMON_R_P512TO1023(x).U)
5920 * Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
5924 * @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
5927 #define BP_ENET_RMON_R_P512TO1023_COUNT (0U) /*!< Bit position for ENET_RMON_R_P512TO1023_COUNT. */
5928 #define BM_ENET_RMON_R_P512TO1023_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P512TO1023_COUNT. */
5929 #define BS_ENET_RMON_R_P512TO1023_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P512TO1023_COUNT. */
5931 /*! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field. */
5932 #define BR_ENET_RMON_R_P512TO1023_COUNT(x) (HW_ENET_RMON_R_P512TO1023(x).B.COUNT)
5935 /*******************************************************************************
5936 * HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
5937 ******************************************************************************/
5940 * @brief HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
5942 * Reset value: 0x00000000U
5944 typedef union _hw_enet_rmon_r_p1024to2047
5947 struct _hw_enet_rmon_r_p1024to2047_bitfields
5949 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5950 uint32_t RESERVED0 : 16; /*!< [31:16] */
5952 } hw_enet_rmon_r_p1024to2047_t;
5955 * @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
5958 #define HW_ENET_RMON_R_P1024TO2047_ADDR(x) ((x) + 0x2BCU)
5960 #define HW_ENET_RMON_R_P1024TO2047(x) (*(__I hw_enet_rmon_r_p1024to2047_t *) HW_ENET_RMON_R_P1024TO2047_ADDR(x))
5961 #define HW_ENET_RMON_R_P1024TO2047_RD(x) (HW_ENET_RMON_R_P1024TO2047(x).U)
5965 * Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
5969 * @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
5972 #define BP_ENET_RMON_R_P1024TO2047_COUNT (0U) /*!< Bit position for ENET_RMON_R_P1024TO2047_COUNT. */
5973 #define BM_ENET_RMON_R_P1024TO2047_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P1024TO2047_COUNT. */
5974 #define BS_ENET_RMON_R_P1024TO2047_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P1024TO2047_COUNT. */
5976 /*! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field. */
5977 #define BR_ENET_RMON_R_P1024TO2047_COUNT(x) (HW_ENET_RMON_R_P1024TO2047(x).B.COUNT)
5980 /*******************************************************************************
5981 * HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
5982 ******************************************************************************/
5985 * @brief HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
5987 * Reset value: 0x00000000U
5989 typedef union _hw_enet_rmon_r_p_gte2048
5992 struct _hw_enet_rmon_r_p_gte2048_bitfields
5994 uint32_t COUNT : 16; /*!< [15:0] Packet count */
5995 uint32_t RESERVED0 : 16; /*!< [31:16] */
5997 } hw_enet_rmon_r_p_gte2048_t;
6000 * @name Constants and macros for entire ENET_RMON_R_P_GTE2048 register
6003 #define HW_ENET_RMON_R_P_GTE2048_ADDR(x) ((x) + 0x2C0U)
6005 #define HW_ENET_RMON_R_P_GTE2048(x) (*(__I hw_enet_rmon_r_p_gte2048_t *) HW_ENET_RMON_R_P_GTE2048_ADDR(x))
6006 #define HW_ENET_RMON_R_P_GTE2048_RD(x) (HW_ENET_RMON_R_P_GTE2048(x).U)
6010 * Constants & macros for individual ENET_RMON_R_P_GTE2048 bitfields
6014 * @name Register ENET_RMON_R_P_GTE2048, field COUNT[15:0] (RO)
6017 #define BP_ENET_RMON_R_P_GTE2048_COUNT (0U) /*!< Bit position for ENET_RMON_R_P_GTE2048_COUNT. */
6018 #define BM_ENET_RMON_R_P_GTE2048_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P_GTE2048_COUNT. */
6019 #define BS_ENET_RMON_R_P_GTE2048_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P_GTE2048_COUNT. */
6021 /*! @brief Read current value of the ENET_RMON_R_P_GTE2048_COUNT field. */
6022 #define BR_ENET_RMON_R_P_GTE2048_COUNT(x) (HW_ENET_RMON_R_P_GTE2048(x).B.COUNT)
6025 /*******************************************************************************
6026 * HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
6027 ******************************************************************************/
6030 * @brief HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
6032 * Reset value: 0x00000000U
6034 typedef union _hw_enet_rmon_r_octets
6037 struct _hw_enet_rmon_r_octets_bitfields
6039 uint32_t COUNT : 32; /*!< [31:0] Octet count */
6041 } hw_enet_rmon_r_octets_t;
6044 * @name Constants and macros for entire ENET_RMON_R_OCTETS register
6047 #define HW_ENET_RMON_R_OCTETS_ADDR(x) ((x) + 0x2C4U)
6049 #define HW_ENET_RMON_R_OCTETS(x) (*(__I hw_enet_rmon_r_octets_t *) HW_ENET_RMON_R_OCTETS_ADDR(x))
6050 #define HW_ENET_RMON_R_OCTETS_RD(x) (HW_ENET_RMON_R_OCTETS(x).U)
6054 * Constants & macros for individual ENET_RMON_R_OCTETS bitfields
6058 * @name Register ENET_RMON_R_OCTETS, field COUNT[31:0] (RO)
6061 #define BP_ENET_RMON_R_OCTETS_COUNT (0U) /*!< Bit position for ENET_RMON_R_OCTETS_COUNT. */
6062 #define BM_ENET_RMON_R_OCTETS_COUNT (0xFFFFFFFFU) /*!< Bit mask for ENET_RMON_R_OCTETS_COUNT. */
6063 #define BS_ENET_RMON_R_OCTETS_COUNT (32U) /*!< Bit field size in bits for ENET_RMON_R_OCTETS_COUNT. */
6065 /*! @brief Read current value of the ENET_RMON_R_OCTETS_COUNT field. */
6066 #define BR_ENET_RMON_R_OCTETS_COUNT(x) (HW_ENET_RMON_R_OCTETS(x).U)
6069 /*******************************************************************************
6070 * HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
6071 ******************************************************************************/
6074 * @brief HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
6076 * Reset value: 0x00000000U
6078 * Counter increments if a frame with invalid or missing SFD character is
6079 * detected and has been dropped. None of the other counters increments if this counter
6082 typedef union _hw_enet_ieee_r_drop
6085 struct _hw_enet_ieee_r_drop_bitfields
6087 uint32_t COUNT : 16; /*!< [15:0] Frame count */
6088 uint32_t RESERVED0 : 16; /*!< [31:16] */
6090 } hw_enet_ieee_r_drop_t;
6093 * @name Constants and macros for entire ENET_IEEE_R_DROP register
6096 #define HW_ENET_IEEE_R_DROP_ADDR(x) ((x) + 0x2C8U)
6098 #define HW_ENET_IEEE_R_DROP(x) (*(__I hw_enet_ieee_r_drop_t *) HW_ENET_IEEE_R_DROP_ADDR(x))
6099 #define HW_ENET_IEEE_R_DROP_RD(x) (HW_ENET_IEEE_R_DROP(x).U)
6103 * Constants & macros for individual ENET_IEEE_R_DROP bitfields
6107 * @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
6110 #define BP_ENET_IEEE_R_DROP_COUNT (0U) /*!< Bit position for ENET_IEEE_R_DROP_COUNT. */
6111 #define BM_ENET_IEEE_R_DROP_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_DROP_COUNT. */
6112 #define BS_ENET_IEEE_R_DROP_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_R_DROP_COUNT. */
6114 /*! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field. */
6115 #define BR_ENET_IEEE_R_DROP_COUNT(x) (HW_ENET_IEEE_R_DROP(x).B.COUNT)
6118 /*******************************************************************************
6119 * HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
6120 ******************************************************************************/
6123 * @brief HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
6125 * Reset value: 0x00000000U
6127 typedef union _hw_enet_ieee_r_frame_ok
6130 struct _hw_enet_ieee_r_frame_ok_bitfields
6132 uint32_t COUNT : 16; /*!< [15:0] Frame count */
6133 uint32_t RESERVED0 : 16; /*!< [31:16] */
6135 } hw_enet_ieee_r_frame_ok_t;
6138 * @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
6141 #define HW_ENET_IEEE_R_FRAME_OK_ADDR(x) ((x) + 0x2CCU)
6143 #define HW_ENET_IEEE_R_FRAME_OK(x) (*(__I hw_enet_ieee_r_frame_ok_t *) HW_ENET_IEEE_R_FRAME_OK_ADDR(x))
6144 #define HW_ENET_IEEE_R_FRAME_OK_RD(x) (HW_ENET_IEEE_R_FRAME_OK(x).U)
6148 * Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
6152 * @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
6155 #define BP_ENET_IEEE_R_FRAME_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_R_FRAME_OK_COUNT. */
6156 #define BM_ENET_IEEE_R_FRAME_OK_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_FRAME_OK_COUNT. */
6157 #define BS_ENET_IEEE_R_FRAME_OK_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_R_FRAME_OK_COUNT. */
6159 /*! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field. */
6160 #define BR_ENET_IEEE_R_FRAME_OK_COUNT(x) (HW_ENET_IEEE_R_FRAME_OK(x).B.COUNT)
6163 /*******************************************************************************
6164 * HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
6165 ******************************************************************************/
6168 * @brief HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
6170 * Reset value: 0x00000000U
6172 typedef union _hw_enet_ieee_r_crc
6175 struct _hw_enet_ieee_r_crc_bitfields
6177 uint32_t COUNT : 16; /*!< [15:0] Frame count */
6178 uint32_t RESERVED0 : 16; /*!< [31:16] */
6180 } hw_enet_ieee_r_crc_t;
6183 * @name Constants and macros for entire ENET_IEEE_R_CRC register
6186 #define HW_ENET_IEEE_R_CRC_ADDR(x) ((x) + 0x2D0U)
6188 #define HW_ENET_IEEE_R_CRC(x) (*(__I hw_enet_ieee_r_crc_t *) HW_ENET_IEEE_R_CRC_ADDR(x))
6189 #define HW_ENET_IEEE_R_CRC_RD(x) (HW_ENET_IEEE_R_CRC(x).U)
6193 * Constants & macros for individual ENET_IEEE_R_CRC bitfields
6197 * @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
6200 #define BP_ENET_IEEE_R_CRC_COUNT (0U) /*!< Bit position for ENET_IEEE_R_CRC_COUNT. */
6201 #define BM_ENET_IEEE_R_CRC_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_CRC_COUNT. */
6202 #define BS_ENET_IEEE_R_CRC_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_R_CRC_COUNT. */
6204 /*! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field. */
6205 #define BR_ENET_IEEE_R_CRC_COUNT(x) (HW_ENET_IEEE_R_CRC(x).B.COUNT)
6208 /*******************************************************************************
6209 * HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
6210 ******************************************************************************/
6213 * @brief HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
6215 * Reset value: 0x00000000U
6217 typedef union _hw_enet_ieee_r_align
6220 struct _hw_enet_ieee_r_align_bitfields
6222 uint32_t COUNT : 16; /*!< [15:0] Frame count */
6223 uint32_t RESERVED0 : 16; /*!< [31:16] */
6225 } hw_enet_ieee_r_align_t;
6228 * @name Constants and macros for entire ENET_IEEE_R_ALIGN register
6231 #define HW_ENET_IEEE_R_ALIGN_ADDR(x) ((x) + 0x2D4U)
6233 #define HW_ENET_IEEE_R_ALIGN(x) (*(__I hw_enet_ieee_r_align_t *) HW_ENET_IEEE_R_ALIGN_ADDR(x))
6234 #define HW_ENET_IEEE_R_ALIGN_RD(x) (HW_ENET_IEEE_R_ALIGN(x).U)
6238 * Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
6242 * @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
6245 #define BP_ENET_IEEE_R_ALIGN_COUNT (0U) /*!< Bit position for ENET_IEEE_R_ALIGN_COUNT. */
6246 #define BM_ENET_IEEE_R_ALIGN_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_ALIGN_COUNT. */
6247 #define BS_ENET_IEEE_R_ALIGN_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_R_ALIGN_COUNT. */
6249 /*! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field. */
6250 #define BR_ENET_IEEE_R_ALIGN_COUNT(x) (HW_ENET_IEEE_R_ALIGN(x).B.COUNT)
6253 /*******************************************************************************
6254 * HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
6255 ******************************************************************************/
6258 * @brief HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
6260 * Reset value: 0x00000000U
6262 typedef union _hw_enet_ieee_r_macerr
6265 struct _hw_enet_ieee_r_macerr_bitfields
6267 uint32_t COUNT : 16; /*!< [15:0] Count */
6268 uint32_t RESERVED0 : 16; /*!< [31:16] */
6270 } hw_enet_ieee_r_macerr_t;
6273 * @name Constants and macros for entire ENET_IEEE_R_MACERR register
6276 #define HW_ENET_IEEE_R_MACERR_ADDR(x) ((x) + 0x2D8U)
6278 #define HW_ENET_IEEE_R_MACERR(x) (*(__I hw_enet_ieee_r_macerr_t *) HW_ENET_IEEE_R_MACERR_ADDR(x))
6279 #define HW_ENET_IEEE_R_MACERR_RD(x) (HW_ENET_IEEE_R_MACERR(x).U)
6283 * Constants & macros for individual ENET_IEEE_R_MACERR bitfields
6287 * @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
6290 #define BP_ENET_IEEE_R_MACERR_COUNT (0U) /*!< Bit position for ENET_IEEE_R_MACERR_COUNT. */
6291 #define BM_ENET_IEEE_R_MACERR_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_MACERR_COUNT. */
6292 #define BS_ENET_IEEE_R_MACERR_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_R_MACERR_COUNT. */
6294 /*! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field. */
6295 #define BR_ENET_IEEE_R_MACERR_COUNT(x) (HW_ENET_IEEE_R_MACERR(x).B.COUNT)
6298 /*******************************************************************************
6299 * HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
6300 ******************************************************************************/
6303 * @brief HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
6305 * Reset value: 0x00000000U
6307 typedef union _hw_enet_ieee_r_fdxfc
6310 struct _hw_enet_ieee_r_fdxfc_bitfields
6312 uint32_t COUNT : 16; /*!< [15:0] Pause frame count */
6313 uint32_t RESERVED0 : 16; /*!< [31:16] */
6315 } hw_enet_ieee_r_fdxfc_t;
6318 * @name Constants and macros for entire ENET_IEEE_R_FDXFC register
6321 #define HW_ENET_IEEE_R_FDXFC_ADDR(x) ((x) + 0x2DCU)
6323 #define HW_ENET_IEEE_R_FDXFC(x) (*(__I hw_enet_ieee_r_fdxfc_t *) HW_ENET_IEEE_R_FDXFC_ADDR(x))
6324 #define HW_ENET_IEEE_R_FDXFC_RD(x) (HW_ENET_IEEE_R_FDXFC(x).U)
6328 * Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
6332 * @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
6335 #define BP_ENET_IEEE_R_FDXFC_COUNT (0U) /*!< Bit position for ENET_IEEE_R_FDXFC_COUNT. */
6336 #define BM_ENET_IEEE_R_FDXFC_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_FDXFC_COUNT. */
6337 #define BS_ENET_IEEE_R_FDXFC_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_R_FDXFC_COUNT. */
6339 /*! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field. */
6340 #define BR_ENET_IEEE_R_FDXFC_COUNT(x) (HW_ENET_IEEE_R_FDXFC(x).B.COUNT)
6343 /*******************************************************************************
6344 * HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
6345 ******************************************************************************/
6348 * @brief HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
6350 * Reset value: 0x00000000U
6352 typedef union _hw_enet_ieee_r_octets_ok
6355 struct _hw_enet_ieee_r_octets_ok_bitfields
6357 uint32_t COUNT : 32; /*!< [31:0] Octet count */
6359 } hw_enet_ieee_r_octets_ok_t;
6362 * @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
6365 #define HW_ENET_IEEE_R_OCTETS_OK_ADDR(x) ((x) + 0x2E0U)
6367 #define HW_ENET_IEEE_R_OCTETS_OK(x) (*(__I hw_enet_ieee_r_octets_ok_t *) HW_ENET_IEEE_R_OCTETS_OK_ADDR(x))
6368 #define HW_ENET_IEEE_R_OCTETS_OK_RD(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
6372 * Constants & macros for individual ENET_IEEE_R_OCTETS_OK bitfields
6376 * @name Register ENET_IEEE_R_OCTETS_OK, field COUNT[31:0] (RO)
6379 #define BP_ENET_IEEE_R_OCTETS_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_R_OCTETS_OK_COUNT. */
6380 #define BM_ENET_IEEE_R_OCTETS_OK_COUNT (0xFFFFFFFFU) /*!< Bit mask for ENET_IEEE_R_OCTETS_OK_COUNT. */
6381 #define BS_ENET_IEEE_R_OCTETS_OK_COUNT (32U) /*!< Bit field size in bits for ENET_IEEE_R_OCTETS_OK_COUNT. */
6383 /*! @brief Read current value of the ENET_IEEE_R_OCTETS_OK_COUNT field. */
6384 #define BR_ENET_IEEE_R_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
6387 /*******************************************************************************
6388 * HW_ENET_ATCR - Adjustable Timer Control Register
6389 ******************************************************************************/
6392 * @brief HW_ENET_ATCR - Adjustable Timer Control Register (RW)
6394 * Reset value: 0x00000000U
6396 * ATCR command fields can trigger the corresponding events directly. It is not
6397 * necessary to preserve any of the configuration fields when a command field is
6398 * set in the register, that is, no read-modify-write is required. The fields are
6399 * automatically cleared after the command completes.
6401 typedef union _hw_enet_atcr
6404 struct _hw_enet_atcr_bitfields
6406 uint32_t EN : 1; /*!< [0] Enable Timer */
6407 uint32_t RESERVED0 : 1; /*!< [1] */
6408 uint32_t OFFEN : 1; /*!< [2] Enable One-Shot Offset Event */
6409 uint32_t OFFRST : 1; /*!< [3] Reset Timer On Offset Event */
6410 uint32_t PEREN : 1; /*!< [4] Enable Periodical Event */
6411 uint32_t RESERVED1 : 2; /*!< [6:5] */
6412 uint32_t PINPER : 1; /*!< [7] */
6413 uint32_t RESERVED2 : 1; /*!< [8] */
6414 uint32_t RESTART : 1; /*!< [9] Reset Timer */
6415 uint32_t RESERVED3 : 1; /*!< [10] */
6416 uint32_t CAPTURE : 1; /*!< [11] Capture Timer Value */
6417 uint32_t RESERVED4 : 1; /*!< [12] */
6418 uint32_t SLAVE : 1; /*!< [13] Enable Timer Slave Mode */
6419 uint32_t RESERVED5 : 18; /*!< [31:14] */
6424 * @name Constants and macros for entire ENET_ATCR register
6427 #define HW_ENET_ATCR_ADDR(x) ((x) + 0x400U)
6429 #define HW_ENET_ATCR(x) (*(__IO hw_enet_atcr_t *) HW_ENET_ATCR_ADDR(x))
6430 #define HW_ENET_ATCR_RD(x) (HW_ENET_ATCR(x).U)
6431 #define HW_ENET_ATCR_WR(x, v) (HW_ENET_ATCR(x).U = (v))
6432 #define HW_ENET_ATCR_SET(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) | (v)))
6433 #define HW_ENET_ATCR_CLR(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) & ~(v)))
6434 #define HW_ENET_ATCR_TOG(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) ^ (v)))
6438 * Constants & macros for individual ENET_ATCR bitfields
6442 * @name Register ENET_ATCR, field EN[0] (RW)
6445 * - 0 - The timer stops at the current value.
6446 * - 1 - The timer starts incrementing.
6449 #define BP_ENET_ATCR_EN (0U) /*!< Bit position for ENET_ATCR_EN. */
6450 #define BM_ENET_ATCR_EN (0x00000001U) /*!< Bit mask for ENET_ATCR_EN. */
6451 #define BS_ENET_ATCR_EN (1U) /*!< Bit field size in bits for ENET_ATCR_EN. */
6453 /*! @brief Read current value of the ENET_ATCR_EN field. */
6454 #define BR_ENET_ATCR_EN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN))
6456 /*! @brief Format value for bitfield ENET_ATCR_EN. */
6457 #define BF_ENET_ATCR_EN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_EN) & BM_ENET_ATCR_EN)
6459 /*! @brief Set the EN field to a new value. */
6460 #define BW_ENET_ATCR_EN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN) = (v))
6464 * @name Register ENET_ATCR, field OFFEN[2] (RW)
6468 * - 1 - The timer can be reset to zero when the given offset time is reached
6469 * (offset event). The field is cleared when the offset event is reached, so no
6470 * further event occurs until the field is set again. The timer offset value
6471 * must be set before setting this field.
6474 #define BP_ENET_ATCR_OFFEN (2U) /*!< Bit position for ENET_ATCR_OFFEN. */
6475 #define BM_ENET_ATCR_OFFEN (0x00000004U) /*!< Bit mask for ENET_ATCR_OFFEN. */
6476 #define BS_ENET_ATCR_OFFEN (1U) /*!< Bit field size in bits for ENET_ATCR_OFFEN. */
6478 /*! @brief Read current value of the ENET_ATCR_OFFEN field. */
6479 #define BR_ENET_ATCR_OFFEN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN))
6481 /*! @brief Format value for bitfield ENET_ATCR_OFFEN. */
6482 #define BF_ENET_ATCR_OFFEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_OFFEN) & BM_ENET_ATCR_OFFEN)
6484 /*! @brief Set the OFFEN field to a new value. */
6485 #define BW_ENET_ATCR_OFFEN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN) = (v))
6489 * @name Register ENET_ATCR, field OFFRST[3] (RW)
6492 * - 0 - The timer is not affected and no action occurs, besides clearing OFFEN,
6493 * when the offset is reached.
6494 * - 1 - If OFFEN is set, the timer resets to zero when the offset setting is
6495 * reached. The offset event does not cause a timer interrupt.
6498 #define BP_ENET_ATCR_OFFRST (3U) /*!< Bit position for ENET_ATCR_OFFRST. */
6499 #define BM_ENET_ATCR_OFFRST (0x00000008U) /*!< Bit mask for ENET_ATCR_OFFRST. */
6500 #define BS_ENET_ATCR_OFFRST (1U) /*!< Bit field size in bits for ENET_ATCR_OFFRST. */
6502 /*! @brief Read current value of the ENET_ATCR_OFFRST field. */
6503 #define BR_ENET_ATCR_OFFRST(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST))
6505 /*! @brief Format value for bitfield ENET_ATCR_OFFRST. */
6506 #define BF_ENET_ATCR_OFFRST(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_OFFRST) & BM_ENET_ATCR_OFFRST)
6508 /*! @brief Set the OFFRST field to a new value. */
6509 #define BW_ENET_ATCR_OFFRST(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST) = (v))
6513 * @name Register ENET_ATCR, field PEREN[4] (RW)
6517 * - 1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the event
6518 * signal output is asserted when the timer wraps around according to the
6519 * periodic setting ATPER. The timer period value must be set before setting
6520 * this bit. Not all devices contain the event signal output. See the chip
6521 * configuration details.
6524 #define BP_ENET_ATCR_PEREN (4U) /*!< Bit position for ENET_ATCR_PEREN. */
6525 #define BM_ENET_ATCR_PEREN (0x00000010U) /*!< Bit mask for ENET_ATCR_PEREN. */
6526 #define BS_ENET_ATCR_PEREN (1U) /*!< Bit field size in bits for ENET_ATCR_PEREN. */
6528 /*! @brief Read current value of the ENET_ATCR_PEREN field. */
6529 #define BR_ENET_ATCR_PEREN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN))
6531 /*! @brief Format value for bitfield ENET_ATCR_PEREN. */
6532 #define BF_ENET_ATCR_PEREN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_PEREN) & BM_ENET_ATCR_PEREN)
6534 /*! @brief Set the PEREN field to a new value. */
6535 #define BW_ENET_ATCR_PEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN) = (v))
6539 * @name Register ENET_ATCR, field PINPER[7] (RW)
6541 * Enables event signal output assertion on period event. Not all devices
6542 * contain the event signal output. See the chip configuration details.
6549 #define BP_ENET_ATCR_PINPER (7U) /*!< Bit position for ENET_ATCR_PINPER. */
6550 #define BM_ENET_ATCR_PINPER (0x00000080U) /*!< Bit mask for ENET_ATCR_PINPER. */
6551 #define BS_ENET_ATCR_PINPER (1U) /*!< Bit field size in bits for ENET_ATCR_PINPER. */
6553 /*! @brief Read current value of the ENET_ATCR_PINPER field. */
6554 #define BR_ENET_ATCR_PINPER(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER))
6556 /*! @brief Format value for bitfield ENET_ATCR_PINPER. */
6557 #define BF_ENET_ATCR_PINPER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_PINPER) & BM_ENET_ATCR_PINPER)
6559 /*! @brief Set the PINPER field to a new value. */
6560 #define BW_ENET_ATCR_PINPER(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER) = (v))
6564 * @name Register ENET_ATCR, field RESTART[9] (RW)
6566 * Resets the timer to zero. This has no effect on the counter enable. If the
6567 * counter is enabled when this field is set, the timer is reset to zero and starts
6568 * counting from there. When set, all other fields are ignored during a write.
6571 #define BP_ENET_ATCR_RESTART (9U) /*!< Bit position for ENET_ATCR_RESTART. */
6572 #define BM_ENET_ATCR_RESTART (0x00000200U) /*!< Bit mask for ENET_ATCR_RESTART. */
6573 #define BS_ENET_ATCR_RESTART (1U) /*!< Bit field size in bits for ENET_ATCR_RESTART. */
6575 /*! @brief Read current value of the ENET_ATCR_RESTART field. */
6576 #define BR_ENET_ATCR_RESTART(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART))
6578 /*! @brief Format value for bitfield ENET_ATCR_RESTART. */
6579 #define BF_ENET_ATCR_RESTART(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_RESTART) & BM_ENET_ATCR_RESTART)
6581 /*! @brief Set the RESTART field to a new value. */
6582 #define BW_ENET_ATCR_RESTART(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART) = (v))
6586 * @name Register ENET_ATCR, field CAPTURE[11] (RW)
6590 * - 1 - The current time is captured and can be read from the ATVR register.
6593 #define BP_ENET_ATCR_CAPTURE (11U) /*!< Bit position for ENET_ATCR_CAPTURE. */
6594 #define BM_ENET_ATCR_CAPTURE (0x00000800U) /*!< Bit mask for ENET_ATCR_CAPTURE. */
6595 #define BS_ENET_ATCR_CAPTURE (1U) /*!< Bit field size in bits for ENET_ATCR_CAPTURE. */
6597 /*! @brief Read current value of the ENET_ATCR_CAPTURE field. */
6598 #define BR_ENET_ATCR_CAPTURE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE))
6600 /*! @brief Format value for bitfield ENET_ATCR_CAPTURE. */
6601 #define BF_ENET_ATCR_CAPTURE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_CAPTURE) & BM_ENET_ATCR_CAPTURE)
6603 /*! @brief Set the CAPTURE field to a new value. */
6604 #define BW_ENET_ATCR_CAPTURE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE) = (v))
6608 * @name Register ENET_ATCR, field SLAVE[13] (RW)
6611 * - 0 - The timer is active and all configuration fields in this register are
6613 * - 1 - The internal timer is disabled and the externally provided timer value
6614 * is used. All other fields, except CAPTURE, in this register have no
6615 * effect. CAPTURE can still be used to capture the current timer value.
6618 #define BP_ENET_ATCR_SLAVE (13U) /*!< Bit position for ENET_ATCR_SLAVE. */
6619 #define BM_ENET_ATCR_SLAVE (0x00002000U) /*!< Bit mask for ENET_ATCR_SLAVE. */
6620 #define BS_ENET_ATCR_SLAVE (1U) /*!< Bit field size in bits for ENET_ATCR_SLAVE. */
6622 /*! @brief Read current value of the ENET_ATCR_SLAVE field. */
6623 #define BR_ENET_ATCR_SLAVE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE))
6625 /*! @brief Format value for bitfield ENET_ATCR_SLAVE. */
6626 #define BF_ENET_ATCR_SLAVE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_SLAVE) & BM_ENET_ATCR_SLAVE)
6628 /*! @brief Set the SLAVE field to a new value. */
6629 #define BW_ENET_ATCR_SLAVE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE) = (v))
6632 /*******************************************************************************
6633 * HW_ENET_ATVR - Timer Value Register
6634 ******************************************************************************/
6637 * @brief HW_ENET_ATVR - Timer Value Register (RW)
6639 * Reset value: 0x00000000U
6641 typedef union _hw_enet_atvr
6644 struct _hw_enet_atvr_bitfields
6646 uint32_t ATIME : 32; /*!< [31:0] */
6651 * @name Constants and macros for entire ENET_ATVR register
6654 #define HW_ENET_ATVR_ADDR(x) ((x) + 0x404U)
6656 #define HW_ENET_ATVR(x) (*(__IO hw_enet_atvr_t *) HW_ENET_ATVR_ADDR(x))
6657 #define HW_ENET_ATVR_RD(x) (HW_ENET_ATVR(x).U)
6658 #define HW_ENET_ATVR_WR(x, v) (HW_ENET_ATVR(x).U = (v))
6659 #define HW_ENET_ATVR_SET(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) | (v)))
6660 #define HW_ENET_ATVR_CLR(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) & ~(v)))
6661 #define HW_ENET_ATVR_TOG(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) ^ (v)))
6665 * Constants & macros for individual ENET_ATVR bitfields
6669 * @name Register ENET_ATVR, field ATIME[31:0] (RW)
6671 * A write sets the timer. A read returns the last captured value. To read the
6672 * current value, issue a capture command (set ATCR[CAPTURE]) prior to reading
6676 #define BP_ENET_ATVR_ATIME (0U) /*!< Bit position for ENET_ATVR_ATIME. */
6677 #define BM_ENET_ATVR_ATIME (0xFFFFFFFFU) /*!< Bit mask for ENET_ATVR_ATIME. */
6678 #define BS_ENET_ATVR_ATIME (32U) /*!< Bit field size in bits for ENET_ATVR_ATIME. */
6680 /*! @brief Read current value of the ENET_ATVR_ATIME field. */
6681 #define BR_ENET_ATVR_ATIME(x) (HW_ENET_ATVR(x).U)
6683 /*! @brief Format value for bitfield ENET_ATVR_ATIME. */
6684 #define BF_ENET_ATVR_ATIME(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATVR_ATIME) & BM_ENET_ATVR_ATIME)
6686 /*! @brief Set the ATIME field to a new value. */
6687 #define BW_ENET_ATVR_ATIME(x, v) (HW_ENET_ATVR_WR(x, v))
6690 /*******************************************************************************
6691 * HW_ENET_ATOFF - Timer Offset Register
6692 ******************************************************************************/
6695 * @brief HW_ENET_ATOFF - Timer Offset Register (RW)
6697 * Reset value: 0x00000000U
6699 typedef union _hw_enet_atoff
6702 struct _hw_enet_atoff_bitfields
6704 uint32_t OFFSET : 32; /*!< [31:0] */
6709 * @name Constants and macros for entire ENET_ATOFF register
6712 #define HW_ENET_ATOFF_ADDR(x) ((x) + 0x408U)
6714 #define HW_ENET_ATOFF(x) (*(__IO hw_enet_atoff_t *) HW_ENET_ATOFF_ADDR(x))
6715 #define HW_ENET_ATOFF_RD(x) (HW_ENET_ATOFF(x).U)
6716 #define HW_ENET_ATOFF_WR(x, v) (HW_ENET_ATOFF(x).U = (v))
6717 #define HW_ENET_ATOFF_SET(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) | (v)))
6718 #define HW_ENET_ATOFF_CLR(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) & ~(v)))
6719 #define HW_ENET_ATOFF_TOG(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) ^ (v)))
6723 * Constants & macros for individual ENET_ATOFF bitfields
6727 * @name Register ENET_ATOFF, field OFFSET[31:0] (RW)
6729 * Offset value for one-shot event generation. When the timer reaches the value,
6730 * an event can be generated to reset the counter. If the increment value in
6731 * ATINC is given in true nanoseconds, this value is also given in true nanoseconds.
6734 #define BP_ENET_ATOFF_OFFSET (0U) /*!< Bit position for ENET_ATOFF_OFFSET. */
6735 #define BM_ENET_ATOFF_OFFSET (0xFFFFFFFFU) /*!< Bit mask for ENET_ATOFF_OFFSET. */
6736 #define BS_ENET_ATOFF_OFFSET (32U) /*!< Bit field size in bits for ENET_ATOFF_OFFSET. */
6738 /*! @brief Read current value of the ENET_ATOFF_OFFSET field. */
6739 #define BR_ENET_ATOFF_OFFSET(x) (HW_ENET_ATOFF(x).U)
6741 /*! @brief Format value for bitfield ENET_ATOFF_OFFSET. */
6742 #define BF_ENET_ATOFF_OFFSET(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATOFF_OFFSET) & BM_ENET_ATOFF_OFFSET)
6744 /*! @brief Set the OFFSET field to a new value. */
6745 #define BW_ENET_ATOFF_OFFSET(x, v) (HW_ENET_ATOFF_WR(x, v))
6748 /*******************************************************************************
6749 * HW_ENET_ATPER - Timer Period Register
6750 ******************************************************************************/
6753 * @brief HW_ENET_ATPER - Timer Period Register (RW)
6755 * Reset value: 0x3B9ACA00U
6757 typedef union _hw_enet_atper
6760 struct _hw_enet_atper_bitfields
6762 uint32_t PERIOD : 32; /*!< [31:0] */
6767 * @name Constants and macros for entire ENET_ATPER register
6770 #define HW_ENET_ATPER_ADDR(x) ((x) + 0x40CU)
6772 #define HW_ENET_ATPER(x) (*(__IO hw_enet_atper_t *) HW_ENET_ATPER_ADDR(x))
6773 #define HW_ENET_ATPER_RD(x) (HW_ENET_ATPER(x).U)
6774 #define HW_ENET_ATPER_WR(x, v) (HW_ENET_ATPER(x).U = (v))
6775 #define HW_ENET_ATPER_SET(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) | (v)))
6776 #define HW_ENET_ATPER_CLR(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) & ~(v)))
6777 #define HW_ENET_ATPER_TOG(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) ^ (v)))
6781 * Constants & macros for individual ENET_ATPER bitfields
6785 * @name Register ENET_ATPER, field PERIOD[31:0] (RW)
6787 * Value for generating periodic events. Each instance the timer reaches this
6788 * value, the period event occurs and the timer restarts. If the increment value in
6789 * ATINC is given in true nanoseconds, this value is also given in true
6790 * nanoseconds. The value should be initialized to 1,000,000,000 (1 x 10 9 ) to represent
6791 * a timer wrap around of one second. The increment value set in ATINC should be
6792 * set to the true nanoseconds of the period of clock ts_clk, hence implementing
6793 * a true 1 second counter.
6796 #define BP_ENET_ATPER_PERIOD (0U) /*!< Bit position for ENET_ATPER_PERIOD. */
6797 #define BM_ENET_ATPER_PERIOD (0xFFFFFFFFU) /*!< Bit mask for ENET_ATPER_PERIOD. */
6798 #define BS_ENET_ATPER_PERIOD (32U) /*!< Bit field size in bits for ENET_ATPER_PERIOD. */
6800 /*! @brief Read current value of the ENET_ATPER_PERIOD field. */
6801 #define BR_ENET_ATPER_PERIOD(x) (HW_ENET_ATPER(x).U)
6803 /*! @brief Format value for bitfield ENET_ATPER_PERIOD. */
6804 #define BF_ENET_ATPER_PERIOD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATPER_PERIOD) & BM_ENET_ATPER_PERIOD)
6806 /*! @brief Set the PERIOD field to a new value. */
6807 #define BW_ENET_ATPER_PERIOD(x, v) (HW_ENET_ATPER_WR(x, v))
6810 /*******************************************************************************
6811 * HW_ENET_ATCOR - Timer Correction Register
6812 ******************************************************************************/
6815 * @brief HW_ENET_ATCOR - Timer Correction Register (RW)
6817 * Reset value: 0x00000000U
6819 typedef union _hw_enet_atcor
6822 struct _hw_enet_atcor_bitfields
6824 uint32_t COR : 31; /*!< [30:0] Correction Counter Wrap-Around Value */
6825 uint32_t RESERVED0 : 1; /*!< [31] */
6830 * @name Constants and macros for entire ENET_ATCOR register
6833 #define HW_ENET_ATCOR_ADDR(x) ((x) + 0x410U)
6835 #define HW_ENET_ATCOR(x) (*(__IO hw_enet_atcor_t *) HW_ENET_ATCOR_ADDR(x))
6836 #define HW_ENET_ATCOR_RD(x) (HW_ENET_ATCOR(x).U)
6837 #define HW_ENET_ATCOR_WR(x, v) (HW_ENET_ATCOR(x).U = (v))
6838 #define HW_ENET_ATCOR_SET(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) | (v)))
6839 #define HW_ENET_ATCOR_CLR(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) & ~(v)))
6840 #define HW_ENET_ATCOR_TOG(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) ^ (v)))
6844 * Constants & macros for individual ENET_ATCOR bitfields
6848 * @name Register ENET_ATCOR, field COR[30:0] (RW)
6850 * Defines after how many timer clock cycles (ts_clk) the correction counter
6851 * should be reset and trigger a correction increment on the timer. The amount of
6852 * correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
6853 * counter and no corrections occur. This value is given in clock cycles, not in
6854 * nanoseconds as all other values.
6857 #define BP_ENET_ATCOR_COR (0U) /*!< Bit position for ENET_ATCOR_COR. */
6858 #define BM_ENET_ATCOR_COR (0x7FFFFFFFU) /*!< Bit mask for ENET_ATCOR_COR. */
6859 #define BS_ENET_ATCOR_COR (31U) /*!< Bit field size in bits for ENET_ATCOR_COR. */
6861 /*! @brief Read current value of the ENET_ATCOR_COR field. */
6862 #define BR_ENET_ATCOR_COR(x) (HW_ENET_ATCOR(x).B.COR)
6864 /*! @brief Format value for bitfield ENET_ATCOR_COR. */
6865 #define BF_ENET_ATCOR_COR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCOR_COR) & BM_ENET_ATCOR_COR)
6867 /*! @brief Set the COR field to a new value. */
6868 #define BW_ENET_ATCOR_COR(x, v) (HW_ENET_ATCOR_WR(x, (HW_ENET_ATCOR_RD(x) & ~BM_ENET_ATCOR_COR) | BF_ENET_ATCOR_COR(v)))
6871 /*******************************************************************************
6872 * HW_ENET_ATINC - Time-Stamping Clock Period Register
6873 ******************************************************************************/
6876 * @brief HW_ENET_ATINC - Time-Stamping Clock Period Register (RW)
6878 * Reset value: 0x00000000U
6880 typedef union _hw_enet_atinc
6883 struct _hw_enet_atinc_bitfields
6885 uint32_t INC : 7; /*!< [6:0] Clock Period Of The Timestamping Clock
6886 * (ts_clk) In Nanoseconds */
6887 uint32_t RESERVED0 : 1; /*!< [7] */
6888 uint32_t INC_CORR : 7; /*!< [14:8] Correction Increment Value */
6889 uint32_t RESERVED1 : 17; /*!< [31:15] */
6894 * @name Constants and macros for entire ENET_ATINC register
6897 #define HW_ENET_ATINC_ADDR(x) ((x) + 0x414U)
6899 #define HW_ENET_ATINC(x) (*(__IO hw_enet_atinc_t *) HW_ENET_ATINC_ADDR(x))
6900 #define HW_ENET_ATINC_RD(x) (HW_ENET_ATINC(x).U)
6901 #define HW_ENET_ATINC_WR(x, v) (HW_ENET_ATINC(x).U = (v))
6902 #define HW_ENET_ATINC_SET(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) | (v)))
6903 #define HW_ENET_ATINC_CLR(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) & ~(v)))
6904 #define HW_ENET_ATINC_TOG(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) ^ (v)))
6908 * Constants & macros for individual ENET_ATINC bitfields
6912 * @name Register ENET_ATINC, field INC[6:0] (RW)
6914 * The timer increments by this amount each clock cycle. For example, set to 10
6915 * for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
6916 * that is an integer fraction of the period set in ATPER.
6919 #define BP_ENET_ATINC_INC (0U) /*!< Bit position for ENET_ATINC_INC. */
6920 #define BM_ENET_ATINC_INC (0x0000007FU) /*!< Bit mask for ENET_ATINC_INC. */
6921 #define BS_ENET_ATINC_INC (7U) /*!< Bit field size in bits for ENET_ATINC_INC. */
6923 /*! @brief Read current value of the ENET_ATINC_INC field. */
6924 #define BR_ENET_ATINC_INC(x) (HW_ENET_ATINC(x).B.INC)
6926 /*! @brief Format value for bitfield ENET_ATINC_INC. */
6927 #define BF_ENET_ATINC_INC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATINC_INC) & BM_ENET_ATINC_INC)
6929 /*! @brief Set the INC field to a new value. */
6930 #define BW_ENET_ATINC_INC(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC) | BF_ENET_ATINC_INC(v)))
6934 * @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
6936 * This value is added every time the correction timer expires (every clock
6937 * cycle given in ATCOR). A value less than INC slows down the timer. A value greater
6938 * than INC speeds up the timer.
6941 #define BP_ENET_ATINC_INC_CORR (8U) /*!< Bit position for ENET_ATINC_INC_CORR. */
6942 #define BM_ENET_ATINC_INC_CORR (0x00007F00U) /*!< Bit mask for ENET_ATINC_INC_CORR. */
6943 #define BS_ENET_ATINC_INC_CORR (7U) /*!< Bit field size in bits for ENET_ATINC_INC_CORR. */
6945 /*! @brief Read current value of the ENET_ATINC_INC_CORR field. */
6946 #define BR_ENET_ATINC_INC_CORR(x) (HW_ENET_ATINC(x).B.INC_CORR)
6948 /*! @brief Format value for bitfield ENET_ATINC_INC_CORR. */
6949 #define BF_ENET_ATINC_INC_CORR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATINC_INC_CORR) & BM_ENET_ATINC_INC_CORR)
6951 /*! @brief Set the INC_CORR field to a new value. */
6952 #define BW_ENET_ATINC_INC_CORR(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC_CORR) | BF_ENET_ATINC_INC_CORR(v)))
6955 /*******************************************************************************
6956 * HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
6957 ******************************************************************************/
6960 * @brief HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
6962 * Reset value: 0x00000000U
6964 typedef union _hw_enet_atstmp
6967 struct _hw_enet_atstmp_bitfields
6969 uint32_t TIMESTAMP : 32; /*!< [31:0] */
6974 * @name Constants and macros for entire ENET_ATSTMP register
6977 #define HW_ENET_ATSTMP_ADDR(x) ((x) + 0x418U)
6979 #define HW_ENET_ATSTMP(x) (*(__I hw_enet_atstmp_t *) HW_ENET_ATSTMP_ADDR(x))
6980 #define HW_ENET_ATSTMP_RD(x) (HW_ENET_ATSTMP(x).U)
6984 * Constants & macros for individual ENET_ATSTMP bitfields
6988 * @name Register ENET_ATSTMP, field TIMESTAMP[31:0] (RO)
6990 * Timestamp of the last frame transmitted by the core that had TxBD[TS] set .
6991 * This register is only valid when EIR[TS_AVAIL] is set.
6994 #define BP_ENET_ATSTMP_TIMESTAMP (0U) /*!< Bit position for ENET_ATSTMP_TIMESTAMP. */
6995 #define BM_ENET_ATSTMP_TIMESTAMP (0xFFFFFFFFU) /*!< Bit mask for ENET_ATSTMP_TIMESTAMP. */
6996 #define BS_ENET_ATSTMP_TIMESTAMP (32U) /*!< Bit field size in bits for ENET_ATSTMP_TIMESTAMP. */
6998 /*! @brief Read current value of the ENET_ATSTMP_TIMESTAMP field. */
6999 #define BR_ENET_ATSTMP_TIMESTAMP(x) (HW_ENET_ATSTMP(x).U)
7002 /*******************************************************************************
7003 * HW_ENET_TGSR - Timer Global Status Register
7004 ******************************************************************************/
7007 * @brief HW_ENET_TGSR - Timer Global Status Register (RW)
7009 * Reset value: 0x00000000U
7011 typedef union _hw_enet_tgsr
7014 struct _hw_enet_tgsr_bitfields
7016 uint32_t TF0 : 1; /*!< [0] Copy Of Timer Flag For Channel 0 */
7017 uint32_t TF1 : 1; /*!< [1] Copy Of Timer Flag For Channel 1 */
7018 uint32_t TF2 : 1; /*!< [2] Copy Of Timer Flag For Channel 2 */
7019 uint32_t TF3 : 1; /*!< [3] Copy Of Timer Flag For Channel 3 */
7020 uint32_t RESERVED0 : 28; /*!< [31:4] */
7025 * @name Constants and macros for entire ENET_TGSR register
7028 #define HW_ENET_TGSR_ADDR(x) ((x) + 0x604U)
7030 #define HW_ENET_TGSR(x) (*(__IO hw_enet_tgsr_t *) HW_ENET_TGSR_ADDR(x))
7031 #define HW_ENET_TGSR_RD(x) (HW_ENET_TGSR(x).U)
7032 #define HW_ENET_TGSR_WR(x, v) (HW_ENET_TGSR(x).U = (v))
7033 #define HW_ENET_TGSR_SET(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) | (v)))
7034 #define HW_ENET_TGSR_CLR(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) & ~(v)))
7035 #define HW_ENET_TGSR_TOG(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) ^ (v)))
7039 * Constants & macros for individual ENET_TGSR bitfields
7043 * @name Register ENET_TGSR, field TF0[0] (W1C)
7046 * - 0 - Timer Flag for Channel 0 is clear
7047 * - 1 - Timer Flag for Channel 0 is set
7050 #define BP_ENET_TGSR_TF0 (0U) /*!< Bit position for ENET_TGSR_TF0. */
7051 #define BM_ENET_TGSR_TF0 (0x00000001U) /*!< Bit mask for ENET_TGSR_TF0. */
7052 #define BS_ENET_TGSR_TF0 (1U) /*!< Bit field size in bits for ENET_TGSR_TF0. */
7054 /*! @brief Read current value of the ENET_TGSR_TF0 field. */
7055 #define BR_ENET_TGSR_TF0(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0))
7057 /*! @brief Format value for bitfield ENET_TGSR_TF0. */
7058 #define BF_ENET_TGSR_TF0(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF0) & BM_ENET_TGSR_TF0)
7060 /*! @brief Set the TF0 field to a new value. */
7061 #define BW_ENET_TGSR_TF0(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0) = (v))
7065 * @name Register ENET_TGSR, field TF1[1] (W1C)
7068 * - 0 - Timer Flag for Channel 1 is clear
7069 * - 1 - Timer Flag for Channel 1 is set
7072 #define BP_ENET_TGSR_TF1 (1U) /*!< Bit position for ENET_TGSR_TF1. */
7073 #define BM_ENET_TGSR_TF1 (0x00000002U) /*!< Bit mask for ENET_TGSR_TF1. */
7074 #define BS_ENET_TGSR_TF1 (1U) /*!< Bit field size in bits for ENET_TGSR_TF1. */
7076 /*! @brief Read current value of the ENET_TGSR_TF1 field. */
7077 #define BR_ENET_TGSR_TF1(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1))
7079 /*! @brief Format value for bitfield ENET_TGSR_TF1. */
7080 #define BF_ENET_TGSR_TF1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF1) & BM_ENET_TGSR_TF1)
7082 /*! @brief Set the TF1 field to a new value. */
7083 #define BW_ENET_TGSR_TF1(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1) = (v))
7087 * @name Register ENET_TGSR, field TF2[2] (W1C)
7090 * - 0 - Timer Flag for Channel 2 is clear
7091 * - 1 - Timer Flag for Channel 2 is set
7094 #define BP_ENET_TGSR_TF2 (2U) /*!< Bit position for ENET_TGSR_TF2. */
7095 #define BM_ENET_TGSR_TF2 (0x00000004U) /*!< Bit mask for ENET_TGSR_TF2. */
7096 #define BS_ENET_TGSR_TF2 (1U) /*!< Bit field size in bits for ENET_TGSR_TF2. */
7098 /*! @brief Read current value of the ENET_TGSR_TF2 field. */
7099 #define BR_ENET_TGSR_TF2(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2))
7101 /*! @brief Format value for bitfield ENET_TGSR_TF2. */
7102 #define BF_ENET_TGSR_TF2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF2) & BM_ENET_TGSR_TF2)
7104 /*! @brief Set the TF2 field to a new value. */
7105 #define BW_ENET_TGSR_TF2(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2) = (v))
7109 * @name Register ENET_TGSR, field TF3[3] (W1C)
7112 * - 0 - Timer Flag for Channel 3 is clear
7113 * - 1 - Timer Flag for Channel 3 is set
7116 #define BP_ENET_TGSR_TF3 (3U) /*!< Bit position for ENET_TGSR_TF3. */
7117 #define BM_ENET_TGSR_TF3 (0x00000008U) /*!< Bit mask for ENET_TGSR_TF3. */
7118 #define BS_ENET_TGSR_TF3 (1U) /*!< Bit field size in bits for ENET_TGSR_TF3. */
7120 /*! @brief Read current value of the ENET_TGSR_TF3 field. */
7121 #define BR_ENET_TGSR_TF3(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3))
7123 /*! @brief Format value for bitfield ENET_TGSR_TF3. */
7124 #define BF_ENET_TGSR_TF3(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF3) & BM_ENET_TGSR_TF3)
7126 /*! @brief Set the TF3 field to a new value. */
7127 #define BW_ENET_TGSR_TF3(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3) = (v))
7130 /*******************************************************************************
7131 * HW_ENET_TCSRn - Timer Control Status Register
7132 ******************************************************************************/
7135 * @brief HW_ENET_TCSRn - Timer Control Status Register (RW)
7137 * Reset value: 0x00000000U
7139 typedef union _hw_enet_tcsrn
7142 struct _hw_enet_tcsrn_bitfields
7144 uint32_t TDRE : 1; /*!< [0] Timer DMA Request Enable */
7145 uint32_t RESERVED0 : 1; /*!< [1] */
7146 uint32_t TMODE : 4; /*!< [5:2] Timer Mode */
7147 uint32_t TIE : 1; /*!< [6] Timer Interrupt Enable */
7148 uint32_t TF : 1; /*!< [7] Timer Flag */
7149 uint32_t RESERVED1 : 24; /*!< [31:8] */
7154 * @name Constants and macros for entire ENET_TCSRn register
7157 #define HW_ENET_TCSRn_COUNT (4U)
7159 #define HW_ENET_TCSRn_ADDR(x, n) ((x) + 0x608U + (0x8U * (n)))
7161 #define HW_ENET_TCSRn(x, n) (*(__IO hw_enet_tcsrn_t *) HW_ENET_TCSRn_ADDR(x, n))
7162 #define HW_ENET_TCSRn_RD(x, n) (HW_ENET_TCSRn(x, n).U)
7163 #define HW_ENET_TCSRn_WR(x, n, v) (HW_ENET_TCSRn(x, n).U = (v))
7164 #define HW_ENET_TCSRn_SET(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) | (v)))
7165 #define HW_ENET_TCSRn_CLR(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) & ~(v)))
7166 #define HW_ENET_TCSRn_TOG(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) ^ (v)))
7170 * Constants & macros for individual ENET_TCSRn bitfields
7174 * @name Register ENET_TCSRn, field TDRE[0] (RW)
7177 * - 0 - DMA request is disabled
7178 * - 1 - DMA request is enabled
7181 #define BP_ENET_TCSRn_TDRE (0U) /*!< Bit position for ENET_TCSRn_TDRE. */
7182 #define BM_ENET_TCSRn_TDRE (0x00000001U) /*!< Bit mask for ENET_TCSRn_TDRE. */
7183 #define BS_ENET_TCSRn_TDRE (1U) /*!< Bit field size in bits for ENET_TCSRn_TDRE. */
7185 /*! @brief Read current value of the ENET_TCSRn_TDRE field. */
7186 #define BR_ENET_TCSRn_TDRE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE))
7188 /*! @brief Format value for bitfield ENET_TCSRn_TDRE. */
7189 #define BF_ENET_TCSRn_TDRE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TDRE) & BM_ENET_TCSRn_TDRE)
7191 /*! @brief Set the TDRE field to a new value. */
7192 #define BW_ENET_TCSRn_TDRE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE) = (v))
7196 * @name Register ENET_TCSRn, field TMODE[5:2] (RW)
7198 * Updating the Timer Mode field takes a few cycles to register because it is
7199 * synchronized to the 1588 clock. The version of Timer Mode returned on a read is
7200 * from the 1588 clock domain. When changing Timer Mode, always disable the
7201 * channel and read this register to verify the channel is disabled first.
7204 * - 0000 - Timer Channel is disabled.
7205 * - 0001 - Timer Channel is configured for Input Capture on rising edge
7206 * - 0010 - Timer Channel is configured for Input Capture on falling edge
7207 * - 0011 - Timer Channel is configured for Input Capture on both edges
7208 * - 0100 - Timer Channel is configured for Output Compare - software only
7209 * - 0101 - Timer Channel is configured for Output Compare - toggle output on
7211 * - 0110 - Timer Channel is configured for Output Compare - clear output on
7213 * - 0111 - Timer Channel is configured for Output Compare - set output on
7216 * - 1010 - Timer Channel is configured for Output Compare - clear output on
7217 * compare, set output on overflow
7218 * - 10x1 - Timer Channel is configured for Output Compare - set output on
7219 * compare, clear output on overflow
7221 * - 1110 - Timer Channel is configured for Output Compare - pulse output low on
7222 * compare for one 1588 clock cycle
7223 * - 1111 - Timer Channel is configured for Output Compare - pulse output high
7224 * on compare for one 1588 clock cycle
7227 #define BP_ENET_TCSRn_TMODE (2U) /*!< Bit position for ENET_TCSRn_TMODE. */
7228 #define BM_ENET_TCSRn_TMODE (0x0000003CU) /*!< Bit mask for ENET_TCSRn_TMODE. */
7229 #define BS_ENET_TCSRn_TMODE (4U) /*!< Bit field size in bits for ENET_TCSRn_TMODE. */
7231 /*! @brief Read current value of the ENET_TCSRn_TMODE field. */
7232 #define BR_ENET_TCSRn_TMODE(x, n) (HW_ENET_TCSRn(x, n).B.TMODE)
7234 /*! @brief Format value for bitfield ENET_TCSRn_TMODE. */
7235 #define BF_ENET_TCSRn_TMODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TMODE) & BM_ENET_TCSRn_TMODE)
7237 /*! @brief Set the TMODE field to a new value. */
7238 #define BW_ENET_TCSRn_TMODE(x, n, v) (HW_ENET_TCSRn_WR(x, n, (HW_ENET_TCSRn_RD(x, n) & ~BM_ENET_TCSRn_TMODE) | BF_ENET_TCSRn_TMODE(v)))
7242 * @name Register ENET_TCSRn, field TIE[6] (RW)
7245 * - 0 - Interrupt is disabled
7246 * - 1 - Interrupt is enabled
7249 #define BP_ENET_TCSRn_TIE (6U) /*!< Bit position for ENET_TCSRn_TIE. */
7250 #define BM_ENET_TCSRn_TIE (0x00000040U) /*!< Bit mask for ENET_TCSRn_TIE. */
7251 #define BS_ENET_TCSRn_TIE (1U) /*!< Bit field size in bits for ENET_TCSRn_TIE. */
7253 /*! @brief Read current value of the ENET_TCSRn_TIE field. */
7254 #define BR_ENET_TCSRn_TIE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE))
7256 /*! @brief Format value for bitfield ENET_TCSRn_TIE. */
7257 #define BF_ENET_TCSRn_TIE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TIE) & BM_ENET_TCSRn_TIE)
7259 /*! @brief Set the TIE field to a new value. */
7260 #define BW_ENET_TCSRn_TIE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE) = (v))
7264 * @name Register ENET_TCSRn, field TF[7] (W1C)
7266 * Sets when input capture or output compare occurs. This flag is double
7267 * buffered between the module clock and 1588 clock domains. When this field is 1, it
7268 * can be cleared to 0 by writing 1 to it.
7271 * - 0 - Input Capture or Output Compare has not occurred
7272 * - 1 - Input Capture or Output Compare has occurred
7275 #define BP_ENET_TCSRn_TF (7U) /*!< Bit position for ENET_TCSRn_TF. */
7276 #define BM_ENET_TCSRn_TF (0x00000080U) /*!< Bit mask for ENET_TCSRn_TF. */
7277 #define BS_ENET_TCSRn_TF (1U) /*!< Bit field size in bits for ENET_TCSRn_TF. */
7279 /*! @brief Read current value of the ENET_TCSRn_TF field. */
7280 #define BR_ENET_TCSRn_TF(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF))
7282 /*! @brief Format value for bitfield ENET_TCSRn_TF. */
7283 #define BF_ENET_TCSRn_TF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TF) & BM_ENET_TCSRn_TF)
7285 /*! @brief Set the TF field to a new value. */
7286 #define BW_ENET_TCSRn_TF(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF) = (v))
7288 /*******************************************************************************
7289 * HW_ENET_TCCRn - Timer Compare Capture Register
7290 ******************************************************************************/
7293 * @brief HW_ENET_TCCRn - Timer Compare Capture Register (RW)
7295 * Reset value: 0x00000000U
7297 typedef union _hw_enet_tccrn
7300 struct _hw_enet_tccrn_bitfields
7302 uint32_t TCC : 32; /*!< [31:0] Timer Capture Compare */
7307 * @name Constants and macros for entire ENET_TCCRn register
7310 #define HW_ENET_TCCRn_COUNT (4U)
7312 #define HW_ENET_TCCRn_ADDR(x, n) ((x) + 0x60CU + (0x8U * (n)))
7314 #define HW_ENET_TCCRn(x, n) (*(__IO hw_enet_tccrn_t *) HW_ENET_TCCRn_ADDR(x, n))
7315 #define HW_ENET_TCCRn_RD(x, n) (HW_ENET_TCCRn(x, n).U)
7316 #define HW_ENET_TCCRn_WR(x, n, v) (HW_ENET_TCCRn(x, n).U = (v))
7317 #define HW_ENET_TCCRn_SET(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) | (v)))
7318 #define HW_ENET_TCCRn_CLR(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) & ~(v)))
7319 #define HW_ENET_TCCRn_TOG(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) ^ (v)))
7323 * Constants & macros for individual ENET_TCCRn bitfields
7327 * @name Register ENET_TCCRn, field TCC[31:0] (RW)
7329 * This register is double buffered between the module clock and 1588 clock
7330 * domains. When configured for compare, the 1588 clock domain updates with the value
7331 * in the module clock domain whenever the Timer Channel is first enabled and on
7332 * each subsequent compare. Write to this register with the first compare value
7333 * before enabling the Timer Channel. When the Timer Channel is enabled, write
7334 * the second compare value either immediately, or at least before the first
7335 * compare occurs. After each compare, write the next compare value before the previous
7336 * compare occurs and before clearing the Timer Flag. The compare occurs one
7337 * 1588 clock cycle after the IEEE 1588 Counter increments past the compare value in
7338 * the 1588 clock domain. If the compare value is less than the value of the
7339 * 1588 Counter when the Timer Channel is first enabled, then the compare does not
7340 * occur until following the next overflow of the 1588 Counter. If the compare
7341 * value is greater than the IEEE 1588 Counter when the 1588 Counter overflows, or
7342 * the compare value is less than the value of the IEEE 1588 Counter after the
7343 * overflow, then the compare occurs one 1588 clock cycle following the overflow.
7344 * When configured for Capture, the value of the IEEE 1588 Counter is captured into
7345 * the 1588 clock domain and then updated into the module clock domain, provided
7346 * the Timer Flag is clear. Always read the capture value before clearing the
7350 #define BP_ENET_TCCRn_TCC (0U) /*!< Bit position for ENET_TCCRn_TCC. */
7351 #define BM_ENET_TCCRn_TCC (0xFFFFFFFFU) /*!< Bit mask for ENET_TCCRn_TCC. */
7352 #define BS_ENET_TCCRn_TCC (32U) /*!< Bit field size in bits for ENET_TCCRn_TCC. */
7354 /*! @brief Read current value of the ENET_TCCRn_TCC field. */
7355 #define BR_ENET_TCCRn_TCC(x, n) (HW_ENET_TCCRn(x, n).U)
7357 /*! @brief Format value for bitfield ENET_TCCRn_TCC. */
7358 #define BF_ENET_TCCRn_TCC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCCRn_TCC) & BM_ENET_TCCRn_TCC)
7360 /*! @brief Set the TCC field to a new value. */
7361 #define BW_ENET_TCCRn_TCC(x, n, v) (HW_ENET_TCCRn_WR(x, n, v))
7364 /*******************************************************************************
7365 * hw_enet_t - module struct
7366 ******************************************************************************/
7368 * @brief All ENET module registers.
7371 typedef struct _hw_enet
7373 uint8_t _reserved0[4];
7374 __IO hw_enet_eir_t EIR; /*!< [0x4] Interrupt Event Register */
7375 __IO hw_enet_eimr_t EIMR; /*!< [0x8] Interrupt Mask Register */
7376 uint8_t _reserved1[4];
7377 __IO hw_enet_rdar_t RDAR; /*!< [0x10] Receive Descriptor Active Register */
7378 __IO hw_enet_tdar_t TDAR; /*!< [0x14] Transmit Descriptor Active Register */
7379 uint8_t _reserved2[12];
7380 __IO hw_enet_ecr_t ECR; /*!< [0x24] Ethernet Control Register */
7381 uint8_t _reserved3[24];
7382 __IO hw_enet_mmfr_t MMFR; /*!< [0x40] MII Management Frame Register */
7383 __IO hw_enet_mscr_t MSCR; /*!< [0x44] MII Speed Control Register */
7384 uint8_t _reserved4[28];
7385 __IO hw_enet_mibc_t MIBC; /*!< [0x64] MIB Control Register */
7386 uint8_t _reserved5[28];
7387 __IO hw_enet_rcr_t RCR; /*!< [0x84] Receive Control Register */
7388 uint8_t _reserved6[60];
7389 __IO hw_enet_tcr_t TCR; /*!< [0xC4] Transmit Control Register */
7390 uint8_t _reserved7[28];
7391 __IO hw_enet_palr_t PALR; /*!< [0xE4] Physical Address Lower Register */
7392 __IO hw_enet_paur_t PAUR; /*!< [0xE8] Physical Address Upper Register */
7393 __IO hw_enet_opd_t OPD; /*!< [0xEC] Opcode/Pause Duration Register */
7394 uint8_t _reserved8[40];
7395 __IO hw_enet_iaur_t IAUR; /*!< [0x118] Descriptor Individual Upper Address Register */
7396 __IO hw_enet_ialr_t IALR; /*!< [0x11C] Descriptor Individual Lower Address Register */
7397 __IO hw_enet_gaur_t GAUR; /*!< [0x120] Descriptor Group Upper Address Register */
7398 __IO hw_enet_galr_t GALR; /*!< [0x124] Descriptor Group Lower Address Register */
7399 uint8_t _reserved9[28];
7400 __IO hw_enet_tfwr_t TFWR; /*!< [0x144] Transmit FIFO Watermark Register */
7401 uint8_t _reserved10[56];
7402 __IO hw_enet_rdsr_t RDSR; /*!< [0x180] Receive Descriptor Ring Start Register */
7403 __IO hw_enet_tdsr_t TDSR; /*!< [0x184] Transmit Buffer Descriptor Ring Start Register */
7404 __IO hw_enet_mrbr_t MRBR; /*!< [0x188] Maximum Receive Buffer Size Register */
7405 uint8_t _reserved11[4];
7406 __IO hw_enet_rsfl_t RSFL; /*!< [0x190] Receive FIFO Section Full Threshold */
7407 __IO hw_enet_rsem_t RSEM; /*!< [0x194] Receive FIFO Section Empty Threshold */
7408 __IO hw_enet_raem_t RAEM; /*!< [0x198] Receive FIFO Almost Empty Threshold */
7409 __IO hw_enet_rafl_t RAFL; /*!< [0x19C] Receive FIFO Almost Full Threshold */
7410 __IO hw_enet_tsem_t TSEM; /*!< [0x1A0] Transmit FIFO Section Empty Threshold */
7411 __IO hw_enet_taem_t TAEM; /*!< [0x1A4] Transmit FIFO Almost Empty Threshold */
7412 __IO hw_enet_tafl_t TAFL; /*!< [0x1A8] Transmit FIFO Almost Full Threshold */
7413 __IO hw_enet_tipg_t TIPG; /*!< [0x1AC] Transmit Inter-Packet Gap */
7414 __IO hw_enet_ftrl_t FTRL; /*!< [0x1B0] Frame Truncation Length */
7415 uint8_t _reserved12[12];
7416 __IO hw_enet_tacc_t TACC; /*!< [0x1C0] Transmit Accelerator Function Configuration */
7417 __IO hw_enet_racc_t RACC; /*!< [0x1C4] Receive Accelerator Function Configuration */
7418 uint8_t _reserved13[60];
7419 __I hw_enet_rmon_t_packets_t RMON_T_PACKETS; /*!< [0x204] Tx Packet Count Statistic Register */
7420 __I hw_enet_rmon_t_bc_pkt_t RMON_T_BC_PKT; /*!< [0x208] Tx Broadcast Packets Statistic Register */
7421 __I hw_enet_rmon_t_mc_pkt_t RMON_T_MC_PKT; /*!< [0x20C] Tx Multicast Packets Statistic Register */
7422 __I hw_enet_rmon_t_crc_align_t RMON_T_CRC_ALIGN; /*!< [0x210] Tx Packets with CRC/Align Error Statistic Register */
7423 __I hw_enet_rmon_t_undersize_t RMON_T_UNDERSIZE; /*!< [0x214] Tx Packets Less Than Bytes and Good CRC Statistic Register */
7424 __I hw_enet_rmon_t_oversize_t RMON_T_OVERSIZE; /*!< [0x218] Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
7425 __I hw_enet_rmon_t_frag_t RMON_T_FRAG; /*!< [0x21C] Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
7426 __I hw_enet_rmon_t_jab_t RMON_T_JAB; /*!< [0x220] Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
7427 __I hw_enet_rmon_t_col_t RMON_T_COL; /*!< [0x224] Tx Collision Count Statistic Register */
7428 __I hw_enet_rmon_t_p64_t RMON_T_P64; /*!< [0x228] Tx 64-Byte Packets Statistic Register */
7429 __I hw_enet_rmon_t_p65to127_t RMON_T_P65TO127; /*!< [0x22C] Tx 65- to 127-byte Packets Statistic Register */
7430 __I hw_enet_rmon_t_p128to255_t RMON_T_P128TO255; /*!< [0x230] Tx 128- to 255-byte Packets Statistic Register */
7431 __I hw_enet_rmon_t_p256to511_t RMON_T_P256TO511; /*!< [0x234] Tx 256- to 511-byte Packets Statistic Register */
7432 __I hw_enet_rmon_t_p512to1023_t RMON_T_P512TO1023; /*!< [0x238] Tx 512- to 1023-byte Packets Statistic Register */
7433 __I hw_enet_rmon_t_p1024to2047_t RMON_T_P1024TO2047; /*!< [0x23C] Tx 1024- to 2047-byte Packets Statistic Register */
7434 __I hw_enet_rmon_t_p_gte2048_t RMON_T_P_GTE2048; /*!< [0x240] Tx Packets Greater Than 2048 Bytes Statistic Register */
7435 __I hw_enet_rmon_t_octets_t RMON_T_OCTETS; /*!< [0x244] Tx Octets Statistic Register */
7436 uint8_t _reserved14[4];
7437 __I hw_enet_ieee_t_frame_ok_t IEEE_T_FRAME_OK; /*!< [0x24C] Frames Transmitted OK Statistic Register */
7438 __I hw_enet_ieee_t_1col_t IEEE_T_1COL; /*!< [0x250] Frames Transmitted with Single Collision Statistic Register */
7439 __I hw_enet_ieee_t_mcol_t IEEE_T_MCOL; /*!< [0x254] Frames Transmitted with Multiple Collisions Statistic Register */
7440 __I hw_enet_ieee_t_def_t IEEE_T_DEF; /*!< [0x258] Frames Transmitted after Deferral Delay Statistic Register */
7441 __I hw_enet_ieee_t_lcol_t IEEE_T_LCOL; /*!< [0x25C] Frames Transmitted with Late Collision Statistic Register */
7442 __I hw_enet_ieee_t_excol_t IEEE_T_EXCOL; /*!< [0x260] Frames Transmitted with Excessive Collisions Statistic Register */
7443 __I hw_enet_ieee_t_macerr_t IEEE_T_MACERR; /*!< [0x264] Frames Transmitted with Tx FIFO Underrun Statistic Register */
7444 __I hw_enet_ieee_t_cserr_t IEEE_T_CSERR; /*!< [0x268] Frames Transmitted with Carrier Sense Error Statistic Register */
7445 uint8_t _reserved15[4];
7446 __I hw_enet_ieee_t_fdxfc_t IEEE_T_FDXFC; /*!< [0x270] Flow Control Pause Frames Transmitted Statistic Register */
7447 __I hw_enet_ieee_t_octets_ok_t IEEE_T_OCTETS_OK; /*!< [0x274] Octet Count for Frames Transmitted w/o Error Statistic Register */
7448 uint8_t _reserved16[12];
7449 __I hw_enet_rmon_r_packets_t RMON_R_PACKETS; /*!< [0x284] Rx Packet Count Statistic Register */
7450 __I hw_enet_rmon_r_bc_pkt_t RMON_R_BC_PKT; /*!< [0x288] Rx Broadcast Packets Statistic Register */
7451 __I hw_enet_rmon_r_mc_pkt_t RMON_R_MC_PKT; /*!< [0x28C] Rx Multicast Packets Statistic Register */
7452 __I hw_enet_rmon_r_crc_align_t RMON_R_CRC_ALIGN; /*!< [0x290] Rx Packets with CRC/Align Error Statistic Register */
7453 __I hw_enet_rmon_r_undersize_t RMON_R_UNDERSIZE; /*!< [0x294] Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
7454 __I hw_enet_rmon_r_oversize_t RMON_R_OVERSIZE; /*!< [0x298] Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
7455 __I hw_enet_rmon_r_frag_t RMON_R_FRAG; /*!< [0x29C] Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
7456 __I hw_enet_rmon_r_jab_t RMON_R_JAB; /*!< [0x2A0] Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
7457 uint8_t _reserved17[4];
7458 __I hw_enet_rmon_r_p64_t RMON_R_P64; /*!< [0x2A8] Rx 64-Byte Packets Statistic Register */
7459 __I hw_enet_rmon_r_p65to127_t RMON_R_P65TO127; /*!< [0x2AC] Rx 65- to 127-Byte Packets Statistic Register */
7460 __I hw_enet_rmon_r_p128to255_t RMON_R_P128TO255; /*!< [0x2B0] Rx 128- to 255-Byte Packets Statistic Register */
7461 __I hw_enet_rmon_r_p256to511_t RMON_R_P256TO511; /*!< [0x2B4] Rx 256- to 511-Byte Packets Statistic Register */
7462 __I hw_enet_rmon_r_p512to1023_t RMON_R_P512TO1023; /*!< [0x2B8] Rx 512- to 1023-Byte Packets Statistic Register */
7463 __I hw_enet_rmon_r_p1024to2047_t RMON_R_P1024TO2047; /*!< [0x2BC] Rx 1024- to 2047-Byte Packets Statistic Register */
7464 __I hw_enet_rmon_r_p_gte2048_t RMON_R_P_GTE2048; /*!< [0x2C0] Rx Packets Greater than 2048 Bytes Statistic Register */
7465 __I hw_enet_rmon_r_octets_t RMON_R_OCTETS; /*!< [0x2C4] Rx Octets Statistic Register */
7466 __I hw_enet_ieee_r_drop_t IEEE_R_DROP; /*!< [0x2C8] Frames not Counted Correctly Statistic Register */
7467 __I hw_enet_ieee_r_frame_ok_t IEEE_R_FRAME_OK; /*!< [0x2CC] Frames Received OK Statistic Register */
7468 __I hw_enet_ieee_r_crc_t IEEE_R_CRC; /*!< [0x2D0] Frames Received with CRC Error Statistic Register */
7469 __I hw_enet_ieee_r_align_t IEEE_R_ALIGN; /*!< [0x2D4] Frames Received with Alignment Error Statistic Register */
7470 __I hw_enet_ieee_r_macerr_t IEEE_R_MACERR; /*!< [0x2D8] Receive FIFO Overflow Count Statistic Register */
7471 __I hw_enet_ieee_r_fdxfc_t IEEE_R_FDXFC; /*!< [0x2DC] Flow Control Pause Frames Received Statistic Register */
7472 __I hw_enet_ieee_r_octets_ok_t IEEE_R_OCTETS_OK; /*!< [0x2E0] Octet Count for Frames Received without Error Statistic Register */
7473 uint8_t _reserved18[284];
7474 __IO hw_enet_atcr_t ATCR; /*!< [0x400] Adjustable Timer Control Register */
7475 __IO hw_enet_atvr_t ATVR; /*!< [0x404] Timer Value Register */
7476 __IO hw_enet_atoff_t ATOFF; /*!< [0x408] Timer Offset Register */
7477 __IO hw_enet_atper_t ATPER; /*!< [0x40C] Timer Period Register */
7478 __IO hw_enet_atcor_t ATCOR; /*!< [0x410] Timer Correction Register */
7479 __IO hw_enet_atinc_t ATINC; /*!< [0x414] Time-Stamping Clock Period Register */
7480 __I hw_enet_atstmp_t ATSTMP; /*!< [0x418] Timestamp of Last Transmitted Frame */
7481 uint8_t _reserved19[488];
7482 __IO hw_enet_tgsr_t TGSR; /*!< [0x604] Timer Global Status Register */
7484 __IO hw_enet_tcsrn_t TCSRn; /*!< [0x608] Timer Control Status Register */
7485 __IO hw_enet_tccrn_t TCCRn; /*!< [0x60C] Timer Compare Capture Register */
7490 /*! @brief Macro to access all ENET registers. */
7491 /*! @param x ENET module instance base address. */
7492 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
7493 * use the '&' operator, like <code>&HW_ENET(ENET_BASE)</code>. */
7494 #define HW_ENET(x) (*(hw_enet_t *)(x))
7496 #endif /* __HW_ENET_REGISTERS_H__ */