2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_DMAMUX_REGISTERS_H__
81 #define __HW_DMAMUX_REGISTERS_H__
84 #include "fsl_bitaccess.h"
89 * DMA channel multiplexor
91 * Registers defined in this header file:
92 * - HW_DMAMUX_CHCFGn - Channel Configuration register
94 * - hw_dmamux_t - Struct containing all module registers.
97 #define HW_DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
99 /*******************************************************************************
100 * HW_DMAMUX_CHCFGn - Channel Configuration register
101 ******************************************************************************/
104 * @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
108 * Each of the DMA channels can be independently enabled/disabled and associated
109 * with one of the DMA slots (peripheral slots or always-on slots) in the
110 * system. Setting multiple CHCFG registers with the same source value will result in
111 * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
112 * Before changing the trigger or source settings, a DMA channel must be disabled
115 typedef union _hw_dmamux_chcfgn
118 struct _hw_dmamux_chcfgn_bitfields
120 uint8_t SOURCE : 6; /*!< [5:0] DMA Channel Source (Slot) */
121 uint8_t TRIG : 1; /*!< [6] DMA Channel Trigger Enable */
122 uint8_t ENBL : 1; /*!< [7] DMA Channel Enable */
124 } hw_dmamux_chcfgn_t;
127 * @name Constants and macros for entire DMAMUX_CHCFGn register
130 #define HW_DMAMUX_CHCFGn_COUNT (16U)
132 #define HW_DMAMUX_CHCFGn_ADDR(x, n) ((x) + 0x0U + (0x1U * (n)))
134 #define HW_DMAMUX_CHCFGn(x, n) (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
135 #define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
136 #define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
137 #define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) | (v)))
138 #define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
139 #define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^ (v)))
143 * Constants & macros for individual DMAMUX_CHCFGn bitfields
147 * @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
149 * Specifies which DMA source, if any, is routed to a particular DMA channel.
150 * See your device's chip configuration details for information about the
151 * peripherals and their slot numbers.
154 #define BP_DMAMUX_CHCFGn_SOURCE (0U) /*!< Bit position for DMAMUX_CHCFGn_SOURCE. */
155 #define BM_DMAMUX_CHCFGn_SOURCE (0x3FU) /*!< Bit mask for DMAMUX_CHCFGn_SOURCE. */
156 #define BS_DMAMUX_CHCFGn_SOURCE (6U) /*!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE. */
158 /*! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field. */
159 #define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
161 /*! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE. */
162 #define BF_DMAMUX_CHCFGn_SOURCE(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_SOURCE) & BM_DMAMUX_CHCFGn_SOURCE)
164 /*! @brief Set the SOURCE field to a new value. */
165 #define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
169 * @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
171 * Enables the periodic trigger capability for the triggered DMA channel.
174 * - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
175 * DMA Channel will simply route the specified source to the DMA channel.
177 * - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
178 * DMAMUX is in Periodic Trigger mode.
181 #define BP_DMAMUX_CHCFGn_TRIG (6U) /*!< Bit position for DMAMUX_CHCFGn_TRIG. */
182 #define BM_DMAMUX_CHCFGn_TRIG (0x40U) /*!< Bit mask for DMAMUX_CHCFGn_TRIG. */
183 #define BS_DMAMUX_CHCFGn_TRIG (1U) /*!< Bit field size in bits for DMAMUX_CHCFGn_TRIG. */
185 /*! @brief Read current value of the DMAMUX_CHCFGn_TRIG field. */
186 #define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
188 /*! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG. */
189 #define BF_DMAMUX_CHCFGn_TRIG(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_TRIG) & BM_DMAMUX_CHCFGn_TRIG)
191 /*! @brief Set the TRIG field to a new value. */
192 #define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
196 * @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
198 * Enables the DMA channel.
201 * - 0 - DMA channel is disabled. This mode is primarily used during
202 * configuration of the DMAMux. The DMA has separate channel enables/disables, which
203 * should be used to disable or reconfigure a DMA channel.
204 * - 1 - DMA channel is enabled
207 #define BP_DMAMUX_CHCFGn_ENBL (7U) /*!< Bit position for DMAMUX_CHCFGn_ENBL. */
208 #define BM_DMAMUX_CHCFGn_ENBL (0x80U) /*!< Bit mask for DMAMUX_CHCFGn_ENBL. */
209 #define BS_DMAMUX_CHCFGn_ENBL (1U) /*!< Bit field size in bits for DMAMUX_CHCFGn_ENBL. */
211 /*! @brief Read current value of the DMAMUX_CHCFGn_ENBL field. */
212 #define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
214 /*! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL. */
215 #define BF_DMAMUX_CHCFGn_ENBL(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_ENBL) & BM_DMAMUX_CHCFGn_ENBL)
217 /*! @brief Set the ENBL field to a new value. */
218 #define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
221 /*******************************************************************************
222 * hw_dmamux_t - module struct
223 ******************************************************************************/
225 * @brief All DMAMUX module registers.
228 typedef struct _hw_dmamux
230 __IO hw_dmamux_chcfgn_t CHCFGn[16]; /*!< [0x0] Channel Configuration register */
234 /*! @brief Macro to access all DMAMUX registers. */
235 /*! @param x DMAMUX module instance base address. */
236 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
237 * use the '&' operator, like <code>&HW_DMAMUX(DMAMUX_BASE)</code>. */
238 #define HW_DMAMUX(x) (*(hw_dmamux_t *)(x))
240 #endif /* __HW_DMAMUX_REGISTERS_H__ */