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30 #ifndef __FSL_WDOG_HAL_H__
31 #define __FSL_WDOG_HAL_H__
36 #include "fsl_wdog_features.h"
37 #include "fsl_device_registers.h"
40 * @addtogroup wdog_hal
44 /*******************************************************************************
46 *******************************************************************************/
48 #define WDOG_UNLOCK_VALUE_HIGH (0xC520U)
49 #define WDOG_UNLOCK_VALUE_LOW (0xD928U)
51 #define WDOG_REFRESH_VALUE_HIGH (0xA602U)
52 #define WDOG_REFRESH_VALUE_LOW (0xB480U)
54 /*! @brief Watchdog clock source selection.*/
55 typedef enum _wdog_clock_source {
56 kWdogClockSourceLpoClock = 0x0U, /*!< Clock source is LPO clock */
57 kWdogClockSourceBusClock = 0x1U /*!< Clock source is Bus clock */
58 } wdog_clock_source_t;
60 /*! @brief Define the selection of the clock prescaler*/
61 typedef enum _wdog_clock_prescaler_value {
62 kWdogClockPrescalerValueDevide1 = 0x0U, /*!< Divided by 1 */
63 kWdogClockPrescalerValueDevide2 = 0x1U, /*!< Divided by 2 */
64 kWdogClockPrescalerValueDevide3 = 0x2U, /*!< Divided by 3 */
65 kWdogClockPrescalerValueDevide4 = 0x3U, /*!< Divided by 4 */
66 kWdogClockPrescalerValueDevide5 = 0x4U, /*!< Divided by 5 */
67 kWdogClockPrescalerValueDevide6 = 0x5U, /*!< Divided by 6 */
68 kWdogClockPrescalerValueDevide7 = 0x6U, /*!< Divided by 7 */
69 kWdogClockPrescalerValueDevide8 = 0x7U /*!< Divided by 8 */
70 } wdog_clock_prescaler_value_t;
72 /*! @brief Define the common configure */
73 typedef union _wdog_common_config {
76 uint32_t wdogEnable:1; /*!< Enable configure, 1 means enable WDOG */
77 uint32_t clockSource:1; /*!< Clock source */
78 uint32_t interruptEnable:1; /*!< WDOG interrupt configure, 1 means enable interrupt */
79 uint32_t windowModeEnable:1; /*!< Window mode configure, 1 means enable window mode */
80 uint32_t updateRegisterEnable:1; /*!< 1 means WDOG register can reconfigure by unlock */
81 uint32_t workInDebugModeEnable:1; /*!< 1 means WDOG works while CPU in Debug mode */
82 uint32_t workInStopModeEnable:1; /*!< 1 means WDOG works while CPU in Debug mode */
83 uint32_t workInWaitModeEnable:1; /*!< 1 means WDOG works while CPU in Debug mode */
84 uint32_t reserved0:1; /*!< Reserved */
85 uint32_t reserved1:1; /*!< Reserved */
86 uint32_t testWdog:1; /*!< WDOG enable configure */
87 uint32_t testSelect:1; /*!< 0 means quick test, 1 means byte test */
88 uint32_t byteSelect:2; /*!< Test byte select */
89 uint32_t disableTestWdog:1; /*!< 1 means WDOG test mode is disabled */
90 uint32_t reserved2:1; /*!< Reserved */
91 uint32_t reserved3:16; /*!< Reserved */
96 /*******************************************************************************
98 *******************************************************************************/
100 #if defined(__cplusplus)
105 * @name Watchdog HAL.
110 * @brief Sets the WDOG common configure.
112 * This function is used to set the WDOG common configure.
113 * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, the WCT window is still open and
114 * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
115 * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled.
116 * The common configuration is controlled by the WDOG_STCTRLH. This is a write-once register and this interface
117 * is used to set all field of the WDOG_STCTRLH registers at the same time.
118 * If only one field needs to be set, the API can be used. These API write to the WDOG_STCTRLH register:
119 * #WDOG_HAL_Enable,#WDOG_HAL_Disable,#WDOG_HAL_SetIntCmd,#WDOG_HAL_SetClockSourceMode,#WDOG_HAL_SetWindowModeCmd,
120 * #WDOG_HAL_SetRegisterUpdateCmd,#WDOG_HAL_SetWorkInDebugModeCmd,#WDOG_HAL_SetWorkInStopModeCmd,
121 * #WDOG_HAL_SetWorkInWaitModeCmd
123 * @param baseAddr The WDOG peripheral base address
124 * @param commonConfig The common configure of the WDOG
126 static inline void WDOG_HAL_SetCommonConfig(uint32_t baseAddr, wdog_common_config commonConfig)
128 HW_WDOG_STCTRLH_WR(baseAddr,(uint16_t)commonConfig.U);
132 * @brief Enables the Watchdog module.
134 * This function enables the WDOG.
135 * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
136 * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
138 * @param baseAddr The WDOG peripheral base address
140 static inline void WDOG_HAL_Enable(uint32_t baseAddr)
142 BW_WDOG_STCTRLH_WDOGEN(baseAddr, (uint8_t)true);
146 * @brief Disables the Watchdog module.
148 * This function disables the WDOG.
149 * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
150 * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
152 * @param baseAddr The WDOG peripheral base address
154 static inline void WDOG_HAL_Disable(uint32_t baseAddr)
156 BW_WDOG_STCTRLH_WDOGEN(baseAddr, (uint8_t)false);
160 * @brief Checks whether the WDOG is enabled.
162 * This function checks whether the WDOG is enabled.
164 * @param baseAddr The WDOG peripheral base address
165 * @return false means WDOG is disabled, true means WODG is enabled.
168 static inline bool WDOG_HAL_IsEnabled(uint32_t baseAddr)
170 return (bool)BR_WDOG_STCTRLH_WDOGEN(baseAddr);
174 * @brief Enables and disables the Watchdog interrupt.
176 * This function enables or disables the WDOG interrupt.
177 * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
178 * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
179 * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
181 * @param baseAddr The WDOG peripheral base address
182 * @param enable false means disable watchdog interrupt and true means enable watchdog interrupt.
184 static inline void WDOG_HAL_SetIntCmd(uint32_t baseAddr, bool enable)
186 BW_WDOG_STCTRLH_IRQRSTEN(baseAddr, (uint8_t)enable);
190 * @brief Checks whether the WDOG interrupt is enabled.
192 * This function checks whether the WDOG interrupt is enabled.
194 * @param baseAddr The WDOG peripheral base address
195 * @return false means interrupt is disabled, true means interrupt is enabled.
197 static inline bool WDOG_HAL_GetIntCmd(uint32_t baseAddr)
199 return (bool)BR_WDOG_STCTRLH_IRQRSTEN(baseAddr);
203 * @brief Sets the Watchdog clock Source.
205 * This function sets the WDOG clock source. There are two clock sources that can be used:
206 * the LPO clock and the bus clock.
207 * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
208 * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
209 * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
211 * @param baseAddr The WDOG peripheral base address
212 * @param clockSource watchdog clock source, see #wdog_clock_source_t.
214 static inline void WDOG_HAL_SetClockSourceMode(uint32_t baseAddr, wdog_clock_source_t clockSource)
216 BW_WDOG_STCTRLH_CLKSRC(baseAddr, (uint8_t)clockSource);
220 * @brief Gets the Watchdog clock Source.
222 * This function gets the WDOG clock source. There are two clock sources that can be used:
223 * the LPO clock and the bus clock.
224 * A Clock Switching Delay time is about 2 clock A cycles plus 2
225 * clock B, where clock A and B are the two input clocks to the clock mux.
227 * @param baseAddr The WDOG peripheral base address
228 * @return watchdog clock source, see #wdog_clock_source_t.
230 static inline wdog_clock_source_t WDOG_HAL_GetClockSourceMode(uint32_t baseAddr)
232 return (wdog_clock_source_t)BR_WDOG_STCTRLH_CLKSRC(baseAddr);
236 * @brief Enables and disables the Watchdog window mode.
238 * This function configures the WDOG window mode.
239 * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
240 * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
241 * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
243 * @param baseAddr The WDOG peripheral base address
244 * @param enable false means disable watchdog window mode. true means enable watchdog window mode.
246 static inline void WDOG_HAL_SetWindowModeCmd(uint32_t baseAddr, bool enable)
248 BW_WDOG_STCTRLH_WINEN(baseAddr, (uint8_t)enable);
252 * @brief Checks whether the window mode is enabled.
254 * This function checks whether the WDOG window mode is enabled.
256 * @param baseAddr The WDOG peripheral base address
257 * @return false means window mode is disabled, true means window mode is enabled.
259 static inline bool WDOG_HAL_GetWindowModeCmd(uint32_t baseAddr)
261 return (bool)BR_WDOG_STCTRLH_WINEN(baseAddr);
265 * @brief Enables and disables the Watchdog write-once-only register update.
267 * This function configures the WDOG register update feature. If disabled, it means that
268 * all WDOG registers is never written again unless Power On Reset.
269 * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
270 * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
271 * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
273 * @param baseAddr The WDOG peripheral base address
274 * @param enable false means disable watchdog write-once-only register update.
275 * true means enable watchdog write-once-only register update.
277 static inline void WDOG_HAL_SetRegisterUpdateCmd(uint32_t baseAddr, bool enable)
279 BW_WDOG_STCTRLH_ALLOWUPDATE(baseAddr, (uint8_t)enable);
283 * @brief Checks whether the register update is enabled.
285 * This function checks whether the WDOG register update is enabled.
287 * @param baseAddr The WDOG peripheral base address
288 * @return false means register update is disabled, true means register update is enabled.
290 static inline bool WDOG_HAL_GetRegisterUpdateCmd(uint32_t baseAddr)
292 return (bool)BR_WDOG_STCTRLH_ALLOWUPDATE(baseAddr);
296 * @brief Sets whether Watchdog is working while the CPU is in debug mode.
298 * This function configures whether the WDOG is enabled in the CPU debug mode.
299 * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
300 * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
301 * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
303 * @param baseAddr The WDOG peripheral base address
304 * @param enable false means watchdog is disabled in CPU debug mode.
305 * true means watchdog is enabled in CPU debug mode.
307 static inline void WDOG_HAL_SetWorkInDebugModeCmd(uint32_t baseAddr, bool enable)
309 BW_WDOG_STCTRLH_DBGEN(baseAddr, (uint8_t)enable);
313 * @brief Checks whether the WDOG works while in the CPU debug mode.
315 * This function checks whether the WDOG works in the CPU debug mode.
317 * @param baseAddr The WDOG peripheral base address
318 * @return false means not work while in CPU debug mode, true means works while in CPU debug mode.
320 static inline bool WDOG_HAL_GetWorkInDebugModeCmd(uint32_t baseAddr)
322 return (bool)BR_WDOG_STCTRLH_DBGEN(baseAddr);
326 * @brief Sets whether the Watchdog is working while the CPU is in stop mode.
328 * This function configures whether the WDOG is enabled in the CPU stop mode.
329 * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
330 * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
331 * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
333 * @param baseAddr The WDOG peripheral base address
334 * @param enable false means watchdog is disabled in CPU stop mode.
335 * true means watchdog is enabled in CPU stop mode.
337 static inline void WDOG_HAL_SetWorkInStopModeCmd(uint32_t baseAddr, bool enable)
339 BW_WDOG_STCTRLH_STOPEN(baseAddr, (uint8_t)enable);
343 * @brief Checks whether the WDOG works while in CPU stop mode.
345 * This function checks whether the WDOG works in the CPU stop mode.
346 * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
347 * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
348 * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
350 * @param baseAddr The WDOG peripheral base address
351 * @return false means not work while in CPU stop mode, true means works while in CPU stop mode.
353 static inline bool WDOG_HAL_GetWorkInStopModeCmd(uint32_t baseAddr)
355 return (bool)BR_WDOG_STCTRLH_STOPEN(baseAddr);
359 * @brief Sets whether the Watchdog is working while the CPU is in wait mode.
361 * This function configures whether the WDOG is enabled in the CPU wait mode.
362 * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that
363 * the WDOG_STCTRLH register has not been written in this WCT while this function is called.
364 * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
366 * @param baseAddr The WDOG peripheral base address
367 * @param enable false means watchdog is disabled in CPU wait mode.
368 * true means watchdog is enabled in CPU wait mode.
370 static inline void WDOG_HAL_SetWorkInWaitModeCmd(uint32_t baseAddr, bool enable)
372 BW_WDOG_STCTRLH_WAITEN(baseAddr, (uint8_t)enable);
376 * @brief Checks whether the WDOG works while in the CPU wait mode.
378 * This function checks whether the WDOG works in the CPU wait mode.
380 * @param baseAddr The WDOG peripheral base address
381 * @return false means not work while in CPU wait mode, true means works while in CPU wait mode.
384 static inline bool WDOG_HAL_GetWorkInWaitModeCmd(uint32_t baseAddr)
386 return (bool)BR_WDOG_STCTRLH_WAITEN(baseAddr);
390 * @brief Gets the Watchdog interrupt status.
392 * This function gets the WDOG interrupt flag.
394 * @param baseAddr The WDOG peripheral base address
395 * @return Watchdog interrupt status, false means interrupt not asserted, true means interrupt asserted.
397 static inline bool WDOG_HAL_IsIntPending(uint32_t baseAddr)
399 return (bool)BR_WDOG_STCTRLL_INTFLG(baseAddr);
403 * @brief Clears the Watchdog interrupt flag.
405 * This function clears the WDOG interrupt flag.
407 * @param baseAddr The WDOG peripheral base address
409 static inline void WDOG_HAL_ClearIntFlag(uint32_t baseAddr)
411 BW_WDOG_STCTRLL_INTFLG(baseAddr, true);
415 * @brief Set the Watchdog timeout value.
417 * This function sets the WDOG_TOVAL value.
418 * It should be ensured that the time-out value for the Watchdog is always greater than
419 * 2xWCT time + 20 bus clock cycles.
420 * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock , that the WCT window is still open and that
421 * this API has not been called in this WCT while this function is called.
422 * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
424 * @param baseAddr The WDOG peripheral base address
425 * @param timeoutCount watchdog timeout value, count of watchdog clock tick.
427 static inline void WDOG_HAL_SetTimeoutValue(uint32_t baseAddr, uint32_t timeoutCount)
429 HW_WDOG_TOVALH_WR(baseAddr, (uint16_t)((timeoutCount >> 16U) & 0xFFFFU));
430 HW_WDOG_TOVALL_WR(baseAddr, (uint16_t)((timeoutCount) & 0xFFFFU));
434 * @brief Gets the Watchdog timeout value.
436 * This function gets the WDOG_TOVAL value.
438 * @param baseAddr The WDOG peripheral base address
439 * @return value of register WDOG_TOVAL.
441 static inline uint32_t WDOG_HAL_GetTimeoutValue(uint32_t baseAddr)
443 return (uint32_t)((((uint32_t)(HW_WDOG_TOVALH_RD(baseAddr))) << 16U) | (HW_WDOG_TOVALL_RD(baseAddr)));
447 * @brief Gets the Watchdog timer output.
449 * This function gets the WDOG_TMROUT value.
451 * @param baseAddr The WDOG peripheral base address
452 * @return Current value of watchdog timer counter.
454 static inline uint32_t WDOG_HAL_GetTimerOutputValue(uint32_t baseAddr)
456 return (uint32_t)((((uint32_t)(HW_WDOG_TMROUTH_RD(baseAddr))) << 16U) | (HW_WDOG_TMROUTL_RD(baseAddr)));
460 * @brief Sets the Watchdog clock prescaler.
462 * This function sets the WDOG clock prescaler.
463 * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock , that the WCT window is still open and that
464 * this API has not been called in this WCT while this function is called.
465 * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
467 * @param baseAddr The WDOG peripheral base address
468 * @param clockPrescaler watchdog clock prescaler, see #wdog_clock_prescaler_value_t.
470 static inline void WDOG_HAL_SetClockPrescalerValueMode(uint32_t baseAddr, wdog_clock_prescaler_value_t clockPrescaler)
472 BW_WDOG_PRESC_PRESCVAL(baseAddr, (uint8_t)clockPrescaler);
476 * @brief Gets the Watchdog clock prescaler.
478 * This function gets the WDOG clock prescaler.
480 * @param baseAddr The WDOG peripheral base address
481 * @return WDOG clock prescaler, see #wdog_clock_prescaler_value_t.
483 static inline wdog_clock_prescaler_value_t WDOG_HAL_GetClockPrescalerValueMode(uint32_t baseAddr)
485 return (wdog_clock_prescaler_value_t)BR_WDOG_PRESC_PRESCVAL(baseAddr);
489 * @brief Sets the Watchdog window value.
491 * This function sets the WDOG_WIN value.
492 * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock , that the WCT window is still open and that
493 * this API has not been called in this WCT while this function is called.
494 * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled.
496 * @param baseAddr The WDOG peripheral base address
497 * @param windowValue watchdog window value.
499 static inline void WDOG_HAL_SetWindowValue(uint32_t baseAddr, uint32_t windowValue)
501 HW_WDOG_WINH_WR(baseAddr, (uint16_t)((windowValue>>16U) & 0xFFFFU));
502 HW_WDOG_WINL_WR(baseAddr, (uint16_t)((windowValue) & 0xFFFFU));
506 * @brief Gets the Watchdog window value.
508 * This function gets the WDOG_WIN value.
510 * @param baseAddr The WDOG peripheral base address
511 * @return watchdog window value.
513 static inline uint32_t WDOG_HAL_GetWindowValue(uint32_t baseAddr)
515 return (uint32_t)((((uint32_t)(HW_WDOG_WINH_RD(baseAddr))) << 16U) | (HW_WDOG_WINL_RD(baseAddr)));
519 * @brief Unlocks the Watchdog register written.
521 * This function unlocks the WDOG register written.
522 * This function must be called before any configuration is set because watchdog register
523 * will be locked automatically after a WCT(256 bus cycles).
525 * @param baseAddr The WDOG peripheral base address
527 static inline void WDOG_HAL_Unlock(uint32_t baseAddr)
529 HW_WDOG_UNLOCK_WR(baseAddr, WDOG_UNLOCK_VALUE_HIGH);
530 HW_WDOG_UNLOCK_WR(baseAddr, WDOG_UNLOCK_VALUE_LOW);
534 * @brief Refreshes the Watchdog timer.
536 * This function feeds the WDOG.
537 * This function should be called before watchdog timer is in timeout. Otherwise, a reset is asserted.
539 * @param baseAddr The WDOG peripheral base address
541 static inline void WDOG_HAL_Refresh(uint32_t baseAddr)
543 HW_WDOG_REFRESH_WR(baseAddr, WDOG_REFRESH_VALUE_HIGH);
544 HW_WDOG_REFRESH_WR(baseAddr, WDOG_REFRESH_VALUE_LOW);
548 * @brief Resets the chip using the Watchdog.
550 * This function resets the chip using WDOG.
552 * @param baseAddr The WDOG peripheral base address
554 static inline void WDOG_HAL_ResetSystem(uint32_t baseAddr)
556 HW_WDOG_REFRESH_WR(baseAddr, WDOG_REFRESH_VALUE_HIGH);
557 HW_WDOG_REFRESH_WR(baseAddr, 0);
564 * @brief Gets the chip reset count that was reset by Watchdog.
566 * This function gets the value of the WDOG_RSTCNT.
568 * @param baseAddr The WDOG peripheral base address
569 * @return Chip reset count that was reset by Watchdog.
571 static inline uint32_t WDOG_HAL_GetResetCount(uint32_t baseAddr)
573 return HW_WDOG_RSTCNT_RD(baseAddr);
577 * @brief Clears the chip reset count that was reset by Watchdog.
579 * This function clears the WDOG_RSTCNT.
581 * @param baseAddr The WDOG peripheral base address
583 static inline void WDOG_HAL_ClearResetCount(uint32_t baseAddr)
585 HW_WDOG_RSTCNT_WR(baseAddr, 0xFFFFU);
589 * @brief Restores the WDOG module to reset value.
591 * This function restores the WDOG module to reset value.
593 * @param baseAddr The WDOG peripheral base address
595 void WDOG_HAL_Init(uint32_t baseAddr);
599 #if defined(__cplusplus)
605 #endif /* __FSL_WDOG_HAL_H__*/
606 /*******************************************************************************
608 *******************************************************************************/