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30 #if !defined(__FSL_RTC_HAL_H__)
31 #define __FSL_RTC_HAL_H__
36 #include "fsl_rtc_features.h"
37 #include "fsl_device_registers.h"
44 /*******************************************************************************
46 ******************************************************************************/
49 * @brief Structure is used to hold the time in a simple "date" format.
51 typedef struct RtcDatetime
53 uint16_t year; /*!< Range from 1970 to 2099.*/
54 uint16_t month; /*!< Range from 1 to 12.*/
55 uint16_t day; /*!< Range from 1 to 31 (depending on month).*/
56 uint16_t hour; /*!< Range from 0 to 23.*/
57 uint16_t minute; /*!< Range from 0 to 59.*/
58 uint8_t second; /*!< Range from 0 to 59.*/
61 /*******************************************************************************
63 ******************************************************************************/
65 #if defined(__cplusplus)
70 * @name RTC HAL API Functions
75 * @brief Initializes the RTC module.
77 * This function enables the RTC oscillator.
79 * @param rtcBaseAddr The RTC base address.
81 void RTC_HAL_Enable(uint32_t rtcBaseAddr);
84 * @brief Disables the RTC module.
86 * This function disablesS the RTC counter and oscillator.
88 * @param rtcBaseAddr The RTC base address.
90 void RTC_HAL_Disable(uint32_t rtcBaseAddr);
93 * @brief Resets the RTC module.
95 * This function initiates a soft-reset of the RTC module to reset
98 * @param rtcBaseAddr The RTC base address..
100 void RTC_HAL_Init(uint32_t rtcBaseAddr);
103 * @brief Converts seconds to date time format data structure.
105 * @param seconds holds the date and time information in seconds
106 * @param datetime holds the converted information from seconds in date and time format
108 void RTC_HAL_ConvertSecsToDatetime(const uint32_t * seconds, rtc_datetime_t * datetime);
111 * @brief Checks whether the date time structure elements have the information that is within the range.
113 * @param datetime holds the date and time information that needs to be converted to seconds
115 bool RTC_HAL_IsDatetimeCorrectFormat(const rtc_datetime_t * datetime);
118 * @brief Converts the date time format data structure to seconds.
120 * @param datetime holds the date and time information that needs to be converted to seconds
121 * @param seconds holds the converted date and time in seconds
123 void RTC_HAL_ConvertDatetimeToSecs(const rtc_datetime_t * datetime, uint32_t * seconds);
126 * @brief Sets the RTC date and time according to the given time structure.
128 * The function converts the data from the time structure to seconds and writes the seconds
129 * value to the RTC register. The RTC counter is started after setting the time.
131 * @param rtcBaseAddr The RTC base address
132 * @param datetime [in] Pointer to structure where the date and time
133 * details to set are stored.
135 void RTC_HAL_SetDatetime(uint32_t rtcBaseAddr, const rtc_datetime_t * datetime);
138 * @brief Sets the RTC date and time according to the given time provided in seconds.
140 * The RTC counter is started after setting the time.
142 * @param rtcBaseAddr The RTC base address
143 * @param seconds [in] Time in seconds
145 void RTC_HAL_SetDatetimeInsecs(uint32_t rtcBaseAddr, const uint32_t seconds);
148 * @brief Gets the RTC time and stores it in the given time structure.
150 * The function reads the value in seconds from the RTC register. It then converts to the
151 * time structure which provides the time in date, hour, minutes and seconds.
153 * @param rtcBaseAddr The RTC base address
154 * @param datetime [out] pointer to a structure where the date and time details are
157 void RTC_HAL_GetDatetime(uint32_t rtcBaseAddr, rtc_datetime_t * datetime);
160 * @brief Gets the RTC time and returns it in seconds.
162 * @param rtcBaseAddr The RTC base address
163 * @param datetime [out] pointer to variable where the RTC time is stored in seconds
165 void RTC_HAL_GetDatetimeInSecs(uint32_t rtcBaseAddr, uint32_t * seconds);
168 * @brief Reads the value of the time alarm.
170 * @param rtcBaseAddr The RTC base address
171 * @param date [out] pointer to a variable where the alarm date and time
172 * details are stored.
174 void RTC_HAL_GetAlarm(uint32_t rtcBaseAddr, rtc_datetime_t * date);
177 * @brief Sets the RTC alarm time and enables the alarm interrupt.
179 * The function checks whether the specified alarm time is greater than the present
180 * time. If not, the function does not set the alarm and returns an error.
182 * @param rtcBaseAddr The RTC base address..
183 * @param date [in] pointer to structure where the alarm date and time
184 * details will be stored at.
185 * @return true: success in setting the RTC alarm\n
186 * false: error in setting the RTC alarm.
188 bool RTC_HAL_SetAlarm(uint32_t rtcBaseAddr, const rtc_datetime_t * date);
190 #if FSL_FEATURE_RTC_HAS_MONOTONIC
191 /*-------------------------------------------------------------------------------------------*/
192 /* RTC Monotonic Counter*/
193 /*-------------------------------------------------------------------------------------------*/
196 * @brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns
197 * them as a single value.
199 * @param rtcBaseAddr The RTC base address
200 * @param counter [out] pointer to variable where the value is stored.
202 void RTC_HAL_GetMonotonicCounter(uint32_t rtcBaseAddr, uint64_t * counter);
205 * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing
206 * the given single value.
208 * @param rtcBaseAddr The RTC base address
209 * @param counter [in] pointer to variable where the value is stored.
211 void RTC_HAL_SetMonotonicCounter(uint32_t rtcBaseAddr, const uint64_t * counter);
214 * @brief Increments the Monotonic Counter by one.
216 * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting
217 * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the
218 * monotonic counter low that causes it to overflow also increments the monotonic counter high.
220 * @param rtcBaseAddr The RTC base address
222 * @return true: success\n
223 * false: error occurred, either time invalid or monotonic overflow flag was found
225 bool RTC_HAL_IncrementMonotonicCounter(uint32_t rtcBaseAddr);
230 * @name RTC register access functions
235 * @brief Reads the value of the time seconds counter.
237 * The time counter reads as zero if either the SR[TOF] or the SR[TIF] is set.
239 * @param rtcBaseAddr The RTC base address..
241 * @return contents of the seconds register.
243 static inline uint32_t RTC_HAL_GetSecsReg(uint32_t rtcBaseAddr)
245 return BR_RTC_TSR_TSR(rtcBaseAddr);
249 * @brief Writes to the time seconds counter.
251 * When the time counter is enabled, the TSR is read only and increments
252 * once every second provided the SR[TOF] or SR[TIF] is not set. When the time counter
253 * is disabled, the TSR can be read or written. Writing to the TSR when the
254 * time counter is disabled clears the SR[TOF] and/or the SR[TIF]. Writing
255 * to the TSR register with zero is supported, but not recommended, since the TSR
256 * reads as zero when either the SR[TIF] or the SR[TOF] is set (indicating the time is
259 * @param rtcBaseAddr The RTC base address..
260 * @param seconds [in] seconds value.
263 static inline void RTC_HAL_SetSecsReg(uint32_t rtcBaseAddr, const uint32_t seconds)
265 HW_RTC_TPR_WR(rtcBaseAddr, (uint32_t)0x00000000U);
266 BW_RTC_TSR_TSR(rtcBaseAddr, seconds);
270 * @brief Sets the time alarm and clears the time alarm flag.
272 * When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR]
273 * equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR
274 * clears the SR[TAF].
276 * @param rtcBaseAddr The RTC base address..
277 * @param seconds [in] alarm value in seconds.
279 static inline void RTC_HAL_SetAlarmReg(uint32_t rtcBaseAddr, const uint32_t seconds)
281 BW_RTC_TAR_TAR(rtcBaseAddr, seconds);
285 * @brief Gets the time alarm register contents.
287 * @param rtcBaseAddr The RTC base address
289 * @return contents of the alarm register.
291 static inline uint32_t RTC_HAL_GetAlarmReg(uint32_t rtcBaseAddr)
293 return BR_RTC_TAR_TAR(rtcBaseAddr);
298 * @brief Reads the value of the time prescaler.
300 * The time counter reads as zero when either the SR[TOF] or the SR[TIF] is set.
302 * @param rtcBaseAddr The RTC base address
304 * @return contents of the time prescaler register.
306 static inline uint16_t RTC_HAL_GetPrescaler(uint32_t rtcBaseAddr)
308 return BR_RTC_TPR_TPR(rtcBaseAddr);
312 * @brief Sets the time prescaler.
314 * When the time counter is enabled, the TPR is read only and increments
315 * every 32.768 kHz clock cycle. When the time counter is disabled, the TPR
316 * can be read or written. The TSR[TSR] increments when bit 14 of the TPR
317 * transitions from a logic one to a logic zero.
319 * @param rtcBaseAddr The RTC base address
320 * @param prescale Prescaler value
322 static inline void RTC_HAL_SetPrescaler(uint32_t rtcBaseAddr, const uint16_t prescale)
324 BW_RTC_TPR_TPR(rtcBaseAddr, prescale);
327 /*-------------------------------------------------------------------------------------------*/
328 /* RTC Time Compensation*/
329 /*-------------------------------------------------------------------------------------------*/
332 * @brief Reads the time compensation register contents.
334 * @param rtcBaseAddr The RTC base address
336 * @return time compensation register contents.
338 static inline uint32_t RTC_HAL_GetCompensationReg(uint32_t rtcBaseAddr)
340 return HW_RTC_TCR_RD(rtcBaseAddr);
344 * @brief Writes the value to the RTC TCR register.
346 * @param rtcBaseAddr The RTC base address
347 * @param compValue value to be written to the compensation register.
349 static inline void RTC_HAL_SetCompensationReg(uint32_t rtcBaseAddr, const uint32_t compValue)
351 HW_RTC_TCR_WR(rtcBaseAddr, compValue);
355 * @brief Reads the current value of the compensation interval counter, which is the field CIC in the RTC TCR register.
357 * @param rtcBaseAddr The RTC base address..
359 * @return compensation interval value.
361 static inline uint8_t RTC_HAL_GetCompensationIntervalCounter(uint32_t rtcBaseAddr)
363 return BR_RTC_TCR_CIC(rtcBaseAddr);
367 * @brief Reads the current value used by the compensation logic for the present second interval.
369 * @param rtcBaseAddr The RTC base address
371 * @return time compensation value
373 static inline uint8_t RTC_HAL_GetTimeCompensationValue(uint32_t rtcBaseAddr)
375 return BR_RTC_TCR_TCV(rtcBaseAddr);
379 * @brief Reads the compensation interval register.
381 * The value is the configured compensation interval in seconds from 1 to 256 to control
382 * how frequently the time compensation register should adjust the
383 * number of 32.768 kHz cycles in each second. The value is one
384 * less than the number of seconds (for example, zero means a
385 * configuration for a compensation interval of one second).
387 * @param rtcBaseAddr The RTC base address..
389 * @return compensation interval in seconds.
391 static inline uint8_t RTC_HAL_GetCompensationIntervalRegister(uint32_t rtcBaseAddr)
393 return BR_RTC_TCR_CIR(rtcBaseAddr);
397 * @brief Writes the compensation interval.
399 * This configures the compensation interval in seconds from 1 to 256 to control
400 * how frequently the TCR should adjust the number of 32.768 kHz
401 * cycles in each second. The value written should be one less than
402 * the number of seconds (for example, write zero to configure for
403 * a compensation interval of one second). This register is double
404 * buffered and writes do not take affect until the end of the
405 * current compensation interval.
407 * @param rtcBaseAddr The RTC base address..
408 * @param value the compensation interval value.
410 static inline void RTC_HAL_SetCompensationIntervalRegister(uint32_t rtcBaseAddr, const uint8_t value)
412 BW_RTC_TCR_CIR(rtcBaseAddr, value);
416 * @brief Reads the time compensation value which is the configured number
417 * of 32.768 kHz clock cycles in each second.
419 * @param rtcBaseAddr The RTC base address
421 * @return time compensation value.
423 static inline uint8_t RTC_HAL_GetTimeCompensationRegister(uint32_t rtcBaseAddr)
425 return BR_RTC_TCR_TCR(rtcBaseAddr);
429 * @brief Writes to the field Time Compensation Register (TCR) of the RTC Time Compensation Register (RTC_TCR).
431 * Configures the number of 32.768 kHz clock cycles in each second. This register is double
432 * buffered and writes do not take affect until the end of the
433 * current compensation interval.
434 * 80h Time prescaler register overflows every 32896 clock cycles.
436 * FFh Time prescaler register overflows every 32769 clock cycles.\n
437 * 00h Time prescaler register overflows every 32768 clock cycles.\n
438 * 01h Time prescaler register overflows every 32767 clock cycles.\n
440 * 7Fh Time prescaler register overflows every 32641 clock cycles.\n
442 * @param rtcBaseAddr The RTC base address
443 * @param comp_value value of the time compensation.
445 static inline void RTC_HAL_SetTimeCompensationRegister(uint32_t rtcBaseAddr, const uint8_t compValue)
447 BW_RTC_TCR_TCR(rtcBaseAddr, compValue);
450 /*-------------------------------------------------------------------------------------------*/
452 /*-------------------------------------------------------------------------------------------*/
455 * @brief Enables/disables the oscillator configuration for the 2pF load.
457 * @param rtcBaseAddr The RTC base address
458 * @param enable can be true or false\n
459 * true: enables load\n
460 * false: disables load.
462 static inline void RTC_HAL_SetOsc2pfLoadCmd(uint32_t rtcBaseAddr, bool enable)
464 BW_RTC_CR_SC2P(rtcBaseAddr, enable);
468 * @brief Reads the oscillator 2pF load configure bit.
470 * @param rtcBaseAddr The RTC base address
472 * @return true: 2pF additional load enabled.\n
473 * false: 2pF additional load disabled.
475 static inline bool RTC_HAL_GetOsc2pfLoad(uint32_t rtcBaseAddr)
477 return (bool)BR_RTC_CR_SC2P(rtcBaseAddr);
481 * @brief Enables/disables the oscillator configuration for the 4pF load.
483 * @param rtcBaseAddr The RTC base address
484 * @param enable can be true or false\n
485 * true: enables load.\n
486 * false: disables load
488 static inline void RTC_HAL_SetOsc4pfLoadCmd(uint32_t rtcBaseAddr, bool enable)
490 BW_RTC_CR_SC4P(rtcBaseAddr, enable);
494 * @brief Reads the oscillator 4pF load configure bit.
496 * @param rtcBaseAddr The RTC base address
498 * @return true: 4pF additional load enabled.\n
499 * false: 4pF additional load disabled.
501 static inline bool RTC_HAL_GetOsc4pfLoad(uint32_t rtcBaseAddr)
503 return (bool)BR_RTC_CR_SC4P(rtcBaseAddr);
507 * @brief Enables/disables the oscillator configuration for the 8pF load.
509 * @param rtcBaseAddr The RTC base address
510 * @param enable can be true or false\n
511 * true: enables load.\n
512 * false: disables load.
514 static inline void RTC_HAL_SetOsc8pfLoadCmd(uint32_t rtcBaseAddr, bool enable)
516 BW_RTC_CR_SC8P(rtcBaseAddr, enable);
520 * @brief Reads the oscillator 8pF load configure bit.
522 * @param rtcBaseAddr The RTC base address
524 * @return true: 8pF additional load enabled.\n
525 * false: 8pF additional load disabled.
527 static inline bool RTC_HAL_GetOsc8pfLoad(uint32_t rtcBaseAddr)
529 return (bool)BR_RTC_CR_SC8P(rtcBaseAddr);
533 * @brief Enables/disables the oscillator configuration for the 16pF load.
535 * @param rtcBaseAddr The RTC base address
536 * @param enable can be true or false\n
537 * true: enables load.\n
538 * false: disables load.
540 static inline void RTC_HAL_SetOsc16pfLoadCmd(uint32_t rtcBaseAddr, bool enable)
542 BW_RTC_CR_SC16P(rtcBaseAddr, enable);
546 * @brief Reads the oscillator 16pF load configure bit.
548 * @param rtcBaseAddr The RTC base address
550 * @return true: 16pF additional load enabled.\n
551 * false: 16pF additional load disabled.
553 static inline bool RTC_HAL_GetOsc16pfLoad(uint32_t rtcBaseAddr)
555 return (bool)BR_RTC_CR_SC16P(rtcBaseAddr);
559 * @brief Enables/disables the 32 kHz clock output to other peripherals.
561 * @param rtcBaseAddr The RTC base address
562 * @param enable can be true or false\n
563 * true: enables clock out.\n
564 * false: disables clock out.
566 static inline void RTC_HAL_SetClockOutCmd(uint32_t rtcBaseAddr, bool enable)
568 BW_RTC_CR_CLKO(rtcBaseAddr, !enable);
572 * @brief Reads the RTC_CR CLKO bit.
574 * @param rtcBaseAddr The RTC base address
576 * @return true: 32 kHz clock is not output to other peripherals.\n
577 * false: 32 kHz clock is output to other peripherals.
579 static inline bool RTC_HAL_GetClockOutCmd(uint32_t rtcBaseAddr)
581 return (bool)BR_RTC_CR_CLKO(rtcBaseAddr);
585 * @brief Enables/disables the oscillator.
587 * After enabling, waits for the oscillator startup time before enabling the
588 * time counter to allow the 32.768 kHz clock time to stabilize.
590 * @param rtcBaseAddr The RTC base address
591 * @param enable can be true or false\n
592 * true: enables oscillator.\n
593 * false: disables oscillator.
595 static inline void RTC_HAL_SetOscillatorCmd(uint32_t rtcBaseAddr, bool enable)
597 BW_RTC_CR_OSCE(rtcBaseAddr, enable);
598 /* TODO: Wait for oscillator startup period if enabling the oscillator
605 * @brief Reads the RTC_CR OSCE bit.
607 * @param rtcBaseAddr The RTC base address
609 * @return true: 32.768 kHz oscillator is enabled
610 * false: 32.768 kHz oscillator is disabled.
612 static inline bool RTC_HAL_IsOscillatorEnabled(uint32_t rtcBaseAddr)
614 return (bool)BR_RTC_CR_OSCE(rtcBaseAddr);
618 * @brief Enables/disables the update mode.
620 * This mode allows the time counter enable bit in the SR to be written
621 * even when the status register is locked.
622 * When set, the time counter enable, can always be written if the
623 * TIF (Time Invalid Flag) or TOF (Time Overflow Flag) are set or
624 * if the time counter enable is clear. For devices with the
625 * monotonic counter it allows the monotonic enable to be written
626 * when it is locked. When set, the monotonic enable can always be
627 * written if the TIF (Time Invalid Flag) or TOF (Time Overflow Flag)
628 * are set or if the montonic counter enable is clear.
629 * For devices with tamper detect it allows the it to be written
630 * when it is locked. When set, the tamper detect can always be
631 * written if the TIF (Time Invalid Flag) is clear.
632 * Note: Tamper and Monotonic features are not available in all MCUs.
634 * @param rtcBaseAddr The RTC base address
635 * @param lock can be true or false\n
636 * true: registers can be written when locked under limited conditions\n
637 * false: registers cannot be written when locked
639 static inline void RTC_HAL_SetUpdateModeCmd(uint32_t rtcBaseAddr, bool lock)
641 BW_RTC_CR_UM(rtcBaseAddr, lock);
645 * @brief Reads the RTC_CR update mode bit.
647 * @param rtcBaseAddr The RTC base address
649 * @return true: Registers can be written when locked under limited conditions.
650 * false: Registers cannot be written when locked.
652 static inline bool RTC_HAL_GetUpdateMode(uint32_t rtcBaseAddr)
654 return (bool)BR_RTC_CR_UM(rtcBaseAddr);
658 * @brief Enables/disables the supervisor access.
660 * This configures non-supervisor mode write access to all RTC registers and
661 * non-supervisor mode read access to RTC tamper/monotonic registers.
662 * Note: Tamper and Monotonic features are NOT available in all MCUs.
664 * @param rtcBaseAddr The RTC base address..
665 * @param enableRegWrite can be true or false\n
666 * true: non-supervisor mode write accesses are supported.\n
667 * false: non-supervisor mode write accesses are not supported and generate a bus error.
669 static inline void RTC_HAL_SetSupervisorAccessCmd(uint32_t rtcBaseAddr, bool enableRegWrite)
671 BW_RTC_CR_SUP(rtcBaseAddr, enableRegWrite);
675 * @brief Reads the RTC_CR SUP bit.
677 * @param rtcBaseAddr The RTC base address
679 * @return true: Non-supervisor mode write accesses are supported
680 * false: Non-supervisor mode write accesses are not supported.
682 static inline bool RTC_HAL_GetSupervisorAccess(uint32_t rtcBaseAddr)
684 return (bool)BR_RTC_CR_SUP(rtcBaseAddr);
687 #if FSL_FEATURE_RTC_HAS_WAKEUP_PIN
689 * @brief Enables/disables the wakeup pin.
691 * Note: The wakeup pin is optional and not available on all devices.
693 * @param rtcBaseAddr The RTC base address
694 * @param enable_wp can be true or false\n
695 * true: enables wakeup-pin, wakeup pin asserts if the
696 * RTC interrupt asserts and the chip is powered down.\n
697 * false: disables wakeup-pin.
699 static inline void RTC_HAL_SetWakeupPinCmd(uint32_t rtcBaseAddr, bool enableWp)
701 BW_RTC_CR_WPE(rtcBaseAddr, enableWp);
705 * @brief Reads the RTC_CR WPE bit.
707 * @param rtcBaseAddr The RTC base address
709 * @return true: Wakeup pin is enabled.
710 * false: Wakeup pin is disabled.
712 static inline bool RTC_HAL_GetWakeupPin(uint32_t rtcBaseAddr)
714 return (bool)BR_RTC_CR_WPE(rtcBaseAddr);
719 * @brief Performs a software reset on the RTC module.
721 * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR
722 * registers. The SWR bit is cleared after VBAT POR and by software
723 * explicitly clearing it.
724 * Note: access control features (RTC_WAR and RTC_RAR registers)
725 * are not available in all MCUs.
727 * @param rtcBaseAddr The RTC base address
729 static inline void RTC_HAL_SoftwareReset(uint32_t rtcBaseAddr)
731 BW_RTC_CR_SWR(rtcBaseAddr, 1u);
735 * @brief Clears the software reset flag.
737 * @param rtcBaseAddr The RTC base address
739 static inline void RTC_HAL_SoftwareResetFlagClear(uint32_t rtcBaseAddr)
741 BW_RTC_CR_SWR(rtcBaseAddr, 0u);
745 * @brief Reads the RTC_CR SWR bit.
747 * @param rtcBaseAddr The RTC base address
749 * @return true: SWR is set.
750 * false: SWR is cleared.
752 static inline bool RTC_HAL_ReadSoftwareResetStatus(uint32_t rtcBaseAddr)
754 return (bool)BR_RTC_CR_SWR(rtcBaseAddr);
757 /*-------------------------------------------------------------------------------------------*/
759 /*-------------------------------------------------------------------------------------------*/
762 * @brief Reads the time counter status (enabled/disabled).
764 * @param rtcBaseAddr The RTC base address
766 * @return true: time counter is enabled, time seconds register and time
767 * prescaler register are not writeable, but increment.\n
768 * false: time counter is disabled, time seconds register and
769 * time prescaler register are writeable, but do not increment.
771 static inline bool RTC_HAL_IsCounterEnabled(uint32_t rtcBaseAddr)
773 return (bool)BR_RTC_SR_TCE(rtcBaseAddr);
777 * @brief Changes the time counter status.
779 * @param rtcBaseAddr The RTC base address
780 * @param enable can be true or false\n
781 * true: enables the time counter\n
782 * false: disables the time counter.
784 static inline void RTC_HAL_EnableCounter(uint32_t rtcBaseAddr, bool enable)
786 BW_RTC_SR_TCE(rtcBaseAddr, enable);
789 #if FSL_FEATURE_RTC_HAS_MONOTONIC
791 * @brief Reads the value of the Monotonic Overflow Flag (MOF).
793 * This flag is set when the monotonic counter is enabled and the monotonic
794 * counter high overflows. The monotonic counter does not increment and
795 * reads as zero when this bit is set. This bit is cleared by writing the monotonic
796 * counter high register when the monotonic counter is disabled.
798 * @param rtcBaseAddr The RTC base address..
800 * @return true: monotonic counter overflow has occurred and monotonic
801 * counter is read as zero.\n
802 * false: No monotonic counter overflow has occurred.
804 static inline bool RTC_HAL_IsMonotonicCounterOverflow(uint32_t rtcBaseAddr)
806 return (bool)BR_RTC_SR_MOF(rtcBaseAddr);
811 * @brief Checks whether the configured time alarm has occurred.
813 * Reads time alarm flag (TAF). This flag is set when the time
814 * alarm register (TAR) equals the time seconds register (TSR) and
815 * the TSR increments. This flag is cleared by writing the TAR register.
817 * @param rtcBaseAddr The RTC base address..
819 * @return true: time alarm has occurred.\n
820 * false: no time alarm occurred.
822 static inline bool RTC_HAL_HasAlarmOccured(uint32_t rtcBaseAddr)
824 return (bool)BR_RTC_SR_TAF(rtcBaseAddr);
828 * @brief Checks whether a counter overflow has occurred.
830 * Reads the value of RTC Status Register (RTC_SR), field Time
831 * Overflow Flag (TOF). This flag is set when the time counter is
832 * enabled and overflows. The TSR and TPR do not increment and read
833 * as zero when this bit is set. This flag is cleared by writing the
834 * TSR register when the time counter is disabled.
836 * @param rtcBaseAddr The RTC base address..
838 * @return true: time overflow occurred and time counter is zero.\n
839 * false: no time overflow occurred.
841 static inline bool RTC_HAL_HasCounterOverflowed(uint32_t rtcBaseAddr)
843 return (bool)BR_RTC_SR_TOF(rtcBaseAddr);
847 * @brief Checks whether the time has been marked as invalid.
849 * Reads the value of RTC Status Register (RTC_SR), field Time
850 * Invalid Flag (TIF). This flag is set on VBAT POR or software
851 * reset. The TSR and TPR do not increment and read as zero when
852 * this bit is set. This flag is cleared by writing the TSR
853 * register when the time counter is disabled.
855 * @param rtcBaseAddr The RTC base address..
857 * @return true: time is INVALID and time counter is zero.\n
858 * false: time is valid.
860 static inline bool RTC_HAL_IsTimeInvalid(uint32_t rtcBaseAddr)
862 return (bool)BR_RTC_SR_TIF(rtcBaseAddr);
865 /*-------------------------------------------------------------------------------------------*/
867 /*-------------------------------------------------------------------------------------------*/
870 * @brief Configures the register lock to other module fields.
872 * @param rtcBaseAddr The RTC base address..
873 * @param bitfields [in] configuration flags:\n
875 * LRL: Lock Register Lock \n
876 * SRL: Status Register Lock \n
877 * CRL: Control Register Lock \n
878 * TCL: Time Compensation Lock \n
880 * For MCUs that have the Tamper Detect only: \n
881 * TIL: Tamper Interrupt Lock \n
882 * TTL: Tamper Trim Lock \n
883 * TDL: Tamper Detect Lock \n
884 * TEL: Tamper Enable Lock \n
885 * TTSL: Tamper Time Seconds Lock \n
887 * For MCUs that have the Monotonic Counter only: \n
888 * MCHL: Monotonic Counter High Lock \n
889 * MCLL: Monotonic Counter Low Lock \n
890 * MEL: Monotonic Enable Lock \n
892 static inline void RTC_HAL_SetLockRegistersCmd(uint32_t rtcBaseAddr, hw_rtc_lr_t bitfields)
894 uint32_t valid_flags = 0;
896 valid_flags |= (BM_RTC_LR_LRL | BM_RTC_LR_SRL | BM_RTC_LR_CRL |
899 #if FSL_FEATURE_RTC_HAS_MONOTONIC
900 valid_flags |= (BM_RTC_LR_MCHL | BM_RTC_LR_MCLL | BM_RTC_LR_MEL);
902 HW_RTC_LR_WR(rtcBaseAddr, (bitfields.U) & valid_flags);
906 * @brief Obtains the lock status of the lock register.
908 * Reads the value of the field Lock Register Lock (LRL) of the RTC Lock Register (RTC_LR).
910 * @param rtcBaseAddr The RTC base address
912 * @return true: lock register is not locked and writes complete as normal.\n
913 * false: lock register is locked and writes are ignored.
915 static inline bool RTC_HAL_GetLockRegLock(uint32_t rtcBaseAddr)
917 return (bool)BR_RTC_LR_LRL(rtcBaseAddr);
921 * @brief Changes the lock status of the lock register.
923 * Writes to the field Lock Register Lock (LRL) of the RTC Lock Register (RTC_LR).
924 * Once cleared, this can only be set by VBAT POR or software reset.
926 * @param rtcBaseAddr The RTC base address
927 * @param lock can be true or false\n
928 * true: Lock register is not locked and writes complete as normal.\n
929 * false: Lock register is locked and writes are ignored.
931 static inline void RTC_HAL_SetLockRegLock(uint32_t rtcBaseAddr, bool lock)
933 BW_RTC_LR_LRL(rtcBaseAddr, (uint32_t) lock);
937 * @brief Obtains the state of the status register lock.
939 * Reads the value of field Status Register Lock (SRL) of the RTC Lock Register (RTC_LR), which is the field Status Register.
941 * @param rtcBaseAddr The RTC base address
943 * @return true: Status register is not locked and writes complete as
945 * false: Status register is locked and writes are ignored.
947 static inline bool RTC_HAL_GetStatusRegLock(uint32_t rtcBaseAddr)
949 return (bool)BR_RTC_LR_SRL(rtcBaseAddr);
953 * @brief Changes the state of the status register lock.
955 * Writes to the field Status Register Lock (SRL) of the RTC Lock Register (RTC_LR).
956 * Once cleared, this can only be set by VBAT POR or software reset.
958 * @param rtcBaseAddr The RTC base address
959 * @param lock can be true or false\n
960 * true: Status register is not locked and writes complete as
962 * false: Status register is locked and writes are ignored.
964 static inline void RTC_HAL_SetStatusRegLock(uint32_t rtcBaseAddr, bool lock)
966 BW_RTC_LR_SRL(rtcBaseAddr, (uint32_t) lock);
970 * @brief Obtains the state of the control register lock.
972 * Reads the field Control Register Lock (CRL)value of the RTC Lock Register (RTC_LR).
974 * @param rtcBaseAddr The RTC base address
976 * @return true: Control register is not locked and writes complete as
978 * false: Control register is locked and writes are ignored.
980 static inline bool RTC_HAL_GetControlRegLock(uint32_t rtcBaseAddr)
982 return (bool)BR_RTC_LR_CRL(rtcBaseAddr);
986 * @brief Changes the state of the control register lock.
988 * Writes to the field Control Register Lock (CRL) of the RTC Lock Register (RTC_LR).
989 * Once cleared, this can only be set by VBAT POR or software reset.
991 * @param rtcBaseAddr The RTC base address
992 * @param lock can be true or false\n
993 * true: Control register is not locked and writes complete
995 * false: Control register is locked and writes are ignored.
997 static inline void RTC_HAL_SetControlRegLock(uint32_t rtcBaseAddr, bool lock)
999 BW_RTC_LR_CRL(rtcBaseAddr, (uint32_t) lock);
1003 * @brief Obtains the state of the time compensation lock.
1005 * Reads the field Time Compensation Lock (TCL) value of the RTC Lock Register (RTC_LR).
1007 * @param rtcBaseAddr The RTC base address
1009 * @return true: Time compensation register is not locked and writes
1010 * complete as normal.\n
1011 * false: Time compensation register is locked and writes are
1014 static inline bool RTC_HAL_GetTimeCompLock(uint32_t rtcBaseAddr)
1016 return (bool)BR_RTC_LR_TCL(rtcBaseAddr);
1020 * @brief Changes the state of the time compensation lock.
1022 * Writes to the field Time Compensation Lock (TCL) of the RTC Lock Register (RTC_LR).
1023 * Once cleared, this can only be set by VBAT POR or software reset.
1025 * @param rtcBaseAddr The RTC base address
1026 * @param lock can be true or false\n
1027 * true: Time compensation register is not locked and writes
1028 * complete as normal.\n
1029 * false: Time compensation register is locked and writes are
1032 static inline void RTC_HAL_SetTimeCompLock(uint32_t rtcBaseAddr, bool lock)
1034 BW_RTC_LR_TCL(rtcBaseAddr, (uint32_t) lock);
1037 #if FSL_FEATURE_RTC_HAS_MONOTONIC
1039 * @brief Reads the value of the Monotonic Counter High Lock.
1041 * @param rtcBaseAddr The RTC base address
1043 * @return true: Monotonic counter high register is not locked and writes
1044 * complete as normal.\n
1045 * false: Monotonic counter high register is locked and writes are
1048 static inline bool RTC_HAL_ReadMonotonicHcounterLock(uint32_t rtcBaseAddr)
1050 return (bool)BR_RTC_LR_MCHL(rtcBaseAddr);
1054 * @brief Writes 0 to the field Monotonic Counter High Lock (MCHL) of the RTC Lock Register (RTC_LR).
1056 * Once done, this flag can only be set by VBAT POR or software reset.
1058 * @param rtcBaseAddr The RTC base address
1060 static inline void RTC_HAL_ClearMonotonicHcounterLock(uint32_t rtcBaseAddr)
1062 BW_RTC_LR_MCHL(rtcBaseAddr, 0U);
1066 * @brief Reads the value of the Monotonic Counter Low Lock.
1068 * @param rtcBaseAddr The RTC base address
1070 * @return true: Monotonic counter low register is not locked and writes
1071 * complete as normal.\n
1072 * false: Monotonic counter low register is locked and writes are
1075 static inline bool RTC_HAL_ReadMonotonicLcounterLock(uint32_t rtcBaseAddr)
1077 return (bool)BR_RTC_LR_MCLL(rtcBaseAddr);
1081 * @brief Writes 0 to the field Monotonic Counter Low Lock (MCLL) of the RTC Lock Register (RTC_LR).
1083 * Once done, this flag can only be set by VBAT POR or software reset.
1085 * @param rtcBaseAddr The RTC base address
1087 static inline void RTC_HAL_ClearMonotonicLcounterLock(uint32_t rtcBaseAddr)
1089 BW_RTC_LR_MCLL(rtcBaseAddr, 0U);
1093 * @brief Reads the value of the Monotonic Enable Lock.
1095 * @param rtcBaseAddr The RTC base address
1097 * @return true: Monotonic enable register is not locked and writes
1098 * complete as normal.\n
1099 * false: Monotonic enable register is locked and writes are
1102 static inline bool RTC_HAL_ReadMonotonicEnableLock(uint32_t rtcBaseAddr)
1104 return (bool)BR_RTC_LR_MEL(rtcBaseAddr);
1108 * @brief Writes 0 to the Monotonic Enable Lock field of the RTC Lock Register (RTC_LR).
1110 * Once done, this flag can only be set by VBAT POR or software reset.
1112 * @param rtcBaseAddr The RTC base address
1114 static inline void RTC_HAL_ClearMonotonicEnableLock(uint32_t rtcBaseAddr)
1116 BW_RTC_LR_MEL(rtcBaseAddr, 0U);
1120 /*-------------------------------------------------------------------------------------------*/
1121 /* RTC Interrupt Enable*/
1122 /*-------------------------------------------------------------------------------------------*/
1125 * @brief Checks whether the Time Seconds Interrupt is enabled/disabled.
1127 * Reads the value of field Time Seconds Interrupt Enable (TSIE)of the RTC Interrupt Enable Register (RTC_IER).
1128 * The seconds interrupt is an edge-sensitive
1129 * interrupt with a dedicated interrupt vector. It is generated once a second
1130 * and requires no software overhead (there is no corresponding status flag to
1133 * @param rtcBaseAddr The RTC base address
1135 * @return true: Seconds interrupt is enabled.\n
1136 * false: Seconds interrupt is disabled.
1138 static inline bool RTC_HAL_IsSecsIntEnabled(uint32_t rtcBaseAddr)
1140 return (bool)BR_RTC_IER_TSIE(rtcBaseAddr);
1144 * @brief Enables/disables the Time Seconds Interrupt.
1146 * Writes to the field Time Seconds
1147 * Interrupt Enable (TSIE) of the RTC Interrupt Enable Register (RTC_IER).
1148 * Note: The seconds interrupt is an edge-sensitive interrupt with a
1149 * dedicated interrupt vector. It is generated once a second and
1150 * requires no software overhead (there is no corresponding status
1153 * @param rtcBaseAddr The RTC base address
1154 * @param enable can be true or false\n
1155 * true: Seconds interrupt is enabled.\n
1156 * false: Seconds interrupt is disabled.
1158 static inline void RTC_HAL_SetSecsIntCmd(uint32_t rtcBaseAddr, bool enable)
1160 BW_RTC_IER_TSIE(rtcBaseAddr, (uint32_t) enable);
1163 #if FSL_FEATURE_RTC_HAS_MONOTONIC
1166 * @brief Checks whether the Monotonic Overflow Interrupt is enabled/disabled.
1168 * Reads the value of the RTC Interrupt Enable Register (RTC_IER), field
1169 * Monotonic Overflow Interrupt Enable (MOIE).
1171 * @param rtcBaseAddr The RTC base address
1173 * @return true: Monotonic overflow flag does generate an interrupt.\n
1174 * false: Monotonic overflow flag does not generate an interrupt.
1176 static inline bool RTC_HAL_ReadMonotonicOverflowInt(uint32_t rtcBaseAddr)
1178 return (bool)BR_RTC_IER_MOIE(rtcBaseAddr);
1182 * @brief Enables/disables the Monotonic Overflow Interrupt Enable.
1184 * @param rtcBaseAddr The RTC base address
1185 * @param enable can be true or false\n
1186 * true: Monotonic overflow flag does generate an interrupt.\n
1187 * false: Monotonic overflow flag does not generate an interrupt.
1189 static inline void RTC_HAL_SetMonotonicOverflowIntCmd(uint32_t rtcBaseAddr, bool enable)
1191 BW_RTC_IER_MOIE(rtcBaseAddr, (uint32_t)enable);
1197 * @brief Checks whether the Time Alarm Interrupt is enabled/disabled.
1199 * Reads the field Time Alarm Interrupt Enable (TAIE) value of the RTC Interrupt Enable Register (RTC_IER).
1201 * @param rtcBaseAddr The RTC base address
1203 * @return true: Time alarm flag does generate an interrupt.\n
1204 * false: Time alarm flag does not generate an interrupt.
1206 static inline bool RTC_HAL_ReadAlarmInt(uint32_t rtcBaseAddr)
1208 return (bool)BR_RTC_IER_TAIE(rtcBaseAddr);
1212 * @brief Enables/disables the Time Alarm Interrupt.
1214 * Writes to the field Time Alarm
1215 * Interrupt Enable (TAIE) of the RTC Interrupt Enable Register (RTC_IER).
1217 * @param rtcBaseAddr The RTC base address
1218 * @param enable can be true or false\n
1219 * true: Time alarm flag does generate an interrupt.\n
1220 * false: Time alarm flag does not generate an interrupt.
1222 static inline void RTC_HAL_SetAlarmIntCmd(uint32_t rtcBaseAddr, bool enable)
1224 BW_RTC_IER_TAIE(rtcBaseAddr, (uint32_t) enable);
1228 * @brief Checks whether the Time Overflow Interrupt is enabled/disabled.
1231 * Time Overflow Interrupt Enable (TOIE) of the value of the RTC Interrupt Enable Register (RTC_IER).
1233 * @param rtcBaseAddr The RTC base address..
1235 * @return true: Time overflow flag does generate an interrupt.\n
1236 * false: Time overflow flag does not generate an interrupt.
1238 static inline bool RTC_HAL_ReadTimeOverflowInt(uint32_t rtcBaseAddr)
1240 return (bool)BR_RTC_IER_TOIE(rtcBaseAddr);
1244 * @brief Enables/disables the Time Overflow Interrupt.
1246 * Writes to the field Time Overflow Interrupt Enable (TOIE) of the RTC Interrupt Enable Register (RTC_IER).
1248 * @param rtcBaseAddr The RTC base address
1249 * @param enable can be true or false\n
1250 * true: Time overflow flag does generate an interrupt.\n
1251 * false: Time overflow flag does not generate an interrupt.
1253 static inline void RTC_HAL_SetTimeOverflowIntCmd(uint32_t rtcBaseAddr, bool enable)
1255 BW_RTC_IER_TOIE(rtcBaseAddr, (uint32_t) enable);
1259 * @brief Checks whether the Time Invalid Interrupt is enabled/disabled.
1261 * Reads the value of the field Time
1262 * Invalid Interrupt Enable (TIIE)of the RTC Interrupt Enable Register (RTC_IER).
1264 * @param rtcBaseAddr The RTC base address
1266 * @return true: Time invalid flag does generate an interrupt.\n
1267 * false: Time invalid flag does not generate an interrupt.
1269 static inline bool RTC_HAL_ReadTimeInvalidInt(uint32_t rtcBaseAddr)
1271 return (bool)BR_RTC_IER_TIIE(rtcBaseAddr);
1275 * @brief Enables/disables the Time Invalid Interrupt.
1277 * Writes to the field Time Invalid
1278 * Interrupt Enable (TIIE) of the RTC Interrupt Enable Register (RTC_IER).
1280 * @param rtcBaseAddr The RTC base address
1281 * @param enable can be true or false\n
1282 * true: Time invalid flag does generate an interrupt.\n
1283 * false: Time invalid flag does not generate an interrupt.
1285 static inline void RTC_HAL_SetTimeInvalidIntCmd(uint32_t rtcBaseAddr, bool enable)
1287 BW_RTC_IER_TIIE(rtcBaseAddr, (uint32_t) enable);
1290 #if FSL_FEATURE_RTC_HAS_MONOTONIC
1292 /*-------------------------------------------------------------------------------------------*/
1293 /* RTC Monotonic Enable*/
1294 /*-------------------------------------------------------------------------------------------*/
1297 * @brief Reads the Monotonic Counter Enable bit.
1299 * @param rtcBaseAddr The RTC base address
1301 * @return true: This means writing to the monotonic counter increments the counter by one and
1302 * the value written is ignored.\n
1303 * false: This means writing to the monotonic counter loads the counter with the
1306 static inline bool RTC_HAL_ReadMonotonicEnable(uint32_t rtcBaseAddr)
1308 /* Reads value of the RTC_MER register, field Monotonic Counter Enable (MCE). */
1309 return (bool)BR_RTC_MER_MCE(rtcBaseAddr);
1313 * @brief Changes the state of Monotonic Counter Enable bit.
1315 * @param rtcBaseAddr The RTC base address
1316 * @param enable value to be written to the MER[MCE] bit\n
1317 * true: Set the bit to 1 which means writing to the monotonic counter will increment
1318 * the counter by one and the value written will be ignored.\n
1319 * false: Set the bit to 0 which means writing to the monotonic counter loads the counter
1320 * with the value written.
1322 static inline void RTC_HAL_SetMonotonicEnableCmd(uint32_t rtcBaseAddr, bool enable)
1324 /* Writes to the RTC_MER registers Monotonic Counter Enable (MCE) bit.*/
1325 BW_RTC_MER_MCE(rtcBaseAddr, (uint32_t) enable);
1329 * @brief Reads the values of the Monotonic Counter Low register.
1331 * @param rtcBaseAddr The RTC base address
1333 * @return Monotonic Counter Low value.
1335 static inline uint32_t RTC_HAL_GetMonotonicCounterLow(uint32_t rtcBaseAddr)
1337 return BR_RTC_MCLR_MCL(rtcBaseAddr);
1341 * @brief Reads the values of the Monotonic Counter High register.
1343 * @param rtcBaseAddr The RTC base address
1345 * @return Monotonic Counter High value.
1347 static inline uint32_t RTC_HAL_GetMonotonicCounterHigh(uint32_t rtcBaseAddr)
1349 return BR_RTC_MCHR_MCH(rtcBaseAddr);
1353 * @brief Writes values of the Monotonic Counter Low register.
1355 * @param rtcBaseAddr The RTC base address
1356 * @param counter [in] Monotonic Counter Low value to be stored.
1358 static inline void RTC_HAL_SetMonotonicCounterLow(uint32_t rtcBaseAddr, const uint32_t counter)
1360 /* enable writing to the counter*/
1361 BW_RTC_MER_MCE(rtcBaseAddr, 0U);
1362 BW_RTC_MCLR_MCL(rtcBaseAddr, counter);
1366 * @brief Writes values of the Monotonic Counter High register.
1368 * @param rtcBaseAddr The RTC base address
1369 * @param counter [in] Monotonic Counter High value to be stored.
1371 static inline void RTC_HAL_SetMonotonicCounterHigh(uint32_t rtcBaseAddr, const uint32_t counter)
1373 /* enable writing to the counter*/
1374 BW_RTC_MER_MCE(rtcBaseAddr, 0U);
1375 BW_RTC_MCHR_MCH(rtcBaseAddr, counter);
1378 #endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */
1380 #if FSL_FEATURE_RTC_HAS_ACCESS_CONTROL
1382 #if FSL_FEATURE_RTC_HAS_MONOTONIC
1384 * @brief Reads the field Monotonic Counter High Write (MCHW) value of the register RTC_WAR.
1386 * @param rtcBaseAddr The RTC base address
1388 * @return true: Writes to the monotonic counter high register will complete as normal.\n
1389 * false: Writes to the monotonic counter high register are ignored.
1391 static inline bool RTC_HAL_GetMonotonicHcountWreg(uint32_t rtcBaseAddr)
1393 return (bool)BR_RTC_WAR_MCHW(rtcBaseAddr);
1397 * @brief Writes 0 to the field Monotonic Counter High Write (MCHW) of the RTC_WAR register.
1399 * Once cleared, this bit is only set by system reset. It is not affected by
1400 * VBAT POR or software reset.
1402 * @param rtcBaseAddr The RTC base address
1404 static inline void RTC_HAL_ClearMonotonicHcountWreg(uint32_t rtcBaseAddr)
1406 BW_RTC_WAR_MCHW(rtcBaseAddr, 0U);
1410 * @brief Reads the field Monotonic Counter Low Write (MCLW) value of the register RTC_WAR.
1412 * @param rtcBaseAddr The RTC base address
1414 * @return true: Writes to the monotonic counter low register will complete as normal.\n
1415 * false: Writes to the monotonic counter low register are ignored.
1417 static inline bool RTC_HAL_GetMonotonicLcountWreg(uint32_t rtcBaseAddr)
1419 return (bool)BR_RTC_WAR_MCLW(rtcBaseAddr);
1423 * @brief Writes 0 to the field Monotonic Counter High Write (MCLW) of the RTC_WAR register.
1425 * Once cleared, this bit is only set by the system reset. It is not affected by
1426 * VBAT POR or software reset.
1428 * @param rtcBaseAddr The RTC base address..
1430 static inline void RTC_HAL_ClearMonotonicLcountWreg(uint32_t rtcBaseAddr)
1432 BW_RTC_WAR_MCLW(rtcBaseAddr, 0U);
1436 * @brief Reads the field Monotonic Enable Register Write (MERW) value of the register RTC_WAR.
1438 * @param rtcBaseAddr The RTC base address
1440 * @return true: Writes to the monotonic enable register will complete as normal.\n
1441 * false: Writes to the monotonic enable register are ignored.
1443 static inline bool RTC_HAL_GetMonotonicEnableWreg(uint32_t rtcBaseAddr)
1445 return (bool)BR_RTC_WAR_MERW(rtcBaseAddr);
1449 * @brief Writes 0 to the field Monotonic Counter High Write (MERW) of the RTC_WAR register.
1451 * Once cleared, this bit is only set by system reset. It is not affected by
1452 * VBAT POR or software reset.
1454 * @param rtcBaseAddr The RTC base address
1456 static inline void RTC_HAL_ClearMonotonicEnableWreg(uint32_t rtcBaseAddr)
1458 BW_RTC_WAR_MERW(rtcBaseAddr, 0U);
1463 * @brief Reads the field Interrupt Enable Register Write (IERW) value of the register RTC_WAR.
1465 * @param rtcBaseAddr The RTC base address
1467 * @return true: Writes to the interrupt enable register will complete as normal.\n
1468 * false: Writes to the interrupt enable register are ignored.
1470 static inline bool RTC_HAL_GetIntEnableWreg(uint32_t rtcBaseAddr)
1472 return (bool)BR_RTC_WAR_IERW(rtcBaseAddr);
1476 * @brief Writes 0 to the field Interrupt Enable Register Write (IERW) of the RTC_WAR register.
1478 * Once cleared, this bit is only set by system reset. It is not affected by
1479 * VBAT POR or software reset.
1481 * @param rtcBaseAddr The RTC base address
1483 static inline void RTC_HAL_ClearIntEnableWreg(uint32_t rtcBaseAddr)
1485 BW_RTC_WAR_IERW(rtcBaseAddr, 0U);
1489 * @brief Reads the field Lock Register Write (LRW) value of the register RTC_WAR.
1491 * @param rtcBaseAddr The RTC base address
1493 * @return true: Writes to the lock register will complete as normal.\n
1494 * false: Writes to the lock register are ignored.
1496 static inline bool RTC_HAL_GetLockWreg(uint32_t rtcBaseAddr)
1498 return (bool)BR_RTC_WAR_LRW(rtcBaseAddr);
1502 * @brief Writes 0 to the field Lock Register Write (LRW) of the RTC_WAR register.
1504 * Once cleared, this bit is only set by system reset. It is not affected by
1505 * VBAT POR or software reset.
1507 * @param rtcBaseAddr The RTC base address
1509 static inline void RTC_HAL_ClearLockWreg(uint32_t rtcBaseAddr)
1511 BW_RTC_WAR_LRW(rtcBaseAddr, 0U);
1515 * @brief Reads the field Status Register Write (SRW) value of the register RTC_WAR.
1517 * @param rtcBaseAddr The RTC base address
1519 * @return true: Writes to the status register completes as normal.\n
1520 * false: Writes to the status register are ignored.
1522 static inline bool RTC_HAL_GetStatusWreg(uint32_t rtcBaseAddr)
1524 return (bool)BR_RTC_WAR_SRW(rtcBaseAddr);
1528 * @brief Writes 0 to the field Status Register Write (SRW) of the RTC_WAR register.
1530 * Once cleared, this bit is only set by system reset. It is not affected by
1531 * VBAT POR or software reset.
1533 * @param rtcBaseAddr The RTC base address
1535 static inline void RTC_HAL_ClearStatusWreg(uint32_t rtcBaseAddr)
1537 BW_RTC_WAR_SRW(rtcBaseAddr, 0U);
1541 * @brief Reads the field Control Register Write (CRW) value of the register RTC_WAR.
1543 * @param rtcBaseAddr The RTC base address
1545 * @return true: Writes to the control register will complete as normal.\n
1546 * false: Writes to the control register are ignored.
1548 static inline bool RTC_HAL_GetControlWreg(uint32_t rtcBaseAddr)
1550 return (bool)BR_RTC_WAR_CRW(rtcBaseAddr);
1554 * @brief Writes 0 to the field Control Register Write (CRW) of the RTC_WAR register.
1556 * Once cleared, this bit is only set by system reset. It is not affected by
1557 * VBAT POR or software reset.
1559 * @param rtcBaseAddr The RTC base address
1561 static inline void RTC_HAL_ClearControlWreg(uint32_t rtcBaseAddr)
1563 BW_RTC_WAR_CRW(rtcBaseAddr, 0U);
1567 * @brief Reads the field Time Compensation Register Write (TCRW) value of the register RTC_WAR.
1569 * @param rtcBaseAddr The RTC base address
1571 * @return true: Writes to the time compensation register will complete as normal.\n
1572 * false: Writes to the time compensation register are ignored.
1574 static inline bool RTC_HAL_GetCompensationWreg(uint32_t rtcBaseAddr)
1576 return (bool)BR_RTC_WAR_TCRW(rtcBaseAddr);
1580 * @brief Writes 0 to the field Time Compensation Register Write (TCRW) of the RTC_WAR register.
1582 * Once cleared, this bit is only set by system reset. It is not affected by
1583 * VBAT POR or software reset.
1585 * @param rtcBaseAddr The RTC base address
1587 static inline void RTC_HAL_ClearCompensationWreg(uint32_t rtcBaseAddr)
1589 BW_RTC_WAR_TCRW(rtcBaseAddr, 0U);
1593 * @brief Reads the field Time Alarm Register Write (TARW) value of the register RTC_WAR.
1595 * @param rtcBaseAddr The RTC base address
1597 * @return true: Writes to the time alarm register will complete as normal.\n
1598 * false: Writes to the time alarm register are ignored.
1600 static inline bool RTC_HAL_GetAlarmWreg(uint32_t rtcBaseAddr)
1602 return (bool)BR_RTC_WAR_TARW(rtcBaseAddr);
1606 * @brief Writes 0 to the field Time Alarm Register Write (TARW) of the RTC_WAR register.
1608 * Once cleared, this bit is only set by system reset. It is not affected by
1609 * VBAT POR or software reset.
1611 * @param rtcBaseAddr The RTC base address
1613 static inline void RTC_HAL_ClearAlarmWreg(uint32_t rtcBaseAddr)
1615 BW_RTC_WAR_TARW(rtcBaseAddr, 0U);
1619 * @brief Reads the field Time Prescaler Register Write (TPRW) value of the register RTC_WAR.
1621 * @param rtcBaseAddr The RTC base address
1623 * @return true: Writes to the time prescaler register will complete as normal.\n
1624 * false: Writes to the time prescaler register are ignored.
1626 static inline bool RTC_HAL_GetPrescalerWreg(uint32_t rtcBaseAddr)
1628 return (bool)BR_RTC_WAR_TPRW(rtcBaseAddr);
1632 * @brief Writes 0 to the field Time Prescaler Register Write (TPRW) of the RTC_WAR register.
1634 * Once cleared, this bit is only set by system reset. It is not affected by
1635 * VBAT POR or software reset.
1637 * @param rtcBaseAddr The RTC base address
1639 static inline void RTC_HAL_ClearPrescalerWreg(uint32_t rtcBaseAddr)
1641 BW_RTC_WAR_TPRW(rtcBaseAddr, 0U);
1645 * @brief Reads the field Time Seconds Register Write (TSRW) value of the register RTC_WAR.
1647 * @param rtcBaseAddr The RTC base address
1649 * @return true: Writes to the time seconds register will complete as normal.\n
1650 * false: Writes to the time seconds register are ignored.
1652 static inline bool RTC_HAL_GetSecsWreg(uint32_t rtcBaseAddr)
1654 return (bool)BR_RTC_WAR_TSRW(rtcBaseAddr);
1658 * @brief Writes 0 to the field Time Seconds Register Write (TSRW) of the RTC_WAR register.
1660 * Once cleared, this bit is only set by system reset. It is not affected by
1661 * VBAT POR or software reset.
1663 * @param rtcBaseAddr The RTC base address
1665 static inline void RTC_HAL_ClearSecsWreg(uint32_t rtcBaseAddr)
1667 BW_RTC_WAR_TSRW(rtcBaseAddr, 0U);
1670 #if FSL_FEATURE_RTC_HAS_MONOTONIC
1673 * @brief Reads the field Monotonic Counter High Read (MCHR) value of the register RTC_RAR.
1675 * @param rtcBaseAddr The RTC base address
1677 * @return true: Reads to the monotonic counter high register completes as normal.\n
1678 * false: Reads to the monotonic counter high register are ignored.
1680 static inline bool RTC_HAL_GetMonotonicHcountRreg(uint32_t rtcBaseAddr)
1682 return (bool)BR_RTC_RAR_MCHR(rtcBaseAddr);
1686 * @brief Writes 0 to the field Monotonic Counter High Read (MCHR) of the RTC_RAR register.
1688 * Once cleared, this bit is only set by system reset. It is not affected by
1689 * VBAT POR or software reset.
1691 * @param rtcBaseAddr The RTC base address
1693 static inline void RTC_HAL_ClearMonotonicHcountRreg(uint32_t rtcBaseAddr)
1695 BW_RTC_RAR_MCHR(rtcBaseAddr, 0U);
1699 * @brief Reads the field Monotonic Counter Low Read (MCLR) value of the register RTC_RAR.
1701 * @param rtcBaseAddr The RTC base address
1703 * @return true: Reads to the monotonic counter low register will complete as normal.\n
1704 * false: Reads to the monotonic counter low register are ignored.
1706 static inline bool RTC_HAL_GetMonotonicLcountRreg(uint32_t rtcBaseAddr)
1708 return (bool)BR_RTC_RAR_MCLR(rtcBaseAddr);
1712 * @brief Writes 0 to the field Monotonic Counter Low Read (MCLR) of the RTC_RAR register.
1714 * Once cleared, this bit is only set by system reset. It is not affected by
1715 * VBAT POR or software reset.
1717 * @param rtcBaseAddr The RTC base address
1719 static inline void RTC_HAL_ClearMonotonicLcountRreg(uint32_t rtcBaseAddr)
1721 BW_RTC_RAR_MCLR(rtcBaseAddr, 0U);
1725 * @brief Reads the field Monotonic Enable Register Read (MERR) value of the register RTC_RAR.
1727 * @param rtcBaseAddr The RTC base address
1729 * @return true: Reads to the monotonic enable register completes as normal.\n
1730 * false: Reads to the monotonic enable register are ignored.
1732 static inline bool RTC_HAL_GetMonotonicEnableRreg(uint32_t rtcBaseAddr)
1734 return (bool)BR_RTC_RAR_MERR(rtcBaseAddr);
1738 * @brief Writes 0 to the field Monotonic Enable Register Read (MERR) of the RTC_RAR register.
1740 * Once cleared, this bit is only set by system reset. It is not affected by
1741 * VBAT POR or software reset.
1743 * @param rtcBaseAddr The RTC base address
1745 static inline void RTC_HAL_ClearMonotonicEnableRreg(uint32_t rtcBaseAddr)
1747 BW_RTC_RAR_MERR(rtcBaseAddr, 0U);
1753 * @brief Reads the field Interrupt Enable Register Read (IERR) value of the register RTC_RAR.
1755 * @param rtcBaseAddr The RTC base address
1757 * @return true: Reads to the interrupt enable register completes as normal.\n
1758 * false: Reads to the interrupt enable register are ignored.
1760 static inline bool RTC_HAL_GetIntEnableRreg(uint32_t rtcBaseAddr)
1762 return (bool)BR_RTC_RAR_IERR(rtcBaseAddr);
1766 * @brief Writes 0 to the field Interrupt Enable Register Read (IERR) of the RTC_RAR register.
1768 * Once cleared, this bit is only set by system reset. It is not affected by
1769 * VBAT POR or software reset.
1771 * @param rtcBaseAddr The RTC base address
1773 static inline void RTC_HAL_ClearIntEnableRreg(uint32_t rtcBaseAddr)
1775 BW_RTC_RAR_IERR(rtcBaseAddr, 0U);
1779 * @brief Reads the field Lock Register Read (LRR) value of the RTC_RAR register.
1781 * @param rtcBaseAddr The RTC base address
1783 * @return true: Reads to the lock register will complete as normal.\n
1784 * false: Reads to the lock register are ignored.
1786 static inline bool RTC_HAL_GetLockRreg(uint32_t rtcBaseAddr)
1788 return (bool)BR_RTC_RAR_LRR(rtcBaseAddr);
1792 * @brief Writes 0 to the field Lock Register Read (LRR) of the RTC_RAR register.
1794 * Once cleared, this bit is only set by system reset. It is not affected by
1795 * VBAT POR or software reset.
1797 * @param rtcBaseAddr The RTC base address
1799 static inline void RTC_HAL_ClearLockRreg(uint32_t rtcBaseAddr)
1801 BW_RTC_RAR_LRR(rtcBaseAddr, 0U);
1805 * @brief Reads the field Status Register Read (SRR) value of the RTC_RAR register.
1807 * @param rtcBaseAddr The RTC base address
1809 * @return true: Reads to the status register completes as normal.\n
1810 * false: Reads to the status register are ignored.
1812 static inline bool RTC_HAL_GetStatusRreg(uint32_t rtcBaseAddr)
1814 return (bool)BR_RTC_RAR_SRR(rtcBaseAddr);
1818 * @brief Writes 0 to the field Status Register Read (SRR) of the RTC_RAR register.
1820 * Once cleared, this bit is only set by system reset. It is not affected by
1821 * VBAT POR or software reset.
1823 * @param rtcBaseAddr The RTC base address
1825 static inline void RTC_HAL_ClearStatusRreg(uint32_t rtcBaseAddr)
1827 BW_RTC_RAR_SRR(rtcBaseAddr, 0U);
1831 * @brief Reads the field Control Register Read (CRR) value of the RTC_RAR register.
1833 * @param rtcBaseAddr The RTC base address
1835 * @return true: Reads to the control register completes as normal.\n
1836 * false: Reads to the control register are ignored.
1838 static inline bool RTC_HAL_GetControlRreg(uint32_t rtcBaseAddr)
1840 return (bool)BR_RTC_RAR_CRR(rtcBaseAddr);
1844 * @brief Writes 0 to the field Control Register Read (CRR) of the RTC_RAR register.
1846 * Once cleared, this bit is only set by system reset. It is not affected by
1847 * VBAT POR or software reset.
1849 * @param rtcBaseAddr The RTC base address
1851 static inline void RTC_HAL_ClearControlRreg(uint32_t rtcBaseAddr)
1853 BW_RTC_RAR_CRR(rtcBaseAddr, 0U);
1857 * @brief Reads the field Time Compensation Register Read (TCRR) value of the RTC_RAR register.
1859 * @param rtcBaseAddr The RTC base address
1861 * @return true: Reads to the time compensation register completes as normal.\n
1862 * false: Reads to the time compensation register are ignored.
1864 static inline bool RTC_HAL_GetCompensationRreg(uint32_t rtcBaseAddr)
1866 return (bool)BR_RTC_RAR_TCRR(rtcBaseAddr);
1870 * @brief Writes 0 to the field Time Compensation Register Read (TCRR) of the RTC_RAR register.
1872 * Once cleared, this bit is only set by system reset. It is not affected by
1873 * VBAT POR or software reset.
1875 * @param rtcBaseAddr The RTC base address
1877 static inline void RTC_HAL_ClearCompensationRreg(uint32_t rtcBaseAddr)
1879 BW_RTC_RAR_TCRR(rtcBaseAddr, 0U);
1883 * @brief Reads the field Time Alarm Register Read (TARR) value of the RTC_RAR register.
1885 * @param rtcBaseAddr The RTC base address
1887 * @return true: Reads to the time alarm register completes as normal.\n
1888 * false: Reads to the time alarm register are ignored.
1890 static inline bool RTC_HAL_GetAlarmRreg(uint32_t rtcBaseAddr)
1892 return (bool)BR_RTC_RAR_TARR(rtcBaseAddr);
1896 * @brief Writes 0 to the field Time Alarm Register Read (TARR) of the RTC_RAR register.
1898 * Once cleared, this bit is only set by system reset. It is not affected by
1899 * VBAT POR or software reset.
1901 * @param rtcBaseAddr The RTC base address
1903 static inline void RTC_HAL_ClearAlarmRreg(uint32_t rtcBaseAddr)
1905 BW_RTC_RAR_TARR(rtcBaseAddr, 0U);
1909 * @brief Reads the field Time Prescaler Register Read (TPRR) value of the RTC_RAR register.
1911 * @param rtcBaseAddr The RTC base address
1913 * @return true: Reads to the time prescaler register completes as normal.\n
1914 * false: Reads to the time prescaler register are ignored.
1916 static inline bool RTC_HAL_GetPrescalerRreg(uint32_t rtcBaseAddr)
1918 return (bool)BR_RTC_RAR_TPRR(rtcBaseAddr);
1922 * @brief Writes 0 to the field Time Prescaler Register Read (TPRR) of the RTC_RAR register.
1924 * Once cleared, this bit is only set by system reset. It is not affected by
1925 * VBAT POR or software reset.
1927 * @param rtcBaseAddr The RTC base address
1929 static inline void RTC_HAL_ClearPrescalerRreg(uint32_t rtcBaseAddr)
1931 BW_RTC_RAR_TPRR(rtcBaseAddr, 0U);
1935 * @brief Reads the field Time Seconds Register Read (TSRR) value of the RTC_RAR register.
1937 * @param rtcBaseAddr The RTC base address
1939 * @return true: Reads to the time seconds register completes as normal.\n
1940 * false: Reads to the time seconds register are ignored.
1942 static inline bool RTC_HAL_GetSecsRreg(uint32_t rtcBaseAddr)
1944 return (bool)BR_RTC_RAR_TSRR(rtcBaseAddr);
1948 * @brief Writes 0 to the field Time Seconds Register Read (TSRR) of the RTC_RAR register.
1950 * Once cleared, this bit is only set by system reset. It is not affected by
1951 * VBAT POR or software reset.
1953 * @param rtcBaseAddr The RTC base address
1955 static inline void RTC_HAL_ClearSecsRreg(uint32_t rtcBaseAddr)
1957 BW_RTC_RAR_TSRR(rtcBaseAddr, 0U);
1960 #endif /* FSL_FEATURE_RTC_HAS_ACCESS_CONTROL */
1964 #if defined(__cplusplus)
1971 #endif /* __FSL_RTC_HAL_H__*/
1973 /*******************************************************************************
1975 ******************************************************************************/