2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
8 * o Redistributions of source code must retain the above copyright notice, this list
9 * of conditions and the following disclaimer.
11 * o Redistributions in binary form must reproduce the above copyright notice, this
12 * list of conditions and the following disclaimer in the documentation and/or
13 * other materials provided with the distribution.
15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #ifndef __FSL_LPTMR_HAL_H__
31 #define __FSL_LPTMR_HAL_H__
36 #include "fsl_lptmr_features.h"
37 #include "fsl_device_registers.h"
40 * @addtogroup lptmr_hal
44 /*******************************************************************************
46 *******************************************************************************/
48 /*! @brief LPTMR pin selection.*/
49 typedef enum _lptmr_pin_select{
50 kLptmrPinSelectCmpOut = 0x0U, /*!< Lptmr Pin is CMP0 output pin.*/
51 kLptmrPinSelectLptmrAlt1 = 0x1U, /*!< Lptmr Pin is LPTMR_ALT1 pin.*/
52 kLptmrPinSelectLptmrAlt2 = 0x2U, /*!< Lptmr Pin is LPTMR_ALT2 pin.*/
53 kLptmrPinSelectLptmrAlt3 = 0x3U /*!< Lptmr Pin is LPTMR_ALT3 pin.*/
56 /*! @brief LPTMR pin polarity, used while in pluse counter mode.*/
57 typedef enum _lptmr_pin_polarity{
58 kLptmrPinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high.*/
59 kLptmrPinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low.*/
60 } lptmr_pin_polarity_t;
62 /*! @brief LPTMR timer mode selection.*/
63 typedef enum _lptmr_timer_mode{
64 kLptmrTimerModeTimeCounter = 0x0U, /*!< Time Counter mode.*/
65 kLptmrTimerModePluseCounter = 0x1U /*!< Pulse Counter mode.*/
68 /*! @brief LPTMR proscaler value.*/
69 typedef enum _lptmr_prescaler_value{
70 kLptmrPrescalerDivide2 = 0x0U, /*!< Prescaler divide 2, glitch filter invalid.*/
71 kLptmrPrescalerDivide4GlichFiltch2 = 0x1U, /*!< Prescaler divide 4, glitch filter 2.*/
72 kLptmrPrescalerDivide8GlichFiltch4 = 0x2U, /*!< Prescaler divide 8, glitch filter 4.*/
73 kLptmrPrescalerDivide16GlichFiltch8 = 0x3U, /*!< Prescaler divide 16, glitch filter 8.*/
74 kLptmrPrescalerDivide32GlichFiltch16 = 0x4U, /*!< Prescaler divide 32, glitch filter 16.*/
75 kLptmrPrescalerDivide64GlichFiltch32 = 0x5U, /*!< Prescaler divide 64, glitch filter 32.*/
76 kLptmrPrescalerDivide128GlichFiltch64 = 0x6U, /*!< Prescaler divide 128, glitch filter 64.*/
77 kLptmrPrescalerDivide256GlichFiltch128 = 0x7U, /*!< Prescaler divide 256, glitch filter 128.*/
78 kLptmrPrescalerDivide512GlichFiltch256 = 0x8U, /*!< Prescaler divide 512, glitch filter 256.*/
79 kLptmrPrescalerDivide1024GlichFiltch512 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512.*/
80 kLptmrPrescalerDivide2048lichFiltch1024 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024.*/
81 kLptmrPrescalerDivide4096GlichFiltch2048 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048.*/
82 kLptmrPrescalerDivide8192GlichFiltch4096 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096.*/
83 kLptmrPrescalerDivide16384GlichFiltch8192 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192.*/
84 kLptmrPrescalerDivide32768GlichFiltch16384 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384.*/
85 kLptmrPrescalerDivide65535GlichFiltch32768 = 0xFU /*!< Prescaler divide 65535, glitch filter 32768.*/
86 } lptmr_prescaler_value_t;
88 /*! @brief LPTMR clock source selection.*/
89 typedef enum _lptmr_prescaler_clock_source{
90 kLptmrPrescalerClockSourceMcgIrcClk = 0x0U, /*!< Clock source is MCGIRCLK.*/
91 kLptmrPrescalerClockSourceLpo = 0x1U, /*!< Clock source is LPO.*/
92 kLptmrPrescalerClockSourceErClk32K = 0x2U, /*!< Clock source is ERCLK32K.*/
93 kLptmrPrescalerClockSourceOscErClk = 0x3U /*!< Clock source is OSCERCLK.*/
94 } lptmr_prescaler_clock_source_t;
96 /*! @brief LPTMR status return codes.*/
97 typedef enum _lptmr_status {
98 kStatus_LPTMR_Success = 0x0U, /*!< Succeed. */
99 kStatus_LPTMR_NotInitlialized = 0x1U, /*!< LPTMR is not initialized yet. */
100 kStatus_LPTMR_NullArgument = 0x2U, /*!< Argument is NULL.*/
101 kStatus_LPTMR_InvalidPrescalerValue = 0x3U, /*!< Value 0 is not valid in pulse counter mode. */
102 kStatus_LPTMR_InvalidInTimeCounterMode = 0x4U, /*!< Function can not called in time counter mode. */
103 kStatus_LPTMR_InvalidInPluseCounterMode = 0x5U, /*!< Function can not called in pulse counter mode. */
104 kStatus_LPTMR_InvalidPlusePeriodCount = 0x6U, /*!< Pulse period count must be integer multiples of the glitch filter divider. */
105 kStatus_LPTMR_TcfNotSet = 0x7U, /*!< If LPTMR is enabled, compare register can only altered when TCF is set. */
106 kStatus_LPTMR_TimerPeriodUsTooSmall = 0x8U, /*!< Timer period time is too small for current clock source. */
107 kStatus_LPTMR_TimerPeriodUsTooLarge = 0x9U /*!< Timer period time is too large for current clock source. */
110 /*******************************************************************************
112 *******************************************************************************/
114 /*******************************************************************************
116 *******************************************************************************/
118 #if defined(__cplusplus)
128 * @brief Enables the LPTMR module operation.
130 * @param baseAddr The LPTMR peripheral base address.
132 static inline void LPTMR_HAL_Enable(uint32_t baseAddr)
134 BW_LPTMR_CSR_TEN(baseAddr, (uint8_t)true);
138 * @brief Disables the LPTMR module operation.
140 * @param baseAddr The LPTMR peripheral base address.
142 static inline void LPTMR_HAL_Disable(uint32_t baseAddr)
144 BW_LPTMR_CSR_TEN(baseAddr, (uint8_t)false);
148 * @brief Checks whether the LPTMR module is enabled.
150 * @param baseAddr The LPTMR peripheral base address.
151 * @retval true LPTMR module is enabled.
152 * @retval false LPTMR module is disabled.
154 static inline bool LPTMR_HAL_IsEnabled(uint32_t baseAddr)
156 return (bool)BR_LPTMR_CSR_TEN(baseAddr);
160 * @brief Clears the LPTMR interrupt flag if set.
162 * @param baseAddr The LPTMR peripheral base address.
164 static inline void LPTMR_HAL_ClearIntFlag(uint32_t baseAddr)
166 BW_LPTMR_CSR_TCF(baseAddr, 1);
170 * @brief Returns the current LPTMR interrupt flag.
172 * @param baseAddr The LPTMR peripheral base address
173 * @retval true An interrupt is pending.
174 * @retval false No interrupt is pending.
176 static inline bool LPTMR_HAL_IsIntPending(uint32_t baseAddr)
178 return ((bool)BR_LPTMR_CSR_TCF(baseAddr));
182 * @brief Enables or disables the LPTMR interrupt.
184 * @param baseAddr The LPTMR peripheral base address
185 * @param enable Pass true to enable LPTMR interrupt
187 static inline void LPTMR_HAL_SetIntCmd(uint32_t baseAddr, bool enable)
189 BW_LPTMR_CSR_TIE(baseAddr, (uint8_t)enable);
193 * @brief Returns whether the LPTMR interrupt is enabled.
195 * @param baseAddr The LPTMR peripheral base address.
196 * @retval true LPTMR interrupt is enabled.
197 * @retval false LPTMR interrupt is disabled.
199 static inline bool LPTMR_HAL_GetIntCmd(uint32_t baseAddr)
201 return ((bool)BR_LPTMR_CSR_TIE(baseAddr));
205 * @brief Selects the LPTMR pulse input pin select.
207 * @param baseAddr The LPTMR peripheral base address.
208 * @param pinSelect Specifies LPTMR pulse input pin select, see #lptmr_pin_select_t
210 static inline void LPTMR_HAL_SetPinSelectMode(uint32_t baseAddr, lptmr_pin_select_t pinSelect)
212 BW_LPTMR_CSR_TPS(baseAddr, (uint8_t)pinSelect);
216 * @brief Returns the LPTMR pulse input pin select.
218 * @param baseAddr The LPTMR peripheral base address.
219 * @return LPTMR pulse input pin select, see #lptmr_pin_select_t
221 static inline lptmr_pin_select_t LPTMR_HAL_GetPinSelectMode(uint32_t baseAddr)
223 return (lptmr_pin_select_t)BR_LPTMR_CSR_TPS(baseAddr);
227 * @brief Selects the LPTMR pulse input pin polarity.
229 * @param baseAddr The LPTMR peripheral base address.
230 * @param pinPolarity Specifies LPTMR pulse input pin polarity, see #lptmr_pin_polarity_t
232 static inline void LPTMR_HAL_SetPinPolarityMode(uint32_t baseAddr, lptmr_pin_polarity_t pinPolarity)
234 BW_LPTMR_CSR_TPP(baseAddr, (uint8_t)pinPolarity);
238 * @brief Returns the LPTMR pulse input pin polarity.
240 * @param baseAddr The LPTMR peripheral base address.
241 * @return LPTMR pulse input pin polarity, see #lptmr_pin_polarity_t
243 static inline lptmr_pin_polarity_t LPTMR_HAL_GetPinPolarityMode(uint32_t baseAddr)
245 return (lptmr_pin_polarity_t)BR_LPTMR_CSR_TPP(baseAddr);
249 * @brief Enables or disables the LPTMR free running.
251 * @param baseAddr The LPTMR peripheral base address
252 * @param enable Pass true to enable LPTMR free running
254 static inline void LPTMR_HAL_SetFreeRunningCmd(uint32_t baseAddr, bool enable)
256 BW_LPTMR_CSR_TFC(baseAddr, (uint8_t)enable);
260 * @brief Returns whether the LPTMR free running is enabled.
262 * @param baseAddr The LPTMR peripheral base address.
263 * @retval true LPTMR free running is enabled.
264 * @retval false LPTMR free running is disabled.
266 static inline bool LPTMR_HAL_GetFreeRunningCmd(uint32_t baseAddr)
268 return ((bool)BR_LPTMR_CSR_TFC(baseAddr));
272 * @brief Selects the LPTMR working mode.
274 * @param baseAddr The LPTMR peripheral base address.
275 * @param timerMode Specifies LPTMR working mode, see #lptmr_timer_mode_t
277 static inline void LPTMR_HAL_SetTimerModeMode(uint32_t baseAddr, lptmr_timer_mode_t timerMode)
279 BW_LPTMR_CSR_TMS(baseAddr, (uint8_t)timerMode);
283 * @brief Returns the LPTMR working mode.
285 * @param baseAddr The LPTMR peripheral base address.
286 * @return LPTMR working mode, see #lptmr_timer_mode_t
288 static inline lptmr_timer_mode_t LPTMR_HAL_GetTimerModeMode(uint32_t baseAddr)
290 return (lptmr_timer_mode_t)BR_LPTMR_CSR_TMS(baseAddr);
294 * @brief Selects the LPTMR prescaler value.
296 * @param baseAddr The LPTMR peripheral base address.
297 * @param prescaleValue Specifies LPTMR prescaler value, see #lptmr_prescaler_value_t
299 static inline void LPTMR_HAL_SetPrescalerValueMode(uint32_t baseAddr, lptmr_prescaler_value_t prescaleValue)
301 BW_LPTMR_PSR_PRESCALE(baseAddr, (uint8_t)prescaleValue);
305 * @brief Returns the LPTMR prescaler value.
307 * @param baseAddr The LPTMR peripheral base address.
308 * @return LPTMR prescaler value, see #lptmr_prescaler_value_t
310 static inline lptmr_prescaler_value_t LPTMR_HAL_GetPrescalerValueMode(uint32_t baseAddr)
312 return (lptmr_prescaler_value_t)BR_LPTMR_PSR_PRESCALE(baseAddr);
316 * @brief Enables or disables the LPTMR prescaler.
318 * @param baseAddr The LPTMR peripheral base address
319 * @param enable Pass true to enable LPTMR free running
321 static inline void LPTMR_HAL_SetPrescalerCmd(uint32_t baseAddr, bool enable)
323 BW_LPTMR_PSR_PBYP(baseAddr, (uint8_t)(enable == false)); /* 1 means disable prelsaler , 0 means enalbe prescaler */
327 * @brief Returns whether the LPTMR prescaler is enabled.
329 * @param baseAddr The LPTMR peripheral base address.
330 * @retval true LPTMR prescaler is enabled.
331 * @retval false LPTMR prescaler is disabled.
333 static inline bool LPTMR_HAL_GetPrescalerCmd(uint32_t baseAddr)
335 return (bool)(0 == BR_LPTMR_PSR_PBYP(baseAddr)); /* 1 means prelsaler is disabled, 0 means prescaler is enalbed*/
339 * @brief Selects the LPTMR clock source.
341 * @param baseAddr The LPTMR peripheral base address.
342 * @param prescalerClockSource Specifies LPTMR clock source, see #lptmr_prescaler_clock_source_t
344 static inline void LPTMR_HAL_SetPrescalerClockSourceMode(uint32_t baseAddr, lptmr_prescaler_clock_source_t prescalerClockSource)
346 BW_LPTMR_PSR_PCS(baseAddr, (uint8_t)prescalerClockSource);
350 * @brief Gets the LPTMR clock source.
352 * @param baseAddr The LPTMR peripheral base address.
353 * @return LPTMR clock source, see #lptmr_prescaler_clock_source_t
355 static inline lptmr_prescaler_clock_source_t LPTMR_HAL_GetPrescalerClockSourceMode(uint32_t baseAddr)
357 return (lptmr_prescaler_clock_source_t)BR_LPTMR_PSR_PCS(baseAddr);
361 * @brief Sets the LPTMR compare value.
363 * @param baseAddr The LPTMR peripheral base address.
364 * @param compareValue Specifies LPTMR compare value, less than 0xFFFFU
366 static inline void LPTMR_HAL_SetCompareValue(uint32_t baseAddr, uint32_t compareValue)
368 BW_LPTMR_CMR_COMPARE(baseAddr, compareValue & 0xFFFFU);
372 * @brief Gets the LPTMR compare value.
374 * @param baseAddr The LPTMR peripheral base address.
375 * @return Current LPTMR compare value
377 static inline uint32_t LPTMR_HAL_GetCompareValue(uint32_t baseAddr)
379 return (uint32_t)(BR_LPTMR_CMR_COMPARE(baseAddr) & 0xFFFFU);
383 * @brief Gets the LPTMR counter value.
385 * @param baseAddr The LPTMR peripheral base address.
386 * @return Current LPTMR counter value
388 static inline uint32_t LPTMR_HAL_GetCounterValue(uint32_t baseAddr)
390 BW_LPTMR_CNR_COUNTER(baseAddr, 0); /* Must first write to the CNR with any value */
391 return (uint32_t)(BR_LPTMR_CNR_COUNTER(baseAddr) & 0xFFFFU);
395 * @brief Restores the LPTMR module to reset state.
397 * @param baseAddr The LPTMR peripheral base address
399 void LPTMR_HAL_Init(uint32_t baseAddr);
403 #if defined(__cplusplus)
409 #endif /* __FSL_LPTMR_HAL_H__*/
410 /*******************************************************************************
412 *******************************************************************************/