2 ** ###################################################################
3 ** Version: rev. 1.0, 2014-05-14
7 ** Chip specific module features.
9 ** Copyright: 2014 Freescale Semiconductor, Inc.
10 ** All rights reserved.
12 ** Redistribution and use in source and binary forms, with or without modification,
13 ** are permitted provided that the following conditions are met:
15 ** o Redistributions of source code must retain the above copyright notice, this list
16 ** of conditions and the following disclaimer.
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19 ** list of conditions and the following disclaimer in the documentation and/or
20 ** other materials provided with the distribution.
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23 ** contributors may be used to endorse or promote products derived from this
24 ** software without specific prior written permission.
26 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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28 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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31 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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38 ** mail: support@freescale.com
41 ** - rev. 1.0 (2014-05-14)
44 ** ###################################################################
47 #if !defined(__FSL_LLWU_FEATURES_H__)
48 #define __FSL_LLWU_FEATURES_H__
50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
51 defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \
52 defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \
53 defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || \
54 defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12)
55 /* @brief Maximum number of pins connected to LLWU device. */
56 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
57 /* @brief Maximum number of internal modules connected to LLWU device. */
58 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3)
59 /* @brief Number of digital filters. */
60 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
61 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
62 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
63 #elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
64 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
65 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
66 defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
67 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
68 defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
69 defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
70 defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || \
71 defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \
72 defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \
73 defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || \
74 defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
75 defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
76 /* @brief Maximum number of pins connected to LLWU device. */
77 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
78 /* @brief Maximum number of internal modules connected to LLWU device. */
79 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
80 /* @brief Number of digital filters. */
81 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
82 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
83 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1)
84 #elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \
85 defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
86 defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK65FN2M0CAC18) || \
87 defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \
88 defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL13Z64VFM4) || \
89 defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \
90 defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \
91 defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \
92 defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \
93 defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \
94 defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \
95 defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \
96 defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
97 defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \
98 defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \
99 defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
100 defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
101 defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \
102 defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
103 /* @brief Maximum number of pins connected to LLWU device. */
104 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
105 /* @brief Maximum number of internal modules connected to LLWU device. */
106 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
107 /* @brief Number of digital filters. */
108 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
109 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
110 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
111 #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
112 defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4)
113 /* @brief Maximum number of pins connected to LLWU device. */
114 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (8)
115 /* @brief Maximum number of internal modules connected to LLWU device. */
116 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (0)
117 /* @brief Number of digital filters. */
118 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (1)
119 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
120 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
121 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
122 defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
123 defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)
124 /* @brief Maximum number of pins connected to LLWU device. */
125 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (8)
126 /* @brief Maximum number of internal modules connected to LLWU device. */
127 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
128 /* @brief Number of digital filters. */
129 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
130 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
131 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
132 #elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \
133 defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \
134 defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \
135 defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \
136 defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15)
137 /* @brief Maximum number of pins connected to LLWU device. */
138 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
139 /* @brief Maximum number of internal modules connected to LLWU device. */
140 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (4)
141 /* @brief Number of digital filters. */
142 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
143 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
144 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
146 #error "No valid CPU defined!"
149 #endif /* __FSL_LLWU_FEATURES_H__ */
151 /*******************************************************************************
153 ******************************************************************************/