2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
8 * o Redistributions of source code must retain the above copyright notice, this list
9 * of conditions and the following disclaimer.
11 * o Redistributions in binary form must reproduce the above copyright notice, this
12 * list of conditions and the following disclaimer in the documentation and/or
13 * other materials provided with the distribution.
15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #if !defined(__FSL_I2C_HAL_H__)
31 #define __FSL_I2C_HAL_H__
35 #include "fsl_i2c_features.h"
36 #include "fsl_device_registers.h"
43 /*******************************************************************************
45 ******************************************************************************/
46 /*! @brief I2C status return codes.*/
47 typedef enum _i2c_status {
48 kStatus_I2C_Success = 0x0U,
49 kStatus_I2C_OutOfRange = 0x1U,
50 kStatus_I2C_Fail = 0x2U,
51 kStatus_I2C_Busy = 0x3U, /*!< The master is already performing a transfer.*/
52 kStatus_I2C_Timeout = 0x4U, /*!< The transfer timed out.*/
53 kStatus_I2C_ReceivedNak = 0x5U, /*!< The slave device sent a NAK in response to a byte.*/
54 kStatus_I2C_SlaveTxUnderrun = 0x6U, /*!< I2C Slave TX Underrun error.*/
55 kStatus_I2C_SlaveRxOverrun = 0x7U, /*!< I2C Slave RX Overrun error.*/
56 kStatus_I2C_AribtrationLost = 0x8U, /*!< I2C Arbitration Lost error.*/
59 /*! @brief I2C status flags. */
60 typedef enum _i2c_status_flag {
61 kI2CTransferComplete = BP_I2C_S_TCF,
62 kI2CAddressAsSlave = BP_I2C_S_IAAS,
63 kI2CBusBusy = BP_I2C_S_BUSY,
64 kI2CArbitrationLost = BP_I2C_S_ARBL,
65 kI2CAddressMatch = BP_I2C_S_RAM,
66 kI2CSlaveTransmit = BP_I2C_S_SRW,
67 kI2CInterruptPending = BP_I2C_S_IICIF,
68 kI2CReceivedNak = BP_I2C_S_RXAK
71 /*! @brief Direction of master and slave transfers.*/
72 typedef enum _i2c_direction {
73 kI2CReceive = 0U, /*!< Master and slave receive.*/
74 kI2CSend = 1U /*!< Master and slave transmit.*/
77 /*******************************************************************************
79 ******************************************************************************/
81 #if defined(__cplusplus)
86 * @name Module controls
91 * @brief Restores the I2C peripheral to reset state.
93 * @param baseAddr The I2C peripheral base address
95 void I2C_HAL_Init(uint32_t baseAddr);
98 * @brief Enables the I2C module operation.
100 * @param baseAddr The I2C peripheral base address
102 static inline void I2C_HAL_Enable(uint32_t baseAddr)
104 BW_I2C_C1_IICEN(baseAddr, 0x1U);
108 * @brief Disables the I2C module operation.
110 * @param baseAddr The I2C peripheral base address
112 static inline void I2C_HAL_Disable(uint32_t baseAddr)
114 BW_I2C_C1_IICEN(baseAddr, 0x0U);
125 * @brief Enables or disables the DMA support.
127 * @param baseAddr The I2C peripheral base address
128 * @param enable Pass true to enable DMA transfer signalling
130 static inline void I2C_HAL_SetDmaCmd(uint32_t baseAddr, bool enable)
132 BW_I2C_C1_DMAEN(baseAddr, (uint8_t)enable);
136 * @brief Returns whether I2C DMA support is enabled.
138 * @param baseAddr The I2C peripheral base address.
139 * @retval true I2C DMA is enabled.
140 * @retval false I2C DMA is disabled.
142 static inline bool I2C_HAL_GetDmaCmd(uint32_t baseAddr)
144 return BR_I2C_C1_DMAEN(baseAddr);
150 * @name Pin functions
155 * @brief Controls the drive capability of the I2C pads.
157 * @param baseAddr The I2C peripheral base address
158 * @param enable Passing true will enable high drive mode of the I2C pads. False sets normal
161 static inline void I2C_HAL_SetHighDriveCmd(uint32_t baseAddr, bool enable)
163 BW_I2C_C2_HDRS(baseAddr, (uint8_t)enable);
167 * @brief Controls the width of the programmable glitch filter.
169 * Controls the width of the glitch, in terms of bus clock cycles, that the filter must absorb.
170 * The filter does not allow any glitch whose size is less than or equal to this width setting,
173 * @param baseAddr The I2C peripheral base address
174 * @param glitchWidth Maximum width in bus clock cycles of the glitches that is filtered.
175 * Pass zero to disable the glitch filter.
177 static inline void I2C_HAL_SetGlitchWidth(uint32_t baseAddr, uint8_t glitchWidth)
179 BW_I2C_FLT_FLT(baseAddr, glitchWidth);
190 * @brief Controls the I2C wakeup enable.
192 * The I2C module can wake the MCU from low power mode with no peripheral bus running when
193 * slave address matching occurs.
195 * @param baseAddr The I2C peripheral base address.
196 * @param enable true - Enables the wakeup function in low power mode.<br>
197 * false - Normal operation. No interrupt is generated when address matching in
200 static inline void I2C_HAL_SetWakeupCmd(uint32_t baseAddr, bool enable)
202 BW_I2C_C1_WUEN(baseAddr, (uint8_t)enable);
205 #if FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
207 * @brief Controls the stop mode hold off.
209 * This function lets you enable the hold off entry to low power stop mode when any data transmission
210 * or reception is occurring.
212 * @param baseAddr The I2C peripheral base address
213 * @param enable false - Stop hold off is disabled. The MCU's entry to stop mode is not gated.<br>
214 * true - Stop hold off is enabled.
217 static inline void I2C_HAL_SetStopHoldoffCmd(uint32_t baseAddr, bool enable)
219 BW_I2C_FLT_SHEN(baseAddr, (uint8_t)enable);
221 #endif /* FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF*/
231 * @brief Sets the I2C bus frequency for master transactions.
233 * @param baseAddr The I2C peripheral base address
234 * @param sourceClockInHz I2C source input clock in Hertz
235 * @param kbps Requested bus frequency in kilohertz. Common values are either 100 or 400.
236 * @param absoluteError_Hz If this parameter is not NULL, it is filled in with the
237 * difference in Hertz between the requested bus frequency and the closest frequency
238 * possible given available divider values.
240 * @retval kStatus_Success The baud rate was changed successfully. However, there is no
241 * guarantee on the minimum error. If you want to ensure that the baud was set to within
242 * a certain error, then use the @a absoluteError_Hz parameter.
243 * @retval kStatus_OutOfRange The requested baud rate was not within the range of rates
244 * supported by the peripheral.
246 i2c_status_t I2C_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz, uint32_t kbps,
247 uint32_t * absoluteError_Hz);
250 * @brief Sets the I2C baud rate multiplier and table entry.
252 * Use this function to set the I2C bus frequency register values directly, if they are
255 * @param baseAddr The I2C peripheral base address
256 * @param mult Value of the MULT bitfield, ranging from 0-2.
257 * @param icr The ICR bitfield value, which is the index into an internal table in the I2C
258 * hardware that selects the baud rate divisor and SCL hold time.
260 static inline void I2C_HAL_SetFreqDiv(uint32_t baseAddr, uint8_t mult, uint8_t icr)
262 HW_I2C_F_WR(baseAddr, BF_I2C_F_MULT(mult) | BF_I2C_F_ICR(icr));
266 * @brief Slave baud rate control
268 * Enables an independent slave mode baud rate at the maximum frequency. This forces clock stretching
269 * on the SCL in very fast I2C modes.
271 * @param baseAddr The I2C peripheral base address
272 * @param enable true - Slave baud rate is independent of the master baud rate;<br>
273 * false - The slave baud rate follows the master baud rate and clock stretching may occur.
275 static inline void I2C_HAL_SetSlaveBaudCtrlCmd(uint32_t baseAddr, bool enable)
277 BW_I2C_C2_SBRC(baseAddr, (uint8_t)enable);
283 * @name Bus operations
288 * @brief Sends a START or a Repeated START signal on the I2C bus.
290 * This function is used to initiate a new master mode transfer by sending the START signal. It
291 * is also used to send a Repeated START signal when a transfer is already in progress.
293 * @param baseAddr The I2C peripheral base address
295 void I2C_HAL_SendStart(uint32_t baseAddr);
298 * @brief Sends a STOP signal on the I2C bus.
300 * This function changes the direction to receive.
302 * @param baseAddr The I2C peripheral base address
304 static inline void I2C_HAL_SendStop(uint32_t baseAddr)
306 assert(BR_I2C_C1_MST(baseAddr) == 1);
307 HW_I2C_C1_CLR(baseAddr, BM_I2C_C1_MST | BM_I2C_C1_TX);
311 * @brief Causes an ACK to be sent on the bus.
313 * This function specifies that an ACK signal is sent in response to the next received byte.
315 * Note that the behavior of this function is changed when the I2C peripheral is placed in
316 * Fast ACK mode. In this case, this function causes an ACK signal to be sent in
317 * response to the current byte, rather than the next received byte.
319 * @param baseAddr The I2C peripheral base address
321 static inline void I2C_HAL_SendAck(uint32_t baseAddr)
323 BW_I2C_C1_TXAK(baseAddr, 0x0U);
327 * @brief Causes a NAK to be sent on the bus.
329 * This function specifies that a NAK signal is sent in response to the next received byte.
331 * Note that the behavior of this function is changed when the I2C peripheral is placed in the
332 * Fast ACK mode. In this case, this function causes an NAK signal to be sent in
333 * response to the current byte, rather than the next received byte.
335 * @param baseAddr The I2C peripheral base address
337 static inline void I2C_HAL_SendNak(uint32_t baseAddr)
339 BW_I2C_C1_TXAK(baseAddr, 0x1U);
343 * @brief Selects either transmit or receive mode.
345 * @param baseAddr The I2C peripheral base address.
346 * @param direction Specifies either transmit mode or receive mode. The valid values are:
350 static inline void I2C_HAL_SetDirMode(uint32_t baseAddr, i2c_direction_t direction)
352 BW_I2C_C1_TX(baseAddr, (uint8_t)direction);
356 * @brief Returns the currently selected transmit or receive mode.
358 * @param baseAddr The I2C peripheral base address.
359 * @retval #kI2CTransmit I2C is configured for master or slave transmit mode.
360 * @retval #kI2CReceive I2C is configured for master or slave receive mode.
362 static inline i2c_direction_t I2C_HAL_GetDirMode(uint32_t baseAddr)
364 return (i2c_direction_t)BR_I2C_C1_TX(baseAddr);
370 * @name Data transfer
375 * @brief Returns the last byte of data read from the bus and initiate another read.
377 * In a master receive mode, calling this function initiates receiving the next byte of data.
379 * @param baseAddr The I2C peripheral base address
380 * @return This function returns the last byte received while the I2C module is configured in master
381 * receive or slave receive mode.
383 static inline uint8_t I2C_HAL_ReadByte(uint32_t baseAddr)
385 return HW_I2C_D_RD(baseAddr);
389 * @brief Writes one byte of data to the I2C bus.
391 * When this function is called in the master transmit mode, a data transfer is initiated. In slave
392 * mode, the same function is available after an address match occurs.
394 * In a master transmit mode, the first byte of data written following the start bit or repeated
395 * start bit is used for the address transfer and must consist of the slave address (in bits 7-1)
396 * concatenated with the required R/\#W bit (in position bit 0).
398 * @param baseAddr The I2C peripheral base address.
399 * @param byte The byte of data to transmit.
401 static inline void I2C_HAL_WriteByte(uint32_t baseAddr, uint8_t byte)
403 HW_I2C_D_WR(baseAddr, byte);
409 * @name Slave address
414 * @brief Sets the primary 7-bit slave address.
416 * @param baseAddr The I2C peripheral base address
417 * @param address The slave address in the upper 7 bits. Bit 0 of this value must be 0.
419 void I2C_HAL_SetAddress7bit(uint32_t baseAddr, uint8_t address);
422 * @brief Sets the primary slave address and enables 10-bit address mode.
424 * @param baseAddr The I2C peripheral base address
425 * @param address The 10-bit slave address, in bits [10:1] of the value. Bit 0 must be 0.
427 void I2C_HAL_SetAddress10bit(uint32_t baseAddr, uint16_t address);
430 * @brief Enables or disables the extension address (10-bit).
432 * @param baseAddr The I2C peripheral base address
433 * @param enable true: 10-bit address is enabled.
434 * false: 10-bit address is not enabled.
436 static inline void I2C_HAL_SetExtensionAddrCmd(uint32_t baseAddr, bool enable)
438 BW_I2C_C2_ADEXT(baseAddr, (uint8_t)enable);
442 * @brief Returns whether the extension address is enabled or not.
444 * @param baseAddr The I2C peripheral base address
445 * @return true: 10-bit address is enabled.
446 * false: 10-bit address is not enabled.
448 static inline bool I2C_HAL_GetExtensionAddrCmd(uint32_t baseAddr)
450 return BR_I2C_C2_ADEXT(baseAddr);
454 * @brief Controls whether the general call address is recognized.
456 * @param baseAddr The I2C peripheral base address
457 * @param enable Whether to enable the general call address.
459 static inline void I2C_HAL_SetGeneralCallCmd(uint32_t baseAddr, bool enable)
461 BW_I2C_C2_GCAEN(baseAddr, (uint8_t)enable);
465 * @brief Enables or disables the slave address range matching.
467 * @param baseAddr The I2C peripheral base address.
468 * @param enable Pass true to enable range address matching. You must also call
469 * I2C_HAL_SetUpperAddress7bit() to set the upper address.
471 static inline void I2C_HAL_SetRangeMatchCmd(uint32_t baseAddr, bool enable)
473 BW_I2C_C2_RMEN(baseAddr, (uint8_t)enable);
477 * @brief Sets the upper slave address.
479 * This slave address is used as a secondary slave address. If range address
480 * matching is enabled, this slave address acts as the upper bound on the slave address
483 * This function sets only a 7-bit slave address. If 10-bit addressing was enabled by calling
484 * I2C_HAL_SetAddress10bit(), then the top 3 bits set with that function are also used
485 * with the address set with this function to form a 10-bit address.
487 * Passing 0 for the @a address parameter disables matching the upper slave address.
489 * @param baseAddr The I2C peripheral base address
490 * @param address The upper slave address in the upper 7 bits. Bit 0 of this value must be 0.
491 * In addition, this address must be greater than the primary slave address that is set by
492 * calling I2C_HAL_SetAddress7bit().
494 static inline void I2C_HAL_SetUpperAddress7bit(uint32_t baseAddr, uint8_t address)
496 assert((address & 1) == 0);
497 assert((address == 0) || (address > HW_I2C_A1_RD(baseAddr)));
498 HW_I2C_RA_WR(baseAddr, address);
509 * @brief Gets the I2C status flag state.
511 * @param baseAddr The I2C peripheral base address.
512 * @param statusFlag The status flag, defined in type i2c_status_flag_t.
513 * @return State of the status flag: asserted (true) or not-asserted (false).
514 * - true: related status flag is being set.
515 * - false: related status flag is not set.
517 static inline bool I2C_HAL_GetStatusFlag(uint32_t baseAddr, i2c_status_flag_t statusFlag)
519 return (bool)((HW_I2C_S_RD(baseAddr) >> statusFlag) & 0x1U);
523 * @brief Returns whether the I2C module is in master mode.
525 * @param baseAddr The I2C peripheral base address.
526 * @retval true The module is in master mode, which implies it is also performing a transfer.
527 * @retval false The module is in slave mode.
529 static inline bool I2C_HAL_IsMaster(uint32_t baseAddr)
531 return (bool)BR_I2C_C1_MST(baseAddr);
535 * @brief Clears the arbitration lost flag.
537 * @param baseAddr The I2C peripheral base address
539 static inline void I2C_HAL_ClearArbitrationLost(uint32_t baseAddr)
541 BW_I2C_S_ARBL(baseAddr, 0x1U);
552 * @brief Enables or disables I2C interrupt requests.
554 * @param baseAddr The I2C peripheral base address
555 * @param enable Pass true to enable interrupt, flase to disable.
557 static inline void I2C_HAL_SetIntCmd(uint32_t baseAddr, bool enable)
559 BW_I2C_C1_IICIE(baseAddr, (uint8_t)enable);
563 * @brief Returns whether the I2C interrupts are enabled.
565 * @param baseAddr The I2C peripheral base address
566 * @retval true I2C interrupts are enabled.
567 * @retval false I2C interrupts are disabled.
569 static inline bool I2C_HAL_GetIntCmd(uint32_t baseAddr)
571 return (bool)BR_I2C_C1_IICIE(baseAddr);
575 * @brief Returns the current I2C interrupt flag.
577 * @param baseAddr The I2C peripheral base address
578 * @retval true An interrupt is pending.
579 * @retval false No interrupt is pending.
581 static inline bool I2C_HAL_IsIntPending(uint32_t baseAddr)
583 return (bool)BR_I2C_S_IICIF(baseAddr);
587 * @brief Clears the I2C interrupt if set.
589 * @param baseAddr The I2C peripheral base address
591 static inline void I2C_HAL_ClearInt(uint32_t baseAddr)
593 BW_I2C_S_IICIF(baseAddr, 0x1U);
598 #if FSL_FEATURE_I2C_HAS_STOP_DETECT
601 * @name Bus stop detection status
606 * @brief Gets the flag indicating a STOP signal was detected on the I2C bus.
608 * @param baseAddr The I2C peripheral base address
609 * @retval true STOP signal detected on bus.
610 * @retval false No STOP signal was detected on the bus.
612 static inline bool I2C_HAL_GetStopFlag(uint32_t baseAddr)
614 return (bool)BR_I2C_FLT_STOPF(baseAddr);
618 * @brief Clears the bus STOP signal detected flag.
620 * @param baseAddr The I2C peripheral base address
622 static inline void I2C_HAL_ClearStopFlag(uint32_t baseAddr)
624 BW_I2C_FLT_STOPF(baseAddr, 0x1U);
629 #if FSL_FEATURE_I2C_HAS_START_DETECT
632 * @name Bus stop detection interrupt
637 * @brief Enables the I2C bus stop detection interrupt.
639 * @param baseAddr The I2C peripheral base address
640 * @param enable Pass true to enable interrupt, flase to disable.
642 static inline void I2C_HAL_SetStopIntCmd(uint32_t baseAddr, bool enable)
644 BW_I2C_FLT_SSIE(baseAddr, enable);
648 * @brief Returns whether the I2C bus stop detection interrupts are enabled.
650 * @param baseAddr The I2C peripheral base address
651 * @retval true Stop detect interrupts are enabled.
652 * @retval false Stop detect interrupts are disabled.
654 static inline bool I2C_HAL_GetStopIntCmd(uint32_t baseAddr)
656 return (bool)BR_I2C_FLT_SSIE(baseAddr);
661 /*! @name Bus stop detection interrupt*/
665 * @brief Enables the I2C bus stop detection interrupt.
667 * @param baseAddr The I2C peripheral base address
669 static inline void I2C_HAL_SetStopIntCmd(uint32_t baseAddr, bool enable)
671 BW_I2C_FLT_STOPIE(baseAddr, enable);
675 * @brief Returns whether the I2C bus stop detection interrupts are enabled.
677 * @param baseAddr The I2C peripheral base address
678 * @retval true Stop detect interrupts are enabled.
679 * @retval false Stop detect interrupts are disabled.
681 static inline bool I2C_HAL_GetStopIntCmd(uint32_t baseAddr)
683 return (bool)BR_I2C_FLT_STOPIE(baseAddr);
686 #endif /* FSL_FEATURE_I2C_HAS_START_DETECT*/
689 #endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT*/
691 #if defined(__cplusplus)
697 #endif /* __FSL_I2C_HAL_H__*/
698 /*******************************************************************************
700 ******************************************************************************/