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31 #ifndef __FSL_ADC_HAL_H__
32 #define __FSL_ADC_HAL_H__
37 #include "fsl_device_registers.h"
38 #include "fsl_adc_features.h"
45 /******************************************************************************
47 *****************************************************************************/
50 * @brief ADC status return codes.
52 typedef enum _adc_status
54 kStatus_ADC_Success = 0U, /*!< Success. */
55 kStatus_ADC_InvalidArgument = 1U, /*!< Invalid argument existed. */
56 kStatus_ADC_Failed = 2U /*!< Execution failed. */
59 #if FSL_FEATURE_ADC_HAS_MUX_SELECT
62 * @brief Defines the type of the enumerating channel multiplexer mode for each channel.
64 * For some ADC channels, there are two selections for the channel multiplexer. For
65 * example, ADC0_SE4a and ADC0_SE4b are the different channels but share the same
68 typedef enum _adc_chn_mux_mode
70 kAdcChnMuxOfA = 0U, /*!< For channel with channel mux a. */
71 kAdcChnMuxOfB = 1U, /*!< For channel with channel mux b. */
72 kAdcChnMuxOfDefault = kAdcChnMuxOfA /*!< For channel without any channel mux identifier. */
74 #endif /* FSL_FEATURE_ADC_HAS_MUX_SELECT */
77 * @brief Defines the type of the enumerating divider for the converter.
79 typedef enum _adc_clk_divider_mode
81 kAdcClkDividerInputOf1 = 0U, /*!< For divider 1 from the input clock to ADC. */
82 kAdcClkDividerInputOf2 = 1U, /*!< For divider 2 from the input clock to ADC. */
83 kAdcClkDividerInputOf4 = 2U, /*!< For divider 4 from the input clock to ADC. */
84 kAdcClkDividerInputOf8 = 3U /*!< For divider 8 from the input clock to ADC. */
85 } adc_clk_divider_mode_t;
88 *@brief Defines the type of the enumerating resolution for the converter.
90 typedef enum _adc_resolution_mode
92 kAdcResolutionBitOf8or9 = 0U,
93 /*!< 8-bit for single end sample, or 9-bit for differential sample. */
94 kAdcResolutionBitOfSingleEndAs8 = kAdcResolutionBitOf8or9, /*!< 8-bit for single end sample. */
95 kAdcResolutionBitOfDiffModeAs9 = kAdcResolutionBitOf8or9, /*!< 9-bit for differential sample. */
97 kAdcResolutionBitOf12or13 = 1U,
98 /*!< 12-bit for single end sample, or 13-bit for differential sample. */
99 kAdcResolutionBitOfSingleEndAs12 = kAdcResolutionBitOf12or13, /*!< 12-bit for single end sample. */
100 kAdcResolutionBitOfDiffModeAs13 = kAdcResolutionBitOf12or13, /*!< 13-bit for differential sample. */
102 kAdcResolutionBitOf10or11 = 2U,
103 /*!< 10-bit for single end sample, or 11-bit for differential sample. */
104 kAdcResolutionBitOfSingleEndAs10 = kAdcResolutionBitOf10or11, /*!< 10-bit for single end sample. */
105 kAdcResolutionBitOfDiffModeAs11 = kAdcResolutionBitOf10or11 /*!< 11-bit for differential sample. */
106 #if (FSL_FEATURE_ADC_MAX_RESOLUTION>=16)
107 , kAdcResolutionBitOf16 = 3U,
108 /*!< 16-bit for both single end sample and differential sample. */
109 kAdcResolutionBitOfSingleEndAs16 = kAdcResolutionBitOf16, /*!< 16-bit for single end sample. */
110 kAdcResolutionBitOfDiffModeAs16 = kAdcResolutionBitOf16 /*!< 16-bit for differential sample. */
112 #endif /* FSL_FEATURE_ADC_MAX_RESOLUTION */
113 } adc_resolution_mode_t;
116 * @brief Defines the type of the enumerating source of the input clock.
118 typedef enum _adc_clk_src_mode
120 kAdcClkSrcOfBusClk = 0U, /*!< For input as bus clock. */
121 kAdcClkSrcOfBusOrAltClk2 = 1U, /*!< For input as bus clock /2 or AltClk2. */
122 kAdcClkSrcOfAltClk = 2U, /*!< For input as alternate clock (ALTCLK). */
123 kAdcClkSrcOfAsynClk = 3U /*!< For input as asynchronous clock (ADACK). */
124 } adc_clk_src_mode_t;
127 * @brief Defines the type of the enumerating long sample cycles.
129 typedef enum _adc_long_sample_cycle_mode
131 kAdcLongSampleCycleOf24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */
132 kAdcLongSampleCycleOf16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */
133 kAdcLongSampleCycleOf10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */
134 kAdcLongSampleCycleOf4 = 3U /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */
135 } adc_long_sample_cycle_mode_t;
138 * @brief Defines the type of the enumerating reference voltage source.
140 typedef enum _adc_ref_volt_src_mode
142 kAdcRefVoltSrcOfVref = 0U, /*!< For external pins pair of VrefH and VrefL. */
143 kAdcRefVoltSrcOfValt = 1U /*!< For alternate reference pair of ValtH and ValtL.*/
144 } adc_ref_volt_src_mode_t;
146 #if FSL_FEATURE_ADC_HAS_HW_AVERAGE
149 * @brief Defines the type of the enumerating hardware average mode.
151 typedef enum _adc_hw_average_count_mode
153 kAdcHwAverageCountOf4 = 0U, /*!< For hardware average with 4 samples. */
154 kAdcHwAverageCountOf8 = 1U, /*!< For hardware average with 8 samples. */
155 kAdcHwAverageCountOf16 = 2U, /*!< For hardware average with 16 samples. */
156 kAdcHwAverageCountOf32 = 3U /*!< For hardware average with 32 samples. */
157 } adc_hw_average_count_mode_t;
159 #endif /* FSL_FEATURE_ADC_HAS_HW_AVERAGE */
162 * @brief Defines the type of the enumerating asserted range in the hardware compare.
164 * When the internal CMP is enabled, the COCO flag, which represents the complement
165 * of the conversion, is not asserted if the sample value is not in the indicated
166 * range. Eventually, the data of conversion result is not kept in the result
167 * data register. The two values, cmpValue1 and cmpValue2, mark
168 * the thresholds with the comparator feature.
169 * kAdcHwCmpRangeModeOf1:
170 * Both greater than and in range switchers are disabled.
171 * The available range is "< cmpValue1".
172 * kAdcHwCmpRangeModeOf2:
173 * Greater than switcher is enabled while the in range switcher is disabled.
174 * The available range is " > cmpValue1".
175 * kAdcHwCmpRangeModeOf3:
176 * Greater than switcher is disabled while in range switcher is enabled.
177 * The available range is "< cmpValue1" or "> cmpValue2" when
178 * cmpValue1 <= cmpValue2, or "< cmpValue1" and "> cmpValue2" when
179 * cmpValue1 >= cmpValue2.
180 * kAdcHwCmpRangeModeOf4:
181 * Both greater than and in range switchers are enabled.
182 * The available range is "> cmpValue1" and "< cmpValue2" when
183 * cmpValue1 <= cmpValue2, or "> cmpValue1" or "< cmpValue2" when
184 * cmpValue1 < cmpValue2.
186 typedef enum _adc_hw_cmp_range_mode
188 kAdcHwCmpRangeModeOf1 = 0U, /*!< For selection mode 1. */
189 kAdcHwCmpRangeModeOf2 = 1U, /*!< For selection mode 2. */
190 kAdcHwCmpRangeModeOf3 = 2U, /*!< For selection mode 3. */
191 kAdcHwCmpRangeModeOf4 = 3U /*!< For selection mode 4. */
192 } adc_hw_cmp_range_mode_t;
194 #if FSL_FEATURE_ADC_HAS_PGA
197 * @brief Defines the type of enumerating PGA's Gain mode.
199 typedef enum _adc_pga_gain_mode
201 kAdcPgaGainValueOf1 = 0U, /*!< For amplifier gain of 1.*/
202 kAdcPgaGainValueOf2 = 1U, /*!< For amplifier gain of 2.*/
203 kAdcPgaGainValueOf4 = 2U, /*!< For amplifier gain of 4.*/
204 kAdcPgaGainValueOf8 = 3U, /*!< For amplifier gain of 8.*/
205 kAdcPgaGainValueOf16 = 4U, /*!< For amplifier gain of 16.*/
206 kAdcPgaGainValueOf32 = 5U, /*!< For amplifier gain of 32.*/
207 kAdcPgaGainValueOf64 = 6U /*!< For amplifier gain of 64.*/
208 } adc_pga_gain_mode_t;
210 #endif /* FSL_FEATURE_ADC_HAS_PGA */
212 #if defined(__cplusplus)
216 /*******************************************************************************
218 ******************************************************************************/
222 * @brief Resets all registers into a known state for the ADC module.
224 * This function resets all registers into a known state for the ADC
225 * module. This known state is the reset value indicated by the Reference
226 * manual. It is strongly recommended to call this API before any other operation
227 * when initializing the ADC module.
229 * @param baseAddr Register base address for the module.
231 void ADC_HAL_Init(uint32_t baseAddr);
234 * @brief Configures the conversion channel for the ADC module.
236 * This function configures the channel for the ADC module. At any point,
237 * only one of the configuration groups takes effect. The other channel mux of
238 * the first group (group A, 0) is only for the hardware trigger. Both software and
239 * hardware trigger can be used to the first group. When in software trigger
240 * mode, once the available channel is set, the conversion begins to execute.
242 * @param baseAddr Register base address for the module.
243 * @param chnGroup Channel configuration group ID.
244 * @param intEnable Switcher to enable interrupt when conversion is completed.
245 * @param diffEnable Switcher to enable differential channel mode.
246 * @param chnNum ADC channel for next conversion.
248 static inline void ADC_HAL_ConfigChn(uint32_t baseAddr, uint32_t chnGroup,
249 bool intEnable, bool diffEnable, uint8_t chnNum)
251 assert(chnGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
253 #if FSL_FEATURE_ADC_HAS_DIFF_MODE
254 HW_ADC_SC1n_WR(baseAddr, chnGroup, \
255 ( (intEnable ? BM_ADC_SC1n_AIEN : 0U) \
256 | ( (diffEnable)? BM_ADC_SC1n_DIFF : 0U) \
257 | BF_ADC_SC1n_ADCH(chnNum) \
260 HW_ADC_SC1n_WR(baseAddr, chnGroup, \
261 ( (intEnable ? BM_ADC_SC1n_AIEN : 0U) \
262 | BF_ADC_SC1n_ADCH(chnNum) \
265 #endif /* FSL_FEATURE_ADC_HAS_DIFF_MODE */
269 #if FSL_FEATURE_ADC_HAS_DIFF_MODE
272 * @brief Checks whether the channel differential mode is enabled.
274 * This function checks whether the channel differential mode for
277 * @param baseAddr Register base address for the module.
278 * @param chnGroup Channel configuration group ID.
279 * @return Assertion of enabling differential mode.
281 static inline bool ADC_HAL_GetChnDiffCmd(uint32_t baseAddr, uint32_t chnGroup)
283 assert(chnGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
284 return (1U == BR_ADC_SC1n_DIFF(baseAddr, chnGroup));
286 #endif /* FSL_FEATURE_ADC_HAS_DIFF_MODE */
289 * @brief Checks whether the channel conversion is completed.
291 * This function checks whether the channel conversion for the ADC
292 * module is completed.
294 * @param baseAddr Register base address for the module.
295 * @param chnGroup Channel configuration group ID.
296 * @return Assertion of completed conversion mode.
298 static inline bool ADC_HAL_GetChnConvCompletedCmd(uint32_t baseAddr, uint32_t chnGroup)
300 assert(chnGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
301 return (1U == BR_ADC_SC1n_COCO(baseAddr, chnGroup) );
305 * @brief Switches to enable the low power mode for ADC module.
307 * This function switches to enable the low power mode for ADC module.
309 * @param baseAddr Register base address for the module.
310 * @param enable Switcher to asserted the feature.
312 static inline void ADC_HAL_SetLowPowerCmd(uint32_t baseAddr, bool enable)
314 BW_ADC_CFG1_ADLPC(baseAddr, (enable ? 1U : 0U) );
318 * @brief Selects the clock divider mode for the ADC module.
320 * This function selects the clock divider mode for the ADC module.
322 * @param baseAddr Register base address for the module.
323 * @param mode Selection of mode enumeration. See to "adc_clk_divider_mode_t".
325 static inline void ADC_HAL_SetClkDividerMode(uint32_t baseAddr, adc_clk_divider_mode_t mode)
327 BW_ADC_CFG1_ADIV(baseAddr, (uint32_t)mode );
331 * @brief Switches to enable the long sample mode for the ADC module.
333 * This function switches to enable the long sample mode for the ADC module.
334 * This function adjusts the sample period to allow the higher impedance inputs to
335 * be accurately sampled or to maximize the conversion speed for the lower impedance
336 * inputs. Longer sample times can also be used to lower overall power
337 * consumption if the continuous conversions are enabled and the high conversion rates
338 * are not required. If the long sample mode is enabled, more configuration
339 * is set by calling the "ADC_HAL_SetLongSampleCycleMode()" function.
341 * @param baseAddr Register base address for the module.
342 * @param enable Switcher to asserted the feature.
344 static inline void ADC_HAL_SetLongSampleCmd(uint32_t baseAddr, bool enable)
346 BW_ADC_CFG1_ADLSMP(baseAddr, (enable ? 1U : 0U) );
350 * @brief Selects the conversion resolution mode for ADC module.
352 * This function selects the conversion resolution mode for the ADC module.
354 * @param baseAddr Register base address for the module.
355 * @param mode Selection of mode enumeration. See to "adc_resolution_mode_t".
357 static inline void ADC_HAL_SetResolutionMode(uint32_t baseAddr, adc_resolution_mode_t mode)
359 BW_ADC_CFG1_MODE(baseAddr, (uint32_t)mode );
363 * @brief Gets the conversion resolution mode for ADC module.
365 * This function gets the conversion resolution mode for the ADC module.
366 * It is specially used when processing the conversion result of RAW format.
368 * @param baseAddr Register base address for the module.
369 * @return Current conversion resolution mode.
371 static inline adc_resolution_mode_t ADC_HAL_GetResolutionMode(uint32_t baseAddr)
373 return (adc_resolution_mode_t)( BR_ADC_CFG1_MODE(baseAddr) );
377 * @brief Selects the input clock source for the ADC module.
379 * This function selects the input clock source for the ADC module.
381 * @param baseAddr Register base address for the module.
382 * @param mode Selection of mode enumeration. See to "adc_clk_src_mode_t".
384 static inline void ADC_HAL_SetClkSrcMode(uint32_t baseAddr, adc_clk_src_mode_t mode)
386 BW_ADC_CFG1_ADICLK(baseAddr, (uint32_t)mode );
389 #if FSL_FEATURE_ADC_HAS_MUX_SELECT
392 * @brief Selects the channel mux mode for the ADC module.
394 * This function selects the channel mux mode for the ADC module.
396 * @param baseAddr Register base address for the module.
397 * @param mode Selection of mode enumeration. See to "adc_chn_mux_mode_t".
399 static inline void ADC_HAL_SetChnMuxMode(uint32_t baseAddr, adc_chn_mux_mode_t mode)
401 BW_ADC_CFG2_MUXSEL(baseAddr, ((kAdcChnMuxOfA == mode) ? 0U : 1U) );
405 * @brief Gets the current channel mux mode for the ADC module.
407 * This function selects the channel mux mode for the ADC module.
409 * @param baseAddr Register base address for the module.
410 * @return Selection of mode enumeration. See to "adc_chn_mux_mode_t".
412 static inline adc_chn_mux_mode_t ADC_HAL_GetChnMuxMode(uint32_t baseAddr)
414 return (adc_chn_mux_mode_t)(BR_ADC_CFG2_MUXSEL(baseAddr) );
417 #endif /* FSL_FEATURE_ADC_HAS_MUX_SELECT */
420 * @brief Switches to enable the asynchronous clock for the ADC module.
422 * This function switches to enable the asynchronous clock for the ADC module.
423 * It enables the ADC's asynchronous clock source and the clock source
424 * output regardless of the conversion and the input clock select status of the
425 * ADC. Asserting this function allows the clock to be used even while the ADC
426 * is idle or operating from a different clock source. Also, latency of
427 * initiating a single or first-continuous conversion with the asynchronous
428 * clock selected is reduced since the ADC internal clock has been already
431 * @param baseAddr Register base address for the module.
432 * @param enable Switcher to asserted the feature.
434 static inline void ADC_HAL_SetAsyncClkCmd(uint32_t baseAddr, bool enable)
436 BW_ADC_CFG2_ADACKEN(baseAddr, (enable ? 1U : 0U) );
440 * @brief Switches to enable the high speed mode for the ADC module.
442 * This function switches to enable the high speed mode for the ADC module.
444 * @param baseAddr Register base address for the module.
445 * @param enable Switcher to asserted the feature.
447 static inline void ADC_HAL_SetHighSpeedCmd(uint32_t baseAddr, bool enable)
449 BW_ADC_CFG2_ADHSC(baseAddr, (enable ? 1U : 0U) );
453 * @brief Selects the long sample cycle mode for the ADC module.
455 * This function selects the long sample cycle mode for the ADC module.
456 * This function should be called along with "ADC_HAL_SetLongSampleCmd()".
458 * @param baseAddr Register base address for the module.
459 * @param mode Selection of long sample cycle mode. See the "adc_long_sample_cycle_mode_t".
461 static inline void ADC_HAL_SetLongSampleCycleMode(uint32_t baseAddr,
462 adc_long_sample_cycle_mode_t mode)
464 BW_ADC_CFG2_ADLSTS(baseAddr, (uint32_t)mode );
468 * @brief Gets the raw result data of channel conversion for the ADC module.
470 * This function gets the result data of conversion for the ADC module.
471 * The return value is raw data that is not processed. The unavailable bits would be
472 * filled with "0" in single-ended mode and sign bit in differential mode.
474 * @param baseAddr Register base address for the module.
475 * @param chnGroup Channel configuration group ID.
476 * @return Conversion value of RAW.
478 static inline uint16_t ADC_HAL_GetChnConvValueRAW(uint32_t baseAddr,
481 assert(chnGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
482 return (uint16_t)(BR_ADC_Rn_D(baseAddr, chnGroup) );
486 * @brief Sets the compare value of the lower limitation for the ADC module.
488 * This function sets the compare value of the lower limitation for the ADC module.
490 * @param baseAddr Register base address for the module.
491 * @param value Setting value.
493 static inline void ADC_HAL_SetHwCmpValue1(uint32_t baseAddr, uint16_t value)
495 BW_ADC_CV1_CV(baseAddr,value);
499 * @brief Sets the compare value of the higher limitation for the ADC module.
501 * This function sets the compare value of the higher limitation for the ADC module.
503 * @param baseAddr Register base address for the module.
504 * @param value Setting value.
506 static inline void ADC_HAL_SetHwCmpValue2(uint32_t baseAddr, uint16_t value)
508 BW_ADC_CV2_CV(baseAddr,value);
512 * @brief Checks whether the converter is active for the ADC module.
514 * This function checks whether the converter is active for the ADC
515 * module. If it is dis-asserted when the conversion is completed, one of the
516 * completed flag is asserted for the indicated group mux. See the
517 * "ADC_HAL_GetChnConvCompletedCmd()".
519 * @param baseAddr Register base address for the module.
520 * @return Assertion of that the converter is active.
522 static inline bool ADC_HAL_GetConvActiveCmd(uint32_t baseAddr)
524 return (1U == BR_ADC_SC2_ADACT(baseAddr) );
528 * @brief Switches to enable the hardware trigger mode for the ADC module.
530 * This function switches to enable the hardware trigger mode for the ADC
533 * @param baseAddr Register base address for the module.
534 * @param enable Switcher to asserted the feature.
536 static inline void ADC_HAL_SetHwTriggerCmd(uint32_t baseAddr, bool enable)
538 BW_ADC_SC2_ADTRG(baseAddr,(enable ? 1U : 0U) );
542 * @brief Switches to enable the hardware comparator for the ADC module.
544 * This function switches to enable the hardware comparator for the ADC module.
546 * @param baseAddr Register base address for the module.
547 * @param enable Switcher to asserted the feature.
549 static inline void ADC_HAL_SetHwCmpCmd(uint32_t baseAddr, bool enable)
551 BW_ADC_SC2_ACFE(baseAddr, (enable ? 1U : 0U) );
555 * @brief Switches to enable the setting that is greater than the hardware comparator.
557 * This function switches to enable the setting that is greater than the
558 * hardware comparator.
560 * @param baseAddr Register base address for the module.
561 * @param enable Switcher to asserted the feature.
563 static inline void ADC_HAL_SetHwCmpGreaterCmd(uint32_t baseAddr, bool enable)
565 BW_ADC_SC2_ACFGT(baseAddr, (enable ? 1U : 0U) );
569 * @brief Switches to enable the setting of the range for hardware comparator.
571 * This function switches to enable the setting of range for the hardware
574 * @param baseAddr Register base address for the module.
575 * @param enable Switcher to asserted the feature.
577 static inline void ADC_HAL_SetHwCmpRangeCmd(uint32_t baseAddr, bool enable)
579 BW_ADC_SC2_ACREN(baseAddr, (enable ? 1U : 0U) );
583 * @brief Configures the asserted range of the hardware comparator for the ADC module.
585 * This function configures the asserted range of the hardware comparator for the
588 * @param baseAddr Register base address for the module.
589 * @param mode Selection of range mode, see to "adc_hw_cmp_range_mode_t".
591 void ADC_HAL_SetHwCmpMode(uint32_t baseAddr, adc_hw_cmp_range_mode_t mode);
593 #if FSL_FEATURE_ADC_HAS_DMA
596 * @brief Switches to enable the DMA for the ADC module.
598 * This function switches to enable the DMA for the ADC module. When enabled, the
599 * DMA request is asserted during the ADC conversion complete event, which is noted
600 * by the assertion of any of the ADC channel completed flags.
602 * @param baseAddr Register base address for the module.
603 * @param enable Switcher to asserted the feature.
605 static inline void ADC_HAL_SetDmaCmd(uint32_t baseAddr, bool enable)
607 BW_ADC_SC2_DMAEN(baseAddr, (enable ? 1U : 0U) );
610 #endif /* FSL_FEATURE_ADC_HAS_DMA */
613 * @brief Selects the reference voltage source for the ADC module.
615 * This function selects the reference voltage source for the ADC module.
617 * @param baseAddr Register base address for the module.
618 * @param mode Selection of asserted the feature.
620 static inline void ADC_HAL_SetRefVoltSrcMode(uint32_t baseAddr, adc_ref_volt_src_mode_t mode)
622 BW_ADC_SC2_REFSEL(baseAddr, (uint32_t)mode );
625 #if FSL_FEATURE_ADC_HAS_CALIBRATION
628 * @brief Switches to enable the hardware calibration for the ADC module.
630 * This function launches the hardware calibration for the ADC module.
632 * @param baseAddr Register base address for the module.
633 * @param enable Switcher to asserted the feature.
635 static inline void ADC_HAL_SetAutoCalibrationCmd(uint32_t baseAddr, bool enable)
637 BW_ADC_SC3_CAL(baseAddr, (enable ? 1U : 0U) );
641 * @brief Gets the hardware calibration status for the ADC module.
643 * This function gets the status whether the hardware calibration is active
644 * for the ADC module. The return value holds on as asserted during the hardware
645 * calibration. Then, it is cleared and dis-asserted after the
648 * @param baseAddr Register base address for the module.
650 static inline bool ADC_HAL_GetAutoCalibrationActiveCmd(uint32_t baseAddr)
652 return (1U == BR_ADC_SC3_CAL(baseAddr) );
656 * @brief Gets the hardware calibration status for the ADC module.
658 * This function gets the status whether the hardware calibration has failed
659 * for the ADC module. The return value is asserted if there is anything wrong
660 * with the hardware calibration.
662 * @param baseAddr Register base address for the module.
664 static inline bool ADC_HAL_GetAutoCalibrationFailedCmd(uint32_t baseAddr)
666 return (1U == BR_ADC_SC3_CALF(baseAddr) );
670 * @brief Gets and calculates the plus side calibration parameter from the auto calibration.
672 * This function gets the values of CLP0 - CLP4 and CLPS internally,
673 * accumulates them, and returns the value that can be used to be set in the PG
674 * register directly. Note that this API should be called after the process of
675 * auto calibration is complete.
677 * @param baseAddr Register base address for the module.
678 * @return value that can be set into PG directly.
680 uint16_t ADC_HAL_GetAutoPlusSideGainValue(uint32_t baseAddr);
683 * @brief Sets the plus side gain calibration value for the ADC module.
685 * This function sets the plus side gain calibration value for the ADC module.
687 * @param baseAddr Register base address for the module.
688 * @param value Setting value for plus side gain.
690 static inline void ADC_HAL_SetPlusSideGainValue(uint32_t baseAddr, uint16_t value)
692 BW_ADC_PG_PG(baseAddr, value);
695 #if FSL_FEATURE_ADC_HAS_DIFF_MODE
698 * @brief Gets and calculates the minus side calibration parameter from the auto calibration.
700 * This function gets the values of CLM0 - CLM4 and CLMS internally,
701 * accumulates them, and returns the value that can be used to be set in the MG
702 * register directly. Note that this API should be called after the process of
703 * auto calibration is complete.
705 * @param baseAddr Register base address for the module.
706 * @return value that can be set into MG directly.
708 uint16_t ADC_HAL_GetAutoMinusSideGainValue(uint32_t baseAddr);
711 * @brief Sets the minus side gain calibration value for the ADC module.
713 * This function sets the minus side gain calibration value for the ADC module.
715 * @param baseAddr Register base address for the module.
716 * @param value Setting value for minus side gain.
718 static inline void ADC_HAL_SetMinusSideGainValue(uint32_t baseAddr, uint16_t value)
720 BW_ADC_MG_MG(baseAddr, value);
723 #endif /* FSL_FEATURE_ADC_HAS_DIFF_MODE */
725 #endif /* FSL_FEATURE_ADC_HAS_CALIBRATION */
727 #if FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION
730 * @brief Gets the offset correction value for the ADC module.
732 * This function gets the offset correction value for the ADC module.
733 * When auto calibration is executed, the OFS register holds the new value
734 * generated by the calibration. It can be left as default or modified
735 * according to the use case.
737 * @param baseAddr Register base address for the module.
738 * @return current value for OFS.
740 static inline uint16_t ADC_HAL_GetOffsetValue(uint32_t baseAddr)
742 return (uint16_t)(BR_ADC_OFS_OFS(baseAddr) );
746 * @brief Sets the offset correction value for the ADC module.
748 * This function sets the offset correction value for the ADC module. The ADC
749 * offset correction register (OFS) contains the user-selected or calibration-generated
750 * offset error correction value. The value in the offset correction
751 * registers (OFS) is subtracted from the conversion and the result is
752 * transferred into the result registers (Rn). If the result is above the
753 * maximum or below the minimum result value, it is forced to the appropriate
754 * limit for the current mode of operation.
756 * @param baseAddr Register base address for the module.
757 * @param value Setting value for OFS.
759 static inline void ADC_HAL_SetOffsetValue(uint32_t baseAddr, uint16_t value)
761 BW_ADC_OFS_OFS(baseAddr, value);
764 #endif /* FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION */
767 * @brief Switches to enable the continuous conversion mode for the ADC module.
769 * This function switches to enable the continuous conversion mode for the ADC
770 * module. Once enabled, continuous conversions, or sets of conversions if the
771 * hardware average function, is enabled after initiating a conversion.
773 * @param baseAddr Register base address for the module.
774 * @param enable Switcher to asserted the feature.
776 static inline void ADC_HAL_SetContinuousConvCmd(uint32_t baseAddr, bool enable)
778 BW_ADC_SC3_ADCO(baseAddr, (enable ? 1U : 0U) );
781 #if FSL_FEATURE_ADC_HAS_HW_AVERAGE
784 * @brief Switches to enable the hardware average for the ADC module.
786 * This function switches to enable the hardware average for the ADC module.
787 * Once enabled, the conversion does not stop before the average
788 * count has been reached.
790 * @param baseAddr Register base address for the module.
791 * @param enable Switcher to asserted the feature.
793 static inline void ADC_HAL_SetHwAverageCmd(uint32_t baseAddr, bool enable)
795 BW_ADC_SC3_AVGE(baseAddr, (enable ? 1U : 0U) );
799 * @brief Selects the hardware average mode for the ADC module.
801 * This function switches to select the hardware average mode for the ADC
804 * @param baseAddr Register base address for the module.
805 * @param mode Selection of hardware average count mode, see to "adc_hw_average_count_mode_t".
807 static inline void ADC_HAL_SetHwAverageMode(uint32_t baseAddr, adc_hw_average_count_mode_t mode)
809 BW_ADC_SC3_AVGS(baseAddr, (uint32_t)mode );
812 #endif /* FSL_FEATURE_ADC_HAS_HW_AVERAGE */
814 #if FSL_FEATURE_ADC_HAS_PGA
817 * @brief Switches to enable the Programmable Gain Amplifier for ADC module.
819 * This function enables the PGA for the ADC module. The Programmable Gain
820 * Amplifier (PGA) is designed to increase the dynamic range by amplifying the
821 * low-amplitude signals before they are fed to the 16 bit SAR ADC.
823 * @param baseAddr Register base address for the module.
824 * @param enable Switcher to asserted feature.
826 static inline void ADC_HAL_SetPgaCmd(uint32_t baseAddr, bool enable)
828 BW_ADC_PGA_PGAEN(baseAddr, (enable ? 1U : 0U) );
832 * @brief Switches to enable the PGA chopping mode for the ADC module.
834 * This function switches to enable the PGA chopping mode for the ADC module.
835 * The PGA employs chopping to remove/reduce offset and 1/f noise and offers an
836 * offset measurement configuration that aids the offset calibration.
838 * @param baseAddr Register base address for the module.
839 * @param enable Switcher to asserted feature.
841 static inline void ADC_HAL_SetPgaChoppingCmd(uint32_t baseAddr, bool enable)
843 BW_ADC_PGA_PGACHPb(baseAddr, (enable ? 0U : 1U) );
847 * @brief Switches to enable the PGA working in low power mode for the ADC module.
849 * This function switches to enable the PGA working in low power mode for
852 * @param baseAddr Register base address for the module.
853 * @param enable Switcher to asserted feature.
855 static inline void ADC_HAL_SetPgaLowPowerCmd(uint32_t baseAddr, bool enable)
857 BW_ADC_PGA_PGALPb(baseAddr, (enable ? 0U : 1U) );
861 * @brief Selects the amplifier mode for the PGA.
863 * This function selects the amplifier mode for the PGA.
865 * @param baseAddr Register base address for the module.
866 * @param mode Selection of asserted feature. See to "adc_pga_gain_mode_t".
868 static inline void ADC_HAL_SetPgaGainMode(uint32_t baseAddr, adc_pga_gain_mode_t mode)
870 BW_ADC_PGA_PGAG(baseAddr, (uint32_t)mode );
874 * @brief Switches to enable the offset measurement mode for the ADC module.
876 * This function switches to enable the offset measurement mode for the ADC
877 * module. When asserted, the PGA disconnects from the external inputs and
878 * auto-configures into offset measurement mode. With this function asserted,
879 * run the ADC in recommended settings and enable maximum hardware averaging
880 * to get the PGA offset number. The output is the (PGA offset * (64+1))
881 * for a given setting.
883 * @param baseAddr Register base address for the module.
884 * @param enable Switcher to asserted feature.
886 static inline void ADC_HAL_SetPgaOffsetMeasurementCmd(uint32_t baseAddr, bool enable)
888 BW_ADC_PGA_PGAOFSM(baseAddr, (enable ? 1U : 0U) );
891 #endif /* FSL_FEATURE_ADC_HAS_PGA */
893 #if defined(__cplusplus)
901 #endif /* __FSL_ADC_HAL_H__ */
903 /******************************************************************************
905 *****************************************************************************/