2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
9 ** Version: rev. 2.5, 2014-05-06
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-07-23)
49 ** - rev. 1.1 (2013-09-17)
50 ** RM rev. 0.4 update.
51 ** - rev. 2.0 (2013-10-29)
52 ** Register accessor macros added to the memory map.
53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
54 ** Startup file for gcc has been updated according to CMSIS 3.2.
55 ** System initialization updated.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-20)
59 ** Update according to reference manual rev. 0.6,
60 ** - rev. 2.3 (2014-01-13)
61 ** Update according to reference manual rev. 0.61,
62 ** - rev. 2.4 (2014-02-10)
63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
64 ** - rev. 2.5 (2014-05-06)
65 ** Update according to reference manual rev. 1.0,
66 ** Update of system and startup files.
67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
69 ** ###################################################################
73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
75 * This file was generated automatically and any changes may be lost.
77 #ifndef __HW_SPI_REGISTERS_H__
78 #define __HW_SPI_REGISTERS_H__
80 #include "MK22F51212.h"
81 #include "fsl_bitaccess.h"
86 * Serial Peripheral Interface
88 * Registers defined in this header file:
89 * - HW_SPI_MCR - Module Configuration Register
90 * - HW_SPI_TCR - Transfer Count Register
91 * - HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
92 * - HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
93 * - HW_SPI_SR - Status Register
94 * - HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
95 * - HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
96 * - HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
97 * - HW_SPI_POPR - POP RX FIFO Register
98 * - HW_SPI_TXFRn - Transmit FIFO Registers
99 * - HW_SPI_RXFRn - Receive FIFO Registers
101 * - hw_spi_t - Struct containing all module registers.
104 #define HW_SPI_INSTANCE_COUNT (2U) /*!< Number of instances of the SPI module. */
105 #define HW_SPI0 (0U) /*!< Instance number for SPI0. */
106 #define HW_SPI1 (1U) /*!< Instance number for SPI1. */
108 /*******************************************************************************
109 * HW_SPI_MCR - Module Configuration Register
110 ******************************************************************************/
113 * @brief HW_SPI_MCR - Module Configuration Register (RW)
115 * Reset value: 0x00004001U
117 * Contains bits to configure various attributes associated with the module
118 * operations. The HALT and MDIS bits can be changed at any time, but the effect
119 * takes place only on the next frame boundary. Only the HALT and MDIS bits in the
120 * MCR can be changed, while the module is in the Running state.
122 typedef union _hw_spi_mcr
125 struct _hw_spi_mcr_bitfields
127 uint32_t HALT : 1; /*!< [0] Halt */
128 uint32_t RESERVED0 : 7; /*!< [7:1] */
129 uint32_t SMPL_PT : 2; /*!< [9:8] Sample Point */
130 uint32_t CLR_RXF : 1; /*!< [10] */
131 uint32_t CLR_TXF : 1; /*!< [11] Clear TX FIFO */
132 uint32_t DIS_RXF : 1; /*!< [12] Disable Receive FIFO */
133 uint32_t DIS_TXF : 1; /*!< [13] Disable Transmit FIFO */
134 uint32_t MDIS : 1; /*!< [14] Module Disable */
135 uint32_t DOZE : 1; /*!< [15] Doze Enable */
136 uint32_t PCSIS : 6; /*!< [21:16] Peripheral Chip Select x Inactive
138 uint32_t RESERVED1 : 2; /*!< [23:22] */
139 uint32_t ROOE : 1; /*!< [24] Receive FIFO Overflow Overwrite Enable */
140 uint32_t PCSSE : 1; /*!< [25] Peripheral Chip Select Strobe Enable */
141 uint32_t MTFE : 1; /*!< [26] Modified Timing Format Enable */
142 uint32_t FRZ : 1; /*!< [27] Freeze */
143 uint32_t DCONF : 2; /*!< [29:28] SPI Configuration. */
144 uint32_t CONT_SCKE : 1; /*!< [30] Continuous SCK Enable */
145 uint32_t MSTR : 1; /*!< [31] Master/Slave Mode Select */
150 * @name Constants and macros for entire SPI_MCR register
153 #define HW_SPI_MCR_ADDR(x) ((x) + 0x0U)
155 #define HW_SPI_MCR(x) (*(__IO hw_spi_mcr_t *) HW_SPI_MCR_ADDR(x))
156 #define HW_SPI_MCR_RD(x) (HW_SPI_MCR(x).U)
157 #define HW_SPI_MCR_WR(x, v) (HW_SPI_MCR(x).U = (v))
158 #define HW_SPI_MCR_SET(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) | (v)))
159 #define HW_SPI_MCR_CLR(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) & ~(v)))
160 #define HW_SPI_MCR_TOG(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) ^ (v)))
164 * Constants & macros for individual SPI_MCR bitfields
168 * @name Register SPI_MCR, field HALT[0] (RW)
170 * The HALT bit starts and stops frame transfers. See Start and Stop of Module
174 * - 0 - Start transfers.
175 * - 1 - Stop transfers.
178 #define BP_SPI_MCR_HALT (0U) /*!< Bit position for SPI_MCR_HALT. */
179 #define BM_SPI_MCR_HALT (0x00000001U) /*!< Bit mask for SPI_MCR_HALT. */
180 #define BS_SPI_MCR_HALT (1U) /*!< Bit field size in bits for SPI_MCR_HALT. */
182 /*! @brief Read current value of the SPI_MCR_HALT field. */
183 #define BR_SPI_MCR_HALT(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT))
185 /*! @brief Format value for bitfield SPI_MCR_HALT. */
186 #define BF_SPI_MCR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_HALT) & BM_SPI_MCR_HALT)
188 /*! @brief Set the HALT field to a new value. */
189 #define BW_SPI_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT) = (v))
193 * @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
195 * Controls when the module master samples SIN in Modified Transfer Format. This
196 * field is valid only when CPHA bit in CTARn[CPHA] is 0.
199 * - 00 - 0 protocol clock cycles between SCK edge and SIN sample
200 * - 01 - 1 protocol clock cycle between SCK edge and SIN sample
201 * - 10 - 2 protocol clock cycles between SCK edge and SIN sample
205 #define BP_SPI_MCR_SMPL_PT (8U) /*!< Bit position for SPI_MCR_SMPL_PT. */
206 #define BM_SPI_MCR_SMPL_PT (0x00000300U) /*!< Bit mask for SPI_MCR_SMPL_PT. */
207 #define BS_SPI_MCR_SMPL_PT (2U) /*!< Bit field size in bits for SPI_MCR_SMPL_PT. */
209 /*! @brief Read current value of the SPI_MCR_SMPL_PT field. */
210 #define BR_SPI_MCR_SMPL_PT(x) (HW_SPI_MCR(x).B.SMPL_PT)
212 /*! @brief Format value for bitfield SPI_MCR_SMPL_PT. */
213 #define BF_SPI_MCR_SMPL_PT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_SMPL_PT) & BM_SPI_MCR_SMPL_PT)
215 /*! @brief Set the SMPL_PT field to a new value. */
216 #define BW_SPI_MCR_SMPL_PT(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_SMPL_PT) | BF_SPI_MCR_SMPL_PT(v)))
220 * @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
222 * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
223 * CLR_RXF bit is always read as zero.
226 * - 0 - Do not clear the RX FIFO counter.
227 * - 1 - Clear the RX FIFO counter.
230 #define BP_SPI_MCR_CLR_RXF (10U) /*!< Bit position for SPI_MCR_CLR_RXF. */
231 #define BM_SPI_MCR_CLR_RXF (0x00000400U) /*!< Bit mask for SPI_MCR_CLR_RXF. */
232 #define BS_SPI_MCR_CLR_RXF (1U) /*!< Bit field size in bits for SPI_MCR_CLR_RXF. */
234 /*! @brief Format value for bitfield SPI_MCR_CLR_RXF. */
235 #define BF_SPI_MCR_CLR_RXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CLR_RXF) & BM_SPI_MCR_CLR_RXF)
237 /*! @brief Set the CLR_RXF field to a new value. */
238 #define BW_SPI_MCR_CLR_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_RXF) = (v))
242 * @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
244 * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
245 * CLR_TXF bit is always read as zero.
248 * - 0 - Do not clear the TX FIFO counter.
249 * - 1 - Clear the TX FIFO counter.
252 #define BP_SPI_MCR_CLR_TXF (11U) /*!< Bit position for SPI_MCR_CLR_TXF. */
253 #define BM_SPI_MCR_CLR_TXF (0x00000800U) /*!< Bit mask for SPI_MCR_CLR_TXF. */
254 #define BS_SPI_MCR_CLR_TXF (1U) /*!< Bit field size in bits for SPI_MCR_CLR_TXF. */
256 /*! @brief Format value for bitfield SPI_MCR_CLR_TXF. */
257 #define BF_SPI_MCR_CLR_TXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CLR_TXF) & BM_SPI_MCR_CLR_TXF)
259 /*! @brief Set the CLR_TXF field to a new value. */
260 #define BW_SPI_MCR_CLR_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_TXF) = (v))
264 * @name Register SPI_MCR, field DIS_RXF[12] (RW)
266 * When the RX FIFO is disabled, the receive part of the module operates as a
267 * simplified double-buffered SPI. This bit can only be written when the MDIS bit
271 * - 0 - RX FIFO is enabled.
272 * - 1 - RX FIFO is disabled.
275 #define BP_SPI_MCR_DIS_RXF (12U) /*!< Bit position for SPI_MCR_DIS_RXF. */
276 #define BM_SPI_MCR_DIS_RXF (0x00001000U) /*!< Bit mask for SPI_MCR_DIS_RXF. */
277 #define BS_SPI_MCR_DIS_RXF (1U) /*!< Bit field size in bits for SPI_MCR_DIS_RXF. */
279 /*! @brief Read current value of the SPI_MCR_DIS_RXF field. */
280 #define BR_SPI_MCR_DIS_RXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF))
282 /*! @brief Format value for bitfield SPI_MCR_DIS_RXF. */
283 #define BF_SPI_MCR_DIS_RXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DIS_RXF) & BM_SPI_MCR_DIS_RXF)
285 /*! @brief Set the DIS_RXF field to a new value. */
286 #define BW_SPI_MCR_DIS_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF) = (v))
290 * @name Register SPI_MCR, field DIS_TXF[13] (RW)
292 * When the TX FIFO is disabled, the transmit part of the module operates as a
293 * simplified double-buffered SPI. This bit can be written only when the MDIS bit
297 * - 0 - TX FIFO is enabled.
298 * - 1 - TX FIFO is disabled.
301 #define BP_SPI_MCR_DIS_TXF (13U) /*!< Bit position for SPI_MCR_DIS_TXF. */
302 #define BM_SPI_MCR_DIS_TXF (0x00002000U) /*!< Bit mask for SPI_MCR_DIS_TXF. */
303 #define BS_SPI_MCR_DIS_TXF (1U) /*!< Bit field size in bits for SPI_MCR_DIS_TXF. */
305 /*! @brief Read current value of the SPI_MCR_DIS_TXF field. */
306 #define BR_SPI_MCR_DIS_TXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF))
308 /*! @brief Format value for bitfield SPI_MCR_DIS_TXF. */
309 #define BF_SPI_MCR_DIS_TXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DIS_TXF) & BM_SPI_MCR_DIS_TXF)
311 /*! @brief Set the DIS_TXF field to a new value. */
312 #define BW_SPI_MCR_DIS_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF) = (v))
316 * @name Register SPI_MCR, field MDIS[14] (RW)
318 * Allows the clock to be stopped to the non-memory mapped logic in the module
319 * effectively putting it in a software-controlled power-saving state. The reset
320 * value of the MDIS bit is parameterized, with a default reset value of 0. When
321 * the module is used in Slave Mode, we recommend leaving this bit 0, because a
322 * slave doesn't have control over master transactions.
325 * - 0 - Enables the module clocks.
326 * - 1 - Allows external logic to disable the module clocks.
329 #define BP_SPI_MCR_MDIS (14U) /*!< Bit position for SPI_MCR_MDIS. */
330 #define BM_SPI_MCR_MDIS (0x00004000U) /*!< Bit mask for SPI_MCR_MDIS. */
331 #define BS_SPI_MCR_MDIS (1U) /*!< Bit field size in bits for SPI_MCR_MDIS. */
333 /*! @brief Read current value of the SPI_MCR_MDIS field. */
334 #define BR_SPI_MCR_MDIS(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS))
336 /*! @brief Format value for bitfield SPI_MCR_MDIS. */
337 #define BF_SPI_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MDIS) & BM_SPI_MCR_MDIS)
339 /*! @brief Set the MDIS field to a new value. */
340 #define BW_SPI_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS) = (v))
344 * @name Register SPI_MCR, field DOZE[15] (RW)
346 * Provides support for an externally controlled Doze mode power-saving
350 * - 0 - Doze mode has no effect on the module.
351 * - 1 - Doze mode disables the module.
354 #define BP_SPI_MCR_DOZE (15U) /*!< Bit position for SPI_MCR_DOZE. */
355 #define BM_SPI_MCR_DOZE (0x00008000U) /*!< Bit mask for SPI_MCR_DOZE. */
356 #define BS_SPI_MCR_DOZE (1U) /*!< Bit field size in bits for SPI_MCR_DOZE. */
358 /*! @brief Read current value of the SPI_MCR_DOZE field. */
359 #define BR_SPI_MCR_DOZE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE))
361 /*! @brief Format value for bitfield SPI_MCR_DOZE. */
362 #define BF_SPI_MCR_DOZE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DOZE) & BM_SPI_MCR_DOZE)
364 /*! @brief Set the DOZE field to a new value. */
365 #define BW_SPI_MCR_DOZE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE) = (v))
369 * @name Register SPI_MCR, field PCSIS[21:16] (RW)
371 * Determines the inactive state of PCSx.
374 * - 0 - The inactive state of PCSx is low.
375 * - 1 - The inactive state of PCSx is high.
378 #define BP_SPI_MCR_PCSIS (16U) /*!< Bit position for SPI_MCR_PCSIS. */
379 #define BM_SPI_MCR_PCSIS (0x003F0000U) /*!< Bit mask for SPI_MCR_PCSIS. */
380 #define BS_SPI_MCR_PCSIS (6U) /*!< Bit field size in bits for SPI_MCR_PCSIS. */
382 /*! @brief Read current value of the SPI_MCR_PCSIS field. */
383 #define BR_SPI_MCR_PCSIS(x) (HW_SPI_MCR(x).B.PCSIS)
385 /*! @brief Format value for bitfield SPI_MCR_PCSIS. */
386 #define BF_SPI_MCR_PCSIS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_PCSIS) & BM_SPI_MCR_PCSIS)
388 /*! @brief Set the PCSIS field to a new value. */
389 #define BW_SPI_MCR_PCSIS(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_PCSIS) | BF_SPI_MCR_PCSIS(v)))
393 * @name Register SPI_MCR, field ROOE[24] (RW)
395 * In the RX FIFO overflow condition, configures the module to ignore the
396 * incoming serial data or overwrite existing data. If the RX FIFO is full and new data
397 * is received, the data from the transfer, generating the overflow, is ignored
398 * or shifted into the shift register.
401 * - 0 - Incoming data is ignored.
402 * - 1 - Incoming data is shifted into the shift register.
405 #define BP_SPI_MCR_ROOE (24U) /*!< Bit position for SPI_MCR_ROOE. */
406 #define BM_SPI_MCR_ROOE (0x01000000U) /*!< Bit mask for SPI_MCR_ROOE. */
407 #define BS_SPI_MCR_ROOE (1U) /*!< Bit field size in bits for SPI_MCR_ROOE. */
409 /*! @brief Read current value of the SPI_MCR_ROOE field. */
410 #define BR_SPI_MCR_ROOE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE))
412 /*! @brief Format value for bitfield SPI_MCR_ROOE. */
413 #define BF_SPI_MCR_ROOE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_ROOE) & BM_SPI_MCR_ROOE)
415 /*! @brief Set the ROOE field to a new value. */
416 #define BW_SPI_MCR_ROOE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE) = (v))
420 * @name Register SPI_MCR, field PCSSE[25] (RW)
422 * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
425 * - 0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
426 * - 1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
429 #define BP_SPI_MCR_PCSSE (25U) /*!< Bit position for SPI_MCR_PCSSE. */
430 #define BM_SPI_MCR_PCSSE (0x02000000U) /*!< Bit mask for SPI_MCR_PCSSE. */
431 #define BS_SPI_MCR_PCSSE (1U) /*!< Bit field size in bits for SPI_MCR_PCSSE. */
433 /*! @brief Read current value of the SPI_MCR_PCSSE field. */
434 #define BR_SPI_MCR_PCSSE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE))
436 /*! @brief Format value for bitfield SPI_MCR_PCSSE. */
437 #define BF_SPI_MCR_PCSSE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_PCSSE) & BM_SPI_MCR_PCSSE)
439 /*! @brief Set the PCSSE field to a new value. */
440 #define BW_SPI_MCR_PCSSE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE) = (v))
444 * @name Register SPI_MCR, field MTFE[26] (RW)
446 * Enables a modified transfer format to be used.
449 * - 0 - Modified SPI transfer format disabled.
450 * - 1 - Modified SPI transfer format enabled.
453 #define BP_SPI_MCR_MTFE (26U) /*!< Bit position for SPI_MCR_MTFE. */
454 #define BM_SPI_MCR_MTFE (0x04000000U) /*!< Bit mask for SPI_MCR_MTFE. */
455 #define BS_SPI_MCR_MTFE (1U) /*!< Bit field size in bits for SPI_MCR_MTFE. */
457 /*! @brief Read current value of the SPI_MCR_MTFE field. */
458 #define BR_SPI_MCR_MTFE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE))
460 /*! @brief Format value for bitfield SPI_MCR_MTFE. */
461 #define BF_SPI_MCR_MTFE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MTFE) & BM_SPI_MCR_MTFE)
463 /*! @brief Set the MTFE field to a new value. */
464 #define BW_SPI_MCR_MTFE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE) = (v))
468 * @name Register SPI_MCR, field FRZ[27] (RW)
470 * Enables transfers to be stopped on the next frame boundary when the device
474 * - 0 - Do not halt serial transfers in Debug mode.
475 * - 1 - Halt serial transfers in Debug mode.
478 #define BP_SPI_MCR_FRZ (27U) /*!< Bit position for SPI_MCR_FRZ. */
479 #define BM_SPI_MCR_FRZ (0x08000000U) /*!< Bit mask for SPI_MCR_FRZ. */
480 #define BS_SPI_MCR_FRZ (1U) /*!< Bit field size in bits for SPI_MCR_FRZ. */
482 /*! @brief Read current value of the SPI_MCR_FRZ field. */
483 #define BR_SPI_MCR_FRZ(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ))
485 /*! @brief Format value for bitfield SPI_MCR_FRZ. */
486 #define BF_SPI_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_FRZ) & BM_SPI_MCR_FRZ)
488 /*! @brief Set the FRZ field to a new value. */
489 #define BW_SPI_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ) = (v))
493 * @name Register SPI_MCR, field DCONF[29:28] (RO)
495 * Selects among the different configurations of the module.
504 #define BP_SPI_MCR_DCONF (28U) /*!< Bit position for SPI_MCR_DCONF. */
505 #define BM_SPI_MCR_DCONF (0x30000000U) /*!< Bit mask for SPI_MCR_DCONF. */
506 #define BS_SPI_MCR_DCONF (2U) /*!< Bit field size in bits for SPI_MCR_DCONF. */
508 /*! @brief Read current value of the SPI_MCR_DCONF field. */
509 #define BR_SPI_MCR_DCONF(x) (HW_SPI_MCR(x).B.DCONF)
513 * @name Register SPI_MCR, field CONT_SCKE[30] (RW)
515 * Enables the Serial Communication Clock (SCK) to run continuously.
518 * - 0 - Continuous SCK disabled.
519 * - 1 - Continuous SCK enabled.
522 #define BP_SPI_MCR_CONT_SCKE (30U) /*!< Bit position for SPI_MCR_CONT_SCKE. */
523 #define BM_SPI_MCR_CONT_SCKE (0x40000000U) /*!< Bit mask for SPI_MCR_CONT_SCKE. */
524 #define BS_SPI_MCR_CONT_SCKE (1U) /*!< Bit field size in bits for SPI_MCR_CONT_SCKE. */
526 /*! @brief Read current value of the SPI_MCR_CONT_SCKE field. */
527 #define BR_SPI_MCR_CONT_SCKE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE))
529 /*! @brief Format value for bitfield SPI_MCR_CONT_SCKE. */
530 #define BF_SPI_MCR_CONT_SCKE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CONT_SCKE) & BM_SPI_MCR_CONT_SCKE)
532 /*! @brief Set the CONT_SCKE field to a new value. */
533 #define BW_SPI_MCR_CONT_SCKE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE) = (v))
537 * @name Register SPI_MCR, field MSTR[31] (RW)
539 * Enables either Master mode (if supported) or Slave mode (if supported)
543 * - 0 - Enables Slave mode
544 * - 1 - Enables Master mode
547 #define BP_SPI_MCR_MSTR (31U) /*!< Bit position for SPI_MCR_MSTR. */
548 #define BM_SPI_MCR_MSTR (0x80000000U) /*!< Bit mask for SPI_MCR_MSTR. */
549 #define BS_SPI_MCR_MSTR (1U) /*!< Bit field size in bits for SPI_MCR_MSTR. */
551 /*! @brief Read current value of the SPI_MCR_MSTR field. */
552 #define BR_SPI_MCR_MSTR(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR))
554 /*! @brief Format value for bitfield SPI_MCR_MSTR. */
555 #define BF_SPI_MCR_MSTR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MSTR) & BM_SPI_MCR_MSTR)
557 /*! @brief Set the MSTR field to a new value. */
558 #define BW_SPI_MCR_MSTR(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR) = (v))
561 /*******************************************************************************
562 * HW_SPI_TCR - Transfer Count Register
563 ******************************************************************************/
566 * @brief HW_SPI_TCR - Transfer Count Register (RW)
568 * Reset value: 0x00000000U
570 * TCR contains a counter that indicates the number of SPI transfers made. The
571 * transfer counter is intended to assist in queue management. Do not write the
572 * TCR when the module is in the Running state.
574 typedef union _hw_spi_tcr
577 struct _hw_spi_tcr_bitfields
579 uint32_t RESERVED0 : 16; /*!< [15:0] */
580 uint32_t SPI_TCNT : 16; /*!< [31:16] SPI Transfer Counter */
585 * @name Constants and macros for entire SPI_TCR register
588 #define HW_SPI_TCR_ADDR(x) ((x) + 0x8U)
590 #define HW_SPI_TCR(x) (*(__IO hw_spi_tcr_t *) HW_SPI_TCR_ADDR(x))
591 #define HW_SPI_TCR_RD(x) (HW_SPI_TCR(x).U)
592 #define HW_SPI_TCR_WR(x, v) (HW_SPI_TCR(x).U = (v))
593 #define HW_SPI_TCR_SET(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) | (v)))
594 #define HW_SPI_TCR_CLR(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) & ~(v)))
595 #define HW_SPI_TCR_TOG(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) ^ (v)))
599 * Constants & macros for individual SPI_TCR bitfields
603 * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
605 * Counts the number of SPI transfers the module makes. The SPI_TCNT field
606 * increments every time the last bit of an SPI frame is transmitted. A value written
607 * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
608 * the beginning of the frame when the CTCNT field is set in the executing SPI
609 * command. The Transfer Counter wraps around; incrementing the counter past 65535
610 * resets the counter to zero.
613 #define BP_SPI_TCR_SPI_TCNT (16U) /*!< Bit position for SPI_TCR_SPI_TCNT. */
614 #define BM_SPI_TCR_SPI_TCNT (0xFFFF0000U) /*!< Bit mask for SPI_TCR_SPI_TCNT. */
615 #define BS_SPI_TCR_SPI_TCNT (16U) /*!< Bit field size in bits for SPI_TCR_SPI_TCNT. */
617 /*! @brief Read current value of the SPI_TCR_SPI_TCNT field. */
618 #define BR_SPI_TCR_SPI_TCNT(x) (HW_SPI_TCR(x).B.SPI_TCNT)
620 /*! @brief Format value for bitfield SPI_TCR_SPI_TCNT. */
621 #define BF_SPI_TCR_SPI_TCNT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_TCR_SPI_TCNT) & BM_SPI_TCR_SPI_TCNT)
623 /*! @brief Set the SPI_TCNT field to a new value. */
624 #define BW_SPI_TCR_SPI_TCNT(x, v) (HW_SPI_TCR_WR(x, (HW_SPI_TCR_RD(x) & ~BM_SPI_TCR_SPI_TCNT) | BF_SPI_TCR_SPI_TCNT(v)))
627 /*******************************************************************************
628 * HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
629 ******************************************************************************/
632 * @brief HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) (RW)
634 * Reset value: 0x78000000U
636 * CTAR registers are used to define different transfer attributes. Do not write
637 * to the CTAR registers while the module is in the Running state. In Master
638 * mode, the CTAR registers define combinations of transfer attributes such as frame
639 * size, clock phase and polarity, data bit ordering, baud rate, and various
640 * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
641 * slave transfer attributes. When the module is configured as an SPI master, the
642 * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
643 * registers is used. When the module is configured as an SPI bus slave, it uses
644 * the CTAR0 register.
646 typedef union _hw_spi_ctarn
649 struct _hw_spi_ctarn_bitfields
651 uint32_t BR : 4; /*!< [3:0] Baud Rate Scaler */
652 uint32_t DT : 4; /*!< [7:4] Delay After Transfer Scaler */
653 uint32_t ASC : 4; /*!< [11:8] After SCK Delay Scaler */
654 uint32_t CSSCK : 4; /*!< [15:12] PCS to SCK Delay Scaler */
655 uint32_t PBR : 2; /*!< [17:16] Baud Rate Prescaler */
656 uint32_t PDT : 2; /*!< [19:18] Delay after Transfer Prescaler */
657 uint32_t PASC : 2; /*!< [21:20] After SCK Delay Prescaler */
658 uint32_t PCSSCK : 2; /*!< [23:22] PCS to SCK Delay Prescaler */
659 uint32_t LSBFE : 1; /*!< [24] LSB First */
660 uint32_t CPHA : 1; /*!< [25] Clock Phase */
661 uint32_t CPOL : 1; /*!< [26] Clock Polarity */
662 uint32_t FMSZ : 4; /*!< [30:27] Frame Size */
663 uint32_t DBR : 1; /*!< [31] Double Baud Rate */
668 * @name Constants and macros for entire SPI_CTARn register
671 #define HW_SPI_CTARn_COUNT (2U)
673 #define HW_SPI_CTARn_ADDR(x, n) ((x) + 0xCU + (0x4U * (n)))
675 #define HW_SPI_CTARn(x, n) (*(__IO hw_spi_ctarn_t *) HW_SPI_CTARn_ADDR(x, n))
676 #define HW_SPI_CTARn_RD(x, n) (HW_SPI_CTARn(x, n).U)
677 #define HW_SPI_CTARn_WR(x, n, v) (HW_SPI_CTARn(x, n).U = (v))
678 #define HW_SPI_CTARn_SET(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) | (v)))
679 #define HW_SPI_CTARn_CLR(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) & ~(v)))
680 #define HW_SPI_CTARn_TOG(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) ^ (v)))
684 * Constants & macros for individual SPI_CTARn bitfields
688 * @name Register SPI_CTARn, field BR[3:0] (RW)
690 * Selects the scaler value for the baud rate. This field is used only in master
691 * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
692 * generate the frequency of the SCK. The baud rate is computed according to the
693 * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
694 * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
695 * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
696 * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
699 #define BP_SPI_CTARn_BR (0U) /*!< Bit position for SPI_CTARn_BR. */
700 #define BM_SPI_CTARn_BR (0x0000000FU) /*!< Bit mask for SPI_CTARn_BR. */
701 #define BS_SPI_CTARn_BR (4U) /*!< Bit field size in bits for SPI_CTARn_BR. */
703 /*! @brief Read current value of the SPI_CTARn_BR field. */
704 #define BR_SPI_CTARn_BR(x, n) (HW_SPI_CTARn(x, n).B.BR)
706 /*! @brief Format value for bitfield SPI_CTARn_BR. */
707 #define BF_SPI_CTARn_BR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_BR) & BM_SPI_CTARn_BR)
709 /*! @brief Set the BR field to a new value. */
710 #define BW_SPI_CTARn_BR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_BR) | BF_SPI_CTARn_BR(v)))
714 * @name Register SPI_CTARn, field DT[7:4] (RW)
716 * Selects the Delay after Transfer Scaler. This field is used only in master
717 * mode. The Delay after Transfer is the time between the negation of the PCS
718 * signal at the end of a frame and the assertion of PCS at the beginning of the next
719 * frame. In the Continuous Serial Communications Clock operation, the DT value
720 * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
721 * protocol clock period, and it is computed according to the following
722 * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
723 * field description for scaler values.
726 #define BP_SPI_CTARn_DT (4U) /*!< Bit position for SPI_CTARn_DT. */
727 #define BM_SPI_CTARn_DT (0x000000F0U) /*!< Bit mask for SPI_CTARn_DT. */
728 #define BS_SPI_CTARn_DT (4U) /*!< Bit field size in bits for SPI_CTARn_DT. */
730 /*! @brief Read current value of the SPI_CTARn_DT field. */
731 #define BR_SPI_CTARn_DT(x, n) (HW_SPI_CTARn(x, n).B.DT)
733 /*! @brief Format value for bitfield SPI_CTARn_DT. */
734 #define BF_SPI_CTARn_DT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_DT) & BM_SPI_CTARn_DT)
736 /*! @brief Set the DT field to a new value. */
737 #define BW_SPI_CTARn_DT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_DT) | BF_SPI_CTARn_DT(v)))
741 * @name Register SPI_CTARn, field ASC[11:8] (RW)
743 * Selects the scaler value for the After SCK Delay. This field is used only in
744 * master mode. The After SCK Delay is the delay between the last edge of SCK and
745 * the negation of PCS. The delay is a multiple of the protocol clock period,
746 * and it is computed according to the following equation: t ASC = (1/fP) x PASC x
747 * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
748 * scaler values. Refer After SCK Delay (tASC ) for more details.
751 #define BP_SPI_CTARn_ASC (8U) /*!< Bit position for SPI_CTARn_ASC. */
752 #define BM_SPI_CTARn_ASC (0x00000F00U) /*!< Bit mask for SPI_CTARn_ASC. */
753 #define BS_SPI_CTARn_ASC (4U) /*!< Bit field size in bits for SPI_CTARn_ASC. */
755 /*! @brief Read current value of the SPI_CTARn_ASC field. */
756 #define BR_SPI_CTARn_ASC(x, n) (HW_SPI_CTARn(x, n).B.ASC)
758 /*! @brief Format value for bitfield SPI_CTARn_ASC. */
759 #define BF_SPI_CTARn_ASC(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_ASC) & BM_SPI_CTARn_ASC)
761 /*! @brief Set the ASC field to a new value. */
762 #define BW_SPI_CTARn_ASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_ASC) | BF_SPI_CTARn_ASC(v)))
766 * @name Register SPI_CTARn, field CSSCK[15:12] (RW)
768 * Selects the scaler value for the PCS to SCK delay. This field is used only in
769 * master mode. The PCS to SCK Delay is the delay between the assertion of PCS
770 * and the first edge of the SCK. The delay is a multiple of the protocol clock
771 * period, and it is computed according to the following equation: t CSC = (1/fP )
772 * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
773 * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
774 * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
775 * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
779 #define BP_SPI_CTARn_CSSCK (12U) /*!< Bit position for SPI_CTARn_CSSCK. */
780 #define BM_SPI_CTARn_CSSCK (0x0000F000U) /*!< Bit mask for SPI_CTARn_CSSCK. */
781 #define BS_SPI_CTARn_CSSCK (4U) /*!< Bit field size in bits for SPI_CTARn_CSSCK. */
783 /*! @brief Read current value of the SPI_CTARn_CSSCK field. */
784 #define BR_SPI_CTARn_CSSCK(x, n) (HW_SPI_CTARn(x, n).B.CSSCK)
786 /*! @brief Format value for bitfield SPI_CTARn_CSSCK. */
787 #define BF_SPI_CTARn_CSSCK(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CSSCK) & BM_SPI_CTARn_CSSCK)
789 /*! @brief Set the CSSCK field to a new value. */
790 #define BW_SPI_CTARn_CSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_CSSCK) | BF_SPI_CTARn_CSSCK(v)))
794 * @name Register SPI_CTARn, field PBR[17:16] (RW)
796 * Selects the prescaler value for the baud rate. This field is used only in
797 * master mode. The baud rate is the frequency of the SCK. The protocol clock is
798 * divided by the prescaler value before the baud rate selection takes place. See
799 * the BR field description for details on how to compute the baud rate.
802 * - 00 - Baud Rate Prescaler value is 2.
803 * - 01 - Baud Rate Prescaler value is 3.
804 * - 10 - Baud Rate Prescaler value is 5.
805 * - 11 - Baud Rate Prescaler value is 7.
808 #define BP_SPI_CTARn_PBR (16U) /*!< Bit position for SPI_CTARn_PBR. */
809 #define BM_SPI_CTARn_PBR (0x00030000U) /*!< Bit mask for SPI_CTARn_PBR. */
810 #define BS_SPI_CTARn_PBR (2U) /*!< Bit field size in bits for SPI_CTARn_PBR. */
812 /*! @brief Read current value of the SPI_CTARn_PBR field. */
813 #define BR_SPI_CTARn_PBR(x, n) (HW_SPI_CTARn(x, n).B.PBR)
815 /*! @brief Format value for bitfield SPI_CTARn_PBR. */
816 #define BF_SPI_CTARn_PBR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PBR) & BM_SPI_CTARn_PBR)
818 /*! @brief Set the PBR field to a new value. */
819 #define BW_SPI_CTARn_PBR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PBR) | BF_SPI_CTARn_PBR(v)))
823 * @name Register SPI_CTARn, field PDT[19:18] (RW)
825 * Selects the prescaler value for the delay between the negation of the PCS
826 * signal at the end of a frame and the assertion of PCS at the beginning of the
827 * next frame. The PDT field is only used in master mode. See the DT field
828 * description for details on how to compute the Delay after Transfer. Refer Delay after
829 * Transfer (tDT ) for more details.
832 * - 00 - Delay after Transfer Prescaler value is 1.
833 * - 01 - Delay after Transfer Prescaler value is 3.
834 * - 10 - Delay after Transfer Prescaler value is 5.
835 * - 11 - Delay after Transfer Prescaler value is 7.
838 #define BP_SPI_CTARn_PDT (18U) /*!< Bit position for SPI_CTARn_PDT. */
839 #define BM_SPI_CTARn_PDT (0x000C0000U) /*!< Bit mask for SPI_CTARn_PDT. */
840 #define BS_SPI_CTARn_PDT (2U) /*!< Bit field size in bits for SPI_CTARn_PDT. */
842 /*! @brief Read current value of the SPI_CTARn_PDT field. */
843 #define BR_SPI_CTARn_PDT(x, n) (HW_SPI_CTARn(x, n).B.PDT)
845 /*! @brief Format value for bitfield SPI_CTARn_PDT. */
846 #define BF_SPI_CTARn_PDT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PDT) & BM_SPI_CTARn_PDT)
848 /*! @brief Set the PDT field to a new value. */
849 #define BW_SPI_CTARn_PDT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PDT) | BF_SPI_CTARn_PDT(v)))
853 * @name Register SPI_CTARn, field PASC[21:20] (RW)
855 * Selects the prescaler value for the delay between the last edge of SCK and
856 * the negation of PCS. See the ASC field description for information on how to
857 * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
860 * - 00 - Delay after Transfer Prescaler value is 1.
861 * - 01 - Delay after Transfer Prescaler value is 3.
862 * - 10 - Delay after Transfer Prescaler value is 5.
863 * - 11 - Delay after Transfer Prescaler value is 7.
866 #define BP_SPI_CTARn_PASC (20U) /*!< Bit position for SPI_CTARn_PASC. */
867 #define BM_SPI_CTARn_PASC (0x00300000U) /*!< Bit mask for SPI_CTARn_PASC. */
868 #define BS_SPI_CTARn_PASC (2U) /*!< Bit field size in bits for SPI_CTARn_PASC. */
870 /*! @brief Read current value of the SPI_CTARn_PASC field. */
871 #define BR_SPI_CTARn_PASC(x, n) (HW_SPI_CTARn(x, n).B.PASC)
873 /*! @brief Format value for bitfield SPI_CTARn_PASC. */
874 #define BF_SPI_CTARn_PASC(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PASC) & BM_SPI_CTARn_PASC)
876 /*! @brief Set the PASC field to a new value. */
877 #define BW_SPI_CTARn_PASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PASC) | BF_SPI_CTARn_PASC(v)))
881 * @name Register SPI_CTARn, field PCSSCK[23:22] (RW)
883 * Selects the prescaler value for the delay between assertion of PCS and the
884 * first edge of the SCK. See the CSSCK field description for information on how to
885 * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
888 * - 00 - PCS to SCK Prescaler value is 1.
889 * - 01 - PCS to SCK Prescaler value is 3.
890 * - 10 - PCS to SCK Prescaler value is 5.
891 * - 11 - PCS to SCK Prescaler value is 7.
894 #define BP_SPI_CTARn_PCSSCK (22U) /*!< Bit position for SPI_CTARn_PCSSCK. */
895 #define BM_SPI_CTARn_PCSSCK (0x00C00000U) /*!< Bit mask for SPI_CTARn_PCSSCK. */
896 #define BS_SPI_CTARn_PCSSCK (2U) /*!< Bit field size in bits for SPI_CTARn_PCSSCK. */
898 /*! @brief Read current value of the SPI_CTARn_PCSSCK field. */
899 #define BR_SPI_CTARn_PCSSCK(x, n) (HW_SPI_CTARn(x, n).B.PCSSCK)
901 /*! @brief Format value for bitfield SPI_CTARn_PCSSCK. */
902 #define BF_SPI_CTARn_PCSSCK(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PCSSCK) & BM_SPI_CTARn_PCSSCK)
904 /*! @brief Set the PCSSCK field to a new value. */
905 #define BW_SPI_CTARn_PCSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PCSSCK) | BF_SPI_CTARn_PCSSCK(v)))
909 * @name Register SPI_CTARn, field LSBFE[24] (RW)
911 * Specifies whether the LSB or MSB of the frame is transferred first.
914 * - 0 - Data is transferred MSB first.
915 * - 1 - Data is transferred LSB first.
918 #define BP_SPI_CTARn_LSBFE (24U) /*!< Bit position for SPI_CTARn_LSBFE. */
919 #define BM_SPI_CTARn_LSBFE (0x01000000U) /*!< Bit mask for SPI_CTARn_LSBFE. */
920 #define BS_SPI_CTARn_LSBFE (1U) /*!< Bit field size in bits for SPI_CTARn_LSBFE. */
922 /*! @brief Read current value of the SPI_CTARn_LSBFE field. */
923 #define BR_SPI_CTARn_LSBFE(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE))
925 /*! @brief Format value for bitfield SPI_CTARn_LSBFE. */
926 #define BF_SPI_CTARn_LSBFE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_LSBFE) & BM_SPI_CTARn_LSBFE)
928 /*! @brief Set the LSBFE field to a new value. */
929 #define BW_SPI_CTARn_LSBFE(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE) = (v))
933 * @name Register SPI_CTARn, field CPHA[25] (RW)
935 * Selects which edge of SCK causes data to change and which edge causes data to
936 * be captured. This bit is used in both master and slave mode. For successful
937 * communication between serial devices, the devices must have identical clock
938 * phase settings. In Continuous SCK mode, the bit value is ignored and the
939 * transfers are done as if the CPHA bit is set to 1.
942 * - 0 - Data is captured on the leading edge of SCK and changed on the
944 * - 1 - Data is changed on the leading edge of SCK and captured on the
948 #define BP_SPI_CTARn_CPHA (25U) /*!< Bit position for SPI_CTARn_CPHA. */
949 #define BM_SPI_CTARn_CPHA (0x02000000U) /*!< Bit mask for SPI_CTARn_CPHA. */
950 #define BS_SPI_CTARn_CPHA (1U) /*!< Bit field size in bits for SPI_CTARn_CPHA. */
952 /*! @brief Read current value of the SPI_CTARn_CPHA field. */
953 #define BR_SPI_CTARn_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA))
955 /*! @brief Format value for bitfield SPI_CTARn_CPHA. */
956 #define BF_SPI_CTARn_CPHA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CPHA) & BM_SPI_CTARn_CPHA)
958 /*! @brief Set the CPHA field to a new value. */
959 #define BW_SPI_CTARn_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA) = (v))
963 * @name Register SPI_CTARn, field CPOL[26] (RW)
965 * Selects the inactive state of the Serial Communications Clock (SCK). This bit
966 * is used in both master and slave mode. For successful communication between
967 * serial devices, the devices must have identical clock polarities. When the
968 * Continuous Selection Format is selected, switching between clock polarities
969 * without stopping the module can cause errors in the transfer due to the peripheral
970 * device interpreting the switch of clock polarity as a valid clock edge. In case
971 * of continous sck mode, when the module goes in low power mode(disabled),
972 * inactive state of sck is not guaranted.
975 * - 0 - The inactive state value of SCK is low.
976 * - 1 - The inactive state value of SCK is high.
979 #define BP_SPI_CTARn_CPOL (26U) /*!< Bit position for SPI_CTARn_CPOL. */
980 #define BM_SPI_CTARn_CPOL (0x04000000U) /*!< Bit mask for SPI_CTARn_CPOL. */
981 #define BS_SPI_CTARn_CPOL (1U) /*!< Bit field size in bits for SPI_CTARn_CPOL. */
983 /*! @brief Read current value of the SPI_CTARn_CPOL field. */
984 #define BR_SPI_CTARn_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL))
986 /*! @brief Format value for bitfield SPI_CTARn_CPOL. */
987 #define BF_SPI_CTARn_CPOL(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CPOL) & BM_SPI_CTARn_CPOL)
989 /*! @brief Set the CPOL field to a new value. */
990 #define BW_SPI_CTARn_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL) = (v))
994 * @name Register SPI_CTARn, field FMSZ[30:27] (RW)
996 * The number of bits transferred per frame is equal to the FMSZ value plus 1.
997 * Regardless of the transmission mode, the minimum valid frame size value is 4.
1000 #define BP_SPI_CTARn_FMSZ (27U) /*!< Bit position for SPI_CTARn_FMSZ. */
1001 #define BM_SPI_CTARn_FMSZ (0x78000000U) /*!< Bit mask for SPI_CTARn_FMSZ. */
1002 #define BS_SPI_CTARn_FMSZ (4U) /*!< Bit field size in bits for SPI_CTARn_FMSZ. */
1004 /*! @brief Read current value of the SPI_CTARn_FMSZ field. */
1005 #define BR_SPI_CTARn_FMSZ(x, n) (HW_SPI_CTARn(x, n).B.FMSZ)
1007 /*! @brief Format value for bitfield SPI_CTARn_FMSZ. */
1008 #define BF_SPI_CTARn_FMSZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_FMSZ) & BM_SPI_CTARn_FMSZ)
1010 /*! @brief Set the FMSZ field to a new value. */
1011 #define BW_SPI_CTARn_FMSZ(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_FMSZ) | BF_SPI_CTARn_FMSZ(v)))
1015 * @name Register SPI_CTARn, field DBR[31] (RW)
1017 * Doubles the effective baud rate of the Serial Communications Clock (SCK).
1018 * This field is used only in master mode. It effectively halves the Baud Rate
1019 * division ratio, supporting faster frequencies, and odd division ratios for the
1020 * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
1021 * Serial Communications Clock (SCK) depends on the value in the Baud Rate
1022 * Prescaler and the Clock Phase bit as listed in the following table. See the BR field
1023 * description for details on how to compute the baud rate. SPI SCK Duty Cycle
1024 * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
1025 * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
1028 * - 0 - The baud rate is computed normally with a 50/50 duty cycle.
1029 * - 1 - The baud rate is doubled with the duty cycle depending on the Baud Rate
1033 #define BP_SPI_CTARn_DBR (31U) /*!< Bit position for SPI_CTARn_DBR. */
1034 #define BM_SPI_CTARn_DBR (0x80000000U) /*!< Bit mask for SPI_CTARn_DBR. */
1035 #define BS_SPI_CTARn_DBR (1U) /*!< Bit field size in bits for SPI_CTARn_DBR. */
1037 /*! @brief Read current value of the SPI_CTARn_DBR field. */
1038 #define BR_SPI_CTARn_DBR(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR))
1040 /*! @brief Format value for bitfield SPI_CTARn_DBR. */
1041 #define BF_SPI_CTARn_DBR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_DBR) & BM_SPI_CTARn_DBR)
1043 /*! @brief Set the DBR field to a new value. */
1044 #define BW_SPI_CTARn_DBR(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR) = (v))
1046 /*******************************************************************************
1047 * HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
1048 ******************************************************************************/
1051 * @brief HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
1053 * Reset value: 0x78000000U
1055 * When the module is configured as an SPI bus slave, the CTAR0 register is used.
1057 typedef union _hw_spi_ctarn_slave
1060 struct _hw_spi_ctarn_slave_bitfields
1062 uint32_t RESERVED0 : 25; /*!< [24:0] */
1063 uint32_t CPHA : 1; /*!< [25] Clock Phase */
1064 uint32_t CPOL : 1; /*!< [26] Clock Polarity */
1065 uint32_t FMSZ : 5; /*!< [31:27] Frame Size */
1067 } hw_spi_ctarn_slave_t;
1070 * @name Constants and macros for entire SPI_CTARn_SLAVE register
1073 #define HW_SPI_CTARn_SLAVE_COUNT (1U)
1075 #define HW_SPI_CTARn_SLAVE_ADDR(x, n) ((x) + 0xCU + (0x4U * (n)))
1077 #define HW_SPI_CTARn_SLAVE(x, n) (*(__IO hw_spi_ctarn_slave_t *) HW_SPI_CTARn_SLAVE_ADDR(x, n))
1078 #define HW_SPI_CTARn_SLAVE_RD(x, n) (HW_SPI_CTARn_SLAVE(x, n).U)
1079 #define HW_SPI_CTARn_SLAVE_WR(x, n, v) (HW_SPI_CTARn_SLAVE(x, n).U = (v))
1080 #define HW_SPI_CTARn_SLAVE_SET(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) | (v)))
1081 #define HW_SPI_CTARn_SLAVE_CLR(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) & ~(v)))
1082 #define HW_SPI_CTARn_SLAVE_TOG(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) ^ (v)))
1086 * Constants & macros for individual SPI_CTARn_SLAVE bitfields
1090 * @name Register SPI_CTARn_SLAVE, field CPHA[25] (RW)
1092 * Selects which edge of SCK causes data to change and which edge causes data to
1093 * be captured. This bit is used in both master and slave mode. For successful
1094 * communication between serial devices, the devices must have identical clock
1095 * phase settings. In Continuous SCK mode, the bit value is ignored and the
1096 * transfers are done as if the CPHA bit is set to 1.
1099 * - 0 - Data is captured on the leading edge of SCK and changed on the
1101 * - 1 - Data is changed on the leading edge of SCK and captured on the
1105 #define BP_SPI_CTARn_SLAVE_CPHA (25U) /*!< Bit position for SPI_CTARn_SLAVE_CPHA. */
1106 #define BM_SPI_CTARn_SLAVE_CPHA (0x02000000U) /*!< Bit mask for SPI_CTARn_SLAVE_CPHA. */
1107 #define BS_SPI_CTARn_SLAVE_CPHA (1U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_CPHA. */
1109 /*! @brief Read current value of the SPI_CTARn_SLAVE_CPHA field. */
1110 #define BR_SPI_CTARn_SLAVE_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA))
1112 /*! @brief Format value for bitfield SPI_CTARn_SLAVE_CPHA. */
1113 #define BF_SPI_CTARn_SLAVE_CPHA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_CPHA) & BM_SPI_CTARn_SLAVE_CPHA)
1115 /*! @brief Set the CPHA field to a new value. */
1116 #define BW_SPI_CTARn_SLAVE_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA) = (v))
1120 * @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW)
1122 * Selects the inactive state of the Serial Communications Clock (SCK). In case
1123 * of continous sck mode, when the module goes in low power mode(disabled),
1124 * inactive state of sck is not guaranted.
1127 * - 0 - The inactive state value of SCK is low.
1128 * - 1 - The inactive state value of SCK is high.
1131 #define BP_SPI_CTARn_SLAVE_CPOL (26U) /*!< Bit position for SPI_CTARn_SLAVE_CPOL. */
1132 #define BM_SPI_CTARn_SLAVE_CPOL (0x04000000U) /*!< Bit mask for SPI_CTARn_SLAVE_CPOL. */
1133 #define BS_SPI_CTARn_SLAVE_CPOL (1U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_CPOL. */
1135 /*! @brief Read current value of the SPI_CTARn_SLAVE_CPOL field. */
1136 #define BR_SPI_CTARn_SLAVE_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL))
1138 /*! @brief Format value for bitfield SPI_CTARn_SLAVE_CPOL. */
1139 #define BF_SPI_CTARn_SLAVE_CPOL(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_CPOL) & BM_SPI_CTARn_SLAVE_CPOL)
1141 /*! @brief Set the CPOL field to a new value. */
1142 #define BW_SPI_CTARn_SLAVE_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL) = (v))
1146 * @name Register SPI_CTARn_SLAVE, field FMSZ[31:27] (RW)
1148 * The number of bits transfered per frame is equal to the FMSZ field value plus
1149 * 1. Note that the minimum valid value of frame size is 4.
1152 #define BP_SPI_CTARn_SLAVE_FMSZ (27U) /*!< Bit position for SPI_CTARn_SLAVE_FMSZ. */
1153 #define BM_SPI_CTARn_SLAVE_FMSZ (0xF8000000U) /*!< Bit mask for SPI_CTARn_SLAVE_FMSZ. */
1154 #define BS_SPI_CTARn_SLAVE_FMSZ (5U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_FMSZ. */
1156 /*! @brief Read current value of the SPI_CTARn_SLAVE_FMSZ field. */
1157 #define BR_SPI_CTARn_SLAVE_FMSZ(x, n) (HW_SPI_CTARn_SLAVE(x, n).B.FMSZ)
1159 /*! @brief Format value for bitfield SPI_CTARn_SLAVE_FMSZ. */
1160 #define BF_SPI_CTARn_SLAVE_FMSZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_FMSZ) & BM_SPI_CTARn_SLAVE_FMSZ)
1162 /*! @brief Set the FMSZ field to a new value. */
1163 #define BW_SPI_CTARn_SLAVE_FMSZ(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, (HW_SPI_CTARn_SLAVE_RD(x, n) & ~BM_SPI_CTARn_SLAVE_FMSZ) | BF_SPI_CTARn_SLAVE_FMSZ(v)))
1166 /*******************************************************************************
1167 * HW_SPI_SR - Status Register
1168 ******************************************************************************/
1171 * @brief HW_SPI_SR - Status Register (RW)
1173 * Reset value: 0x02000000U
1175 * SR contains status and flag bits. The bits reflect the status of the module
1176 * and indicate the occurrence of events that can generate interrupt or DMA
1177 * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
1178 * to a flag bit has no effect. This register may not be writable in Module
1179 * Disable mode due to the use of power saving mechanisms.
1181 typedef union _hw_spi_sr
1184 struct _hw_spi_sr_bitfields
1186 uint32_t POPNXTPTR : 4; /*!< [3:0] Pop Next Pointer */
1187 uint32_t RXCTR : 4; /*!< [7:4] RX FIFO Counter */
1188 uint32_t TXNXTPTR : 4; /*!< [11:8] Transmit Next Pointer */
1189 uint32_t TXCTR : 4; /*!< [15:12] TX FIFO Counter */
1190 uint32_t RESERVED0 : 1; /*!< [16] */
1191 uint32_t RFDF : 1; /*!< [17] Receive FIFO Drain Flag */
1192 uint32_t RESERVED1 : 1; /*!< [18] */
1193 uint32_t RFOF : 1; /*!< [19] Receive FIFO Overflow Flag */
1194 uint32_t RESERVED2 : 5; /*!< [24:20] */
1195 uint32_t TFFF : 1; /*!< [25] Transmit FIFO Fill Flag */
1196 uint32_t RESERVED3 : 1; /*!< [26] */
1197 uint32_t TFUF : 1; /*!< [27] Transmit FIFO Underflow Flag */
1198 uint32_t EOQF : 1; /*!< [28] End of Queue Flag */
1199 uint32_t RESERVED4 : 1; /*!< [29] */
1200 uint32_t TXRXS : 1; /*!< [30] TX and RX Status */
1201 uint32_t TCF : 1; /*!< [31] Transfer Complete Flag */
1206 * @name Constants and macros for entire SPI_SR register
1209 #define HW_SPI_SR_ADDR(x) ((x) + 0x2CU)
1211 #define HW_SPI_SR(x) (*(__IO hw_spi_sr_t *) HW_SPI_SR_ADDR(x))
1212 #define HW_SPI_SR_RD(x) (HW_SPI_SR(x).U)
1213 #define HW_SPI_SR_WR(x, v) (HW_SPI_SR(x).U = (v))
1214 #define HW_SPI_SR_SET(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) | (v)))
1215 #define HW_SPI_SR_CLR(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) & ~(v)))
1216 #define HW_SPI_SR_TOG(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) ^ (v)))
1220 * Constants & macros for individual SPI_SR bitfields
1224 * @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
1226 * Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
1227 * The POPNXTPTR is updated when the POPR is read.
1230 #define BP_SPI_SR_POPNXTPTR (0U) /*!< Bit position for SPI_SR_POPNXTPTR. */
1231 #define BM_SPI_SR_POPNXTPTR (0x0000000FU) /*!< Bit mask for SPI_SR_POPNXTPTR. */
1232 #define BS_SPI_SR_POPNXTPTR (4U) /*!< Bit field size in bits for SPI_SR_POPNXTPTR. */
1234 /*! @brief Read current value of the SPI_SR_POPNXTPTR field. */
1235 #define BR_SPI_SR_POPNXTPTR(x) (HW_SPI_SR(x).B.POPNXTPTR)
1239 * @name Register SPI_SR, field RXCTR[7:4] (RO)
1241 * Indicates the number of entries in the RX FIFO. The RXCTR is decremented
1242 * every time the POPR is read. The RXCTR is incremented every time data is
1243 * transferred from the shift register to the RX FIFO.
1246 #define BP_SPI_SR_RXCTR (4U) /*!< Bit position for SPI_SR_RXCTR. */
1247 #define BM_SPI_SR_RXCTR (0x000000F0U) /*!< Bit mask for SPI_SR_RXCTR. */
1248 #define BS_SPI_SR_RXCTR (4U) /*!< Bit field size in bits for SPI_SR_RXCTR. */
1250 /*! @brief Read current value of the SPI_SR_RXCTR field. */
1251 #define BR_SPI_SR_RXCTR(x) (HW_SPI_SR(x).B.RXCTR)
1255 * @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
1257 * Indicates which TX FIFO entry is transmitted during the next transfer. The
1258 * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
1259 * the shift register.
1262 #define BP_SPI_SR_TXNXTPTR (8U) /*!< Bit position for SPI_SR_TXNXTPTR. */
1263 #define BM_SPI_SR_TXNXTPTR (0x00000F00U) /*!< Bit mask for SPI_SR_TXNXTPTR. */
1264 #define BS_SPI_SR_TXNXTPTR (4U) /*!< Bit field size in bits for SPI_SR_TXNXTPTR. */
1266 /*! @brief Read current value of the SPI_SR_TXNXTPTR field. */
1267 #define BR_SPI_SR_TXNXTPTR(x) (HW_SPI_SR(x).B.TXNXTPTR)
1271 * @name Register SPI_SR, field TXCTR[15:12] (RO)
1273 * Indicates the number of valid entries in the TX FIFO. The TXCTR is
1274 * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
1275 * command is executed and the SPI data is transferred to the shift register.
1278 #define BP_SPI_SR_TXCTR (12U) /*!< Bit position for SPI_SR_TXCTR. */
1279 #define BM_SPI_SR_TXCTR (0x0000F000U) /*!< Bit mask for SPI_SR_TXCTR. */
1280 #define BS_SPI_SR_TXCTR (4U) /*!< Bit field size in bits for SPI_SR_TXCTR. */
1282 /*! @brief Read current value of the SPI_SR_TXCTR field. */
1283 #define BR_SPI_SR_TXCTR(x) (HW_SPI_SR(x).B.TXCTR)
1287 * @name Register SPI_SR, field RFDF[17] (W1C)
1289 * Provides a method for the module to request that entries be removed from the
1290 * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
1291 * cleared by writing 1 to it or by acknowledgement from the DMA controller when
1292 * the RX FIFO is empty.
1295 * - 0 - RX FIFO is empty.
1296 * - 1 - RX FIFO is not empty.
1299 #define BP_SPI_SR_RFDF (17U) /*!< Bit position for SPI_SR_RFDF. */
1300 #define BM_SPI_SR_RFDF (0x00020000U) /*!< Bit mask for SPI_SR_RFDF. */
1301 #define BS_SPI_SR_RFDF (1U) /*!< Bit field size in bits for SPI_SR_RFDF. */
1303 /*! @brief Read current value of the SPI_SR_RFDF field. */
1304 #define BR_SPI_SR_RFDF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF))
1306 /*! @brief Format value for bitfield SPI_SR_RFDF. */
1307 #define BF_SPI_SR_RFDF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_RFDF) & BM_SPI_SR_RFDF)
1309 /*! @brief Set the RFDF field to a new value. */
1310 #define BW_SPI_SR_RFDF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF) = (v))
1314 * @name Register SPI_SR, field RFOF[19] (W1C)
1316 * Indicates an overflow condition in the RX FIFO. The field is set when the RX
1317 * FIFO and shift register are full and a transfer is initiated. The bit remains
1318 * set until it is cleared by writing a 1 to it.
1321 * - 0 - No Rx FIFO overflow.
1322 * - 1 - Rx FIFO overflow has occurred.
1325 #define BP_SPI_SR_RFOF (19U) /*!< Bit position for SPI_SR_RFOF. */
1326 #define BM_SPI_SR_RFOF (0x00080000U) /*!< Bit mask for SPI_SR_RFOF. */
1327 #define BS_SPI_SR_RFOF (1U) /*!< Bit field size in bits for SPI_SR_RFOF. */
1329 /*! @brief Read current value of the SPI_SR_RFOF field. */
1330 #define BR_SPI_SR_RFOF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF))
1332 /*! @brief Format value for bitfield SPI_SR_RFOF. */
1333 #define BF_SPI_SR_RFOF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_RFOF) & BM_SPI_SR_RFOF)
1335 /*! @brief Set the RFOF field to a new value. */
1336 #define BW_SPI_SR_RFOF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF) = (v))
1340 * @name Register SPI_SR, field TFFF[25] (W1C)
1342 * Provides a method for the module to request more entries to be added to the
1343 * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
1344 * cleared by writing 1 to it or by acknowledgement from the DMA controller to
1345 * the TX FIFO full request.
1348 * - 0 - TX FIFO is full.
1349 * - 1 - TX FIFO is not full.
1352 #define BP_SPI_SR_TFFF (25U) /*!< Bit position for SPI_SR_TFFF. */
1353 #define BM_SPI_SR_TFFF (0x02000000U) /*!< Bit mask for SPI_SR_TFFF. */
1354 #define BS_SPI_SR_TFFF (1U) /*!< Bit field size in bits for SPI_SR_TFFF. */
1356 /*! @brief Read current value of the SPI_SR_TFFF field. */
1357 #define BR_SPI_SR_TFFF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF))
1359 /*! @brief Format value for bitfield SPI_SR_TFFF. */
1360 #define BF_SPI_SR_TFFF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TFFF) & BM_SPI_SR_TFFF)
1362 /*! @brief Set the TFFF field to a new value. */
1363 #define BW_SPI_SR_TFFF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF) = (v))
1367 * @name Register SPI_SR, field TFUF[27] (W1C)
1369 * Indicates an underflow condition in the TX FIFO. The transmit underflow
1370 * condition is detected only for SPI blocks operating in Slave mode and SPI
1371 * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
1372 * is empty and an external SPI master initiates a transfer. The TFUF bit remains
1373 * set until cleared by writing 1 to it.
1376 * - 0 - No TX FIFO underflow.
1377 * - 1 - TX FIFO underflow has occurred.
1380 #define BP_SPI_SR_TFUF (27U) /*!< Bit position for SPI_SR_TFUF. */
1381 #define BM_SPI_SR_TFUF (0x08000000U) /*!< Bit mask for SPI_SR_TFUF. */
1382 #define BS_SPI_SR_TFUF (1U) /*!< Bit field size in bits for SPI_SR_TFUF. */
1384 /*! @brief Read current value of the SPI_SR_TFUF field. */
1385 #define BR_SPI_SR_TFUF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF))
1387 /*! @brief Format value for bitfield SPI_SR_TFUF. */
1388 #define BF_SPI_SR_TFUF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TFUF) & BM_SPI_SR_TFUF)
1390 /*! @brief Set the TFUF field to a new value. */
1391 #define BW_SPI_SR_TFUF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF) = (v))
1395 * @name Register SPI_SR, field EOQF[28] (W1C)
1397 * Indicates that the last entry in a queue has been transmitted when the module
1398 * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
1399 * set in the command halfword and the end of the transfer is reached. The EOQF
1400 * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
1401 * the TXRXS bit is automatically cleared.
1404 * - 0 - EOQ is not set in the executing command.
1405 * - 1 - EOQ is set in the executing SPI command.
1408 #define BP_SPI_SR_EOQF (28U) /*!< Bit position for SPI_SR_EOQF. */
1409 #define BM_SPI_SR_EOQF (0x10000000U) /*!< Bit mask for SPI_SR_EOQF. */
1410 #define BS_SPI_SR_EOQF (1U) /*!< Bit field size in bits for SPI_SR_EOQF. */
1412 /*! @brief Read current value of the SPI_SR_EOQF field. */
1413 #define BR_SPI_SR_EOQF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF))
1415 /*! @brief Format value for bitfield SPI_SR_EOQF. */
1416 #define BF_SPI_SR_EOQF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_EOQF) & BM_SPI_SR_EOQF)
1418 /*! @brief Set the EOQF field to a new value. */
1419 #define BW_SPI_SR_EOQF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF) = (v))
1423 * @name Register SPI_SR, field TXRXS[30] (W1C)
1425 * Reflects the run status of the module.
1428 * - 0 - Transmit and receive operations are disabled (The module is in Stopped
1430 * - 1 - Transmit and receive operations are enabled (The module is in Running
1434 #define BP_SPI_SR_TXRXS (30U) /*!< Bit position for SPI_SR_TXRXS. */
1435 #define BM_SPI_SR_TXRXS (0x40000000U) /*!< Bit mask for SPI_SR_TXRXS. */
1436 #define BS_SPI_SR_TXRXS (1U) /*!< Bit field size in bits for SPI_SR_TXRXS. */
1438 /*! @brief Read current value of the SPI_SR_TXRXS field. */
1439 #define BR_SPI_SR_TXRXS(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS))
1441 /*! @brief Format value for bitfield SPI_SR_TXRXS. */
1442 #define BF_SPI_SR_TXRXS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TXRXS) & BM_SPI_SR_TXRXS)
1444 /*! @brief Set the TXRXS field to a new value. */
1445 #define BW_SPI_SR_TXRXS(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS) = (v))
1449 * @name Register SPI_SR, field TCF[31] (W1C)
1451 * Indicates that all bits in a frame have been shifted out. TCF remains set
1452 * until it is cleared by writing a 1 to it.
1455 * - 0 - Transfer not complete.
1456 * - 1 - Transfer complete.
1459 #define BP_SPI_SR_TCF (31U) /*!< Bit position for SPI_SR_TCF. */
1460 #define BM_SPI_SR_TCF (0x80000000U) /*!< Bit mask for SPI_SR_TCF. */
1461 #define BS_SPI_SR_TCF (1U) /*!< Bit field size in bits for SPI_SR_TCF. */
1463 /*! @brief Read current value of the SPI_SR_TCF field. */
1464 #define BR_SPI_SR_TCF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF))
1466 /*! @brief Format value for bitfield SPI_SR_TCF. */
1467 #define BF_SPI_SR_TCF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TCF) & BM_SPI_SR_TCF)
1469 /*! @brief Set the TCF field to a new value. */
1470 #define BW_SPI_SR_TCF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF) = (v))
1473 /*******************************************************************************
1474 * HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
1475 ******************************************************************************/
1478 * @brief HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
1480 * Reset value: 0x00000000U
1482 * RSER controls DMA and interrupt requests. Do not write to the RSER while the
1483 * module is in the Running state.
1485 typedef union _hw_spi_rser
1488 struct _hw_spi_rser_bitfields
1490 uint32_t RESERVED0 : 16; /*!< [15:0] */
1491 uint32_t RFDF_DIRS : 1; /*!< [16] Receive FIFO Drain DMA or Interrupt
1493 uint32_t RFDF_RE : 1; /*!< [17] Receive FIFO Drain Request Enable */
1494 uint32_t RESERVED1 : 1; /*!< [18] */
1495 uint32_t RFOF_RE : 1; /*!< [19] Receive FIFO Overflow Request Enable
1497 uint32_t RESERVED2 : 4; /*!< [23:20] */
1498 uint32_t TFFF_DIRS : 1; /*!< [24] Transmit FIFO Fill DMA or Interrupt
1500 uint32_t TFFF_RE : 1; /*!< [25] Transmit FIFO Fill Request Enable */
1501 uint32_t RESERVED3 : 1; /*!< [26] */
1502 uint32_t TFUF_RE : 1; /*!< [27] Transmit FIFO Underflow Request
1504 uint32_t EOQF_RE : 1; /*!< [28] Finished Request Enable */
1505 uint32_t RESERVED4 : 2; /*!< [30:29] */
1506 uint32_t TCF_RE : 1; /*!< [31] Transmission Complete Request Enable */
1511 * @name Constants and macros for entire SPI_RSER register
1514 #define HW_SPI_RSER_ADDR(x) ((x) + 0x30U)
1516 #define HW_SPI_RSER(x) (*(__IO hw_spi_rser_t *) HW_SPI_RSER_ADDR(x))
1517 #define HW_SPI_RSER_RD(x) (HW_SPI_RSER(x).U)
1518 #define HW_SPI_RSER_WR(x, v) (HW_SPI_RSER(x).U = (v))
1519 #define HW_SPI_RSER_SET(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) | (v)))
1520 #define HW_SPI_RSER_CLR(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) & ~(v)))
1521 #define HW_SPI_RSER_TOG(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) ^ (v)))
1525 * Constants & macros for individual SPI_RSER bitfields
1529 * @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
1531 * Selects between generating a DMA request or an interrupt request. When the
1532 * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
1533 * RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
1536 * - 0 - Interrupt request.
1537 * - 1 - DMA request.
1540 #define BP_SPI_RSER_RFDF_DIRS (16U) /*!< Bit position for SPI_RSER_RFDF_DIRS. */
1541 #define BM_SPI_RSER_RFDF_DIRS (0x00010000U) /*!< Bit mask for SPI_RSER_RFDF_DIRS. */
1542 #define BS_SPI_RSER_RFDF_DIRS (1U) /*!< Bit field size in bits for SPI_RSER_RFDF_DIRS. */
1544 /*! @brief Read current value of the SPI_RSER_RFDF_DIRS field. */
1545 #define BR_SPI_RSER_RFDF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS))
1547 /*! @brief Format value for bitfield SPI_RSER_RFDF_DIRS. */
1548 #define BF_SPI_RSER_RFDF_DIRS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFDF_DIRS) & BM_SPI_RSER_RFDF_DIRS)
1550 /*! @brief Set the RFDF_DIRS field to a new value. */
1551 #define BW_SPI_RSER_RFDF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS) = (v))
1555 * @name Register SPI_RSER, field RFDF_RE[17] (RW)
1557 * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
1558 * selects between generating an interrupt request or a DMA request.
1561 * - 0 - RFDF interrupt or DMA requests are disabled.
1562 * - 1 - RFDF interrupt or DMA requests are enabled.
1565 #define BP_SPI_RSER_RFDF_RE (17U) /*!< Bit position for SPI_RSER_RFDF_RE. */
1566 #define BM_SPI_RSER_RFDF_RE (0x00020000U) /*!< Bit mask for SPI_RSER_RFDF_RE. */
1567 #define BS_SPI_RSER_RFDF_RE (1U) /*!< Bit field size in bits for SPI_RSER_RFDF_RE. */
1569 /*! @brief Read current value of the SPI_RSER_RFDF_RE field. */
1570 #define BR_SPI_RSER_RFDF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE))
1572 /*! @brief Format value for bitfield SPI_RSER_RFDF_RE. */
1573 #define BF_SPI_RSER_RFDF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFDF_RE) & BM_SPI_RSER_RFDF_RE)
1575 /*! @brief Set the RFDF_RE field to a new value. */
1576 #define BW_SPI_RSER_RFDF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE) = (v))
1580 * @name Register SPI_RSER, field RFOF_RE[19] (RW)
1582 * Enables the RFOF flag in the SR to generate an interrupt request.
1585 * - 0 - RFOF interrupt requests are disabled.
1586 * - 1 - RFOF interrupt requests are enabled.
1589 #define BP_SPI_RSER_RFOF_RE (19U) /*!< Bit position for SPI_RSER_RFOF_RE. */
1590 #define BM_SPI_RSER_RFOF_RE (0x00080000U) /*!< Bit mask for SPI_RSER_RFOF_RE. */
1591 #define BS_SPI_RSER_RFOF_RE (1U) /*!< Bit field size in bits for SPI_RSER_RFOF_RE. */
1593 /*! @brief Read current value of the SPI_RSER_RFOF_RE field. */
1594 #define BR_SPI_RSER_RFOF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE))
1596 /*! @brief Format value for bitfield SPI_RSER_RFOF_RE. */
1597 #define BF_SPI_RSER_RFOF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFOF_RE) & BM_SPI_RSER_RFOF_RE)
1599 /*! @brief Set the RFOF_RE field to a new value. */
1600 #define BW_SPI_RSER_RFOF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE) = (v))
1604 * @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
1606 * Selects between generating a DMA request or an interrupt request. When
1607 * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
1608 * interrupt request or a DMA request.
1611 * - 0 - TFFF flag generates interrupt requests.
1612 * - 1 - TFFF flag generates DMA requests.
1615 #define BP_SPI_RSER_TFFF_DIRS (24U) /*!< Bit position for SPI_RSER_TFFF_DIRS. */
1616 #define BM_SPI_RSER_TFFF_DIRS (0x01000000U) /*!< Bit mask for SPI_RSER_TFFF_DIRS. */
1617 #define BS_SPI_RSER_TFFF_DIRS (1U) /*!< Bit field size in bits for SPI_RSER_TFFF_DIRS. */
1619 /*! @brief Read current value of the SPI_RSER_TFFF_DIRS field. */
1620 #define BR_SPI_RSER_TFFF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS))
1622 /*! @brief Format value for bitfield SPI_RSER_TFFF_DIRS. */
1623 #define BF_SPI_RSER_TFFF_DIRS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFFF_DIRS) & BM_SPI_RSER_TFFF_DIRS)
1625 /*! @brief Set the TFFF_DIRS field to a new value. */
1626 #define BW_SPI_RSER_TFFF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS) = (v))
1630 * @name Register SPI_RSER, field TFFF_RE[25] (RW)
1632 * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
1633 * selects between generating an interrupt request or a DMA request.
1636 * - 0 - TFFF interrupts or DMA requests are disabled.
1637 * - 1 - TFFF interrupts or DMA requests are enabled.
1640 #define BP_SPI_RSER_TFFF_RE (25U) /*!< Bit position for SPI_RSER_TFFF_RE. */
1641 #define BM_SPI_RSER_TFFF_RE (0x02000000U) /*!< Bit mask for SPI_RSER_TFFF_RE. */
1642 #define BS_SPI_RSER_TFFF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TFFF_RE. */
1644 /*! @brief Read current value of the SPI_RSER_TFFF_RE field. */
1645 #define BR_SPI_RSER_TFFF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE))
1647 /*! @brief Format value for bitfield SPI_RSER_TFFF_RE. */
1648 #define BF_SPI_RSER_TFFF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFFF_RE) & BM_SPI_RSER_TFFF_RE)
1650 /*! @brief Set the TFFF_RE field to a new value. */
1651 #define BW_SPI_RSER_TFFF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE) = (v))
1655 * @name Register SPI_RSER, field TFUF_RE[27] (RW)
1657 * Enables the TFUF flag in the SR to generate an interrupt request.
1660 * - 0 - TFUF interrupt requests are disabled.
1661 * - 1 - TFUF interrupt requests are enabled.
1664 #define BP_SPI_RSER_TFUF_RE (27U) /*!< Bit position for SPI_RSER_TFUF_RE. */
1665 #define BM_SPI_RSER_TFUF_RE (0x08000000U) /*!< Bit mask for SPI_RSER_TFUF_RE. */
1666 #define BS_SPI_RSER_TFUF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TFUF_RE. */
1668 /*! @brief Read current value of the SPI_RSER_TFUF_RE field. */
1669 #define BR_SPI_RSER_TFUF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE))
1671 /*! @brief Format value for bitfield SPI_RSER_TFUF_RE. */
1672 #define BF_SPI_RSER_TFUF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFUF_RE) & BM_SPI_RSER_TFUF_RE)
1674 /*! @brief Set the TFUF_RE field to a new value. */
1675 #define BW_SPI_RSER_TFUF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE) = (v))
1679 * @name Register SPI_RSER, field EOQF_RE[28] (RW)
1681 * Enables the EOQF flag in the SR to generate an interrupt request.
1684 * - 0 - EOQF interrupt requests are disabled.
1685 * - 1 - EOQF interrupt requests are enabled.
1688 #define BP_SPI_RSER_EOQF_RE (28U) /*!< Bit position for SPI_RSER_EOQF_RE. */
1689 #define BM_SPI_RSER_EOQF_RE (0x10000000U) /*!< Bit mask for SPI_RSER_EOQF_RE. */
1690 #define BS_SPI_RSER_EOQF_RE (1U) /*!< Bit field size in bits for SPI_RSER_EOQF_RE. */
1692 /*! @brief Read current value of the SPI_RSER_EOQF_RE field. */
1693 #define BR_SPI_RSER_EOQF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE))
1695 /*! @brief Format value for bitfield SPI_RSER_EOQF_RE. */
1696 #define BF_SPI_RSER_EOQF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_EOQF_RE) & BM_SPI_RSER_EOQF_RE)
1698 /*! @brief Set the EOQF_RE field to a new value. */
1699 #define BW_SPI_RSER_EOQF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE) = (v))
1703 * @name Register SPI_RSER, field TCF_RE[31] (RW)
1705 * Enables TCF flag in the SR to generate an interrupt request.
1708 * - 0 - TCF interrupt requests are disabled.
1709 * - 1 - TCF interrupt requests are enabled.
1712 #define BP_SPI_RSER_TCF_RE (31U) /*!< Bit position for SPI_RSER_TCF_RE. */
1713 #define BM_SPI_RSER_TCF_RE (0x80000000U) /*!< Bit mask for SPI_RSER_TCF_RE. */
1714 #define BS_SPI_RSER_TCF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TCF_RE. */
1716 /*! @brief Read current value of the SPI_RSER_TCF_RE field. */
1717 #define BR_SPI_RSER_TCF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE))
1719 /*! @brief Format value for bitfield SPI_RSER_TCF_RE. */
1720 #define BF_SPI_RSER_TCF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TCF_RE) & BM_SPI_RSER_TCF_RE)
1722 /*! @brief Set the TCF_RE field to a new value. */
1723 #define BW_SPI_RSER_TCF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE) = (v))
1726 /*******************************************************************************
1727 * HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
1728 ******************************************************************************/
1731 * @brief HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
1733 * Reset value: 0x00000000U
1735 * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
1736 * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
1737 * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
1738 * can be used as data, supporting up to 32-bit frame operation. A read access
1739 * of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
1740 * writing to this register does not update the FIFO. Therefore, any reads performed
1741 * while the module is disabled return the last PUSHR write performed while the
1742 * module was still enabled.
1744 typedef union _hw_spi_pushr
1747 struct _hw_spi_pushr_bitfields
1749 uint32_t TXDATA : 16; /*!< [15:0] Transmit Data */
1750 uint32_t PCS : 6; /*!< [21:16] */
1751 uint32_t RESERVED0 : 4; /*!< [25:22] */
1752 uint32_t CTCNT : 1; /*!< [26] Clear Transfer Counter */
1753 uint32_t EOQ : 1; /*!< [27] End Of Queue */
1754 uint32_t CTAS : 3; /*!< [30:28] Clock and Transfer Attributes Select
1756 uint32_t CONT : 1; /*!< [31] Continuous Peripheral Chip Select Enable
1762 * @name Constants and macros for entire SPI_PUSHR register
1765 #define HW_SPI_PUSHR_ADDR(x) ((x) + 0x34U)
1767 #define HW_SPI_PUSHR(x) (*(__IO hw_spi_pushr_t *) HW_SPI_PUSHR_ADDR(x))
1768 #define HW_SPI_PUSHR_RD(x) (HW_SPI_PUSHR(x).U)
1769 #define HW_SPI_PUSHR_WR(x, v) (HW_SPI_PUSHR(x).U = (v))
1770 #define HW_SPI_PUSHR_SET(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) | (v)))
1771 #define HW_SPI_PUSHR_CLR(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) & ~(v)))
1772 #define HW_SPI_PUSHR_TOG(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) ^ (v)))
1776 * Constants & macros for individual SPI_PUSHR bitfields
1780 * @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
1782 * Holds SPI data to be transferred according to the associated SPI command.
1785 #define BP_SPI_PUSHR_TXDATA (0U) /*!< Bit position for SPI_PUSHR_TXDATA. */
1786 #define BM_SPI_PUSHR_TXDATA (0x0000FFFFU) /*!< Bit mask for SPI_PUSHR_TXDATA. */
1787 #define BS_SPI_PUSHR_TXDATA (16U) /*!< Bit field size in bits for SPI_PUSHR_TXDATA. */
1789 /*! @brief Read current value of the SPI_PUSHR_TXDATA field. */
1790 #define BR_SPI_PUSHR_TXDATA(x) (HW_SPI_PUSHR(x).B.TXDATA)
1792 /*! @brief Format value for bitfield SPI_PUSHR_TXDATA. */
1793 #define BF_SPI_PUSHR_TXDATA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_TXDATA) & BM_SPI_PUSHR_TXDATA)
1795 /*! @brief Set the TXDATA field to a new value. */
1796 #define BW_SPI_PUSHR_TXDATA(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_TXDATA) | BF_SPI_PUSHR_TXDATA(v)))
1800 * @name Register SPI_PUSHR, field PCS[21:16] (RW)
1802 * Select which PCS signals are to be asserted for the transfer. Refer to the
1803 * chip configuration details for the number of PCS signals used in this MCU.
1806 * - 0 - Negate the PCS[x] signal.
1807 * - 1 - Assert the PCS[x] signal.
1810 #define BP_SPI_PUSHR_PCS (16U) /*!< Bit position for SPI_PUSHR_PCS. */
1811 #define BM_SPI_PUSHR_PCS (0x003F0000U) /*!< Bit mask for SPI_PUSHR_PCS. */
1812 #define BS_SPI_PUSHR_PCS (6U) /*!< Bit field size in bits for SPI_PUSHR_PCS. */
1814 /*! @brief Read current value of the SPI_PUSHR_PCS field. */
1815 #define BR_SPI_PUSHR_PCS(x) (HW_SPI_PUSHR(x).B.PCS)
1817 /*! @brief Format value for bitfield SPI_PUSHR_PCS. */
1818 #define BF_SPI_PUSHR_PCS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_PCS) & BM_SPI_PUSHR_PCS)
1820 /*! @brief Set the PCS field to a new value. */
1821 #define BW_SPI_PUSHR_PCS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_PCS) | BF_SPI_PUSHR_PCS(v)))
1825 * @name Register SPI_PUSHR, field CTCNT[26] (RW)
1827 * Clears the TCNT field in the TCR register. The TCNT field is cleared before
1828 * the module starts transmitting the current SPI frame.
1831 * - 0 - Do not clear the TCR[TCNT] field.
1832 * - 1 - Clear the TCR[TCNT] field.
1835 #define BP_SPI_PUSHR_CTCNT (26U) /*!< Bit position for SPI_PUSHR_CTCNT. */
1836 #define BM_SPI_PUSHR_CTCNT (0x04000000U) /*!< Bit mask for SPI_PUSHR_CTCNT. */
1837 #define BS_SPI_PUSHR_CTCNT (1U) /*!< Bit field size in bits for SPI_PUSHR_CTCNT. */
1839 /*! @brief Read current value of the SPI_PUSHR_CTCNT field. */
1840 #define BR_SPI_PUSHR_CTCNT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT))
1842 /*! @brief Format value for bitfield SPI_PUSHR_CTCNT. */
1843 #define BF_SPI_PUSHR_CTCNT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CTCNT) & BM_SPI_PUSHR_CTCNT)
1845 /*! @brief Set the CTCNT field to a new value. */
1846 #define BW_SPI_PUSHR_CTCNT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT) = (v))
1850 * @name Register SPI_PUSHR, field EOQ[27] (RW)
1852 * Host software uses this bit to signal to the module that the current SPI
1853 * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
1857 * - 0 - The SPI data is not the last data to transfer.
1858 * - 1 - The SPI data is the last data to transfer.
1861 #define BP_SPI_PUSHR_EOQ (27U) /*!< Bit position for SPI_PUSHR_EOQ. */
1862 #define BM_SPI_PUSHR_EOQ (0x08000000U) /*!< Bit mask for SPI_PUSHR_EOQ. */
1863 #define BS_SPI_PUSHR_EOQ (1U) /*!< Bit field size in bits for SPI_PUSHR_EOQ. */
1865 /*! @brief Read current value of the SPI_PUSHR_EOQ field. */
1866 #define BR_SPI_PUSHR_EOQ(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ))
1868 /*! @brief Format value for bitfield SPI_PUSHR_EOQ. */
1869 #define BF_SPI_PUSHR_EOQ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_EOQ) & BM_SPI_PUSHR_EOQ)
1871 /*! @brief Set the EOQ field to a new value. */
1872 #define BW_SPI_PUSHR_EOQ(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ) = (v))
1876 * @name Register SPI_PUSHR, field CTAS[30:28] (RW)
1878 * Selects which CTAR to use in master mode to specify the transfer attributes
1879 * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
1880 * configuration details to determine how many CTARs this device has. You should
1881 * not program a value in this field for a register that is not present.
1894 #define BP_SPI_PUSHR_CTAS (28U) /*!< Bit position for SPI_PUSHR_CTAS. */
1895 #define BM_SPI_PUSHR_CTAS (0x70000000U) /*!< Bit mask for SPI_PUSHR_CTAS. */
1896 #define BS_SPI_PUSHR_CTAS (3U) /*!< Bit field size in bits for SPI_PUSHR_CTAS. */
1898 /*! @brief Read current value of the SPI_PUSHR_CTAS field. */
1899 #define BR_SPI_PUSHR_CTAS(x) (HW_SPI_PUSHR(x).B.CTAS)
1901 /*! @brief Format value for bitfield SPI_PUSHR_CTAS. */
1902 #define BF_SPI_PUSHR_CTAS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CTAS) & BM_SPI_PUSHR_CTAS)
1904 /*! @brief Set the CTAS field to a new value. */
1905 #define BW_SPI_PUSHR_CTAS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_CTAS) | BF_SPI_PUSHR_CTAS(v)))
1909 * @name Register SPI_PUSHR, field CONT[31] (RW)
1911 * Selects a continuous selection format. The bit is used in SPI Master mode.
1912 * The bit enables the selected PCS signals to remain asserted between transfers.
1915 * - 0 - Return PCSn signals to their inactive state between transfers.
1916 * - 1 - Keep PCSn signals asserted between transfers.
1919 #define BP_SPI_PUSHR_CONT (31U) /*!< Bit position for SPI_PUSHR_CONT. */
1920 #define BM_SPI_PUSHR_CONT (0x80000000U) /*!< Bit mask for SPI_PUSHR_CONT. */
1921 #define BS_SPI_PUSHR_CONT (1U) /*!< Bit field size in bits for SPI_PUSHR_CONT. */
1923 /*! @brief Read current value of the SPI_PUSHR_CONT field. */
1924 #define BR_SPI_PUSHR_CONT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT))
1926 /*! @brief Format value for bitfield SPI_PUSHR_CONT. */
1927 #define BF_SPI_PUSHR_CONT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CONT) & BM_SPI_PUSHR_CONT)
1929 /*! @brief Set the CONT field to a new value. */
1930 #define BW_SPI_PUSHR_CONT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT) = (v))
1932 /*******************************************************************************
1933 * HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
1934 ******************************************************************************/
1937 * @brief HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
1939 * Reset value: 0x00000000U
1941 * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
1942 * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
1943 * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
1944 * slave mode, all 32 register bits can be used as data, supporting up to 32-bit
1945 * SPI Frame operation.
1947 typedef union _hw_spi_pushr_slave
1950 struct _hw_spi_pushr_slave_bitfields
1952 uint32_t TXDATA : 32; /*!< [31:0] Transmit Data */
1954 } hw_spi_pushr_slave_t;
1957 * @name Constants and macros for entire SPI_PUSHR_SLAVE register
1960 #define HW_SPI_PUSHR_SLAVE_ADDR(x) ((x) + 0x34U)
1962 #define HW_SPI_PUSHR_SLAVE(x) (*(__IO hw_spi_pushr_slave_t *) HW_SPI_PUSHR_SLAVE_ADDR(x))
1963 #define HW_SPI_PUSHR_SLAVE_RD(x) (HW_SPI_PUSHR_SLAVE(x).U)
1964 #define HW_SPI_PUSHR_SLAVE_WR(x, v) (HW_SPI_PUSHR_SLAVE(x).U = (v))
1965 #define HW_SPI_PUSHR_SLAVE_SET(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) | (v)))
1966 #define HW_SPI_PUSHR_SLAVE_CLR(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) & ~(v)))
1967 #define HW_SPI_PUSHR_SLAVE_TOG(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) ^ (v)))
1971 * Constants & macros for individual SPI_PUSHR_SLAVE bitfields
1975 * @name Register SPI_PUSHR_SLAVE, field TXDATA[31:0] (RW)
1977 * Holds SPI data to be transferred according to the associated SPI command.
1980 #define BP_SPI_PUSHR_SLAVE_TXDATA (0U) /*!< Bit position for SPI_PUSHR_SLAVE_TXDATA. */
1981 #define BM_SPI_PUSHR_SLAVE_TXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_PUSHR_SLAVE_TXDATA. */
1982 #define BS_SPI_PUSHR_SLAVE_TXDATA (32U) /*!< Bit field size in bits for SPI_PUSHR_SLAVE_TXDATA. */
1984 /*! @brief Read current value of the SPI_PUSHR_SLAVE_TXDATA field. */
1985 #define BR_SPI_PUSHR_SLAVE_TXDATA(x) (HW_SPI_PUSHR_SLAVE(x).U)
1987 /*! @brief Format value for bitfield SPI_PUSHR_SLAVE_TXDATA. */
1988 #define BF_SPI_PUSHR_SLAVE_TXDATA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_SLAVE_TXDATA) & BM_SPI_PUSHR_SLAVE_TXDATA)
1990 /*! @brief Set the TXDATA field to a new value. */
1991 #define BW_SPI_PUSHR_SLAVE_TXDATA(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, v))
1994 /*******************************************************************************
1995 * HW_SPI_POPR - POP RX FIFO Register
1996 ******************************************************************************/
1999 * @brief HW_SPI_POPR - POP RX FIFO Register (RO)
2001 * Reset value: 0x00000000U
2003 * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
2004 * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
2005 * this register will generate a Transfer Error.
2007 typedef union _hw_spi_popr
2010 struct _hw_spi_popr_bitfields
2012 uint32_t RXDATA : 32; /*!< [31:0] Received Data */
2017 * @name Constants and macros for entire SPI_POPR register
2020 #define HW_SPI_POPR_ADDR(x) ((x) + 0x38U)
2022 #define HW_SPI_POPR(x) (*(__I hw_spi_popr_t *) HW_SPI_POPR_ADDR(x))
2023 #define HW_SPI_POPR_RD(x) (HW_SPI_POPR(x).U)
2027 * Constants & macros for individual SPI_POPR bitfields
2031 * @name Register SPI_POPR, field RXDATA[31:0] (RO)
2033 * Contains the SPI data from the RX FIFO entry to which the Pop Next Data
2037 #define BP_SPI_POPR_RXDATA (0U) /*!< Bit position for SPI_POPR_RXDATA. */
2038 #define BM_SPI_POPR_RXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_POPR_RXDATA. */
2039 #define BS_SPI_POPR_RXDATA (32U) /*!< Bit field size in bits for SPI_POPR_RXDATA. */
2041 /*! @brief Read current value of the SPI_POPR_RXDATA field. */
2042 #define BR_SPI_POPR_RXDATA(x) (HW_SPI_POPR(x).U)
2045 /*******************************************************************************
2046 * HW_SPI_TXFRn - Transmit FIFO Registers
2047 ******************************************************************************/
2050 * @brief HW_SPI_TXFRn - Transmit FIFO Registers (RO)
2052 * Reset value: 0x00000000U
2054 * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
2055 * Each register is an entry in the TX FIFO. The registers are read-only and
2056 * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
2059 typedef union _hw_spi_txfrn
2062 struct _hw_spi_txfrn_bitfields
2064 uint32_t TXDATA : 16; /*!< [15:0] Transmit Data */
2065 uint32_t TXCMD_TXDATA : 16; /*!< [31:16] Transmit Command or Transmit
2071 * @name Constants and macros for entire SPI_TXFRn register
2074 #define HW_SPI_TXFRn_COUNT (4U)
2076 #define HW_SPI_TXFRn_ADDR(x, n) ((x) + 0x3CU + (0x4U * (n)))
2078 #define HW_SPI_TXFRn(x, n) (*(__I hw_spi_txfrn_t *) HW_SPI_TXFRn_ADDR(x, n))
2079 #define HW_SPI_TXFRn_RD(x, n) (HW_SPI_TXFRn(x, n).U)
2083 * Constants & macros for individual SPI_TXFRn bitfields
2087 * @name Register SPI_TXFRn, field TXDATA[15:0] (RO)
2089 * Contains the SPI data to be shifted out.
2092 #define BP_SPI_TXFRn_TXDATA (0U) /*!< Bit position for SPI_TXFRn_TXDATA. */
2093 #define BM_SPI_TXFRn_TXDATA (0x0000FFFFU) /*!< Bit mask for SPI_TXFRn_TXDATA. */
2094 #define BS_SPI_TXFRn_TXDATA (16U) /*!< Bit field size in bits for SPI_TXFRn_TXDATA. */
2096 /*! @brief Read current value of the SPI_TXFRn_TXDATA field. */
2097 #define BR_SPI_TXFRn_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXDATA)
2101 * @name Register SPI_TXFRn, field TXCMD_TXDATA[31:16] (RO)
2103 * In Master mode the TXCMD field contains the command that sets the transfer
2104 * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
2105 * the SPI data to be shifted out.
2108 #define BP_SPI_TXFRn_TXCMD_TXDATA (16U) /*!< Bit position for SPI_TXFRn_TXCMD_TXDATA. */
2109 #define BM_SPI_TXFRn_TXCMD_TXDATA (0xFFFF0000U) /*!< Bit mask for SPI_TXFRn_TXCMD_TXDATA. */
2110 #define BS_SPI_TXFRn_TXCMD_TXDATA (16U) /*!< Bit field size in bits for SPI_TXFRn_TXCMD_TXDATA. */
2112 /*! @brief Read current value of the SPI_TXFRn_TXCMD_TXDATA field. */
2113 #define BR_SPI_TXFRn_TXCMD_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXCMD_TXDATA)
2116 /*******************************************************************************
2117 * HW_SPI_RXFRn - Receive FIFO Registers
2118 ******************************************************************************/
2121 * @brief HW_SPI_RXFRn - Receive FIFO Registers (RO)
2123 * Reset value: 0x00000000U
2125 * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
2126 * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
2127 * RXFRx registers does not alter the state of the RX FIFO.
2129 typedef union _hw_spi_rxfrn
2132 struct _hw_spi_rxfrn_bitfields
2134 uint32_t RXDATA : 32; /*!< [31:0] Receive Data */
2139 * @name Constants and macros for entire SPI_RXFRn register
2142 #define HW_SPI_RXFRn_COUNT (4U)
2144 #define HW_SPI_RXFRn_ADDR(x, n) ((x) + 0x7CU + (0x4U * (n)))
2146 #define HW_SPI_RXFRn(x, n) (*(__I hw_spi_rxfrn_t *) HW_SPI_RXFRn_ADDR(x, n))
2147 #define HW_SPI_RXFRn_RD(x, n) (HW_SPI_RXFRn(x, n).U)
2151 * Constants & macros for individual SPI_RXFRn bitfields
2155 * @name Register SPI_RXFRn, field RXDATA[31:0] (RO)
2157 * Contains the received SPI data.
2160 #define BP_SPI_RXFRn_RXDATA (0U) /*!< Bit position for SPI_RXFRn_RXDATA. */
2161 #define BM_SPI_RXFRn_RXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_RXFRn_RXDATA. */
2162 #define BS_SPI_RXFRn_RXDATA (32U) /*!< Bit field size in bits for SPI_RXFRn_RXDATA. */
2164 /*! @brief Read current value of the SPI_RXFRn_RXDATA field. */
2165 #define BR_SPI_RXFRn_RXDATA(x, n) (HW_SPI_RXFRn(x, n).U)
2169 ** Start of section using anonymous unions
2172 #if defined(__ARMCC_VERSION)
2175 #elif defined(__CWCC__)
2177 #pragma cpp_extensions on
2178 #elif defined(__GNUC__)
2179 /* anonymous unions are enabled by default */
2180 #elif defined(__IAR_SYSTEMS_ICC__)
2181 #pragma language=extended
2183 #error Not supported compiler type
2186 /*******************************************************************************
2187 * hw_spi_t - module struct
2188 ******************************************************************************/
2190 * @brief All SPI module registers.
2193 typedef struct _hw_spi
2195 __IO hw_spi_mcr_t MCR; /*!< [0x0] Module Configuration Register */
2196 uint8_t _reserved0[4];
2197 __IO hw_spi_tcr_t TCR; /*!< [0x8] Transfer Count Register */
2199 __IO hw_spi_ctarn_t CTARn[2]; /*!< [0xC] Clock and Transfer Attributes Register (In Master Mode) */
2200 __IO hw_spi_ctarn_slave_t CTARn_SLAVE[1]; /*!< [0xC] Clock and Transfer Attributes Register (In Slave Mode) */
2202 uint8_t _reserved1[24];
2203 __IO hw_spi_sr_t SR; /*!< [0x2C] Status Register */
2204 __IO hw_spi_rser_t RSER; /*!< [0x30] DMA/Interrupt Request Select and Enable Register */
2206 __IO hw_spi_pushr_t PUSHR; /*!< [0x34] PUSH TX FIFO Register In Master Mode */
2207 __IO hw_spi_pushr_slave_t PUSHR_SLAVE; /*!< [0x34] PUSH TX FIFO Register In Slave Mode */
2209 __I hw_spi_popr_t POPR; /*!< [0x38] POP RX FIFO Register */
2210 __I hw_spi_txfrn_t TXFRn[4]; /*!< [0x3C] Transmit FIFO Registers */
2211 uint8_t _reserved2[48];
2212 __I hw_spi_rxfrn_t RXFRn[4]; /*!< [0x7C] Receive FIFO Registers */
2216 /*! @brief Macro to access all SPI registers. */
2217 /*! @param x SPI module instance base address. */
2218 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
2219 * use the '&' operator, like <code>&HW_SPI(SPI0_BASE)</code>. */
2220 #define HW_SPI(x) (*(hw_spi_t *)(x))
2223 ** End of section using anonymous unions
2226 #if defined(__ARMCC_VERSION)
2228 #elif defined(__CWCC__)
2230 #elif defined(__GNUC__)
2231 /* leave anonymous unions enabled */
2232 #elif defined(__IAR_SYSTEMS_ICC__)
2233 #pragma language=default
2235 #error Not supported compiler type
2238 #endif /* __HW_SPI_REGISTERS_H__ */