2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
9 ** Version: rev. 2.5, 2014-05-06
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-07-23)
49 ** - rev. 1.1 (2013-09-17)
50 ** RM rev. 0.4 update.
51 ** - rev. 2.0 (2013-10-29)
52 ** Register accessor macros added to the memory map.
53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
54 ** Startup file for gcc has been updated according to CMSIS 3.2.
55 ** System initialization updated.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-20)
59 ** Update according to reference manual rev. 0.6,
60 ** - rev. 2.3 (2014-01-13)
61 ** Update according to reference manual rev. 0.61,
62 ** - rev. 2.4 (2014-02-10)
63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
64 ** - rev. 2.5 (2014-05-06)
65 ** Update according to reference manual rev. 1.0,
66 ** Update of system and startup files.
67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
69 ** ###################################################################
73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
75 * This file was generated automatically and any changes may be lost.
77 #ifndef __HW_SIM_REGISTERS_H__
78 #define __HW_SIM_REGISTERS_H__
80 #include "MK22F51212.h"
81 #include "fsl_bitaccess.h"
86 * System Integration Module
88 * Registers defined in this header file:
89 * - HW_SIM_SOPT1 - System Options Register 1
90 * - HW_SIM_SOPT1CFG - SOPT1 Configuration Register
91 * - HW_SIM_SOPT2 - System Options Register 2
92 * - HW_SIM_SOPT4 - System Options Register 4
93 * - HW_SIM_SOPT5 - System Options Register 5
94 * - HW_SIM_SOPT7 - System Options Register 7
95 * - HW_SIM_SOPT8 - System Options Register 8
96 * - HW_SIM_SDID - System Device Identification Register
97 * - HW_SIM_SCGC4 - System Clock Gating Control Register 4
98 * - HW_SIM_SCGC5 - System Clock Gating Control Register 5
99 * - HW_SIM_SCGC6 - System Clock Gating Control Register 6
100 * - HW_SIM_SCGC7 - System Clock Gating Control Register 7
101 * - HW_SIM_CLKDIV1 - System Clock Divider Register 1
102 * - HW_SIM_CLKDIV2 - System Clock Divider Register 2
103 * - HW_SIM_FCFG1 - Flash Configuration Register 1
104 * - HW_SIM_FCFG2 - Flash Configuration Register 2
105 * - HW_SIM_UIDH - Unique Identification Register High
106 * - HW_SIM_UIDMH - Unique Identification Register Mid-High
107 * - HW_SIM_UIDML - Unique Identification Register Mid Low
108 * - HW_SIM_UIDL - Unique Identification Register Low
110 * - hw_sim_t - Struct containing all module registers.
113 #define HW_SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */
115 /*******************************************************************************
116 * HW_SIM_SOPT1 - System Options Register 1
117 ******************************************************************************/
120 * @brief HW_SIM_SOPT1 - System Options Register 1 (RW)
122 * Reset value: 0x80000000U
124 * The SOPT1 register is only reset on POR or LVD.
126 typedef union _hw_sim_sopt1
129 struct _hw_sim_sopt1_bitfields
131 uint32_t RESERVED0 : 12; /*!< [11:0] */
132 uint32_t RAMSIZE : 4; /*!< [15:12] RAM size */
133 uint32_t OSC32KOUT : 2; /*!< [17:16] 32K Oscillator Clock Output */
134 uint32_t OSC32KSEL : 2; /*!< [19:18] 32K oscillator clock select */
135 uint32_t RESERVED1 : 9; /*!< [28:20] */
136 uint32_t USBVSTBY : 1; /*!< [29] USB voltage regulator in standby
137 * mode during VLPR and VLPW modes */
138 uint32_t USBSSTBY : 1; /*!< [30] USB voltage regulator in standby
139 * mode during Stop, VLPS, LLS and VLLS modes. */
140 uint32_t USBREGEN : 1; /*!< [31] USB voltage regulator enable */
145 * @name Constants and macros for entire SIM_SOPT1 register
148 #define HW_SIM_SOPT1_ADDR(x) ((x) + 0x0U)
150 #define HW_SIM_SOPT1(x) (*(__IO hw_sim_sopt1_t *) HW_SIM_SOPT1_ADDR(x))
151 #define HW_SIM_SOPT1_RD(x) (HW_SIM_SOPT1(x).U)
152 #define HW_SIM_SOPT1_WR(x, v) (HW_SIM_SOPT1(x).U = (v))
153 #define HW_SIM_SOPT1_SET(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) | (v)))
154 #define HW_SIM_SOPT1_CLR(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) & ~(v)))
155 #define HW_SIM_SOPT1_TOG(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) ^ (v)))
159 * Constants & macros for individual SIM_SOPT1 bitfields
163 * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
165 * This field specifies the amount of system RAM available on the device.
179 #define BP_SIM_SOPT1_RAMSIZE (12U) /*!< Bit position for SIM_SOPT1_RAMSIZE. */
180 #define BM_SIM_SOPT1_RAMSIZE (0x0000F000U) /*!< Bit mask for SIM_SOPT1_RAMSIZE. */
181 #define BS_SIM_SOPT1_RAMSIZE (4U) /*!< Bit field size in bits for SIM_SOPT1_RAMSIZE. */
183 /*! @brief Read current value of the SIM_SOPT1_RAMSIZE field. */
184 #define BR_SIM_SOPT1_RAMSIZE(x) (HW_SIM_SOPT1(x).B.RAMSIZE)
188 * @name Register SIM_SOPT1, field OSC32KOUT[17:16] (RW)
190 * Outputs the ERCLK32K on the selected pin in all modes of operation (including
191 * LLS/VLLS and System Reset), overriding the existing pin mux configuration for
192 * that pin. This field is reset only on POR/LVD.
195 * - 00 - ERCLK32K is not output.
196 * - 01 - ERCLK32K is output on PTE0.
197 * - 10 - ERCLK32K is output on PTE26.
201 #define BP_SIM_SOPT1_OSC32KOUT (16U) /*!< Bit position for SIM_SOPT1_OSC32KOUT. */
202 #define BM_SIM_SOPT1_OSC32KOUT (0x00030000U) /*!< Bit mask for SIM_SOPT1_OSC32KOUT. */
203 #define BS_SIM_SOPT1_OSC32KOUT (2U) /*!< Bit field size in bits for SIM_SOPT1_OSC32KOUT. */
205 /*! @brief Read current value of the SIM_SOPT1_OSC32KOUT field. */
206 #define BR_SIM_SOPT1_OSC32KOUT(x) (HW_SIM_SOPT1(x).B.OSC32KOUT)
208 /*! @brief Format value for bitfield SIM_SOPT1_OSC32KOUT. */
209 #define BF_SIM_SOPT1_OSC32KOUT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_OSC32KOUT) & BM_SIM_SOPT1_OSC32KOUT)
211 /*! @brief Set the OSC32KOUT field to a new value. */
212 #define BW_SIM_SOPT1_OSC32KOUT(x, v) (HW_SIM_SOPT1_WR(x, (HW_SIM_SOPT1_RD(x) & ~BM_SIM_SOPT1_OSC32KOUT) | BF_SIM_SOPT1_OSC32KOUT(v)))
216 * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
218 * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
222 * - 00 - System oscillator (OSC32KCLK)
224 * - 10 - RTC 32.768kHz oscillator
228 #define BP_SIM_SOPT1_OSC32KSEL (18U) /*!< Bit position for SIM_SOPT1_OSC32KSEL. */
229 #define BM_SIM_SOPT1_OSC32KSEL (0x000C0000U) /*!< Bit mask for SIM_SOPT1_OSC32KSEL. */
230 #define BS_SIM_SOPT1_OSC32KSEL (2U) /*!< Bit field size in bits for SIM_SOPT1_OSC32KSEL. */
232 /*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */
233 #define BR_SIM_SOPT1_OSC32KSEL(x) (HW_SIM_SOPT1(x).B.OSC32KSEL)
235 /*! @brief Format value for bitfield SIM_SOPT1_OSC32KSEL. */
236 #define BF_SIM_SOPT1_OSC32KSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_OSC32KSEL) & BM_SIM_SOPT1_OSC32KSEL)
238 /*! @brief Set the OSC32KSEL field to a new value. */
239 #define BW_SIM_SOPT1_OSC32KSEL(x, v) (HW_SIM_SOPT1_WR(x, (HW_SIM_SOPT1_RD(x) & ~BM_SIM_SOPT1_OSC32KSEL) | BF_SIM_SOPT1_OSC32KSEL(v)))
243 * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
245 * Controls whether the USB voltage regulator is placed in standby mode during
246 * VLPR and VLPW modes.
249 * - 0 - USB voltage regulator not in standby during VLPR and VLPW modes.
250 * - 1 - USB voltage regulator in standby during VLPR and VLPW modes.
253 #define BP_SIM_SOPT1_USBVSTBY (29U) /*!< Bit position for SIM_SOPT1_USBVSTBY. */
254 #define BM_SIM_SOPT1_USBVSTBY (0x20000000U) /*!< Bit mask for SIM_SOPT1_USBVSTBY. */
255 #define BS_SIM_SOPT1_USBVSTBY (1U) /*!< Bit field size in bits for SIM_SOPT1_USBVSTBY. */
257 /*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */
258 #define BR_SIM_SOPT1_USBVSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY))
260 /*! @brief Format value for bitfield SIM_SOPT1_USBVSTBY. */
261 #define BF_SIM_SOPT1_USBVSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBVSTBY) & BM_SIM_SOPT1_USBVSTBY)
263 /*! @brief Set the USBVSTBY field to a new value. */
264 #define BW_SIM_SOPT1_USBVSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY) = (v))
268 * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
270 * Controls whether the USB voltage regulator is placed in standby mode during
271 * Stop, VLPS, LLS and VLLS modes.
274 * - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
276 * - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
279 #define BP_SIM_SOPT1_USBSSTBY (30U) /*!< Bit position for SIM_SOPT1_USBSSTBY. */
280 #define BM_SIM_SOPT1_USBSSTBY (0x40000000U) /*!< Bit mask for SIM_SOPT1_USBSSTBY. */
281 #define BS_SIM_SOPT1_USBSSTBY (1U) /*!< Bit field size in bits for SIM_SOPT1_USBSSTBY. */
283 /*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */
284 #define BR_SIM_SOPT1_USBSSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY))
286 /*! @brief Format value for bitfield SIM_SOPT1_USBSSTBY. */
287 #define BF_SIM_SOPT1_USBSSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBSSTBY) & BM_SIM_SOPT1_USBSSTBY)
289 /*! @brief Set the USBSSTBY field to a new value. */
290 #define BW_SIM_SOPT1_USBSSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY) = (v))
294 * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
296 * Controls whether the USB voltage regulator is enabled.
299 * - 0 - USB voltage regulator is disabled.
300 * - 1 - USB voltage regulator is enabled.
303 #define BP_SIM_SOPT1_USBREGEN (31U) /*!< Bit position for SIM_SOPT1_USBREGEN. */
304 #define BM_SIM_SOPT1_USBREGEN (0x80000000U) /*!< Bit mask for SIM_SOPT1_USBREGEN. */
305 #define BS_SIM_SOPT1_USBREGEN (1U) /*!< Bit field size in bits for SIM_SOPT1_USBREGEN. */
307 /*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */
308 #define BR_SIM_SOPT1_USBREGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN))
310 /*! @brief Format value for bitfield SIM_SOPT1_USBREGEN. */
311 #define BF_SIM_SOPT1_USBREGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBREGEN) & BM_SIM_SOPT1_USBREGEN)
313 /*! @brief Set the USBREGEN field to a new value. */
314 #define BW_SIM_SOPT1_USBREGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN) = (v))
317 /*******************************************************************************
318 * HW_SIM_SOPT1CFG - SOPT1 Configuration Register
319 ******************************************************************************/
322 * @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
324 * Reset value: 0x00000000U
326 * The SOPT1CFG register is reset on System Reset not VLLS.
328 typedef union _hw_sim_sopt1cfg
331 struct _hw_sim_sopt1cfg_bitfields
333 uint32_t RESERVED0 : 24; /*!< [23:0] */
334 uint32_t URWE : 1; /*!< [24] USB voltage regulator enable write
336 uint32_t UVSWE : 1; /*!< [25] USB voltage regulator VLP standby write
338 uint32_t USSWE : 1; /*!< [26] USB voltage regulator stop standby
340 uint32_t RESERVED1 : 5; /*!< [31:27] */
345 * @name Constants and macros for entire SIM_SOPT1CFG register
348 #define HW_SIM_SOPT1CFG_ADDR(x) ((x) + 0x4U)
350 #define HW_SIM_SOPT1CFG(x) (*(__IO hw_sim_sopt1cfg_t *) HW_SIM_SOPT1CFG_ADDR(x))
351 #define HW_SIM_SOPT1CFG_RD(x) (HW_SIM_SOPT1CFG(x).U)
352 #define HW_SIM_SOPT1CFG_WR(x, v) (HW_SIM_SOPT1CFG(x).U = (v))
353 #define HW_SIM_SOPT1CFG_SET(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) | (v)))
354 #define HW_SIM_SOPT1CFG_CLR(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) & ~(v)))
355 #define HW_SIM_SOPT1CFG_TOG(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) ^ (v)))
359 * Constants & macros for individual SIM_SOPT1CFG bitfields
363 * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
365 * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
366 * register bit clears after a write to USBREGEN.
369 * - 0 - SOPT1 USBREGEN cannot be written.
370 * - 1 - SOPT1 USBREGEN can be written.
373 #define BP_SIM_SOPT1CFG_URWE (24U) /*!< Bit position for SIM_SOPT1CFG_URWE. */
374 #define BM_SIM_SOPT1CFG_URWE (0x01000000U) /*!< Bit mask for SIM_SOPT1CFG_URWE. */
375 #define BS_SIM_SOPT1CFG_URWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_URWE. */
377 /*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */
378 #define BR_SIM_SOPT1CFG_URWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE))
380 /*! @brief Format value for bitfield SIM_SOPT1CFG_URWE. */
381 #define BF_SIM_SOPT1CFG_URWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_URWE) & BM_SIM_SOPT1CFG_URWE)
383 /*! @brief Set the URWE field to a new value. */
384 #define BW_SIM_SOPT1CFG_URWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE) = (v))
388 * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
390 * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
391 * This register bit clears after a write to USBVSTBY.
394 * - 0 - SOPT1 USBVSTBY cannot be written.
395 * - 1 - SOPT1 USBVSTBY can be written.
398 #define BP_SIM_SOPT1CFG_UVSWE (25U) /*!< Bit position for SIM_SOPT1CFG_UVSWE. */
399 #define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) /*!< Bit mask for SIM_SOPT1CFG_UVSWE. */
400 #define BS_SIM_SOPT1CFG_UVSWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_UVSWE. */
402 /*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */
403 #define BR_SIM_SOPT1CFG_UVSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE))
405 /*! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE. */
406 #define BF_SIM_SOPT1CFG_UVSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_UVSWE) & BM_SIM_SOPT1CFG_UVSWE)
408 /*! @brief Set the UVSWE field to a new value. */
409 #define BW_SIM_SOPT1CFG_UVSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE) = (v))
413 * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
415 * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
416 * This register bit clears after a write to USBSSTBY.
419 * - 0 - SOPT1 USBSSTBY cannot be written.
420 * - 1 - SOPT1 USBSSTBY can be written.
423 #define BP_SIM_SOPT1CFG_USSWE (26U) /*!< Bit position for SIM_SOPT1CFG_USSWE. */
424 #define BM_SIM_SOPT1CFG_USSWE (0x04000000U) /*!< Bit mask for SIM_SOPT1CFG_USSWE. */
425 #define BS_SIM_SOPT1CFG_USSWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_USSWE. */
427 /*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */
428 #define BR_SIM_SOPT1CFG_USSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE))
430 /*! @brief Format value for bitfield SIM_SOPT1CFG_USSWE. */
431 #define BF_SIM_SOPT1CFG_USSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_USSWE) & BM_SIM_SOPT1CFG_USSWE)
433 /*! @brief Set the USSWE field to a new value. */
434 #define BW_SIM_SOPT1CFG_USSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE) = (v))
437 /*******************************************************************************
438 * HW_SIM_SOPT2 - System Options Register 2
439 ******************************************************************************/
442 * @brief HW_SIM_SOPT2 - System Options Register 2 (RW)
444 * Reset value: 0x00001000U
446 * SOPT2 contains the controls for selecting many of the module clock source
447 * options on this device. See the Clock Distribution chapter for more information
448 * including clocking diagrams and definitions of device clocks.
450 typedef union _hw_sim_sopt2
453 struct _hw_sim_sopt2_bitfields
455 uint32_t RESERVED0 : 4; /*!< [3:0] */
456 uint32_t RTCCLKOUTSEL : 1; /*!< [4] RTC clock out select */
457 uint32_t CLKOUTSEL : 3; /*!< [7:5] CLKOUT select */
458 uint32_t FBSL : 2; /*!< [9:8] FlexBus security level */
459 uint32_t RESERVED1 : 2; /*!< [11:10] */
460 uint32_t TRACECLKSEL : 1; /*!< [12] Debug trace clock select */
461 uint32_t RESERVED2 : 3; /*!< [15:13] */
462 uint32_t PLLFLLSEL : 2; /*!< [17:16] PLL/FLL clock select */
463 uint32_t USBSRC : 1; /*!< [18] USB clock source select */
464 uint32_t RESERVED3 : 7; /*!< [25:19] */
465 uint32_t LPUARTSRC : 2; /*!< [27:26] LPUART clock source select */
466 uint32_t RESERVED4 : 4; /*!< [31:28] */
471 * @name Constants and macros for entire SIM_SOPT2 register
474 #define HW_SIM_SOPT2_ADDR(x) ((x) + 0x1004U)
476 #define HW_SIM_SOPT2(x) (*(__IO hw_sim_sopt2_t *) HW_SIM_SOPT2_ADDR(x))
477 #define HW_SIM_SOPT2_RD(x) (HW_SIM_SOPT2(x).U)
478 #define HW_SIM_SOPT2_WR(x, v) (HW_SIM_SOPT2(x).U = (v))
479 #define HW_SIM_SOPT2_SET(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) | (v)))
480 #define HW_SIM_SOPT2_CLR(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) & ~(v)))
481 #define HW_SIM_SOPT2_TOG(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) ^ (v)))
485 * Constants & macros for individual SIM_SOPT2 bitfields
489 * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
491 * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
495 * - 0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
496 * - 1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
499 #define BP_SIM_SOPT2_RTCCLKOUTSEL (4U) /*!< Bit position for SIM_SOPT2_RTCCLKOUTSEL. */
500 #define BM_SIM_SOPT2_RTCCLKOUTSEL (0x00000010U) /*!< Bit mask for SIM_SOPT2_RTCCLKOUTSEL. */
501 #define BS_SIM_SOPT2_RTCCLKOUTSEL (1U) /*!< Bit field size in bits for SIM_SOPT2_RTCCLKOUTSEL. */
503 /*! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. */
504 #define BR_SIM_SOPT2_RTCCLKOUTSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL))
506 /*! @brief Format value for bitfield SIM_SOPT2_RTCCLKOUTSEL. */
507 #define BF_SIM_SOPT2_RTCCLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RTCCLKOUTSEL) & BM_SIM_SOPT2_RTCCLKOUTSEL)
509 /*! @brief Set the RTCCLKOUTSEL field to a new value. */
510 #define BW_SIM_SOPT2_RTCCLKOUTSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL) = (v))
514 * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
516 * Selects the clock to output on the CLKOUT pin.
519 * - 000 - FlexBus CLKOUT
521 * - 010 - Flash clock
522 * - 011 - LPO clock (1 kHz)
524 * - 101 - RTC 32.768kHz clock
526 * - 111 - IRC 48 MHz clock
529 #define BP_SIM_SOPT2_CLKOUTSEL (5U) /*!< Bit position for SIM_SOPT2_CLKOUTSEL. */
530 #define BM_SIM_SOPT2_CLKOUTSEL (0x000000E0U) /*!< Bit mask for SIM_SOPT2_CLKOUTSEL. */
531 #define BS_SIM_SOPT2_CLKOUTSEL (3U) /*!< Bit field size in bits for SIM_SOPT2_CLKOUTSEL. */
533 /*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */
534 #define BR_SIM_SOPT2_CLKOUTSEL(x) (HW_SIM_SOPT2(x).B.CLKOUTSEL)
536 /*! @brief Format value for bitfield SIM_SOPT2_CLKOUTSEL. */
537 #define BF_SIM_SOPT2_CLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_CLKOUTSEL) & BM_SIM_SOPT2_CLKOUTSEL)
539 /*! @brief Set the CLKOUTSEL field to a new value. */
540 #define BW_SIM_SOPT2_CLKOUTSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_CLKOUTSEL) | BF_SIM_SOPT2_CLKOUTSEL(v)))
544 * @name Register SIM_SOPT2, field FBSL[9:8] (RW)
546 * If flash security is enabled, then this field affects what CPU operations can
547 * access off-chip via the FlexBus interface. This field has no effect if flash
548 * security is not enabled.
551 * - 00 - All off-chip accesses (instruction and data) via the FlexBus are
553 * - 01 - All off-chip accesses (instruction and data) via the FlexBus are
555 * - 10 - Off-chip instruction accesses are disallowed. Data accesses are
557 * - 11 - Off-chip instruction accesses and data accesses are allowed.
560 #define BP_SIM_SOPT2_FBSL (8U) /*!< Bit position for SIM_SOPT2_FBSL. */
561 #define BM_SIM_SOPT2_FBSL (0x00000300U) /*!< Bit mask for SIM_SOPT2_FBSL. */
562 #define BS_SIM_SOPT2_FBSL (2U) /*!< Bit field size in bits for SIM_SOPT2_FBSL. */
564 /*! @brief Read current value of the SIM_SOPT2_FBSL field. */
565 #define BR_SIM_SOPT2_FBSL(x) (HW_SIM_SOPT2(x).B.FBSL)
567 /*! @brief Format value for bitfield SIM_SOPT2_FBSL. */
568 #define BF_SIM_SOPT2_FBSL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_FBSL) & BM_SIM_SOPT2_FBSL)
570 /*! @brief Set the FBSL field to a new value. */
571 #define BW_SIM_SOPT2_FBSL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_FBSL) | BF_SIM_SOPT2_FBSL(v)))
575 * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
577 * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
582 * - 1 - Core/system clock
585 #define BP_SIM_SOPT2_TRACECLKSEL (12U) /*!< Bit position for SIM_SOPT2_TRACECLKSEL. */
586 #define BM_SIM_SOPT2_TRACECLKSEL (0x00001000U) /*!< Bit mask for SIM_SOPT2_TRACECLKSEL. */
587 #define BS_SIM_SOPT2_TRACECLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT2_TRACECLKSEL. */
589 /*! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. */
590 #define BR_SIM_SOPT2_TRACECLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL))
592 /*! @brief Format value for bitfield SIM_SOPT2_TRACECLKSEL. */
593 #define BF_SIM_SOPT2_TRACECLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TRACECLKSEL) & BM_SIM_SOPT2_TRACECLKSEL)
595 /*! @brief Set the TRACECLKSEL field to a new value. */
596 #define BW_SIM_SOPT2_TRACECLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL) = (v))
600 * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
602 * Selects the high frequency clock for various peripheral clocking options.
605 * - 00 - MCGFLLCLK clock
606 * - 01 - MCGPLLCLK clock
608 * - 11 - IRC48 MHz clock
611 #define BP_SIM_SOPT2_PLLFLLSEL (16U) /*!< Bit position for SIM_SOPT2_PLLFLLSEL. */
612 #define BM_SIM_SOPT2_PLLFLLSEL (0x00030000U) /*!< Bit mask for SIM_SOPT2_PLLFLLSEL. */
613 #define BS_SIM_SOPT2_PLLFLLSEL (2U) /*!< Bit field size in bits for SIM_SOPT2_PLLFLLSEL. */
615 /*! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. */
616 #define BR_SIM_SOPT2_PLLFLLSEL(x) (HW_SIM_SOPT2(x).B.PLLFLLSEL)
618 /*! @brief Format value for bitfield SIM_SOPT2_PLLFLLSEL. */
619 #define BF_SIM_SOPT2_PLLFLLSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PLLFLLSEL) & BM_SIM_SOPT2_PLLFLLSEL)
621 /*! @brief Set the PLLFLLSEL field to a new value. */
622 #define BW_SIM_SOPT2_PLLFLLSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_PLLFLLSEL) | BF_SIM_SOPT2_PLLFLLSEL(v)))
626 * @name Register SIM_SOPT2, field USBSRC[18] (RW)
628 * Selects the clock source for the USB 48 MHz clock.
631 * - 0 - External bypass clock (USB_CLKIN).
632 * - 1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
633 * SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
634 * SIM_CLKDIV2[USBFRAC, USBDIV].
637 #define BP_SIM_SOPT2_USBSRC (18U) /*!< Bit position for SIM_SOPT2_USBSRC. */
638 #define BM_SIM_SOPT2_USBSRC (0x00040000U) /*!< Bit mask for SIM_SOPT2_USBSRC. */
639 #define BS_SIM_SOPT2_USBSRC (1U) /*!< Bit field size in bits for SIM_SOPT2_USBSRC. */
641 /*! @brief Read current value of the SIM_SOPT2_USBSRC field. */
642 #define BR_SIM_SOPT2_USBSRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC))
644 /*! @brief Format value for bitfield SIM_SOPT2_USBSRC. */
645 #define BF_SIM_SOPT2_USBSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_USBSRC) & BM_SIM_SOPT2_USBSRC)
647 /*! @brief Set the USBSRC field to a new value. */
648 #define BW_SIM_SOPT2_USBSRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC) = (v))
652 * @name Register SIM_SOPT2, field LPUARTSRC[27:26] (RW)
654 * Selects the clock source for the LPUART transmit and receive clock.
657 * - 00 - Clock disabled
658 * - 01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
660 * - 10 - OSCERCLK clock
661 * - 11 - MCGIRCLK clock
664 #define BP_SIM_SOPT2_LPUARTSRC (26U) /*!< Bit position for SIM_SOPT2_LPUARTSRC. */
665 #define BM_SIM_SOPT2_LPUARTSRC (0x0C000000U) /*!< Bit mask for SIM_SOPT2_LPUARTSRC. */
666 #define BS_SIM_SOPT2_LPUARTSRC (2U) /*!< Bit field size in bits for SIM_SOPT2_LPUARTSRC. */
668 /*! @brief Read current value of the SIM_SOPT2_LPUARTSRC field. */
669 #define BR_SIM_SOPT2_LPUARTSRC(x) (HW_SIM_SOPT2(x).B.LPUARTSRC)
671 /*! @brief Format value for bitfield SIM_SOPT2_LPUARTSRC. */
672 #define BF_SIM_SOPT2_LPUARTSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_LPUARTSRC) & BM_SIM_SOPT2_LPUARTSRC)
674 /*! @brief Set the LPUARTSRC field to a new value. */
675 #define BW_SIM_SOPT2_LPUARTSRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_LPUARTSRC) | BF_SIM_SOPT2_LPUARTSRC(v)))
678 /*******************************************************************************
679 * HW_SIM_SOPT4 - System Options Register 4
680 ******************************************************************************/
683 * @brief HW_SIM_SOPT4 - System Options Register 4 (RW)
685 * Reset value: 0x00000000U
687 typedef union _hw_sim_sopt4
690 struct _hw_sim_sopt4_bitfields
692 uint32_t FTM0FLT0 : 1; /*!< [0] FTM0 Fault 0 Select */
693 uint32_t FTM0FLT1 : 1; /*!< [1] FTM0 Fault 1 Select */
694 uint32_t RESERVED0 : 2; /*!< [3:2] */
695 uint32_t FTM1FLT0 : 1; /*!< [4] FTM1 Fault 0 Select */
696 uint32_t RESERVED1 : 3; /*!< [7:5] */
697 uint32_t FTM2FLT0 : 1; /*!< [8] FTM2 Fault 0 Select */
698 uint32_t RESERVED2 : 3; /*!< [11:9] */
699 uint32_t FTM3FLT0 : 1; /*!< [12] FTM3 Fault 0 Select */
700 uint32_t RESERVED3 : 5; /*!< [17:13] */
701 uint32_t FTM1CH0SRC : 2; /*!< [19:18] FTM1 channel 0 input capture
703 uint32_t FTM2CH0SRC : 2; /*!< [21:20] FTM2 channel 0 input capture
705 uint32_t FTM2CH1SRC : 1; /*!< [22] FTM2 channel 1 input capture
707 uint32_t RESERVED4 : 1; /*!< [23] */
708 uint32_t FTM0CLKSEL : 1; /*!< [24] FlexTimer 0 External Clock Pin
710 uint32_t FTM1CLKSEL : 1; /*!< [25] FTM1 External Clock Pin Select */
711 uint32_t FTM2CLKSEL : 1; /*!< [26] FlexTimer 2 External Clock Pin
713 uint32_t FTM3CLKSEL : 1; /*!< [27] FlexTimer 3 External Clock Pin
715 uint32_t FTM0TRG0SRC : 1; /*!< [28] FlexTimer 0 Hardware Trigger 0
717 uint32_t FTM0TRG1SRC : 1; /*!< [29] FlexTimer 0 Hardware Trigger 1
719 uint32_t FTM3TRG0SRC : 1; /*!< [30] FlexTimer 3 Hardware Trigger 0
721 uint32_t FTM3TRG1SRC : 1; /*!< [31] FlexTimer 3 Hardware Trigger 1
727 * @name Constants and macros for entire SIM_SOPT4 register
730 #define HW_SIM_SOPT4_ADDR(x) ((x) + 0x100CU)
732 #define HW_SIM_SOPT4(x) (*(__IO hw_sim_sopt4_t *) HW_SIM_SOPT4_ADDR(x))
733 #define HW_SIM_SOPT4_RD(x) (HW_SIM_SOPT4(x).U)
734 #define HW_SIM_SOPT4_WR(x, v) (HW_SIM_SOPT4(x).U = (v))
735 #define HW_SIM_SOPT4_SET(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) | (v)))
736 #define HW_SIM_SOPT4_CLR(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) & ~(v)))
737 #define HW_SIM_SOPT4_TOG(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) ^ (v)))
741 * Constants & macros for individual SIM_SOPT4 bitfields
745 * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
747 * Selects the source of FTM0 fault 0. The pin source for fault 0 must be
748 * configured for the FTM module fault function through the appropriate pin control
749 * register in the port control module.
752 * - 0 - FTM0_FLT0 pin
756 #define BP_SIM_SOPT4_FTM0FLT0 (0U) /*!< Bit position for SIM_SOPT4_FTM0FLT0. */
757 #define BM_SIM_SOPT4_FTM0FLT0 (0x00000001U) /*!< Bit mask for SIM_SOPT4_FTM0FLT0. */
758 #define BS_SIM_SOPT4_FTM0FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT0. */
760 /*! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. */
761 #define BR_SIM_SOPT4_FTM0FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0))
763 /*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT0. */
764 #define BF_SIM_SOPT4_FTM0FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT0) & BM_SIM_SOPT4_FTM0FLT0)
766 /*! @brief Set the FTM0FLT0 field to a new value. */
767 #define BW_SIM_SOPT4_FTM0FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0) = (v))
771 * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
773 * Selects the source of FTM0 fault 1. The pin source for fault 1 must be
774 * configured for the FTM module fault function through the appropriate pin control
775 * register in the port control module.
778 * - 0 - FTM0_FLT1 pin
782 #define BP_SIM_SOPT4_FTM0FLT1 (1U) /*!< Bit position for SIM_SOPT4_FTM0FLT1. */
783 #define BM_SIM_SOPT4_FTM0FLT1 (0x00000002U) /*!< Bit mask for SIM_SOPT4_FTM0FLT1. */
784 #define BS_SIM_SOPT4_FTM0FLT1 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT1. */
786 /*! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. */
787 #define BR_SIM_SOPT4_FTM0FLT1(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1))
789 /*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT1. */
790 #define BF_SIM_SOPT4_FTM0FLT1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT1) & BM_SIM_SOPT4_FTM0FLT1)
792 /*! @brief Set the FTM0FLT1 field to a new value. */
793 #define BW_SIM_SOPT4_FTM0FLT1(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1) = (v))
797 * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
799 * Selects the source of FTM1 fault 0. The pin source for fault 0 must be
800 * configured for the FTM module fault function through the appropriate pin control
801 * register in the port control module.
804 * - 0 - FTM1_FLT0 pin
808 #define BP_SIM_SOPT4_FTM1FLT0 (4U) /*!< Bit position for SIM_SOPT4_FTM1FLT0. */
809 #define BM_SIM_SOPT4_FTM1FLT0 (0x00000010U) /*!< Bit mask for SIM_SOPT4_FTM1FLT0. */
810 #define BS_SIM_SOPT4_FTM1FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM1FLT0. */
812 /*! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. */
813 #define BR_SIM_SOPT4_FTM1FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0))
815 /*! @brief Format value for bitfield SIM_SOPT4_FTM1FLT0. */
816 #define BF_SIM_SOPT4_FTM1FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1FLT0) & BM_SIM_SOPT4_FTM1FLT0)
818 /*! @brief Set the FTM1FLT0 field to a new value. */
819 #define BW_SIM_SOPT4_FTM1FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0) = (v))
823 * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
825 * Selects the source of FTM2 fault 0. The pin source for fault 0 must be
826 * configured for the FTM module fault function through the appropriate PORTx pin
830 * - 0 - FTM2_FLT0 pin
834 #define BP_SIM_SOPT4_FTM2FLT0 (8U) /*!< Bit position for SIM_SOPT4_FTM2FLT0. */
835 #define BM_SIM_SOPT4_FTM2FLT0 (0x00000100U) /*!< Bit mask for SIM_SOPT4_FTM2FLT0. */
836 #define BS_SIM_SOPT4_FTM2FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM2FLT0. */
838 /*! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. */
839 #define BR_SIM_SOPT4_FTM2FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0))
841 /*! @brief Format value for bitfield SIM_SOPT4_FTM2FLT0. */
842 #define BF_SIM_SOPT4_FTM2FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2FLT0) & BM_SIM_SOPT4_FTM2FLT0)
844 /*! @brief Set the FTM2FLT0 field to a new value. */
845 #define BW_SIM_SOPT4_FTM2FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0) = (v))
849 * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
851 * Selects the source of FTM3 fault 0. The pin source for fault 0 must be
852 * configured for the FTM module fault function through the appropriate PORTx pin
856 * - 0 - FTM3_FLT0 pin
860 #define BP_SIM_SOPT4_FTM3FLT0 (12U) /*!< Bit position for SIM_SOPT4_FTM3FLT0. */
861 #define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) /*!< Bit mask for SIM_SOPT4_FTM3FLT0. */
862 #define BS_SIM_SOPT4_FTM3FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3FLT0. */
864 /*! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. */
865 #define BR_SIM_SOPT4_FTM3FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0))
867 /*! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0. */
868 #define BF_SIM_SOPT4_FTM3FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3FLT0) & BM_SIM_SOPT4_FTM3FLT0)
870 /*! @brief Set the FTM3FLT0 field to a new value. */
871 #define BW_SIM_SOPT4_FTM3FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0) = (v))
875 * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
877 * Selects the source for FTM1 channel 0 input capture. When the FTM is not in
878 * input capture mode, clear this field.
881 * - 00 - FTM1_CH0 signal
884 * - 11 - USB start of frame pulse
887 #define BP_SIM_SOPT4_FTM1CH0SRC (18U) /*!< Bit position for SIM_SOPT4_FTM1CH0SRC. */
888 #define BM_SIM_SOPT4_FTM1CH0SRC (0x000C0000U) /*!< Bit mask for SIM_SOPT4_FTM1CH0SRC. */
889 #define BS_SIM_SOPT4_FTM1CH0SRC (2U) /*!< Bit field size in bits for SIM_SOPT4_FTM1CH0SRC. */
891 /*! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. */
892 #define BR_SIM_SOPT4_FTM1CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM1CH0SRC)
894 /*! @brief Format value for bitfield SIM_SOPT4_FTM1CH0SRC. */
895 #define BF_SIM_SOPT4_FTM1CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CH0SRC) & BM_SIM_SOPT4_FTM1CH0SRC)
897 /*! @brief Set the FTM1CH0SRC field to a new value. */
898 #define BW_SIM_SOPT4_FTM1CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM1CH0SRC) | BF_SIM_SOPT4_FTM1CH0SRC(v)))
902 * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
904 * Selects the source for FTM2 channel 0 input capture. When the FTM is not in
905 * input capture mode, clear this field.
908 * - 00 - FTM2_CH0 signal
914 #define BP_SIM_SOPT4_FTM2CH0SRC (20U) /*!< Bit position for SIM_SOPT4_FTM2CH0SRC. */
915 #define BM_SIM_SOPT4_FTM2CH0SRC (0x00300000U) /*!< Bit mask for SIM_SOPT4_FTM2CH0SRC. */
916 #define BS_SIM_SOPT4_FTM2CH0SRC (2U) /*!< Bit field size in bits for SIM_SOPT4_FTM2CH0SRC. */
918 /*! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. */
919 #define BR_SIM_SOPT4_FTM2CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM2CH0SRC)
921 /*! @brief Format value for bitfield SIM_SOPT4_FTM2CH0SRC. */
922 #define BF_SIM_SOPT4_FTM2CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CH0SRC) & BM_SIM_SOPT4_FTM2CH0SRC)
924 /*! @brief Set the FTM2CH0SRC field to a new value. */
925 #define BW_SIM_SOPT4_FTM2CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM2CH0SRC) | BF_SIM_SOPT4_FTM2CH0SRC(v)))
929 * @name Register SIM_SOPT4, field FTM2CH1SRC[22] (RW)
932 * - 0 - FTM2_CH1 signal
933 * - 1 - Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1.
936 #define BP_SIM_SOPT4_FTM2CH1SRC (22U) /*!< Bit position for SIM_SOPT4_FTM2CH1SRC. */
937 #define BM_SIM_SOPT4_FTM2CH1SRC (0x00400000U) /*!< Bit mask for SIM_SOPT4_FTM2CH1SRC. */
938 #define BS_SIM_SOPT4_FTM2CH1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM2CH1SRC. */
940 /*! @brief Read current value of the SIM_SOPT4_FTM2CH1SRC field. */
941 #define BR_SIM_SOPT4_FTM2CH1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CH1SRC))
943 /*! @brief Format value for bitfield SIM_SOPT4_FTM2CH1SRC. */
944 #define BF_SIM_SOPT4_FTM2CH1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CH1SRC) & BM_SIM_SOPT4_FTM2CH1SRC)
946 /*! @brief Set the FTM2CH1SRC field to a new value. */
947 #define BW_SIM_SOPT4_FTM2CH1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CH1SRC) = (v))
951 * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
953 * Selects the external pin used to drive the clock to the FTM0 module. The
954 * selected pin must also be configured for the FTM external clock function through
955 * the appropriate pin control register in the port control module.
962 #define BP_SIM_SOPT4_FTM0CLKSEL (24U) /*!< Bit position for SIM_SOPT4_FTM0CLKSEL. */
963 #define BM_SIM_SOPT4_FTM0CLKSEL (0x01000000U) /*!< Bit mask for SIM_SOPT4_FTM0CLKSEL. */
964 #define BS_SIM_SOPT4_FTM0CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0CLKSEL. */
966 /*! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. */
967 #define BR_SIM_SOPT4_FTM0CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL))
969 /*! @brief Format value for bitfield SIM_SOPT4_FTM0CLKSEL. */
970 #define BF_SIM_SOPT4_FTM0CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0CLKSEL) & BM_SIM_SOPT4_FTM0CLKSEL)
972 /*! @brief Set the FTM0CLKSEL field to a new value. */
973 #define BW_SIM_SOPT4_FTM0CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL) = (v))
977 * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
979 * Selects the external pin used to drive the clock to the FTM1 module. The
980 * selected pin must also be configured for the FTM external clock function through
981 * the appropriate pin control register in the port control module.
988 #define BP_SIM_SOPT4_FTM1CLKSEL (25U) /*!< Bit position for SIM_SOPT4_FTM1CLKSEL. */
989 #define BM_SIM_SOPT4_FTM1CLKSEL (0x02000000U) /*!< Bit mask for SIM_SOPT4_FTM1CLKSEL. */
990 #define BS_SIM_SOPT4_FTM1CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM1CLKSEL. */
992 /*! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. */
993 #define BR_SIM_SOPT4_FTM1CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL))
995 /*! @brief Format value for bitfield SIM_SOPT4_FTM1CLKSEL. */
996 #define BF_SIM_SOPT4_FTM1CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CLKSEL) & BM_SIM_SOPT4_FTM1CLKSEL)
998 /*! @brief Set the FTM1CLKSEL field to a new value. */
999 #define BW_SIM_SOPT4_FTM1CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL) = (v))
1003 * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
1005 * Selects the external pin used to drive the clock to the FTM2 module. The
1006 * selected pin must also be configured for the FTM2 module external clock function
1007 * through the appropriate pin control register in the port control module.
1010 * - 0 - FTM2 external clock driven by FTM_CLK0 pin.
1011 * - 1 - FTM2 external clock driven by FTM_CLK1 pin.
1014 #define BP_SIM_SOPT4_FTM2CLKSEL (26U) /*!< Bit position for SIM_SOPT4_FTM2CLKSEL. */
1015 #define BM_SIM_SOPT4_FTM2CLKSEL (0x04000000U) /*!< Bit mask for SIM_SOPT4_FTM2CLKSEL. */
1016 #define BS_SIM_SOPT4_FTM2CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM2CLKSEL. */
1018 /*! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. */
1019 #define BR_SIM_SOPT4_FTM2CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL))
1021 /*! @brief Format value for bitfield SIM_SOPT4_FTM2CLKSEL. */
1022 #define BF_SIM_SOPT4_FTM2CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CLKSEL) & BM_SIM_SOPT4_FTM2CLKSEL)
1024 /*! @brief Set the FTM2CLKSEL field to a new value. */
1025 #define BW_SIM_SOPT4_FTM2CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL) = (v))
1029 * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
1031 * Selects the external pin used to drive the clock to the FTM3 module. The
1032 * selected pin must also be configured for the FTM3 module external clock function
1033 * through the appropriate pin control register in the port control module.
1036 * - 0 - FTM3 external clock driven by FTM_CLK0 pin.
1037 * - 1 - FTM3 external clock driven by FTM_CLK1 pin.
1040 #define BP_SIM_SOPT4_FTM3CLKSEL (27U) /*!< Bit position for SIM_SOPT4_FTM3CLKSEL. */
1041 #define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) /*!< Bit mask for SIM_SOPT4_FTM3CLKSEL. */
1042 #define BS_SIM_SOPT4_FTM3CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL. */
1044 /*! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. */
1045 #define BR_SIM_SOPT4_FTM3CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL))
1047 /*! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL. */
1048 #define BF_SIM_SOPT4_FTM3CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3CLKSEL) & BM_SIM_SOPT4_FTM3CLKSEL)
1050 /*! @brief Set the FTM3CLKSEL field to a new value. */
1051 #define BW_SIM_SOPT4_FTM3CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL) = (v))
1055 * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
1057 * Selects the source of FTM0 hardware trigger 0.
1060 * - 0 - HSCMP0 output drives FTM0 hardware trigger 0
1061 * - 1 - FTM1 channel match drives FTM0 hardware trigger 0
1064 #define BP_SIM_SOPT4_FTM0TRG0SRC (28U) /*!< Bit position for SIM_SOPT4_FTM0TRG0SRC. */
1065 #define BM_SIM_SOPT4_FTM0TRG0SRC (0x10000000U) /*!< Bit mask for SIM_SOPT4_FTM0TRG0SRC. */
1066 #define BS_SIM_SOPT4_FTM0TRG0SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0TRG0SRC. */
1068 /*! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. */
1069 #define BR_SIM_SOPT4_FTM0TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC))
1071 /*! @brief Format value for bitfield SIM_SOPT4_FTM0TRG0SRC. */
1072 #define BF_SIM_SOPT4_FTM0TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG0SRC) & BM_SIM_SOPT4_FTM0TRG0SRC)
1074 /*! @brief Set the FTM0TRG0SRC field to a new value. */
1075 #define BW_SIM_SOPT4_FTM0TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC) = (v))
1079 * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
1081 * Selects the source of FTM0 hardware trigger 1.
1084 * - 0 - PDB output trigger 1 drives FTM0 hardware trigger 1
1085 * - 1 - FTM2 channel match drives FTM0 hardware trigger 1
1088 #define BP_SIM_SOPT4_FTM0TRG1SRC (29U) /*!< Bit position for SIM_SOPT4_FTM0TRG1SRC. */
1089 #define BM_SIM_SOPT4_FTM0TRG1SRC (0x20000000U) /*!< Bit mask for SIM_SOPT4_FTM0TRG1SRC. */
1090 #define BS_SIM_SOPT4_FTM0TRG1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0TRG1SRC. */
1092 /*! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. */
1093 #define BR_SIM_SOPT4_FTM0TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC))
1095 /*! @brief Format value for bitfield SIM_SOPT4_FTM0TRG1SRC. */
1096 #define BF_SIM_SOPT4_FTM0TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG1SRC) & BM_SIM_SOPT4_FTM0TRG1SRC)
1098 /*! @brief Set the FTM0TRG1SRC field to a new value. */
1099 #define BW_SIM_SOPT4_FTM0TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC) = (v))
1103 * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
1105 * Selects the source of FTM3 hardware trigger 0.
1109 * - 1 - FTM1 channel match drives FTM3 hardware trigger 0
1112 #define BP_SIM_SOPT4_FTM3TRG0SRC (30U) /*!< Bit position for SIM_SOPT4_FTM3TRG0SRC. */
1113 #define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG0SRC. */
1114 #define BS_SIM_SOPT4_FTM3TRG0SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC. */
1116 /*! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. */
1117 #define BR_SIM_SOPT4_FTM3TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC))
1119 /*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC. */
1120 #define BF_SIM_SOPT4_FTM3TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG0SRC) & BM_SIM_SOPT4_FTM3TRG0SRC)
1122 /*! @brief Set the FTM3TRG0SRC field to a new value. */
1123 #define BW_SIM_SOPT4_FTM3TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC) = (v))
1127 * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
1129 * Selects the source of FTM3 hardware trigger 1.
1133 * - 1 - FTM2 channel match drives FTM3 hardware trigger 1
1136 #define BP_SIM_SOPT4_FTM3TRG1SRC (31U) /*!< Bit position for SIM_SOPT4_FTM3TRG1SRC. */
1137 #define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG1SRC. */
1138 #define BS_SIM_SOPT4_FTM3TRG1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC. */
1140 /*! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. */
1141 #define BR_SIM_SOPT4_FTM3TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC))
1143 /*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC. */
1144 #define BF_SIM_SOPT4_FTM3TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG1SRC) & BM_SIM_SOPT4_FTM3TRG1SRC)
1146 /*! @brief Set the FTM3TRG1SRC field to a new value. */
1147 #define BW_SIM_SOPT4_FTM3TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC) = (v))
1150 /*******************************************************************************
1151 * HW_SIM_SOPT5 - System Options Register 5
1152 ******************************************************************************/
1155 * @brief HW_SIM_SOPT5 - System Options Register 5 (RW)
1157 * Reset value: 0x00000000U
1159 typedef union _hw_sim_sopt5
1162 struct _hw_sim_sopt5_bitfields
1164 uint32_t UART0TXSRC : 2; /*!< [1:0] UART 0 transmit data source
1166 uint32_t UART0RXSRC : 2; /*!< [3:2] UART 0 receive data source select
1168 uint32_t UART1TXSRC : 2; /*!< [5:4] UART 1 transmit data source
1170 uint32_t UART1RXSRC : 2; /*!< [7:6] UART 1 receive data source select
1172 uint32_t RESERVED0 : 10; /*!< [17:8] */
1173 uint32_t LPUART0RXSRC : 2; /*!< [19:18] LPUART0 receive data source
1175 uint32_t RESERVED1 : 12; /*!< [31:20] */
1180 * @name Constants and macros for entire SIM_SOPT5 register
1183 #define HW_SIM_SOPT5_ADDR(x) ((x) + 0x1010U)
1185 #define HW_SIM_SOPT5(x) (*(__IO hw_sim_sopt5_t *) HW_SIM_SOPT5_ADDR(x))
1186 #define HW_SIM_SOPT5_RD(x) (HW_SIM_SOPT5(x).U)
1187 #define HW_SIM_SOPT5_WR(x, v) (HW_SIM_SOPT5(x).U = (v))
1188 #define HW_SIM_SOPT5_SET(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) | (v)))
1189 #define HW_SIM_SOPT5_CLR(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) & ~(v)))
1190 #define HW_SIM_SOPT5_TOG(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) ^ (v)))
1194 * Constants & macros for individual SIM_SOPT5 bitfields
1198 * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
1200 * Selects the source for the UART 0 transmit data.
1203 * - 00 - UART0_TX pin
1204 * - 01 - UART0_TX pin modulated with FTM1 channel 0 output
1205 * - 10 - UART0_TX pin modulated with FTM2 channel 0 output
1209 #define BP_SIM_SOPT5_UART0TXSRC (0U) /*!< Bit position for SIM_SOPT5_UART0TXSRC. */
1210 #define BM_SIM_SOPT5_UART0TXSRC (0x00000003U) /*!< Bit mask for SIM_SOPT5_UART0TXSRC. */
1211 #define BS_SIM_SOPT5_UART0TXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART0TXSRC. */
1213 /*! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. */
1214 #define BR_SIM_SOPT5_UART0TXSRC(x) (HW_SIM_SOPT5(x).B.UART0TXSRC)
1216 /*! @brief Format value for bitfield SIM_SOPT5_UART0TXSRC. */
1217 #define BF_SIM_SOPT5_UART0TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0TXSRC) & BM_SIM_SOPT5_UART0TXSRC)
1219 /*! @brief Set the UART0TXSRC field to a new value. */
1220 #define BW_SIM_SOPT5_UART0TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0TXSRC) | BF_SIM_SOPT5_UART0TXSRC(v)))
1224 * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
1226 * Selects the source for the UART 0 receive data.
1229 * - 00 - UART0_RX pin
1235 #define BP_SIM_SOPT5_UART0RXSRC (2U) /*!< Bit position for SIM_SOPT5_UART0RXSRC. */
1236 #define BM_SIM_SOPT5_UART0RXSRC (0x0000000CU) /*!< Bit mask for SIM_SOPT5_UART0RXSRC. */
1237 #define BS_SIM_SOPT5_UART0RXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART0RXSRC. */
1239 /*! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. */
1240 #define BR_SIM_SOPT5_UART0RXSRC(x) (HW_SIM_SOPT5(x).B.UART0RXSRC)
1242 /*! @brief Format value for bitfield SIM_SOPT5_UART0RXSRC. */
1243 #define BF_SIM_SOPT5_UART0RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0RXSRC) & BM_SIM_SOPT5_UART0RXSRC)
1245 /*! @brief Set the UART0RXSRC field to a new value. */
1246 #define BW_SIM_SOPT5_UART0RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0RXSRC) | BF_SIM_SOPT5_UART0RXSRC(v)))
1250 * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
1252 * Selects the source for the UART 1 transmit data.
1255 * - 00 - UART1_TX pin
1256 * - 01 - UART1_TX pin modulated with FTM1 channel 0 output
1257 * - 10 - UART1_TX pin modulated with FTM2 channel 0 output
1261 #define BP_SIM_SOPT5_UART1TXSRC (4U) /*!< Bit position for SIM_SOPT5_UART1TXSRC. */
1262 #define BM_SIM_SOPT5_UART1TXSRC (0x00000030U) /*!< Bit mask for SIM_SOPT5_UART1TXSRC. */
1263 #define BS_SIM_SOPT5_UART1TXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART1TXSRC. */
1265 /*! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. */
1266 #define BR_SIM_SOPT5_UART1TXSRC(x) (HW_SIM_SOPT5(x).B.UART1TXSRC)
1268 /*! @brief Format value for bitfield SIM_SOPT5_UART1TXSRC. */
1269 #define BF_SIM_SOPT5_UART1TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1TXSRC) & BM_SIM_SOPT5_UART1TXSRC)
1271 /*! @brief Set the UART1TXSRC field to a new value. */
1272 #define BW_SIM_SOPT5_UART1TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1TXSRC) | BF_SIM_SOPT5_UART1TXSRC(v)))
1276 * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
1278 * Selects the source for the UART 1 receive data.
1281 * - 00 - UART1_RX pin
1287 #define BP_SIM_SOPT5_UART1RXSRC (6U) /*!< Bit position for SIM_SOPT5_UART1RXSRC. */
1288 #define BM_SIM_SOPT5_UART1RXSRC (0x000000C0U) /*!< Bit mask for SIM_SOPT5_UART1RXSRC. */
1289 #define BS_SIM_SOPT5_UART1RXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART1RXSRC. */
1291 /*! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. */
1292 #define BR_SIM_SOPT5_UART1RXSRC(x) (HW_SIM_SOPT5(x).B.UART1RXSRC)
1294 /*! @brief Format value for bitfield SIM_SOPT5_UART1RXSRC. */
1295 #define BF_SIM_SOPT5_UART1RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1RXSRC) & BM_SIM_SOPT5_UART1RXSRC)
1297 /*! @brief Set the UART1RXSRC field to a new value. */
1298 #define BW_SIM_SOPT5_UART1RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1RXSRC) | BF_SIM_SOPT5_UART1RXSRC(v)))
1302 * @name Register SIM_SOPT5, field LPUART0RXSRC[19:18] (RW)
1304 * Selects the source for the LPUART0 receive data.
1307 * - 00 - LPUART0_RX pin
1308 * - 01 - CMP0 output
1309 * - 10 - CMP1 output
1313 #define BP_SIM_SOPT5_LPUART0RXSRC (18U) /*!< Bit position for SIM_SOPT5_LPUART0RXSRC. */
1314 #define BM_SIM_SOPT5_LPUART0RXSRC (0x000C0000U) /*!< Bit mask for SIM_SOPT5_LPUART0RXSRC. */
1315 #define BS_SIM_SOPT5_LPUART0RXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_LPUART0RXSRC. */
1317 /*! @brief Read current value of the SIM_SOPT5_LPUART0RXSRC field. */
1318 #define BR_SIM_SOPT5_LPUART0RXSRC(x) (HW_SIM_SOPT5(x).B.LPUART0RXSRC)
1320 /*! @brief Format value for bitfield SIM_SOPT5_LPUART0RXSRC. */
1321 #define BF_SIM_SOPT5_LPUART0RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_LPUART0RXSRC) & BM_SIM_SOPT5_LPUART0RXSRC)
1323 /*! @brief Set the LPUART0RXSRC field to a new value. */
1324 #define BW_SIM_SOPT5_LPUART0RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_LPUART0RXSRC) | BF_SIM_SOPT5_LPUART0RXSRC(v)))
1327 /*******************************************************************************
1328 * HW_SIM_SOPT7 - System Options Register 7
1329 ******************************************************************************/
1332 * @brief HW_SIM_SOPT7 - System Options Register 7 (RW)
1334 * Reset value: 0x00000000U
1336 typedef union _hw_sim_sopt7
1339 struct _hw_sim_sopt7_bitfields
1341 uint32_t ADC0TRGSEL : 4; /*!< [3:0] ADC0 trigger select */
1342 uint32_t ADC0PRETRGSEL : 1; /*!< [4] ADC0 pretrigger select */
1343 uint32_t RESERVED0 : 2; /*!< [6:5] */
1344 uint32_t ADC0ALTTRGEN : 1; /*!< [7] ADC0 alternate trigger enable */
1345 uint32_t ADC1TRGSEL : 4; /*!< [11:8] ADC1 trigger select */
1346 uint32_t ADC1PRETRGSEL : 1; /*!< [12] ADC1 pre-trigger select */
1347 uint32_t RESERVED1 : 2; /*!< [14:13] */
1348 uint32_t ADC1ALTTRGEN : 1; /*!< [15] ADC1 alternate trigger enable */
1349 uint32_t RESERVED2 : 16; /*!< [31:16] */
1354 * @name Constants and macros for entire SIM_SOPT7 register
1357 #define HW_SIM_SOPT7_ADDR(x) ((x) + 0x1018U)
1359 #define HW_SIM_SOPT7(x) (*(__IO hw_sim_sopt7_t *) HW_SIM_SOPT7_ADDR(x))
1360 #define HW_SIM_SOPT7_RD(x) (HW_SIM_SOPT7(x).U)
1361 #define HW_SIM_SOPT7_WR(x, v) (HW_SIM_SOPT7(x).U = (v))
1362 #define HW_SIM_SOPT7_SET(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) | (v)))
1363 #define HW_SIM_SOPT7_CLR(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) & ~(v)))
1364 #define HW_SIM_SOPT7_TOG(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) ^ (v)))
1368 * Constants & macros for individual SIM_SOPT7 bitfields
1372 * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
1374 * Selects the ADC0 trigger source when alternative triggers are functional in
1375 * stop and VLPS modes. .
1378 * - 0000 - PDB external trigger pin input (PDB0_EXTRG)
1379 * - 0001 - High speed comparator 0 output
1380 * - 0010 - High speed comparator 1 output
1382 * - 0100 - PIT trigger 0
1383 * - 0101 - PIT trigger 1
1384 * - 0110 - PIT trigger 2
1385 * - 0111 - PIT trigger 3
1386 * - 1000 - FTM0 trigger
1387 * - 1001 - FTM1 trigger
1388 * - 1010 - FTM2 trigger
1389 * - 1011 - FTM3 trigger
1390 * - 1100 - RTC alarm
1391 * - 1101 - RTC seconds
1392 * - 1110 - Low-power timer (LPTMR) trigger
1396 #define BP_SIM_SOPT7_ADC0TRGSEL (0U) /*!< Bit position for SIM_SOPT7_ADC0TRGSEL. */
1397 #define BM_SIM_SOPT7_ADC0TRGSEL (0x0000000FU) /*!< Bit mask for SIM_SOPT7_ADC0TRGSEL. */
1398 #define BS_SIM_SOPT7_ADC0TRGSEL (4U) /*!< Bit field size in bits for SIM_SOPT7_ADC0TRGSEL. */
1400 /*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */
1401 #define BR_SIM_SOPT7_ADC0TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC0TRGSEL)
1403 /*! @brief Format value for bitfield SIM_SOPT7_ADC0TRGSEL. */
1404 #define BF_SIM_SOPT7_ADC0TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0TRGSEL) & BM_SIM_SOPT7_ADC0TRGSEL)
1406 /*! @brief Set the ADC0TRGSEL field to a new value. */
1407 #define BW_SIM_SOPT7_ADC0TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC0TRGSEL) | BF_SIM_SOPT7_ADC0TRGSEL(v)))
1411 * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
1413 * Selects the ADC0 pre-trigger source when alternative triggers are enabled
1414 * through ADC0ALTTRGEN.
1417 * - 0 - Pre-trigger A
1418 * - 1 - Pre-trigger B
1421 #define BP_SIM_SOPT7_ADC0PRETRGSEL (4U) /*!< Bit position for SIM_SOPT7_ADC0PRETRGSEL. */
1422 #define BM_SIM_SOPT7_ADC0PRETRGSEL (0x00000010U) /*!< Bit mask for SIM_SOPT7_ADC0PRETRGSEL. */
1423 #define BS_SIM_SOPT7_ADC0PRETRGSEL (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC0PRETRGSEL. */
1425 /*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */
1426 #define BR_SIM_SOPT7_ADC0PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL))
1428 /*! @brief Format value for bitfield SIM_SOPT7_ADC0PRETRGSEL. */
1429 #define BF_SIM_SOPT7_ADC0PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0PRETRGSEL) & BM_SIM_SOPT7_ADC0PRETRGSEL)
1431 /*! @brief Set the ADC0PRETRGSEL field to a new value. */
1432 #define BW_SIM_SOPT7_ADC0PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL) = (v))
1436 * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
1438 * Enable alternative conversion triggers for ADC0.
1441 * - 0 - PDB trigger selected for ADC0.
1442 * - 1 - Alternate trigger selected for ADC0.
1445 #define BP_SIM_SOPT7_ADC0ALTTRGEN (7U) /*!< Bit position for SIM_SOPT7_ADC0ALTTRGEN. */
1446 #define BM_SIM_SOPT7_ADC0ALTTRGEN (0x00000080U) /*!< Bit mask for SIM_SOPT7_ADC0ALTTRGEN. */
1447 #define BS_SIM_SOPT7_ADC0ALTTRGEN (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC0ALTTRGEN. */
1449 /*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */
1450 #define BR_SIM_SOPT7_ADC0ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN))
1452 /*! @brief Format value for bitfield SIM_SOPT7_ADC0ALTTRGEN. */
1453 #define BF_SIM_SOPT7_ADC0ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0ALTTRGEN) & BM_SIM_SOPT7_ADC0ALTTRGEN)
1455 /*! @brief Set the ADC0ALTTRGEN field to a new value. */
1456 #define BW_SIM_SOPT7_ADC0ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN) = (v))
1460 * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
1462 * Selects the ADC1 trigger source when alternative triggers are functional in
1463 * stop and VLPS modes.
1466 * - 0000 - PDB external trigger pin input (PDB0_EXTRG)
1467 * - 0001 - High speed comparator 0 output
1468 * - 0010 - High speed comparator 1 output
1470 * - 0100 - PIT trigger 0
1471 * - 0101 - PIT trigger 1
1472 * - 0110 - PIT trigger 2
1473 * - 0111 - PIT trigger 3
1474 * - 1000 - FTM0 trigger
1475 * - 1001 - FTM1 trigger
1476 * - 1010 - FTM2 trigger
1477 * - 1011 - FTM3 trigger
1478 * - 1100 - RTC alarm
1479 * - 1101 - RTC seconds
1480 * - 1110 - Low-power timer (LPTMR) trigger
1484 #define BP_SIM_SOPT7_ADC1TRGSEL (8U) /*!< Bit position for SIM_SOPT7_ADC1TRGSEL. */
1485 #define BM_SIM_SOPT7_ADC1TRGSEL (0x00000F00U) /*!< Bit mask for SIM_SOPT7_ADC1TRGSEL. */
1486 #define BS_SIM_SOPT7_ADC1TRGSEL (4U) /*!< Bit field size in bits for SIM_SOPT7_ADC1TRGSEL. */
1488 /*! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. */
1489 #define BR_SIM_SOPT7_ADC1TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC1TRGSEL)
1491 /*! @brief Format value for bitfield SIM_SOPT7_ADC1TRGSEL. */
1492 #define BF_SIM_SOPT7_ADC1TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1TRGSEL) & BM_SIM_SOPT7_ADC1TRGSEL)
1494 /*! @brief Set the ADC1TRGSEL field to a new value. */
1495 #define BW_SIM_SOPT7_ADC1TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC1TRGSEL) | BF_SIM_SOPT7_ADC1TRGSEL(v)))
1499 * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
1501 * Selects the ADC1 pre-trigger source when alternative triggers are enabled
1502 * through ADC1ALTTRGEN.
1505 * - 0 - Pre-trigger A selected for ADC1.
1506 * - 1 - Pre-trigger B selected for ADC1.
1509 #define BP_SIM_SOPT7_ADC1PRETRGSEL (12U) /*!< Bit position for SIM_SOPT7_ADC1PRETRGSEL. */
1510 #define BM_SIM_SOPT7_ADC1PRETRGSEL (0x00001000U) /*!< Bit mask for SIM_SOPT7_ADC1PRETRGSEL. */
1511 #define BS_SIM_SOPT7_ADC1PRETRGSEL (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC1PRETRGSEL. */
1513 /*! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. */
1514 #define BR_SIM_SOPT7_ADC1PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL))
1516 /*! @brief Format value for bitfield SIM_SOPT7_ADC1PRETRGSEL. */
1517 #define BF_SIM_SOPT7_ADC1PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1PRETRGSEL) & BM_SIM_SOPT7_ADC1PRETRGSEL)
1519 /*! @brief Set the ADC1PRETRGSEL field to a new value. */
1520 #define BW_SIM_SOPT7_ADC1PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL) = (v))
1524 * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
1526 * Enable alternative conversion triggers for ADC1.
1529 * - 0 - PDB trigger selected for ADC1
1530 * - 1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
1533 #define BP_SIM_SOPT7_ADC1ALTTRGEN (15U) /*!< Bit position for SIM_SOPT7_ADC1ALTTRGEN. */
1534 #define BM_SIM_SOPT7_ADC1ALTTRGEN (0x00008000U) /*!< Bit mask for SIM_SOPT7_ADC1ALTTRGEN. */
1535 #define BS_SIM_SOPT7_ADC1ALTTRGEN (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC1ALTTRGEN. */
1537 /*! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. */
1538 #define BR_SIM_SOPT7_ADC1ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN))
1540 /*! @brief Format value for bitfield SIM_SOPT7_ADC1ALTTRGEN. */
1541 #define BF_SIM_SOPT7_ADC1ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1ALTTRGEN) & BM_SIM_SOPT7_ADC1ALTTRGEN)
1543 /*! @brief Set the ADC1ALTTRGEN field to a new value. */
1544 #define BW_SIM_SOPT7_ADC1ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN) = (v))
1547 /*******************************************************************************
1548 * HW_SIM_SOPT8 - System Options Register 8
1549 ******************************************************************************/
1552 * @brief HW_SIM_SOPT8 - System Options Register 8 (RW)
1554 * Reset value: 0x00000000U
1556 typedef union _hw_sim_sopt8
1559 struct _hw_sim_sopt8_bitfields
1561 uint32_t FTM0SYNCBIT : 1; /*!< [0] FTM0 Hardware Trigger 0 Software
1562 * Synchronization */
1563 uint32_t FTM1SYNCBIT : 1; /*!< [1] FTM1 Hardware Trigger 0 Software
1564 * Synchronization */
1565 uint32_t FTM2SYNCBIT : 1; /*!< [2] FTM2 Hardware Trigger 0 Software
1566 * Synchronization */
1567 uint32_t FTM3SYNCBIT : 1; /*!< [3] FTM3 Hardware Trigger 0 Software
1568 * Synchronization */
1569 uint32_t RESERVED0 : 12; /*!< [15:4] */
1570 uint32_t FTM0OCH0SRC : 1; /*!< [16] FTM0 channel 0 output source */
1571 uint32_t FTM0OCH1SRC : 1; /*!< [17] FTM0 channel 1 output source */
1572 uint32_t FTM0OCH2SRC : 1; /*!< [18] FTM0 channel 2 output source */
1573 uint32_t FTM0OCH3SRC : 1; /*!< [19] FTM0 channel 3 output source */
1574 uint32_t FTM0OCH4SRC : 1; /*!< [20] FTM0 channel 4 output source */
1575 uint32_t FTM0OCH5SRC : 1; /*!< [21] FTM0 channel 5 output source */
1576 uint32_t FTM0OCH6SRC : 1; /*!< [22] FTM0 channel 6 output source */
1577 uint32_t FTM0OCH7SRC : 1; /*!< [23] FTM0 channel 7 output source */
1578 uint32_t FTM3OCH0SRC : 1; /*!< [24] FTM3 channel 0 output source */
1579 uint32_t FTM3OCH1SRC : 1; /*!< [25] FTM3 channel 1 output source */
1580 uint32_t FTM3OCH2SRC : 1; /*!< [26] FTM3 channel 2 output source */
1581 uint32_t FTM3OCH3SRC : 1; /*!< [27] FTM3 channel 3 output source */
1582 uint32_t FTM3OCH4SRC : 1; /*!< [28] FTM3 channel 4 output source */
1583 uint32_t FTM3OCH5SRC : 1; /*!< [29] FTM3 channel 5 output source */
1584 uint32_t FTM3OCH6SRC : 1; /*!< [30] FTM3 channel 6 output source */
1585 uint32_t FTM3OCH7SRC : 1; /*!< [31] FTM3 channel 7 output source */
1590 * @name Constants and macros for entire SIM_SOPT8 register
1593 #define HW_SIM_SOPT8_ADDR(x) ((x) + 0x101CU)
1595 #define HW_SIM_SOPT8(x) (*(__IO hw_sim_sopt8_t *) HW_SIM_SOPT8_ADDR(x))
1596 #define HW_SIM_SOPT8_RD(x) (HW_SIM_SOPT8(x).U)
1597 #define HW_SIM_SOPT8_WR(x, v) (HW_SIM_SOPT8(x).U = (v))
1598 #define HW_SIM_SOPT8_SET(x, v) (HW_SIM_SOPT8_WR(x, HW_SIM_SOPT8_RD(x) | (v)))
1599 #define HW_SIM_SOPT8_CLR(x, v) (HW_SIM_SOPT8_WR(x, HW_SIM_SOPT8_RD(x) & ~(v)))
1600 #define HW_SIM_SOPT8_TOG(x, v) (HW_SIM_SOPT8_WR(x, HW_SIM_SOPT8_RD(x) ^ (v)))
1604 * Constants & macros for individual SIM_SOPT8 bitfields
1608 * @name Register SIM_SOPT8, field FTM0SYNCBIT[0] (RW)
1612 * - 1 - Write 1 to assert the TRIG0 input to FTM0, software must clear this bit
1613 * to allow other trigger sources to assert.
1616 #define BP_SIM_SOPT8_FTM0SYNCBIT (0U) /*!< Bit position for SIM_SOPT8_FTM0SYNCBIT. */
1617 #define BM_SIM_SOPT8_FTM0SYNCBIT (0x00000001U) /*!< Bit mask for SIM_SOPT8_FTM0SYNCBIT. */
1618 #define BS_SIM_SOPT8_FTM0SYNCBIT (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0SYNCBIT. */
1620 /*! @brief Read current value of the SIM_SOPT8_FTM0SYNCBIT field. */
1621 #define BR_SIM_SOPT8_FTM0SYNCBIT(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0SYNCBIT))
1623 /*! @brief Format value for bitfield SIM_SOPT8_FTM0SYNCBIT. */
1624 #define BF_SIM_SOPT8_FTM0SYNCBIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0SYNCBIT) & BM_SIM_SOPT8_FTM0SYNCBIT)
1626 /*! @brief Set the FTM0SYNCBIT field to a new value. */
1627 #define BW_SIM_SOPT8_FTM0SYNCBIT(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0SYNCBIT) = (v))
1631 * @name Register SIM_SOPT8, field FTM1SYNCBIT[1] (RW)
1635 * - 1 - Write 1 to assert the TRIG0 input to FTM1, software must clear this bit
1636 * to allow other trigger sources to assert.
1639 #define BP_SIM_SOPT8_FTM1SYNCBIT (1U) /*!< Bit position for SIM_SOPT8_FTM1SYNCBIT. */
1640 #define BM_SIM_SOPT8_FTM1SYNCBIT (0x00000002U) /*!< Bit mask for SIM_SOPT8_FTM1SYNCBIT. */
1641 #define BS_SIM_SOPT8_FTM1SYNCBIT (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM1SYNCBIT. */
1643 /*! @brief Read current value of the SIM_SOPT8_FTM1SYNCBIT field. */
1644 #define BR_SIM_SOPT8_FTM1SYNCBIT(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM1SYNCBIT))
1646 /*! @brief Format value for bitfield SIM_SOPT8_FTM1SYNCBIT. */
1647 #define BF_SIM_SOPT8_FTM1SYNCBIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM1SYNCBIT) & BM_SIM_SOPT8_FTM1SYNCBIT)
1649 /*! @brief Set the FTM1SYNCBIT field to a new value. */
1650 #define BW_SIM_SOPT8_FTM1SYNCBIT(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM1SYNCBIT) = (v))
1654 * @name Register SIM_SOPT8, field FTM2SYNCBIT[2] (RW)
1658 * - 1 - Write 1 to assert the TRIG0 input to FTM2, software must clear this bit
1659 * to allow other trigger sources to assert.
1662 #define BP_SIM_SOPT8_FTM2SYNCBIT (2U) /*!< Bit position for SIM_SOPT8_FTM2SYNCBIT. */
1663 #define BM_SIM_SOPT8_FTM2SYNCBIT (0x00000004U) /*!< Bit mask for SIM_SOPT8_FTM2SYNCBIT. */
1664 #define BS_SIM_SOPT8_FTM2SYNCBIT (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM2SYNCBIT. */
1666 /*! @brief Read current value of the SIM_SOPT8_FTM2SYNCBIT field. */
1667 #define BR_SIM_SOPT8_FTM2SYNCBIT(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM2SYNCBIT))
1669 /*! @brief Format value for bitfield SIM_SOPT8_FTM2SYNCBIT. */
1670 #define BF_SIM_SOPT8_FTM2SYNCBIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM2SYNCBIT) & BM_SIM_SOPT8_FTM2SYNCBIT)
1672 /*! @brief Set the FTM2SYNCBIT field to a new value. */
1673 #define BW_SIM_SOPT8_FTM2SYNCBIT(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM2SYNCBIT) = (v))
1677 * @name Register SIM_SOPT8, field FTM3SYNCBIT[3] (RW)
1681 * - 1 - Write 1 to assert the TRIG0 input to FTM3, software must clear this bit
1682 * to allow other trigger sources to assert.
1685 #define BP_SIM_SOPT8_FTM3SYNCBIT (3U) /*!< Bit position for SIM_SOPT8_FTM3SYNCBIT. */
1686 #define BM_SIM_SOPT8_FTM3SYNCBIT (0x00000008U) /*!< Bit mask for SIM_SOPT8_FTM3SYNCBIT. */
1687 #define BS_SIM_SOPT8_FTM3SYNCBIT (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3SYNCBIT. */
1689 /*! @brief Read current value of the SIM_SOPT8_FTM3SYNCBIT field. */
1690 #define BR_SIM_SOPT8_FTM3SYNCBIT(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3SYNCBIT))
1692 /*! @brief Format value for bitfield SIM_SOPT8_FTM3SYNCBIT. */
1693 #define BF_SIM_SOPT8_FTM3SYNCBIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3SYNCBIT) & BM_SIM_SOPT8_FTM3SYNCBIT)
1695 /*! @brief Set the FTM3SYNCBIT field to a new value. */
1696 #define BW_SIM_SOPT8_FTM3SYNCBIT(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3SYNCBIT) = (v))
1700 * @name Register SIM_SOPT8, field FTM0OCH0SRC[16] (RW)
1703 * - 0 - FTM0_CH0 pin is output of FTM0 channel 0 output
1704 * - 1 - FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1
1708 #define BP_SIM_SOPT8_FTM0OCH0SRC (16U) /*!< Bit position for SIM_SOPT8_FTM0OCH0SRC. */
1709 #define BM_SIM_SOPT8_FTM0OCH0SRC (0x00010000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH0SRC. */
1710 #define BS_SIM_SOPT8_FTM0OCH0SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH0SRC. */
1712 /*! @brief Read current value of the SIM_SOPT8_FTM0OCH0SRC field. */
1713 #define BR_SIM_SOPT8_FTM0OCH0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH0SRC))
1715 /*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH0SRC. */
1716 #define BF_SIM_SOPT8_FTM0OCH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH0SRC) & BM_SIM_SOPT8_FTM0OCH0SRC)
1718 /*! @brief Set the FTM0OCH0SRC field to a new value. */
1719 #define BW_SIM_SOPT8_FTM0OCH0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH0SRC) = (v))
1723 * @name Register SIM_SOPT8, field FTM0OCH1SRC[17] (RW)
1726 * - 0 - FTM0_CH1 pin is output of FTM0 channel 1 output
1727 * - 1 - FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1
1731 #define BP_SIM_SOPT8_FTM0OCH1SRC (17U) /*!< Bit position for SIM_SOPT8_FTM0OCH1SRC. */
1732 #define BM_SIM_SOPT8_FTM0OCH1SRC (0x00020000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH1SRC. */
1733 #define BS_SIM_SOPT8_FTM0OCH1SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH1SRC. */
1735 /*! @brief Read current value of the SIM_SOPT8_FTM0OCH1SRC field. */
1736 #define BR_SIM_SOPT8_FTM0OCH1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH1SRC))
1738 /*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH1SRC. */
1739 #define BF_SIM_SOPT8_FTM0OCH1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH1SRC) & BM_SIM_SOPT8_FTM0OCH1SRC)
1741 /*! @brief Set the FTM0OCH1SRC field to a new value. */
1742 #define BW_SIM_SOPT8_FTM0OCH1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH1SRC) = (v))
1746 * @name Register SIM_SOPT8, field FTM0OCH2SRC[18] (RW)
1749 * - 0 - FTM0_CH2 pin is output of FTM0 channel 2 output
1750 * - 1 - FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1
1754 #define BP_SIM_SOPT8_FTM0OCH2SRC (18U) /*!< Bit position for SIM_SOPT8_FTM0OCH2SRC. */
1755 #define BM_SIM_SOPT8_FTM0OCH2SRC (0x00040000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH2SRC. */
1756 #define BS_SIM_SOPT8_FTM0OCH2SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH2SRC. */
1758 /*! @brief Read current value of the SIM_SOPT8_FTM0OCH2SRC field. */
1759 #define BR_SIM_SOPT8_FTM0OCH2SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH2SRC))
1761 /*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH2SRC. */
1762 #define BF_SIM_SOPT8_FTM0OCH2SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH2SRC) & BM_SIM_SOPT8_FTM0OCH2SRC)
1764 /*! @brief Set the FTM0OCH2SRC field to a new value. */
1765 #define BW_SIM_SOPT8_FTM0OCH2SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH2SRC) = (v))
1769 * @name Register SIM_SOPT8, field FTM0OCH3SRC[19] (RW)
1772 * - 0 - FTM0_CH3 pin is output of FTM0 channel 3 output
1773 * - 1 - FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1
1777 #define BP_SIM_SOPT8_FTM0OCH3SRC (19U) /*!< Bit position for SIM_SOPT8_FTM0OCH3SRC. */
1778 #define BM_SIM_SOPT8_FTM0OCH3SRC (0x00080000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH3SRC. */
1779 #define BS_SIM_SOPT8_FTM0OCH3SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH3SRC. */
1781 /*! @brief Read current value of the SIM_SOPT8_FTM0OCH3SRC field. */
1782 #define BR_SIM_SOPT8_FTM0OCH3SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH3SRC))
1784 /*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH3SRC. */
1785 #define BF_SIM_SOPT8_FTM0OCH3SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH3SRC) & BM_SIM_SOPT8_FTM0OCH3SRC)
1787 /*! @brief Set the FTM0OCH3SRC field to a new value. */
1788 #define BW_SIM_SOPT8_FTM0OCH3SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH3SRC) = (v))
1792 * @name Register SIM_SOPT8, field FTM0OCH4SRC[20] (RW)
1795 * - 0 - FTM0_CH4 pin is output of FTM0 channel 4 output
1796 * - 1 - FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1
1800 #define BP_SIM_SOPT8_FTM0OCH4SRC (20U) /*!< Bit position for SIM_SOPT8_FTM0OCH4SRC. */
1801 #define BM_SIM_SOPT8_FTM0OCH4SRC (0x00100000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH4SRC. */
1802 #define BS_SIM_SOPT8_FTM0OCH4SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH4SRC. */
1804 /*! @brief Read current value of the SIM_SOPT8_FTM0OCH4SRC field. */
1805 #define BR_SIM_SOPT8_FTM0OCH4SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH4SRC))
1807 /*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH4SRC. */
1808 #define BF_SIM_SOPT8_FTM0OCH4SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH4SRC) & BM_SIM_SOPT8_FTM0OCH4SRC)
1810 /*! @brief Set the FTM0OCH4SRC field to a new value. */
1811 #define BW_SIM_SOPT8_FTM0OCH4SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH4SRC) = (v))
1815 * @name Register SIM_SOPT8, field FTM0OCH5SRC[21] (RW)
1818 * - 0 - FTM0_CH5 pin is output of FTM0 channel 5 output
1819 * - 1 - FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1
1823 #define BP_SIM_SOPT8_FTM0OCH5SRC (21U) /*!< Bit position for SIM_SOPT8_FTM0OCH5SRC. */
1824 #define BM_SIM_SOPT8_FTM0OCH5SRC (0x00200000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH5SRC. */
1825 #define BS_SIM_SOPT8_FTM0OCH5SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH5SRC. */
1827 /*! @brief Read current value of the SIM_SOPT8_FTM0OCH5SRC field. */
1828 #define BR_SIM_SOPT8_FTM0OCH5SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH5SRC))
1830 /*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH5SRC. */
1831 #define BF_SIM_SOPT8_FTM0OCH5SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH5SRC) & BM_SIM_SOPT8_FTM0OCH5SRC)
1833 /*! @brief Set the FTM0OCH5SRC field to a new value. */
1834 #define BW_SIM_SOPT8_FTM0OCH5SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH5SRC) = (v))
1838 * @name Register SIM_SOPT8, field FTM0OCH6SRC[22] (RW)
1841 * - 0 - FTM0_CH6 pin is output of FTM0 channel 6 output
1842 * - 1 - FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1
1846 #define BP_SIM_SOPT8_FTM0OCH6SRC (22U) /*!< Bit position for SIM_SOPT8_FTM0OCH6SRC. */
1847 #define BM_SIM_SOPT8_FTM0OCH6SRC (0x00400000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH6SRC. */
1848 #define BS_SIM_SOPT8_FTM0OCH6SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH6SRC. */
1850 /*! @brief Read current value of the SIM_SOPT8_FTM0OCH6SRC field. */
1851 #define BR_SIM_SOPT8_FTM0OCH6SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH6SRC))
1853 /*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH6SRC. */
1854 #define BF_SIM_SOPT8_FTM0OCH6SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH6SRC) & BM_SIM_SOPT8_FTM0OCH6SRC)
1856 /*! @brief Set the FTM0OCH6SRC field to a new value. */
1857 #define BW_SIM_SOPT8_FTM0OCH6SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH6SRC) = (v))
1861 * @name Register SIM_SOPT8, field FTM0OCH7SRC[23] (RW)
1864 * - 0 - FTM0_CH7 pin is output of FTM0 channel 7 output
1865 * - 1 - FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1
1869 #define BP_SIM_SOPT8_FTM0OCH7SRC (23U) /*!< Bit position for SIM_SOPT8_FTM0OCH7SRC. */
1870 #define BM_SIM_SOPT8_FTM0OCH7SRC (0x00800000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH7SRC. */
1871 #define BS_SIM_SOPT8_FTM0OCH7SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH7SRC. */
1873 /*! @brief Read current value of the SIM_SOPT8_FTM0OCH7SRC field. */
1874 #define BR_SIM_SOPT8_FTM0OCH7SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH7SRC))
1876 /*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH7SRC. */
1877 #define BF_SIM_SOPT8_FTM0OCH7SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH7SRC) & BM_SIM_SOPT8_FTM0OCH7SRC)
1879 /*! @brief Set the FTM0OCH7SRC field to a new value. */
1880 #define BW_SIM_SOPT8_FTM0OCH7SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH7SRC) = (v))
1884 * @name Register SIM_SOPT8, field FTM3OCH0SRC[24] (RW)
1887 * - 0 - FTM3_CH0 pin is output of FTM3 channel 0 output
1888 * - 1 - FTM3_CH0 pin is output of FTM3 channel 0 output modulated by FTM2
1892 #define BP_SIM_SOPT8_FTM3OCH0SRC (24U) /*!< Bit position for SIM_SOPT8_FTM3OCH0SRC. */
1893 #define BM_SIM_SOPT8_FTM3OCH0SRC (0x01000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH0SRC. */
1894 #define BS_SIM_SOPT8_FTM3OCH0SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH0SRC. */
1896 /*! @brief Read current value of the SIM_SOPT8_FTM3OCH0SRC field. */
1897 #define BR_SIM_SOPT8_FTM3OCH0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH0SRC))
1899 /*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH0SRC. */
1900 #define BF_SIM_SOPT8_FTM3OCH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH0SRC) & BM_SIM_SOPT8_FTM3OCH0SRC)
1902 /*! @brief Set the FTM3OCH0SRC field to a new value. */
1903 #define BW_SIM_SOPT8_FTM3OCH0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH0SRC) = (v))
1907 * @name Register SIM_SOPT8, field FTM3OCH1SRC[25] (RW)
1910 * - 0 - FTM3_CH1 pin is output of FTM3 channel 1 output
1911 * - 1 - FTM3_CH1 pin is output of FTM3 channel 1 output modulated by FTM2
1915 #define BP_SIM_SOPT8_FTM3OCH1SRC (25U) /*!< Bit position for SIM_SOPT8_FTM3OCH1SRC. */
1916 #define BM_SIM_SOPT8_FTM3OCH1SRC (0x02000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH1SRC. */
1917 #define BS_SIM_SOPT8_FTM3OCH1SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH1SRC. */
1919 /*! @brief Read current value of the SIM_SOPT8_FTM3OCH1SRC field. */
1920 #define BR_SIM_SOPT8_FTM3OCH1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH1SRC))
1922 /*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH1SRC. */
1923 #define BF_SIM_SOPT8_FTM3OCH1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH1SRC) & BM_SIM_SOPT8_FTM3OCH1SRC)
1925 /*! @brief Set the FTM3OCH1SRC field to a new value. */
1926 #define BW_SIM_SOPT8_FTM3OCH1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH1SRC) = (v))
1930 * @name Register SIM_SOPT8, field FTM3OCH2SRC[26] (RW)
1933 * - 0 - FTM3_CH2 pin is output of FTM3 channel 2 output
1934 * - 1 - FTM3_CH2 pin is output of FTM3 channel 2 output modulated by FTM2
1938 #define BP_SIM_SOPT8_FTM3OCH2SRC (26U) /*!< Bit position for SIM_SOPT8_FTM3OCH2SRC. */
1939 #define BM_SIM_SOPT8_FTM3OCH2SRC (0x04000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH2SRC. */
1940 #define BS_SIM_SOPT8_FTM3OCH2SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH2SRC. */
1942 /*! @brief Read current value of the SIM_SOPT8_FTM3OCH2SRC field. */
1943 #define BR_SIM_SOPT8_FTM3OCH2SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH2SRC))
1945 /*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH2SRC. */
1946 #define BF_SIM_SOPT8_FTM3OCH2SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH2SRC) & BM_SIM_SOPT8_FTM3OCH2SRC)
1948 /*! @brief Set the FTM3OCH2SRC field to a new value. */
1949 #define BW_SIM_SOPT8_FTM3OCH2SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH2SRC) = (v))
1953 * @name Register SIM_SOPT8, field FTM3OCH3SRC[27] (RW)
1956 * - 0 - FTM3_CH3 pin is output of FTM3 channel 3 output
1957 * - 1 - FTM3_CH3 pin is output of FTM3 channel 3 output modulated by FTM2
1961 #define BP_SIM_SOPT8_FTM3OCH3SRC (27U) /*!< Bit position for SIM_SOPT8_FTM3OCH3SRC. */
1962 #define BM_SIM_SOPT8_FTM3OCH3SRC (0x08000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH3SRC. */
1963 #define BS_SIM_SOPT8_FTM3OCH3SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH3SRC. */
1965 /*! @brief Read current value of the SIM_SOPT8_FTM3OCH3SRC field. */
1966 #define BR_SIM_SOPT8_FTM3OCH3SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH3SRC))
1968 /*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH3SRC. */
1969 #define BF_SIM_SOPT8_FTM3OCH3SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH3SRC) & BM_SIM_SOPT8_FTM3OCH3SRC)
1971 /*! @brief Set the FTM3OCH3SRC field to a new value. */
1972 #define BW_SIM_SOPT8_FTM3OCH3SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH3SRC) = (v))
1976 * @name Register SIM_SOPT8, field FTM3OCH4SRC[28] (RW)
1979 * - 0 - FTM3_CH4 pin is output of FTM3 channel 4 output
1980 * - 1 - FTM3_CH4 pin is output of FTM3 channel 4 output modulated by FTM2
1984 #define BP_SIM_SOPT8_FTM3OCH4SRC (28U) /*!< Bit position for SIM_SOPT8_FTM3OCH4SRC. */
1985 #define BM_SIM_SOPT8_FTM3OCH4SRC (0x10000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH4SRC. */
1986 #define BS_SIM_SOPT8_FTM3OCH4SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH4SRC. */
1988 /*! @brief Read current value of the SIM_SOPT8_FTM3OCH4SRC field. */
1989 #define BR_SIM_SOPT8_FTM3OCH4SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH4SRC))
1991 /*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH4SRC. */
1992 #define BF_SIM_SOPT8_FTM3OCH4SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH4SRC) & BM_SIM_SOPT8_FTM3OCH4SRC)
1994 /*! @brief Set the FTM3OCH4SRC field to a new value. */
1995 #define BW_SIM_SOPT8_FTM3OCH4SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH4SRC) = (v))
1999 * @name Register SIM_SOPT8, field FTM3OCH5SRC[29] (RW)
2002 * - 0 - FTM3_CH5 pin is output of FTM3 channel 5 output
2003 * - 1 - FTM3_CH5 pin is output of FTM3 channel 5 output modulated by FTM2
2007 #define BP_SIM_SOPT8_FTM3OCH5SRC (29U) /*!< Bit position for SIM_SOPT8_FTM3OCH5SRC. */
2008 #define BM_SIM_SOPT8_FTM3OCH5SRC (0x20000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH5SRC. */
2009 #define BS_SIM_SOPT8_FTM3OCH5SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH5SRC. */
2011 /*! @brief Read current value of the SIM_SOPT8_FTM3OCH5SRC field. */
2012 #define BR_SIM_SOPT8_FTM3OCH5SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH5SRC))
2014 /*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH5SRC. */
2015 #define BF_SIM_SOPT8_FTM3OCH5SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH5SRC) & BM_SIM_SOPT8_FTM3OCH5SRC)
2017 /*! @brief Set the FTM3OCH5SRC field to a new value. */
2018 #define BW_SIM_SOPT8_FTM3OCH5SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH5SRC) = (v))
2022 * @name Register SIM_SOPT8, field FTM3OCH6SRC[30] (RW)
2025 * - 0 - FTM3_CH6 pin is output of FTM3 channel 6 output
2026 * - 1 - FTM3_CH6 pin is output of FTM3 channel 6 output modulated by FTM2
2030 #define BP_SIM_SOPT8_FTM3OCH6SRC (30U) /*!< Bit position for SIM_SOPT8_FTM3OCH6SRC. */
2031 #define BM_SIM_SOPT8_FTM3OCH6SRC (0x40000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH6SRC. */
2032 #define BS_SIM_SOPT8_FTM3OCH6SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH6SRC. */
2034 /*! @brief Read current value of the SIM_SOPT8_FTM3OCH6SRC field. */
2035 #define BR_SIM_SOPT8_FTM3OCH6SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH6SRC))
2037 /*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH6SRC. */
2038 #define BF_SIM_SOPT8_FTM3OCH6SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH6SRC) & BM_SIM_SOPT8_FTM3OCH6SRC)
2040 /*! @brief Set the FTM3OCH6SRC field to a new value. */
2041 #define BW_SIM_SOPT8_FTM3OCH6SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH6SRC) = (v))
2045 * @name Register SIM_SOPT8, field FTM3OCH7SRC[31] (RW)
2048 * - 0 - FTM3_CH7 pin is output of FTM3 channel 7 output
2049 * - 1 - FTM3_CH7 pin is output of FTM3 channel 7 output modulated by FTM2
2053 #define BP_SIM_SOPT8_FTM3OCH7SRC (31U) /*!< Bit position for SIM_SOPT8_FTM3OCH7SRC. */
2054 #define BM_SIM_SOPT8_FTM3OCH7SRC (0x80000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH7SRC. */
2055 #define BS_SIM_SOPT8_FTM3OCH7SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH7SRC. */
2057 /*! @brief Read current value of the SIM_SOPT8_FTM3OCH7SRC field. */
2058 #define BR_SIM_SOPT8_FTM3OCH7SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH7SRC))
2060 /*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH7SRC. */
2061 #define BF_SIM_SOPT8_FTM3OCH7SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH7SRC) & BM_SIM_SOPT8_FTM3OCH7SRC)
2063 /*! @brief Set the FTM3OCH7SRC field to a new value. */
2064 #define BW_SIM_SOPT8_FTM3OCH7SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH7SRC) = (v))
2067 /*******************************************************************************
2068 * HW_SIM_SDID - System Device Identification Register
2069 ******************************************************************************/
2072 * @brief HW_SIM_SDID - System Device Identification Register (RO)
2074 * Reset value: 0x00000E80U
2076 typedef union _hw_sim_sdid
2079 struct _hw_sim_sdid_bitfields
2081 uint32_t PINID : 4; /*!< [3:0] Pincount identification */
2082 uint32_t FAMID : 3; /*!< [6:4] Kinetis family identification */
2083 uint32_t DIEID : 5; /*!< [11:7] Device Die ID */
2084 uint32_t REVID : 4; /*!< [15:12] Device revision number */
2085 uint32_t RESERVED0 : 4; /*!< [19:16] */
2086 uint32_t SERIESID : 4; /*!< [23:20] Kinetis Series ID */
2087 uint32_t SUBFAMID : 4; /*!< [27:24] Kinetis Sub-Family ID */
2088 uint32_t FAMILYID : 4; /*!< [31:28] Kinetis Family ID */
2093 * @name Constants and macros for entire SIM_SDID register
2096 #define HW_SIM_SDID_ADDR(x) ((x) + 0x1024U)
2098 #define HW_SIM_SDID(x) (*(__I hw_sim_sdid_t *) HW_SIM_SDID_ADDR(x))
2099 #define HW_SIM_SDID_RD(x) (HW_SIM_SDID(x).U)
2103 * Constants & macros for individual SIM_SDID bitfields
2107 * @name Register SIM_SDID, field PINID[3:0] (RO)
2109 * Specifies the pincount of the device.
2119 * - 0111 - 81-pin or 121-pin
2123 * - 1011 - Custom pinout (WLCSP)
2130 #define BP_SIM_SDID_PINID (0U) /*!< Bit position for SIM_SDID_PINID. */
2131 #define BM_SIM_SDID_PINID (0x0000000FU) /*!< Bit mask for SIM_SDID_PINID. */
2132 #define BS_SIM_SDID_PINID (4U) /*!< Bit field size in bits for SIM_SDID_PINID. */
2134 /*! @brief Read current value of the SIM_SDID_PINID field. */
2135 #define BR_SIM_SDID_PINID(x) (HW_SIM_SDID(x).B.PINID)
2139 * @name Register SIM_SDID, field FAMID[6:4] (RO)
2141 * This field is maintained for compatibility only, but has been superceded by
2142 * the SERIESID, FAMILYID and SUBFAMID fields in this register.
2145 * - 000 - K1x Family (without tamper)
2146 * - 001 - K2x Family (without tamper)
2147 * - 010 - K3x Family or K1x/K6x Family (with tamper)
2148 * - 011 - K4x Family or K2x Family (with tamper)
2149 * - 100 - K6x Family (without tamper)
2150 * - 101 - K7x Family
2155 #define BP_SIM_SDID_FAMID (4U) /*!< Bit position for SIM_SDID_FAMID. */
2156 #define BM_SIM_SDID_FAMID (0x00000070U) /*!< Bit mask for SIM_SDID_FAMID. */
2157 #define BS_SIM_SDID_FAMID (3U) /*!< Bit field size in bits for SIM_SDID_FAMID. */
2159 /*! @brief Read current value of the SIM_SDID_FAMID field. */
2160 #define BR_SIM_SDID_FAMID(x) (HW_SIM_SDID(x).B.FAMID)
2164 * @name Register SIM_SDID, field DIEID[11:7] (RO)
2166 * Specifies the silicon feature set identication number for the device.
2169 #define BP_SIM_SDID_DIEID (7U) /*!< Bit position for SIM_SDID_DIEID. */
2170 #define BM_SIM_SDID_DIEID (0x00000F80U) /*!< Bit mask for SIM_SDID_DIEID. */
2171 #define BS_SIM_SDID_DIEID (5U) /*!< Bit field size in bits for SIM_SDID_DIEID. */
2173 /*! @brief Read current value of the SIM_SDID_DIEID field. */
2174 #define BR_SIM_SDID_DIEID(x) (HW_SIM_SDID(x).B.DIEID)
2178 * @name Register SIM_SDID, field REVID[15:12] (RO)
2180 * Specifies the silicon implementation number for the device.
2183 #define BP_SIM_SDID_REVID (12U) /*!< Bit position for SIM_SDID_REVID. */
2184 #define BM_SIM_SDID_REVID (0x0000F000U) /*!< Bit mask for SIM_SDID_REVID. */
2185 #define BS_SIM_SDID_REVID (4U) /*!< Bit field size in bits for SIM_SDID_REVID. */
2187 /*! @brief Read current value of the SIM_SDID_REVID field. */
2188 #define BR_SIM_SDID_REVID(x) (HW_SIM_SDID(x).B.REVID)
2192 * @name Register SIM_SDID, field SERIESID[23:20] (RO)
2194 * Specifies the Kinetis series of the device.
2197 * - 0000 - Kinetis K series
2198 * - 0001 - Kinetis L series
2199 * - 0101 - Kinetis W series
2200 * - 0110 - Kinetis V series
2203 #define BP_SIM_SDID_SERIESID (20U) /*!< Bit position for SIM_SDID_SERIESID. */
2204 #define BM_SIM_SDID_SERIESID (0x00F00000U) /*!< Bit mask for SIM_SDID_SERIESID. */
2205 #define BS_SIM_SDID_SERIESID (4U) /*!< Bit field size in bits for SIM_SDID_SERIESID. */
2207 /*! @brief Read current value of the SIM_SDID_SERIESID field. */
2208 #define BR_SIM_SDID_SERIESID(x) (HW_SIM_SDID(x).B.SERIESID)
2212 * @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
2214 * Specifies the Kinetis sub-family of the device.
2217 * - 0000 - Kx0 Subfamily
2218 * - 0001 - Kx1 Subfamily (tamper detect)
2219 * - 0010 - Kx2 Subfamily
2220 * - 0011 - Kx3 Subfamily (tamper detect)
2221 * - 0100 - Kx4 Subfamily
2222 * - 0101 - Kx5 Subfamily (tamper detect)
2223 * - 0110 - Kx6 Subfamily
2226 #define BP_SIM_SDID_SUBFAMID (24U) /*!< Bit position for SIM_SDID_SUBFAMID. */
2227 #define BM_SIM_SDID_SUBFAMID (0x0F000000U) /*!< Bit mask for SIM_SDID_SUBFAMID. */
2228 #define BS_SIM_SDID_SUBFAMID (4U) /*!< Bit field size in bits for SIM_SDID_SUBFAMID. */
2230 /*! @brief Read current value of the SIM_SDID_SUBFAMID field. */
2231 #define BR_SIM_SDID_SUBFAMID(x) (HW_SIM_SDID(x).B.SUBFAMID)
2235 * @name Register SIM_SDID, field FAMILYID[31:28] (RO)
2237 * Specifies the Kinetis family of the device.
2240 * - 0001 - K1x Family
2241 * - 0010 - K2x Family
2242 * - 0011 - K3x Family
2243 * - 0100 - K4x Family
2244 * - 0110 - K6x Family
2245 * - 0111 - K7x Family
2248 #define BP_SIM_SDID_FAMILYID (28U) /*!< Bit position for SIM_SDID_FAMILYID. */
2249 #define BM_SIM_SDID_FAMILYID (0xF0000000U) /*!< Bit mask for SIM_SDID_FAMILYID. */
2250 #define BS_SIM_SDID_FAMILYID (4U) /*!< Bit field size in bits for SIM_SDID_FAMILYID. */
2252 /*! @brief Read current value of the SIM_SDID_FAMILYID field. */
2253 #define BR_SIM_SDID_FAMILYID(x) (HW_SIM_SDID(x).B.FAMILYID)
2256 /*******************************************************************************
2257 * HW_SIM_SCGC4 - System Clock Gating Control Register 4
2258 ******************************************************************************/
2261 * @brief HW_SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
2263 * Reset value: 0xF0100030U
2265 typedef union _hw_sim_scgc4
2268 struct _hw_sim_scgc4_bitfields
2270 uint32_t RESERVED0 : 1; /*!< [0] */
2271 uint32_t EWMb : 1; /*!< [1] EWM Clock Gate Control */
2272 uint32_t RESERVED1 : 4; /*!< [5:2] */
2273 uint32_t I2C0b : 1; /*!< [6] I2C0 Clock Gate Control */
2274 uint32_t I2C1b : 1; /*!< [7] I2C1 Clock Gate Control */
2275 uint32_t RESERVED2 : 2; /*!< [9:8] */
2276 uint32_t UART0b : 1; /*!< [10] UART0 Clock Gate Control */
2277 uint32_t UART1b : 1; /*!< [11] UART1 Clock Gate Control */
2278 uint32_t UART2b : 1; /*!< [12] UART2 Clock Gate Control */
2279 uint32_t RESERVED3 : 5; /*!< [17:13] */
2280 uint32_t USBOTG : 1; /*!< [18] USB Clock Gate Control */
2281 uint32_t CMP : 1; /*!< [19] Comparator Clock Gate Control */
2282 uint32_t VREFb : 1; /*!< [20] VREF Clock Gate Control */
2283 uint32_t RESERVED4 : 11; /*!< [31:21] */
2288 * @name Constants and macros for entire SIM_SCGC4 register
2291 #define HW_SIM_SCGC4_ADDR(x) ((x) + 0x1034U)
2293 #define HW_SIM_SCGC4(x) (*(__IO hw_sim_scgc4_t *) HW_SIM_SCGC4_ADDR(x))
2294 #define HW_SIM_SCGC4_RD(x) (HW_SIM_SCGC4(x).U)
2295 #define HW_SIM_SCGC4_WR(x, v) (HW_SIM_SCGC4(x).U = (v))
2296 #define HW_SIM_SCGC4_SET(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) | (v)))
2297 #define HW_SIM_SCGC4_CLR(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) & ~(v)))
2298 #define HW_SIM_SCGC4_TOG(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) ^ (v)))
2302 * Constants & macros for individual SIM_SCGC4 bitfields
2306 * @name Register SIM_SCGC4, field EWM[1] (RW)
2308 * This bit controls the clock gate to the EWM module.
2311 * - 0 - Clock disabled
2312 * - 1 - Clock enabled
2315 #define BP_SIM_SCGC4_EWM (1U) /*!< Bit position for SIM_SCGC4_EWM. */
2316 #define BM_SIM_SCGC4_EWM (0x00000002U) /*!< Bit mask for SIM_SCGC4_EWM. */
2317 #define BS_SIM_SCGC4_EWM (1U) /*!< Bit field size in bits for SIM_SCGC4_EWM. */
2319 /*! @brief Read current value of the SIM_SCGC4_EWM field. */
2320 #define BR_SIM_SCGC4_EWM(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM))
2322 /*! @brief Format value for bitfield SIM_SCGC4_EWM. */
2323 #define BF_SIM_SCGC4_EWM(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_EWM) & BM_SIM_SCGC4_EWM)
2325 /*! @brief Set the EWM field to a new value. */
2326 #define BW_SIM_SCGC4_EWM(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM) = (v))
2330 * @name Register SIM_SCGC4, field I2C0[6] (RW)
2332 * This bit controls the clock gate to the I 2 C0 module.
2335 * - 0 - Clock disabled
2336 * - 1 - Clock enabled
2339 #define BP_SIM_SCGC4_I2C0 (6U) /*!< Bit position for SIM_SCGC4_I2C0. */
2340 #define BM_SIM_SCGC4_I2C0 (0x00000040U) /*!< Bit mask for SIM_SCGC4_I2C0. */
2341 #define BS_SIM_SCGC4_I2C0 (1U) /*!< Bit field size in bits for SIM_SCGC4_I2C0. */
2343 /*! @brief Read current value of the SIM_SCGC4_I2C0 field. */
2344 #define BR_SIM_SCGC4_I2C0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0))
2346 /*! @brief Format value for bitfield SIM_SCGC4_I2C0. */
2347 #define BF_SIM_SCGC4_I2C0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C0) & BM_SIM_SCGC4_I2C0)
2349 /*! @brief Set the I2C0 field to a new value. */
2350 #define BW_SIM_SCGC4_I2C0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0) = (v))
2354 * @name Register SIM_SCGC4, field I2C1[7] (RW)
2356 * This bit controls the clock gate to the I 2 C1 module.
2359 * - 0 - Clock disabled
2360 * - 1 - Clock enabled
2363 #define BP_SIM_SCGC4_I2C1 (7U) /*!< Bit position for SIM_SCGC4_I2C1. */
2364 #define BM_SIM_SCGC4_I2C1 (0x00000080U) /*!< Bit mask for SIM_SCGC4_I2C1. */
2365 #define BS_SIM_SCGC4_I2C1 (1U) /*!< Bit field size in bits for SIM_SCGC4_I2C1. */
2367 /*! @brief Read current value of the SIM_SCGC4_I2C1 field. */
2368 #define BR_SIM_SCGC4_I2C1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1))
2370 /*! @brief Format value for bitfield SIM_SCGC4_I2C1. */
2371 #define BF_SIM_SCGC4_I2C1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C1) & BM_SIM_SCGC4_I2C1)
2373 /*! @brief Set the I2C1 field to a new value. */
2374 #define BW_SIM_SCGC4_I2C1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1) = (v))
2378 * @name Register SIM_SCGC4, field UART0[10] (RW)
2380 * This bit controls the clock gate to the UART0 module.
2383 * - 0 - Clock disabled
2384 * - 1 - Clock enabled
2387 #define BP_SIM_SCGC4_UART0 (10U) /*!< Bit position for SIM_SCGC4_UART0. */
2388 #define BM_SIM_SCGC4_UART0 (0x00000400U) /*!< Bit mask for SIM_SCGC4_UART0. */
2389 #define BS_SIM_SCGC4_UART0 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART0. */
2391 /*! @brief Read current value of the SIM_SCGC4_UART0 field. */
2392 #define BR_SIM_SCGC4_UART0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0))
2394 /*! @brief Format value for bitfield SIM_SCGC4_UART0. */
2395 #define BF_SIM_SCGC4_UART0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART0) & BM_SIM_SCGC4_UART0)
2397 /*! @brief Set the UART0 field to a new value. */
2398 #define BW_SIM_SCGC4_UART0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0) = (v))
2402 * @name Register SIM_SCGC4, field UART1[11] (RW)
2404 * This bit controls the clock gate to the UART1 module.
2407 * - 0 - Clock disabled
2408 * - 1 - Clock enabled
2411 #define BP_SIM_SCGC4_UART1 (11U) /*!< Bit position for SIM_SCGC4_UART1. */
2412 #define BM_SIM_SCGC4_UART1 (0x00000800U) /*!< Bit mask for SIM_SCGC4_UART1. */
2413 #define BS_SIM_SCGC4_UART1 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART1. */
2415 /*! @brief Read current value of the SIM_SCGC4_UART1 field. */
2416 #define BR_SIM_SCGC4_UART1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1))
2418 /*! @brief Format value for bitfield SIM_SCGC4_UART1. */
2419 #define BF_SIM_SCGC4_UART1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART1) & BM_SIM_SCGC4_UART1)
2421 /*! @brief Set the UART1 field to a new value. */
2422 #define BW_SIM_SCGC4_UART1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1) = (v))
2426 * @name Register SIM_SCGC4, field UART2[12] (RW)
2428 * This bit controls the clock gate to the UART2 module.
2431 * - 0 - Clock disabled
2432 * - 1 - Clock enabled
2435 #define BP_SIM_SCGC4_UART2 (12U) /*!< Bit position for SIM_SCGC4_UART2. */
2436 #define BM_SIM_SCGC4_UART2 (0x00001000U) /*!< Bit mask for SIM_SCGC4_UART2. */
2437 #define BS_SIM_SCGC4_UART2 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART2. */
2439 /*! @brief Read current value of the SIM_SCGC4_UART2 field. */
2440 #define BR_SIM_SCGC4_UART2(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2))
2442 /*! @brief Format value for bitfield SIM_SCGC4_UART2. */
2443 #define BF_SIM_SCGC4_UART2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART2) & BM_SIM_SCGC4_UART2)
2445 /*! @brief Set the UART2 field to a new value. */
2446 #define BW_SIM_SCGC4_UART2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2) = (v))
2450 * @name Register SIM_SCGC4, field USBOTG[18] (RW)
2452 * This bit controls the clock gate to the USB module.
2455 * - 0 - Clock disabled
2456 * - 1 - Clock enabled
2459 #define BP_SIM_SCGC4_USBOTG (18U) /*!< Bit position for SIM_SCGC4_USBOTG. */
2460 #define BM_SIM_SCGC4_USBOTG (0x00040000U) /*!< Bit mask for SIM_SCGC4_USBOTG. */
2461 #define BS_SIM_SCGC4_USBOTG (1U) /*!< Bit field size in bits for SIM_SCGC4_USBOTG. */
2463 /*! @brief Read current value of the SIM_SCGC4_USBOTG field. */
2464 #define BR_SIM_SCGC4_USBOTG(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG))
2466 /*! @brief Format value for bitfield SIM_SCGC4_USBOTG. */
2467 #define BF_SIM_SCGC4_USBOTG(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_USBOTG) & BM_SIM_SCGC4_USBOTG)
2469 /*! @brief Set the USBOTG field to a new value. */
2470 #define BW_SIM_SCGC4_USBOTG(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG) = (v))
2474 * @name Register SIM_SCGC4, field CMP[19] (RW)
2476 * This bit controls the clock gate to the comparator module.
2479 * - 0 - Clock disabled
2480 * - 1 - Clock enabled
2483 #define BP_SIM_SCGC4_CMP (19U) /*!< Bit position for SIM_SCGC4_CMP. */
2484 #define BM_SIM_SCGC4_CMP (0x00080000U) /*!< Bit mask for SIM_SCGC4_CMP. */
2485 #define BS_SIM_SCGC4_CMP (1U) /*!< Bit field size in bits for SIM_SCGC4_CMP. */
2487 /*! @brief Read current value of the SIM_SCGC4_CMP field. */
2488 #define BR_SIM_SCGC4_CMP(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP))
2490 /*! @brief Format value for bitfield SIM_SCGC4_CMP. */
2491 #define BF_SIM_SCGC4_CMP(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMP) & BM_SIM_SCGC4_CMP)
2493 /*! @brief Set the CMP field to a new value. */
2494 #define BW_SIM_SCGC4_CMP(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP) = (v))
2498 * @name Register SIM_SCGC4, field VREF[20] (RW)
2500 * This bit controls the clock gate to the VREF module.
2503 * - 0 - Clock disabled
2504 * - 1 - Clock enabled
2507 #define BP_SIM_SCGC4_VREF (20U) /*!< Bit position for SIM_SCGC4_VREF. */
2508 #define BM_SIM_SCGC4_VREF (0x00100000U) /*!< Bit mask for SIM_SCGC4_VREF. */
2509 #define BS_SIM_SCGC4_VREF (1U) /*!< Bit field size in bits for SIM_SCGC4_VREF. */
2511 /*! @brief Read current value of the SIM_SCGC4_VREF field. */
2512 #define BR_SIM_SCGC4_VREF(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF))
2514 /*! @brief Format value for bitfield SIM_SCGC4_VREF. */
2515 #define BF_SIM_SCGC4_VREF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_VREF) & BM_SIM_SCGC4_VREF)
2517 /*! @brief Set the VREF field to a new value. */
2518 #define BW_SIM_SCGC4_VREF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF) = (v))
2521 /*******************************************************************************
2522 * HW_SIM_SCGC5 - System Clock Gating Control Register 5
2523 ******************************************************************************/
2526 * @brief HW_SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
2528 * Reset value: 0x00040182U
2530 typedef union _hw_sim_scgc5
2533 struct _hw_sim_scgc5_bitfields
2535 uint32_t LPTMR : 1; /*!< [0] Low Power Timer Access Control */
2536 uint32_t RESERVED0 : 8; /*!< [8:1] */
2537 uint32_t PORTAb : 1; /*!< [9] Port A Clock Gate Control */
2538 uint32_t PORTBb : 1; /*!< [10] Port B Clock Gate Control */
2539 uint32_t PORTCb : 1; /*!< [11] Port C Clock Gate Control */
2540 uint32_t PORTDb : 1; /*!< [12] Port D Clock Gate Control */
2541 uint32_t PORTEb : 1; /*!< [13] Port E Clock Gate Control */
2542 uint32_t RESERVED1 : 18; /*!< [31:14] */
2547 * @name Constants and macros for entire SIM_SCGC5 register
2550 #define HW_SIM_SCGC5_ADDR(x) ((x) + 0x1038U)
2552 #define HW_SIM_SCGC5(x) (*(__IO hw_sim_scgc5_t *) HW_SIM_SCGC5_ADDR(x))
2553 #define HW_SIM_SCGC5_RD(x) (HW_SIM_SCGC5(x).U)
2554 #define HW_SIM_SCGC5_WR(x, v) (HW_SIM_SCGC5(x).U = (v))
2555 #define HW_SIM_SCGC5_SET(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) | (v)))
2556 #define HW_SIM_SCGC5_CLR(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) & ~(v)))
2557 #define HW_SIM_SCGC5_TOG(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) ^ (v)))
2561 * Constants & macros for individual SIM_SCGC5 bitfields
2565 * @name Register SIM_SCGC5, field LPTMR[0] (RW)
2567 * This bit controls software access to the Low Power Timer module.
2570 * - 0 - Access disabled
2571 * - 1 - Access enabled
2574 #define BP_SIM_SCGC5_LPTMR (0U) /*!< Bit position for SIM_SCGC5_LPTMR. */
2575 #define BM_SIM_SCGC5_LPTMR (0x00000001U) /*!< Bit mask for SIM_SCGC5_LPTMR. */
2576 #define BS_SIM_SCGC5_LPTMR (1U) /*!< Bit field size in bits for SIM_SCGC5_LPTMR. */
2578 /*! @brief Read current value of the SIM_SCGC5_LPTMR field. */
2579 #define BR_SIM_SCGC5_LPTMR(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR))
2581 /*! @brief Format value for bitfield SIM_SCGC5_LPTMR. */
2582 #define BF_SIM_SCGC5_LPTMR(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_LPTMR) & BM_SIM_SCGC5_LPTMR)
2584 /*! @brief Set the LPTMR field to a new value. */
2585 #define BW_SIM_SCGC5_LPTMR(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR) = (v))
2589 * @name Register SIM_SCGC5, field PORTA[9] (RW)
2591 * This bit controls the clock gate to the Port A module.
2594 * - 0 - Clock disabled
2595 * - 1 - Clock enabled
2598 #define BP_SIM_SCGC5_PORTA (9U) /*!< Bit position for SIM_SCGC5_PORTA. */
2599 #define BM_SIM_SCGC5_PORTA (0x00000200U) /*!< Bit mask for SIM_SCGC5_PORTA. */
2600 #define BS_SIM_SCGC5_PORTA (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTA. */
2602 /*! @brief Read current value of the SIM_SCGC5_PORTA field. */
2603 #define BR_SIM_SCGC5_PORTA(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA))
2605 /*! @brief Format value for bitfield SIM_SCGC5_PORTA. */
2606 #define BF_SIM_SCGC5_PORTA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTA) & BM_SIM_SCGC5_PORTA)
2608 /*! @brief Set the PORTA field to a new value. */
2609 #define BW_SIM_SCGC5_PORTA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA) = (v))
2613 * @name Register SIM_SCGC5, field PORTB[10] (RW)
2615 * This bit controls the clock gate to the Port B module.
2618 * - 0 - Clock disabled
2619 * - 1 - Clock enabled
2622 #define BP_SIM_SCGC5_PORTB (10U) /*!< Bit position for SIM_SCGC5_PORTB. */
2623 #define BM_SIM_SCGC5_PORTB (0x00000400U) /*!< Bit mask for SIM_SCGC5_PORTB. */
2624 #define BS_SIM_SCGC5_PORTB (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTB. */
2626 /*! @brief Read current value of the SIM_SCGC5_PORTB field. */
2627 #define BR_SIM_SCGC5_PORTB(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB))
2629 /*! @brief Format value for bitfield SIM_SCGC5_PORTB. */
2630 #define BF_SIM_SCGC5_PORTB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTB) & BM_SIM_SCGC5_PORTB)
2632 /*! @brief Set the PORTB field to a new value. */
2633 #define BW_SIM_SCGC5_PORTB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB) = (v))
2637 * @name Register SIM_SCGC5, field PORTC[11] (RW)
2639 * This bit controls the clock gate to the Port C module.
2642 * - 0 - Clock disabled
2643 * - 1 - Clock enabled
2646 #define BP_SIM_SCGC5_PORTC (11U) /*!< Bit position for SIM_SCGC5_PORTC. */
2647 #define BM_SIM_SCGC5_PORTC (0x00000800U) /*!< Bit mask for SIM_SCGC5_PORTC. */
2648 #define BS_SIM_SCGC5_PORTC (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTC. */
2650 /*! @brief Read current value of the SIM_SCGC5_PORTC field. */
2651 #define BR_SIM_SCGC5_PORTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC))
2653 /*! @brief Format value for bitfield SIM_SCGC5_PORTC. */
2654 #define BF_SIM_SCGC5_PORTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTC) & BM_SIM_SCGC5_PORTC)
2656 /*! @brief Set the PORTC field to a new value. */
2657 #define BW_SIM_SCGC5_PORTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC) = (v))
2661 * @name Register SIM_SCGC5, field PORTD[12] (RW)
2663 * This bit controls the clock gate to the Port D module.
2666 * - 0 - Clock disabled
2667 * - 1 - Clock enabled
2670 #define BP_SIM_SCGC5_PORTD (12U) /*!< Bit position for SIM_SCGC5_PORTD. */
2671 #define BM_SIM_SCGC5_PORTD (0x00001000U) /*!< Bit mask for SIM_SCGC5_PORTD. */
2672 #define BS_SIM_SCGC5_PORTD (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTD. */
2674 /*! @brief Read current value of the SIM_SCGC5_PORTD field. */
2675 #define BR_SIM_SCGC5_PORTD(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD))
2677 /*! @brief Format value for bitfield SIM_SCGC5_PORTD. */
2678 #define BF_SIM_SCGC5_PORTD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTD) & BM_SIM_SCGC5_PORTD)
2680 /*! @brief Set the PORTD field to a new value. */
2681 #define BW_SIM_SCGC5_PORTD(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD) = (v))
2685 * @name Register SIM_SCGC5, field PORTE[13] (RW)
2687 * This bit controls the clock gate to the Port E module.
2690 * - 0 - Clock disabled
2691 * - 1 - Clock enabled
2694 #define BP_SIM_SCGC5_PORTE (13U) /*!< Bit position for SIM_SCGC5_PORTE. */
2695 #define BM_SIM_SCGC5_PORTE (0x00002000U) /*!< Bit mask for SIM_SCGC5_PORTE. */
2696 #define BS_SIM_SCGC5_PORTE (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTE. */
2698 /*! @brief Read current value of the SIM_SCGC5_PORTE field. */
2699 #define BR_SIM_SCGC5_PORTE(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE))
2701 /*! @brief Format value for bitfield SIM_SCGC5_PORTE. */
2702 #define BF_SIM_SCGC5_PORTE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTE) & BM_SIM_SCGC5_PORTE)
2704 /*! @brief Set the PORTE field to a new value. */
2705 #define BW_SIM_SCGC5_PORTE(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE) = (v))
2708 /*******************************************************************************
2709 * HW_SIM_SCGC6 - System Clock Gating Control Register 6
2710 ******************************************************************************/
2713 * @brief HW_SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
2715 * Reset value: 0x40000001U
2717 typedef union _hw_sim_scgc6
2720 struct _hw_sim_scgc6_bitfields
2722 uint32_t FTF : 1; /*!< [0] Flash Memory Clock Gate Control */
2723 uint32_t DMAMUXb : 1; /*!< [1] DMA Mux Clock Gate Control */
2724 uint32_t RESERVED0 : 4; /*!< [5:2] */
2725 uint32_t FTM3b : 1; /*!< [6] FTM3 Clock Gate Control */
2726 uint32_t ADC1b : 1; /*!< [7] ADC1 Clock Gate Control */
2727 uint32_t DAC1b : 1; /*!< [8] DAC1 Clock Gate Control */
2728 uint32_t RNGA : 1; /*!< [9] RNGA Clock Gate Control */
2729 uint32_t LPUART0b : 1; /*!< [10] LPUART0 Clock Gate Control */
2730 uint32_t RESERVED1 : 1; /*!< [11] */
2731 uint32_t SPI0b : 1; /*!< [12] SPI0 Clock Gate Control */
2732 uint32_t SPI1b : 1; /*!< [13] SPI1 Clock Gate Control */
2733 uint32_t RESERVED2 : 1; /*!< [14] */
2734 uint32_t I2S : 1; /*!< [15] I2S Clock Gate Control */
2735 uint32_t RESERVED3 : 2; /*!< [17:16] */
2736 uint32_t CRC : 1; /*!< [18] CRC Clock Gate Control */
2737 uint32_t RESERVED4 : 3; /*!< [21:19] */
2738 uint32_t PDB : 1; /*!< [22] PDB Clock Gate Control */
2739 uint32_t PITb : 1; /*!< [23] PIT Clock Gate Control */
2740 uint32_t FTM0b : 1; /*!< [24] FTM0 Clock Gate Control */
2741 uint32_t FTM1b : 1; /*!< [25] FTM1 Clock Gate Control */
2742 uint32_t FTM2b : 1; /*!< [26] FTM2 Clock Gate Control */
2743 uint32_t ADC0b : 1; /*!< [27] ADC0 Clock Gate Control */
2744 uint32_t RESERVED5 : 1; /*!< [28] */
2745 uint32_t RTCb : 1; /*!< [29] RTC Access Control */
2746 uint32_t RESERVED6 : 1; /*!< [30] */
2747 uint32_t DAC0b : 1; /*!< [31] DAC0 Clock Gate Control */
2752 * @name Constants and macros for entire SIM_SCGC6 register
2755 #define HW_SIM_SCGC6_ADDR(x) ((x) + 0x103CU)
2757 #define HW_SIM_SCGC6(x) (*(__IO hw_sim_scgc6_t *) HW_SIM_SCGC6_ADDR(x))
2758 #define HW_SIM_SCGC6_RD(x) (HW_SIM_SCGC6(x).U)
2759 #define HW_SIM_SCGC6_WR(x, v) (HW_SIM_SCGC6(x).U = (v))
2760 #define HW_SIM_SCGC6_SET(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) | (v)))
2761 #define HW_SIM_SCGC6_CLR(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) & ~(v)))
2762 #define HW_SIM_SCGC6_TOG(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) ^ (v)))
2766 * Constants & macros for individual SIM_SCGC6 bitfields
2770 * @name Register SIM_SCGC6, field FTF[0] (RW)
2772 * This bit controls the clock gate to the flash memory. Flash reads are still
2773 * supported while the flash memory is clock gated, but entry into low power modes
2774 * and HSRUN mode is blocked.
2777 * - 0 - Clock disabled
2778 * - 1 - Clock enabled
2781 #define BP_SIM_SCGC6_FTF (0U) /*!< Bit position for SIM_SCGC6_FTF. */
2782 #define BM_SIM_SCGC6_FTF (0x00000001U) /*!< Bit mask for SIM_SCGC6_FTF. */
2783 #define BS_SIM_SCGC6_FTF (1U) /*!< Bit field size in bits for SIM_SCGC6_FTF. */
2785 /*! @brief Read current value of the SIM_SCGC6_FTF field. */
2786 #define BR_SIM_SCGC6_FTF(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF))
2788 /*! @brief Format value for bitfield SIM_SCGC6_FTF. */
2789 #define BF_SIM_SCGC6_FTF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTF) & BM_SIM_SCGC6_FTF)
2791 /*! @brief Set the FTF field to a new value. */
2792 #define BW_SIM_SCGC6_FTF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF) = (v))
2796 * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
2798 * This bit controls the clock gate to the DMA Mux module.
2801 * - 0 - Clock disabled
2802 * - 1 - Clock enabled
2805 #define BP_SIM_SCGC6_DMAMUX (1U) /*!< Bit position for SIM_SCGC6_DMAMUX. */
2806 #define BM_SIM_SCGC6_DMAMUX (0x00000002U) /*!< Bit mask for SIM_SCGC6_DMAMUX. */
2807 #define BS_SIM_SCGC6_DMAMUX (1U) /*!< Bit field size in bits for SIM_SCGC6_DMAMUX. */
2809 /*! @brief Read current value of the SIM_SCGC6_DMAMUX field. */
2810 #define BR_SIM_SCGC6_DMAMUX(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX))
2812 /*! @brief Format value for bitfield SIM_SCGC6_DMAMUX. */
2813 #define BF_SIM_SCGC6_DMAMUX(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DMAMUX) & BM_SIM_SCGC6_DMAMUX)
2815 /*! @brief Set the DMAMUX field to a new value. */
2816 #define BW_SIM_SCGC6_DMAMUX(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX) = (v))
2820 * @name Register SIM_SCGC6, field FTM3[6] (RW)
2822 * This bit controls the clock gate to the FTM3 module.
2825 * - 0 - Clock disabled
2826 * - 1 - Clock enabled
2829 #define BP_SIM_SCGC6_FTM3 (6U) /*!< Bit position for SIM_SCGC6_FTM3. */
2830 #define BM_SIM_SCGC6_FTM3 (0x00000040U) /*!< Bit mask for SIM_SCGC6_FTM3. */
2831 #define BS_SIM_SCGC6_FTM3 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM3. */
2833 /*! @brief Read current value of the SIM_SCGC6_FTM3 field. */
2834 #define BR_SIM_SCGC6_FTM3(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM3))
2836 /*! @brief Format value for bitfield SIM_SCGC6_FTM3. */
2837 #define BF_SIM_SCGC6_FTM3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM3) & BM_SIM_SCGC6_FTM3)
2839 /*! @brief Set the FTM3 field to a new value. */
2840 #define BW_SIM_SCGC6_FTM3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM3) = (v))
2844 * @name Register SIM_SCGC6, field ADC1[7] (RW)
2846 * This bit controls the clock gate to the ADC1 module.
2849 * - 0 - Clock disabled
2850 * - 1 - Clock enabled
2853 #define BP_SIM_SCGC6_ADC1 (7U) /*!< Bit position for SIM_SCGC6_ADC1. */
2854 #define BM_SIM_SCGC6_ADC1 (0x00000080U) /*!< Bit mask for SIM_SCGC6_ADC1. */
2855 #define BS_SIM_SCGC6_ADC1 (1U) /*!< Bit field size in bits for SIM_SCGC6_ADC1. */
2857 /*! @brief Read current value of the SIM_SCGC6_ADC1 field. */
2858 #define BR_SIM_SCGC6_ADC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC1))
2860 /*! @brief Format value for bitfield SIM_SCGC6_ADC1. */
2861 #define BF_SIM_SCGC6_ADC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_ADC1) & BM_SIM_SCGC6_ADC1)
2863 /*! @brief Set the ADC1 field to a new value. */
2864 #define BW_SIM_SCGC6_ADC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC1) = (v))
2868 * @name Register SIM_SCGC6, field DAC1[8] (RW)
2870 * This bit controls the clock gate to the DAC1 module.
2873 * - 0 - Clock disabled
2874 * - 1 - Clock enabled
2877 #define BP_SIM_SCGC6_DAC1 (8U) /*!< Bit position for SIM_SCGC6_DAC1. */
2878 #define BM_SIM_SCGC6_DAC1 (0x00000100U) /*!< Bit mask for SIM_SCGC6_DAC1. */
2879 #define BS_SIM_SCGC6_DAC1 (1U) /*!< Bit field size in bits for SIM_SCGC6_DAC1. */
2881 /*! @brief Read current value of the SIM_SCGC6_DAC1 field. */
2882 #define BR_SIM_SCGC6_DAC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC1))
2884 /*! @brief Format value for bitfield SIM_SCGC6_DAC1. */
2885 #define BF_SIM_SCGC6_DAC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DAC1) & BM_SIM_SCGC6_DAC1)
2887 /*! @brief Set the DAC1 field to a new value. */
2888 #define BW_SIM_SCGC6_DAC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC1) = (v))
2892 * @name Register SIM_SCGC6, field RNGA[9] (RW)
2894 * This bit controls the clock gate to the RNGA module.
2897 #define BP_SIM_SCGC6_RNGA (9U) /*!< Bit position for SIM_SCGC6_RNGA. */
2898 #define BM_SIM_SCGC6_RNGA (0x00000200U) /*!< Bit mask for SIM_SCGC6_RNGA. */
2899 #define BS_SIM_SCGC6_RNGA (1U) /*!< Bit field size in bits for SIM_SCGC6_RNGA. */
2901 /*! @brief Read current value of the SIM_SCGC6_RNGA field. */
2902 #define BR_SIM_SCGC6_RNGA(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA))
2904 /*! @brief Format value for bitfield SIM_SCGC6_RNGA. */
2905 #define BF_SIM_SCGC6_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RNGA) & BM_SIM_SCGC6_RNGA)
2907 /*! @brief Set the RNGA field to a new value. */
2908 #define BW_SIM_SCGC6_RNGA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA) = (v))
2912 * @name Register SIM_SCGC6, field LPUART0[10] (RW)
2914 * This bit controls the clock gate to the LPUART0 module.
2917 * - 0 - Clock disabled
2918 * - 1 - Clock enabled
2921 #define BP_SIM_SCGC6_LPUART0 (10U) /*!< Bit position for SIM_SCGC6_LPUART0. */
2922 #define BM_SIM_SCGC6_LPUART0 (0x00000400U) /*!< Bit mask for SIM_SCGC6_LPUART0. */
2923 #define BS_SIM_SCGC6_LPUART0 (1U) /*!< Bit field size in bits for SIM_SCGC6_LPUART0. */
2925 /*! @brief Read current value of the SIM_SCGC6_LPUART0 field. */
2926 #define BR_SIM_SCGC6_LPUART0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_LPUART0))
2928 /*! @brief Format value for bitfield SIM_SCGC6_LPUART0. */
2929 #define BF_SIM_SCGC6_LPUART0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_LPUART0) & BM_SIM_SCGC6_LPUART0)
2931 /*! @brief Set the LPUART0 field to a new value. */
2932 #define BW_SIM_SCGC6_LPUART0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_LPUART0) = (v))
2936 * @name Register SIM_SCGC6, field SPI0[12] (RW)
2938 * This bit controls the clock gate to the SPI0 module.
2941 * - 0 - Clock disabled
2942 * - 1 - Clock enabled
2945 #define BP_SIM_SCGC6_SPI0 (12U) /*!< Bit position for SIM_SCGC6_SPI0. */
2946 #define BM_SIM_SCGC6_SPI0 (0x00001000U) /*!< Bit mask for SIM_SCGC6_SPI0. */
2947 #define BS_SIM_SCGC6_SPI0 (1U) /*!< Bit field size in bits for SIM_SCGC6_SPI0. */
2949 /*! @brief Read current value of the SIM_SCGC6_SPI0 field. */
2950 #define BR_SIM_SCGC6_SPI0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0))
2952 /*! @brief Format value for bitfield SIM_SCGC6_SPI0. */
2953 #define BF_SIM_SCGC6_SPI0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI0) & BM_SIM_SCGC6_SPI0)
2955 /*! @brief Set the SPI0 field to a new value. */
2956 #define BW_SIM_SCGC6_SPI0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0) = (v))
2960 * @name Register SIM_SCGC6, field SPI1[13] (RW)
2962 * This bit controls the clock gate to the SPI1 module.
2965 * - 0 - Clock disabled
2966 * - 1 - Clock enabled
2969 #define BP_SIM_SCGC6_SPI1 (13U) /*!< Bit position for SIM_SCGC6_SPI1. */
2970 #define BM_SIM_SCGC6_SPI1 (0x00002000U) /*!< Bit mask for SIM_SCGC6_SPI1. */
2971 #define BS_SIM_SCGC6_SPI1 (1U) /*!< Bit field size in bits for SIM_SCGC6_SPI1. */
2973 /*! @brief Read current value of the SIM_SCGC6_SPI1 field. */
2974 #define BR_SIM_SCGC6_SPI1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1))
2976 /*! @brief Format value for bitfield SIM_SCGC6_SPI1. */
2977 #define BF_SIM_SCGC6_SPI1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI1) & BM_SIM_SCGC6_SPI1)
2979 /*! @brief Set the SPI1 field to a new value. */
2980 #define BW_SIM_SCGC6_SPI1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1) = (v))
2984 * @name Register SIM_SCGC6, field I2S[15] (RW)
2986 * This bit controls the clock gate to the I 2 S module.
2989 * - 0 - Clock disabled
2990 * - 1 - Clock enabled
2993 #define BP_SIM_SCGC6_I2S (15U) /*!< Bit position for SIM_SCGC6_I2S. */
2994 #define BM_SIM_SCGC6_I2S (0x00008000U) /*!< Bit mask for SIM_SCGC6_I2S. */
2995 #define BS_SIM_SCGC6_I2S (1U) /*!< Bit field size in bits for SIM_SCGC6_I2S. */
2997 /*! @brief Read current value of the SIM_SCGC6_I2S field. */
2998 #define BR_SIM_SCGC6_I2S(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S))
3000 /*! @brief Format value for bitfield SIM_SCGC6_I2S. */
3001 #define BF_SIM_SCGC6_I2S(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_I2S) & BM_SIM_SCGC6_I2S)
3003 /*! @brief Set the I2S field to a new value. */
3004 #define BW_SIM_SCGC6_I2S(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S) = (v))
3008 * @name Register SIM_SCGC6, field CRC[18] (RW)
3010 * This bit controls the clock gate to the CRC module.
3013 * - 0 - Clock disabled
3014 * - 1 - Clock enabled
3017 #define BP_SIM_SCGC6_CRC (18U) /*!< Bit position for SIM_SCGC6_CRC. */
3018 #define BM_SIM_SCGC6_CRC (0x00040000U) /*!< Bit mask for SIM_SCGC6_CRC. */
3019 #define BS_SIM_SCGC6_CRC (1U) /*!< Bit field size in bits for SIM_SCGC6_CRC. */
3021 /*! @brief Read current value of the SIM_SCGC6_CRC field. */
3022 #define BR_SIM_SCGC6_CRC(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC))
3024 /*! @brief Format value for bitfield SIM_SCGC6_CRC. */
3025 #define BF_SIM_SCGC6_CRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_CRC) & BM_SIM_SCGC6_CRC)
3027 /*! @brief Set the CRC field to a new value. */
3028 #define BW_SIM_SCGC6_CRC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC) = (v))
3032 * @name Register SIM_SCGC6, field PDB[22] (RW)
3034 * This bit controls the clock gate to the PDB module.
3037 * - 0 - Clock disabled
3038 * - 1 - Clock enabled
3041 #define BP_SIM_SCGC6_PDB (22U) /*!< Bit position for SIM_SCGC6_PDB. */
3042 #define BM_SIM_SCGC6_PDB (0x00400000U) /*!< Bit mask for SIM_SCGC6_PDB. */
3043 #define BS_SIM_SCGC6_PDB (1U) /*!< Bit field size in bits for SIM_SCGC6_PDB. */
3045 /*! @brief Read current value of the SIM_SCGC6_PDB field. */
3046 #define BR_SIM_SCGC6_PDB(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB))
3048 /*! @brief Format value for bitfield SIM_SCGC6_PDB. */
3049 #define BF_SIM_SCGC6_PDB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PDB) & BM_SIM_SCGC6_PDB)
3051 /*! @brief Set the PDB field to a new value. */
3052 #define BW_SIM_SCGC6_PDB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB) = (v))
3056 * @name Register SIM_SCGC6, field PIT[23] (RW)
3058 * This bit controls the clock gate to the PIT module.
3061 * - 0 - Clock disabled
3062 * - 1 - Clock enabled
3065 #define BP_SIM_SCGC6_PIT (23U) /*!< Bit position for SIM_SCGC6_PIT. */
3066 #define BM_SIM_SCGC6_PIT (0x00800000U) /*!< Bit mask for SIM_SCGC6_PIT. */
3067 #define BS_SIM_SCGC6_PIT (1U) /*!< Bit field size in bits for SIM_SCGC6_PIT. */
3069 /*! @brief Read current value of the SIM_SCGC6_PIT field. */
3070 #define BR_SIM_SCGC6_PIT(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT))
3072 /*! @brief Format value for bitfield SIM_SCGC6_PIT. */
3073 #define BF_SIM_SCGC6_PIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PIT) & BM_SIM_SCGC6_PIT)
3075 /*! @brief Set the PIT field to a new value. */
3076 #define BW_SIM_SCGC6_PIT(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT) = (v))
3080 * @name Register SIM_SCGC6, field FTM0[24] (RW)
3082 * This bit controls the clock gate to the FTM0 module.
3085 * - 0 - Clock disabled
3086 * - 1 - Clock enabled
3089 #define BP_SIM_SCGC6_FTM0 (24U) /*!< Bit position for SIM_SCGC6_FTM0. */
3090 #define BM_SIM_SCGC6_FTM0 (0x01000000U) /*!< Bit mask for SIM_SCGC6_FTM0. */
3091 #define BS_SIM_SCGC6_FTM0 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM0. */
3093 /*! @brief Read current value of the SIM_SCGC6_FTM0 field. */
3094 #define BR_SIM_SCGC6_FTM0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0))
3096 /*! @brief Format value for bitfield SIM_SCGC6_FTM0. */
3097 #define BF_SIM_SCGC6_FTM0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM0) & BM_SIM_SCGC6_FTM0)
3099 /*! @brief Set the FTM0 field to a new value. */
3100 #define BW_SIM_SCGC6_FTM0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0) = (v))
3104 * @name Register SIM_SCGC6, field FTM1[25] (RW)
3106 * This bit controls the clock gate to the FTM1 module.
3109 * - 0 - Clock disabled
3110 * - 1 - Clock enabled
3113 #define BP_SIM_SCGC6_FTM1 (25U) /*!< Bit position for SIM_SCGC6_FTM1. */
3114 #define BM_SIM_SCGC6_FTM1 (0x02000000U) /*!< Bit mask for SIM_SCGC6_FTM1. */
3115 #define BS_SIM_SCGC6_FTM1 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM1. */
3117 /*! @brief Read current value of the SIM_SCGC6_FTM1 field. */
3118 #define BR_SIM_SCGC6_FTM1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1))
3120 /*! @brief Format value for bitfield SIM_SCGC6_FTM1. */
3121 #define BF_SIM_SCGC6_FTM1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM1) & BM_SIM_SCGC6_FTM1)
3123 /*! @brief Set the FTM1 field to a new value. */
3124 #define BW_SIM_SCGC6_FTM1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1) = (v))
3128 * @name Register SIM_SCGC6, field FTM2[26] (RW)
3130 * This bit controls the clock gate to the FTM2 module.
3133 * - 0 - Clock disabled
3134 * - 1 - Clock enabled
3137 #define BP_SIM_SCGC6_FTM2 (26U) /*!< Bit position for SIM_SCGC6_FTM2. */
3138 #define BM_SIM_SCGC6_FTM2 (0x04000000U) /*!< Bit mask for SIM_SCGC6_FTM2. */
3139 #define BS_SIM_SCGC6_FTM2 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM2. */
3141 /*! @brief Read current value of the SIM_SCGC6_FTM2 field. */
3142 #define BR_SIM_SCGC6_FTM2(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2))
3144 /*! @brief Format value for bitfield SIM_SCGC6_FTM2. */
3145 #define BF_SIM_SCGC6_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM2) & BM_SIM_SCGC6_FTM2)
3147 /*! @brief Set the FTM2 field to a new value. */
3148 #define BW_SIM_SCGC6_FTM2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2) = (v))
3152 * @name Register SIM_SCGC6, field ADC0[27] (RW)
3154 * This bit controls the clock gate to the ADC0 module.
3157 * - 0 - Clock disabled
3158 * - 1 - Clock enabled
3161 #define BP_SIM_SCGC6_ADC0 (27U) /*!< Bit position for SIM_SCGC6_ADC0. */
3162 #define BM_SIM_SCGC6_ADC0 (0x08000000U) /*!< Bit mask for SIM_SCGC6_ADC0. */
3163 #define BS_SIM_SCGC6_ADC0 (1U) /*!< Bit field size in bits for SIM_SCGC6_ADC0. */
3165 /*! @brief Read current value of the SIM_SCGC6_ADC0 field. */
3166 #define BR_SIM_SCGC6_ADC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0))
3168 /*! @brief Format value for bitfield SIM_SCGC6_ADC0. */
3169 #define BF_SIM_SCGC6_ADC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_ADC0) & BM_SIM_SCGC6_ADC0)
3171 /*! @brief Set the ADC0 field to a new value. */
3172 #define BW_SIM_SCGC6_ADC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0) = (v))
3176 * @name Register SIM_SCGC6, field RTC[29] (RW)
3178 * This bit controls software access and interrupts to the RTC module.
3181 * - 0 - Access and interrupts disabled
3182 * - 1 - Access and interrupts enabled
3185 #define BP_SIM_SCGC6_RTC (29U) /*!< Bit position for SIM_SCGC6_RTC. */
3186 #define BM_SIM_SCGC6_RTC (0x20000000U) /*!< Bit mask for SIM_SCGC6_RTC. */
3187 #define BS_SIM_SCGC6_RTC (1U) /*!< Bit field size in bits for SIM_SCGC6_RTC. */
3189 /*! @brief Read current value of the SIM_SCGC6_RTC field. */
3190 #define BR_SIM_SCGC6_RTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC))
3192 /*! @brief Format value for bitfield SIM_SCGC6_RTC. */
3193 #define BF_SIM_SCGC6_RTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RTC) & BM_SIM_SCGC6_RTC)
3195 /*! @brief Set the RTC field to a new value. */
3196 #define BW_SIM_SCGC6_RTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC) = (v))
3200 * @name Register SIM_SCGC6, field DAC0[31] (RW)
3202 * This bit controls the clock gate to the DAC0 module.
3205 * - 0 - Clock disabled
3206 * - 1 - Clock enabled
3209 #define BP_SIM_SCGC6_DAC0 (31U) /*!< Bit position for SIM_SCGC6_DAC0. */
3210 #define BM_SIM_SCGC6_DAC0 (0x80000000U) /*!< Bit mask for SIM_SCGC6_DAC0. */
3211 #define BS_SIM_SCGC6_DAC0 (1U) /*!< Bit field size in bits for SIM_SCGC6_DAC0. */
3213 /*! @brief Read current value of the SIM_SCGC6_DAC0 field. */
3214 #define BR_SIM_SCGC6_DAC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0))
3216 /*! @brief Format value for bitfield SIM_SCGC6_DAC0. */
3217 #define BF_SIM_SCGC6_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DAC0) & BM_SIM_SCGC6_DAC0)
3219 /*! @brief Set the DAC0 field to a new value. */
3220 #define BW_SIM_SCGC6_DAC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0) = (v))
3223 /*******************************************************************************
3224 * HW_SIM_SCGC7 - System Clock Gating Control Register 7
3225 ******************************************************************************/
3228 * @brief HW_SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
3230 * Reset value: 0x00000002U
3232 typedef union _hw_sim_scgc7
3235 struct _hw_sim_scgc7_bitfields
3237 uint32_t FLEXBUS : 1; /*!< [0] FlexBus Clock Gate Control */
3238 uint32_t DMA : 1; /*!< [1] DMA Clock Gate Control */
3239 uint32_t RESERVED0 : 30; /*!< [31:2] */
3244 * @name Constants and macros for entire SIM_SCGC7 register
3247 #define HW_SIM_SCGC7_ADDR(x) ((x) + 0x1040U)
3249 #define HW_SIM_SCGC7(x) (*(__IO hw_sim_scgc7_t *) HW_SIM_SCGC7_ADDR(x))
3250 #define HW_SIM_SCGC7_RD(x) (HW_SIM_SCGC7(x).U)
3251 #define HW_SIM_SCGC7_WR(x, v) (HW_SIM_SCGC7(x).U = (v))
3252 #define HW_SIM_SCGC7_SET(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) | (v)))
3253 #define HW_SIM_SCGC7_CLR(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) & ~(v)))
3254 #define HW_SIM_SCGC7_TOG(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) ^ (v)))
3258 * Constants & macros for individual SIM_SCGC7 bitfields
3262 * @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
3264 * This bit controls the clock gate to the FlexBus module.
3267 * - 0 - Clock disabled
3268 * - 1 - Clock enabled
3271 #define BP_SIM_SCGC7_FLEXBUS (0U) /*!< Bit position for SIM_SCGC7_FLEXBUS. */
3272 #define BM_SIM_SCGC7_FLEXBUS (0x00000001U) /*!< Bit mask for SIM_SCGC7_FLEXBUS. */
3273 #define BS_SIM_SCGC7_FLEXBUS (1U) /*!< Bit field size in bits for SIM_SCGC7_FLEXBUS. */
3275 /*! @brief Read current value of the SIM_SCGC7_FLEXBUS field. */
3276 #define BR_SIM_SCGC7_FLEXBUS(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS))
3278 /*! @brief Format value for bitfield SIM_SCGC7_FLEXBUS. */
3279 #define BF_SIM_SCGC7_FLEXBUS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_FLEXBUS) & BM_SIM_SCGC7_FLEXBUS)
3281 /*! @brief Set the FLEXBUS field to a new value. */
3282 #define BW_SIM_SCGC7_FLEXBUS(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS) = (v))
3286 * @name Register SIM_SCGC7, field DMA[1] (RW)
3288 * This bit controls the clock gate to the DMA module.
3291 * - 0 - Clock disabled
3292 * - 1 - Clock enabled
3295 #define BP_SIM_SCGC7_DMA (1U) /*!< Bit position for SIM_SCGC7_DMA. */
3296 #define BM_SIM_SCGC7_DMA (0x00000002U) /*!< Bit mask for SIM_SCGC7_DMA. */
3297 #define BS_SIM_SCGC7_DMA (1U) /*!< Bit field size in bits for SIM_SCGC7_DMA. */
3299 /*! @brief Read current value of the SIM_SCGC7_DMA field. */
3300 #define BR_SIM_SCGC7_DMA(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA))
3302 /*! @brief Format value for bitfield SIM_SCGC7_DMA. */
3303 #define BF_SIM_SCGC7_DMA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_DMA) & BM_SIM_SCGC7_DMA)
3305 /*! @brief Set the DMA field to a new value. */
3306 #define BW_SIM_SCGC7_DMA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA) = (v))
3309 /*******************************************************************************
3310 * HW_SIM_CLKDIV1 - System Clock Divider Register 1
3311 ******************************************************************************/
3314 * @brief HW_SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
3316 * Reset value: 0x00010000U
3318 * When updating CLKDIV1, update all fields using the one write command.
3319 * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
3320 * write to be ignored. The maximum divide ratio that can be programmed between
3321 * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
3322 * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
3323 * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
3326 typedef union _hw_sim_clkdiv1
3329 struct _hw_sim_clkdiv1_bitfields
3331 uint32_t RESERVED0 : 16; /*!< [15:0] */
3332 uint32_t OUTDIV4 : 4; /*!< [19:16] Clock 4 output divider value */
3333 uint32_t OUTDIV3 : 4; /*!< [23:20] Clock 3 output divider value */
3334 uint32_t OUTDIV2 : 4; /*!< [27:24] Clock 2 output divider value */
3335 uint32_t OUTDIV1 : 4; /*!< [31:28] Clock 1 output divider value */
3340 * @name Constants and macros for entire SIM_CLKDIV1 register
3343 #define HW_SIM_CLKDIV1_ADDR(x) ((x) + 0x1044U)
3345 #define HW_SIM_CLKDIV1(x) (*(__IO hw_sim_clkdiv1_t *) HW_SIM_CLKDIV1_ADDR(x))
3346 #define HW_SIM_CLKDIV1_RD(x) (HW_SIM_CLKDIV1(x).U)
3347 #define HW_SIM_CLKDIV1_WR(x, v) (HW_SIM_CLKDIV1(x).U = (v))
3348 #define HW_SIM_CLKDIV1_SET(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) | (v)))
3349 #define HW_SIM_CLKDIV1_CLR(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) & ~(v)))
3350 #define HW_SIM_CLKDIV1_TOG(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) ^ (v)))
3354 * Constants & macros for individual SIM_CLKDIV1 bitfields
3358 * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
3360 * This field sets the divide value for the flash clock from MCGOUTCLK. At the
3361 * end of reset, it is loaded with either 0001 or 1111 depending on
3362 * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
3366 * - 0000 - Divide-by-1.
3367 * - 0001 - Divide-by-2.
3368 * - 0010 - Divide-by-3.
3369 * - 0011 - Divide-by-4.
3370 * - 0100 - Divide-by-5.
3371 * - 0101 - Divide-by-6.
3372 * - 0110 - Divide-by-7.
3373 * - 0111 - Divide-by-8.
3374 * - 1000 - Divide-by-9.
3375 * - 1001 - Divide-by-10.
3376 * - 1010 - Divide-by-11.
3377 * - 1011 - Divide-by-12.
3378 * - 1100 - Divide-by-13.
3379 * - 1101 - Divide-by-14.
3380 * - 1110 - Divide-by-15.
3381 * - 1111 - Divide-by-16.
3384 #define BP_SIM_CLKDIV1_OUTDIV4 (16U) /*!< Bit position for SIM_CLKDIV1_OUTDIV4. */
3385 #define BM_SIM_CLKDIV1_OUTDIV4 (0x000F0000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV4. */
3386 #define BS_SIM_CLKDIV1_OUTDIV4 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV4. */
3388 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */
3389 #define BR_SIM_CLKDIV1_OUTDIV4(x) (HW_SIM_CLKDIV1(x).B.OUTDIV4)
3391 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV4. */
3392 #define BF_SIM_CLKDIV1_OUTDIV4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV4) & BM_SIM_CLKDIV1_OUTDIV4)
3394 /*! @brief Set the OUTDIV4 field to a new value. */
3395 #define BW_SIM_CLKDIV1_OUTDIV4(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV4) | BF_SIM_CLKDIV1_OUTDIV4(v)))
3399 * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
3401 * This field sets the divide value for the FlexBus clock (external pin FB_CLK)
3402 * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
3403 * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
3404 * divide of the system clock frequency.
3407 * - 0000 - Divide-by-1.
3408 * - 0001 - Divide-by-2.
3409 * - 0010 - Divide-by-3.
3410 * - 0011 - Divide-by-4.
3411 * - 0100 - Divide-by-5.
3412 * - 0101 - Divide-by-6.
3413 * - 0110 - Divide-by-7.
3414 * - 0111 - Divide-by-8.
3415 * - 1000 - Divide-by-9.
3416 * - 1001 - Divide-by-10.
3417 * - 1010 - Divide-by-11.
3418 * - 1011 - Divide-by-12.
3419 * - 1100 - Divide-by-13.
3420 * - 1101 - Divide-by-14.
3421 * - 1110 - Divide-by-15.
3422 * - 1111 - Divide-by-16.
3425 #define BP_SIM_CLKDIV1_OUTDIV3 (20U) /*!< Bit position for SIM_CLKDIV1_OUTDIV3. */
3426 #define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV3. */
3427 #define BS_SIM_CLKDIV1_OUTDIV3 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3. */
3429 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. */
3430 #define BR_SIM_CLKDIV1_OUTDIV3(x) (HW_SIM_CLKDIV1(x).B.OUTDIV3)
3432 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3. */
3433 #define BF_SIM_CLKDIV1_OUTDIV3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV3) & BM_SIM_CLKDIV1_OUTDIV3)
3435 /*! @brief Set the OUTDIV3 field to a new value. */
3436 #define BW_SIM_CLKDIV1_OUTDIV3(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV3) | BF_SIM_CLKDIV1_OUTDIV3(v)))
3440 * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
3442 * This field sets the divide value for the bus clock from MCGOUTCLK. At the end
3443 * of reset, it is loaded with either 0000 or 0111 depending on
3444 * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
3448 * - 0000 - Divide-by-1.
3449 * - 0001 - Divide-by-2.
3450 * - 0010 - Divide-by-3.
3451 * - 0011 - Divide-by-4.
3452 * - 0100 - Divide-by-5.
3453 * - 0101 - Divide-by-6.
3454 * - 0110 - Divide-by-7.
3455 * - 0111 - Divide-by-8.
3456 * - 1000 - Divide-by-9.
3457 * - 1001 - Divide-by-10.
3458 * - 1010 - Divide-by-11.
3459 * - 1011 - Divide-by-12.
3460 * - 1100 - Divide-by-13.
3461 * - 1101 - Divide-by-14.
3462 * - 1110 - Divide-by-15.
3463 * - 1111 - Divide-by-16.
3466 #define BP_SIM_CLKDIV1_OUTDIV2 (24U) /*!< Bit position for SIM_CLKDIV1_OUTDIV2. */
3467 #define BM_SIM_CLKDIV1_OUTDIV2 (0x0F000000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV2. */
3468 #define BS_SIM_CLKDIV1_OUTDIV2 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV2. */
3470 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. */
3471 #define BR_SIM_CLKDIV1_OUTDIV2(x) (HW_SIM_CLKDIV1(x).B.OUTDIV2)
3473 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV2. */
3474 #define BF_SIM_CLKDIV1_OUTDIV2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV2) & BM_SIM_CLKDIV1_OUTDIV2)
3476 /*! @brief Set the OUTDIV2 field to a new value. */
3477 #define BW_SIM_CLKDIV1_OUTDIV2(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV2) | BF_SIM_CLKDIV1_OUTDIV2(v)))
3481 * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
3483 * This field sets the divide value for the core/system clock from MCGOUTCLK. At
3484 * the end of reset, it is loaded with either 0000 or 0111 depending on
3488 * - 0000 - Divide-by-1.
3489 * - 0001 - Divide-by-2.
3490 * - 0010 - Divide-by-3.
3491 * - 0011 - Divide-by-4.
3492 * - 0100 - Divide-by-5.
3493 * - 0101 - Divide-by-6.
3494 * - 0110 - Divide-by-7.
3495 * - 0111 - Divide-by-8.
3496 * - 1000 - Divide-by-9.
3497 * - 1001 - Divide-by-10.
3498 * - 1010 - Divide-by-11.
3499 * - 1011 - Divide-by-12.
3500 * - 1100 - Divide-by-13.
3501 * - 1101 - Divide-by-14.
3502 * - 1110 - Divide-by-15.
3503 * - 1111 - Divide-by-16.
3506 #define BP_SIM_CLKDIV1_OUTDIV1 (28U) /*!< Bit position for SIM_CLKDIV1_OUTDIV1. */
3507 #define BM_SIM_CLKDIV1_OUTDIV1 (0xF0000000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV1. */
3508 #define BS_SIM_CLKDIV1_OUTDIV1 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV1. */
3510 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */
3511 #define BR_SIM_CLKDIV1_OUTDIV1(x) (HW_SIM_CLKDIV1(x).B.OUTDIV1)
3513 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV1. */
3514 #define BF_SIM_CLKDIV1_OUTDIV1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV1) & BM_SIM_CLKDIV1_OUTDIV1)
3516 /*! @brief Set the OUTDIV1 field to a new value. */
3517 #define BW_SIM_CLKDIV1_OUTDIV1(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV1) | BF_SIM_CLKDIV1_OUTDIV1(v)))
3520 /*******************************************************************************
3521 * HW_SIM_CLKDIV2 - System Clock Divider Register 2
3522 ******************************************************************************/
3525 * @brief HW_SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
3527 * Reset value: 0x00000000U
3529 typedef union _hw_sim_clkdiv2
3532 struct _hw_sim_clkdiv2_bitfields
3534 uint32_t USBFRAC : 1; /*!< [0] USB clock divider fraction */
3535 uint32_t USBDIV : 3; /*!< [3:1] USB clock divider divisor */
3536 uint32_t RESERVED0 : 28; /*!< [31:4] */
3541 * @name Constants and macros for entire SIM_CLKDIV2 register
3544 #define HW_SIM_CLKDIV2_ADDR(x) ((x) + 0x1048U)
3546 #define HW_SIM_CLKDIV2(x) (*(__IO hw_sim_clkdiv2_t *) HW_SIM_CLKDIV2_ADDR(x))
3547 #define HW_SIM_CLKDIV2_RD(x) (HW_SIM_CLKDIV2(x).U)
3548 #define HW_SIM_CLKDIV2_WR(x, v) (HW_SIM_CLKDIV2(x).U = (v))
3549 #define HW_SIM_CLKDIV2_SET(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) | (v)))
3550 #define HW_SIM_CLKDIV2_CLR(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) & ~(v)))
3551 #define HW_SIM_CLKDIV2_TOG(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) ^ (v)))
3555 * Constants & macros for individual SIM_CLKDIV2 bitfields
3559 * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
3561 * This field sets the fraction multiply value for the fractional clock divider
3562 * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
3563 * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
3566 #define BP_SIM_CLKDIV2_USBFRAC (0U) /*!< Bit position for SIM_CLKDIV2_USBFRAC. */
3567 #define BM_SIM_CLKDIV2_USBFRAC (0x00000001U) /*!< Bit mask for SIM_CLKDIV2_USBFRAC. */
3568 #define BS_SIM_CLKDIV2_USBFRAC (1U) /*!< Bit field size in bits for SIM_CLKDIV2_USBFRAC. */
3570 /*! @brief Read current value of the SIM_CLKDIV2_USBFRAC field. */
3571 #define BR_SIM_CLKDIV2_USBFRAC(x) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC))
3573 /*! @brief Format value for bitfield SIM_CLKDIV2_USBFRAC. */
3574 #define BF_SIM_CLKDIV2_USBFRAC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBFRAC) & BM_SIM_CLKDIV2_USBFRAC)
3576 /*! @brief Set the USBFRAC field to a new value. */
3577 #define BW_SIM_CLKDIV2_USBFRAC(x, v) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC) = (v))
3581 * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
3583 * This field sets the divide value for the fractional clock divider when the
3584 * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
3585 * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
3588 #define BP_SIM_CLKDIV2_USBDIV (1U) /*!< Bit position for SIM_CLKDIV2_USBDIV. */
3589 #define BM_SIM_CLKDIV2_USBDIV (0x0000000EU) /*!< Bit mask for SIM_CLKDIV2_USBDIV. */
3590 #define BS_SIM_CLKDIV2_USBDIV (3U) /*!< Bit field size in bits for SIM_CLKDIV2_USBDIV. */
3592 /*! @brief Read current value of the SIM_CLKDIV2_USBDIV field. */
3593 #define BR_SIM_CLKDIV2_USBDIV(x) (HW_SIM_CLKDIV2(x).B.USBDIV)
3595 /*! @brief Format value for bitfield SIM_CLKDIV2_USBDIV. */
3596 #define BF_SIM_CLKDIV2_USBDIV(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBDIV) & BM_SIM_CLKDIV2_USBDIV)
3598 /*! @brief Set the USBDIV field to a new value. */
3599 #define BW_SIM_CLKDIV2_USBDIV(x, v) (HW_SIM_CLKDIV2_WR(x, (HW_SIM_CLKDIV2_RD(x) & ~BM_SIM_CLKDIV2_USBDIV) | BF_SIM_CLKDIV2_USBDIV(v)))
3602 /*******************************************************************************
3603 * HW_SIM_FCFG1 - Flash Configuration Register 1
3604 ******************************************************************************/
3607 * @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW)
3609 * Reset value: 0x0F0F0F00U
3611 * The EESIZE and DEPART filelds are not applicable.
3613 typedef union _hw_sim_fcfg1
3616 struct _hw_sim_fcfg1_bitfields
3618 uint32_t FLASHDIS : 1; /*!< [0] Flash Disable */
3619 uint32_t FLASHDOZE : 1; /*!< [1] Flash Doze */
3620 uint32_t RESERVED0 : 22; /*!< [23:2] */
3621 uint32_t PFSIZE : 4; /*!< [27:24] Program flash size */
3622 uint32_t RESERVED1 : 4; /*!< [31:28] */
3627 * @name Constants and macros for entire SIM_FCFG1 register
3630 #define HW_SIM_FCFG1_ADDR(x) ((x) + 0x104CU)
3632 #define HW_SIM_FCFG1(x) (*(__IO hw_sim_fcfg1_t *) HW_SIM_FCFG1_ADDR(x))
3633 #define HW_SIM_FCFG1_RD(x) (HW_SIM_FCFG1(x).U)
3634 #define HW_SIM_FCFG1_WR(x, v) (HW_SIM_FCFG1(x).U = (v))
3635 #define HW_SIM_FCFG1_SET(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) | (v)))
3636 #define HW_SIM_FCFG1_CLR(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) & ~(v)))
3637 #define HW_SIM_FCFG1_TOG(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) ^ (v)))
3641 * Constants & macros for individual SIM_FCFG1 bitfields
3645 * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
3647 * Flash accesses are disabled (and generate a bus error) and the Flash memory
3648 * is placed in a low power state. This bit should not be changed during VLP
3649 * modes. Relocate the interrupt vectors out of Flash memory before disabling the
3653 * - 0 - Flash is enabled
3654 * - 1 - Flash is disabled
3657 #define BP_SIM_FCFG1_FLASHDIS (0U) /*!< Bit position for SIM_FCFG1_FLASHDIS. */
3658 #define BM_SIM_FCFG1_FLASHDIS (0x00000001U) /*!< Bit mask for SIM_FCFG1_FLASHDIS. */
3659 #define BS_SIM_FCFG1_FLASHDIS (1U) /*!< Bit field size in bits for SIM_FCFG1_FLASHDIS. */
3661 /*! @brief Read current value of the SIM_FCFG1_FLASHDIS field. */
3662 #define BR_SIM_FCFG1_FLASHDIS(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS))
3664 /*! @brief Format value for bitfield SIM_FCFG1_FLASHDIS. */
3665 #define BF_SIM_FCFG1_FLASHDIS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDIS) & BM_SIM_FCFG1_FLASHDIS)
3667 /*! @brief Set the FLASHDIS field to a new value. */
3668 #define BW_SIM_FCFG1_FLASHDIS(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS) = (v))
3672 * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
3674 * When set, Flash memory is disabled for the duration of Wait mode. An attempt
3675 * by the DMA or other bus master to access the Flash when the Flash is disabled
3676 * will result in a bus error. This bit should be clear during VLP modes. The
3677 * Flash will be automatically enabled again at the end of Wait mode so interrupt
3678 * vectors do not need to be relocated out of Flash memory. The wakeup time from
3679 * Wait mode is extended when this bit is set.
3682 * - 0 - Flash remains enabled during Wait mode
3683 * - 1 - Flash is disabled for the duration of Wait mode
3686 #define BP_SIM_FCFG1_FLASHDOZE (1U) /*!< Bit position for SIM_FCFG1_FLASHDOZE. */
3687 #define BM_SIM_FCFG1_FLASHDOZE (0x00000002U) /*!< Bit mask for SIM_FCFG1_FLASHDOZE. */
3688 #define BS_SIM_FCFG1_FLASHDOZE (1U) /*!< Bit field size in bits for SIM_FCFG1_FLASHDOZE. */
3690 /*! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. */
3691 #define BR_SIM_FCFG1_FLASHDOZE(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE))
3693 /*! @brief Format value for bitfield SIM_FCFG1_FLASHDOZE. */
3694 #define BF_SIM_FCFG1_FLASHDOZE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDOZE) & BM_SIM_FCFG1_FLASHDOZE)
3696 /*! @brief Set the FLASHDOZE field to a new value. */
3697 #define BW_SIM_FCFG1_FLASHDOZE(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE) = (v))
3701 * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
3703 * This field specifies the amount of program flash memory available on the
3704 * device . Undefined values are reserved.
3707 * - 0011 - 32 KB of program flash memory
3708 * - 0101 - 64 KB of program flash memory
3709 * - 0111 - 128 KB of program flash memory
3710 * - 1001 - 256 KB of program flash memory
3711 * - 1011 - 512 KB of program flash memory
3712 * - 1101 - 1024 KB of program flash memory
3713 * - 1111 - 512 KB of program flash memory
3716 #define BP_SIM_FCFG1_PFSIZE (24U) /*!< Bit position for SIM_FCFG1_PFSIZE. */
3717 #define BM_SIM_FCFG1_PFSIZE (0x0F000000U) /*!< Bit mask for SIM_FCFG1_PFSIZE. */
3718 #define BS_SIM_FCFG1_PFSIZE (4U) /*!< Bit field size in bits for SIM_FCFG1_PFSIZE. */
3720 /*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */
3721 #define BR_SIM_FCFG1_PFSIZE(x) (HW_SIM_FCFG1(x).B.PFSIZE)
3724 /*******************************************************************************
3725 * HW_SIM_FCFG2 - Flash Configuration Register 2
3726 ******************************************************************************/
3729 * @brief HW_SIM_FCFG2 - Flash Configuration Register 2 (RO)
3731 * Reset value: 0x7FFF0000U
3733 typedef union _hw_sim_fcfg2
3736 struct _hw_sim_fcfg2_bitfields
3738 uint32_t RESERVED0 : 16; /*!< [15:0] */
3739 uint32_t MAXADDR1 : 7; /*!< [22:16] Max address block 1 */
3740 uint32_t RESERVED1 : 1; /*!< [23] */
3741 uint32_t MAXADDR0 : 7; /*!< [30:24] Max address block 0 */
3742 uint32_t RESERVED2 : 1; /*!< [31] */
3747 * @name Constants and macros for entire SIM_FCFG2 register
3750 #define HW_SIM_FCFG2_ADDR(x) ((x) + 0x1050U)
3752 #define HW_SIM_FCFG2(x) (*(__I hw_sim_fcfg2_t *) HW_SIM_FCFG2_ADDR(x))
3753 #define HW_SIM_FCFG2_RD(x) (HW_SIM_FCFG2(x).U)
3757 * Constants & macros for individual SIM_FCFG2 bitfields
3761 * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
3763 * This field equals zero if there is only one program flash block, otherwise it
3764 * equals the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1
3765 * = 0x20 the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000.
3766 * This would be the MAXADDR1 value for a device with 512 KB program flash memory
3767 * across two flash blocks and no FlexNVM.
3770 #define BP_SIM_FCFG2_MAXADDR1 (16U) /*!< Bit position for SIM_FCFG2_MAXADDR1. */
3771 #define BM_SIM_FCFG2_MAXADDR1 (0x007F0000U) /*!< Bit mask for SIM_FCFG2_MAXADDR1. */
3772 #define BS_SIM_FCFG2_MAXADDR1 (7U) /*!< Bit field size in bits for SIM_FCFG2_MAXADDR1. */
3774 /*! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. */
3775 #define BR_SIM_FCFG2_MAXADDR1(x) (HW_SIM_FCFG2(x).B.MAXADDR1)
3779 * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
3781 * This field concatenated with 13 trailing zeros indicates the first invalid
3782 * address of each program flash block. For example, if MAXADDR0 = 0x20 the first
3783 * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
3784 * value for a device with 256 KB program flash in flash block 0.
3787 #define BP_SIM_FCFG2_MAXADDR0 (24U) /*!< Bit position for SIM_FCFG2_MAXADDR0. */
3788 #define BM_SIM_FCFG2_MAXADDR0 (0x7F000000U) /*!< Bit mask for SIM_FCFG2_MAXADDR0. */
3789 #define BS_SIM_FCFG2_MAXADDR0 (7U) /*!< Bit field size in bits for SIM_FCFG2_MAXADDR0. */
3791 /*! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. */
3792 #define BR_SIM_FCFG2_MAXADDR0(x) (HW_SIM_FCFG2(x).B.MAXADDR0)
3795 /*******************************************************************************
3796 * HW_SIM_UIDH - Unique Identification Register High
3797 ******************************************************************************/
3800 * @brief HW_SIM_UIDH - Unique Identification Register High (RO)
3802 * Reset value: 0x00000000U
3804 typedef union _hw_sim_uidh
3807 struct _hw_sim_uidh_bitfields
3809 uint32_t UID : 32; /*!< [31:0] Unique Identification */
3814 * @name Constants and macros for entire SIM_UIDH register
3817 #define HW_SIM_UIDH_ADDR(x) ((x) + 0x1054U)
3819 #define HW_SIM_UIDH(x) (*(__I hw_sim_uidh_t *) HW_SIM_UIDH_ADDR(x))
3820 #define HW_SIM_UIDH_RD(x) (HW_SIM_UIDH(x).U)
3824 * Constants & macros for individual SIM_UIDH bitfields
3828 * @name Register SIM_UIDH, field UID[31:0] (RO)
3830 * Unique identification for the device.
3833 #define BP_SIM_UIDH_UID (0U) /*!< Bit position for SIM_UIDH_UID. */
3834 #define BM_SIM_UIDH_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDH_UID. */
3835 #define BS_SIM_UIDH_UID (32U) /*!< Bit field size in bits for SIM_UIDH_UID. */
3837 /*! @brief Read current value of the SIM_UIDH_UID field. */
3838 #define BR_SIM_UIDH_UID(x) (HW_SIM_UIDH(x).U)
3841 /*******************************************************************************
3842 * HW_SIM_UIDMH - Unique Identification Register Mid-High
3843 ******************************************************************************/
3846 * @brief HW_SIM_UIDMH - Unique Identification Register Mid-High (RO)
3848 * Reset value: 0x00000000U
3850 typedef union _hw_sim_uidmh
3853 struct _hw_sim_uidmh_bitfields
3855 uint32_t UID : 32; /*!< [31:0] Unique Identification */
3860 * @name Constants and macros for entire SIM_UIDMH register
3863 #define HW_SIM_UIDMH_ADDR(x) ((x) + 0x1058U)
3865 #define HW_SIM_UIDMH(x) (*(__I hw_sim_uidmh_t *) HW_SIM_UIDMH_ADDR(x))
3866 #define HW_SIM_UIDMH_RD(x) (HW_SIM_UIDMH(x).U)
3870 * Constants & macros for individual SIM_UIDMH bitfields
3874 * @name Register SIM_UIDMH, field UID[31:0] (RO)
3876 * Unique identification for the device.
3879 #define BP_SIM_UIDMH_UID (0U) /*!< Bit position for SIM_UIDMH_UID. */
3880 #define BM_SIM_UIDMH_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDMH_UID. */
3881 #define BS_SIM_UIDMH_UID (32U) /*!< Bit field size in bits for SIM_UIDMH_UID. */
3883 /*! @brief Read current value of the SIM_UIDMH_UID field. */
3884 #define BR_SIM_UIDMH_UID(x) (HW_SIM_UIDMH(x).U)
3887 /*******************************************************************************
3888 * HW_SIM_UIDML - Unique Identification Register Mid Low
3889 ******************************************************************************/
3892 * @brief HW_SIM_UIDML - Unique Identification Register Mid Low (RO)
3894 * Reset value: 0x00000000U
3896 typedef union _hw_sim_uidml
3899 struct _hw_sim_uidml_bitfields
3901 uint32_t UID : 32; /*!< [31:0] Unique Identification */
3906 * @name Constants and macros for entire SIM_UIDML register
3909 #define HW_SIM_UIDML_ADDR(x) ((x) + 0x105CU)
3911 #define HW_SIM_UIDML(x) (*(__I hw_sim_uidml_t *) HW_SIM_UIDML_ADDR(x))
3912 #define HW_SIM_UIDML_RD(x) (HW_SIM_UIDML(x).U)
3916 * Constants & macros for individual SIM_UIDML bitfields
3920 * @name Register SIM_UIDML, field UID[31:0] (RO)
3922 * Unique identification for the device.
3925 #define BP_SIM_UIDML_UID (0U) /*!< Bit position for SIM_UIDML_UID. */
3926 #define BM_SIM_UIDML_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDML_UID. */
3927 #define BS_SIM_UIDML_UID (32U) /*!< Bit field size in bits for SIM_UIDML_UID. */
3929 /*! @brief Read current value of the SIM_UIDML_UID field. */
3930 #define BR_SIM_UIDML_UID(x) (HW_SIM_UIDML(x).U)
3933 /*******************************************************************************
3934 * HW_SIM_UIDL - Unique Identification Register Low
3935 ******************************************************************************/
3938 * @brief HW_SIM_UIDL - Unique Identification Register Low (RO)
3940 * Reset value: 0x00000000U
3942 typedef union _hw_sim_uidl
3945 struct _hw_sim_uidl_bitfields
3947 uint32_t UID : 32; /*!< [31:0] Unique Identification */
3952 * @name Constants and macros for entire SIM_UIDL register
3955 #define HW_SIM_UIDL_ADDR(x) ((x) + 0x1060U)
3957 #define HW_SIM_UIDL(x) (*(__I hw_sim_uidl_t *) HW_SIM_UIDL_ADDR(x))
3958 #define HW_SIM_UIDL_RD(x) (HW_SIM_UIDL(x).U)
3962 * Constants & macros for individual SIM_UIDL bitfields
3966 * @name Register SIM_UIDL, field UID[31:0] (RO)
3968 * Unique identification for the device.
3971 #define BP_SIM_UIDL_UID (0U) /*!< Bit position for SIM_UIDL_UID. */
3972 #define BM_SIM_UIDL_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDL_UID. */
3973 #define BS_SIM_UIDL_UID (32U) /*!< Bit field size in bits for SIM_UIDL_UID. */
3975 /*! @brief Read current value of the SIM_UIDL_UID field. */
3976 #define BR_SIM_UIDL_UID(x) (HW_SIM_UIDL(x).U)
3979 /*******************************************************************************
3980 * hw_sim_t - module struct
3981 ******************************************************************************/
3983 * @brief All SIM module registers.
3986 typedef struct _hw_sim
3988 __IO hw_sim_sopt1_t SOPT1; /*!< [0x0] System Options Register 1 */
3989 __IO hw_sim_sopt1cfg_t SOPT1CFG; /*!< [0x4] SOPT1 Configuration Register */
3990 uint8_t _reserved0[4092];
3991 __IO hw_sim_sopt2_t SOPT2; /*!< [0x1004] System Options Register 2 */
3992 uint8_t _reserved1[4];
3993 __IO hw_sim_sopt4_t SOPT4; /*!< [0x100C] System Options Register 4 */
3994 __IO hw_sim_sopt5_t SOPT5; /*!< [0x1010] System Options Register 5 */
3995 uint8_t _reserved2[4];
3996 __IO hw_sim_sopt7_t SOPT7; /*!< [0x1018] System Options Register 7 */
3997 __IO hw_sim_sopt8_t SOPT8; /*!< [0x101C] System Options Register 8 */
3998 uint8_t _reserved3[4];
3999 __I hw_sim_sdid_t SDID; /*!< [0x1024] System Device Identification Register */
4000 uint8_t _reserved4[12];
4001 __IO hw_sim_scgc4_t SCGC4; /*!< [0x1034] System Clock Gating Control Register 4 */
4002 __IO hw_sim_scgc5_t SCGC5; /*!< [0x1038] System Clock Gating Control Register 5 */
4003 __IO hw_sim_scgc6_t SCGC6; /*!< [0x103C] System Clock Gating Control Register 6 */
4004 __IO hw_sim_scgc7_t SCGC7; /*!< [0x1040] System Clock Gating Control Register 7 */
4005 __IO hw_sim_clkdiv1_t CLKDIV1; /*!< [0x1044] System Clock Divider Register 1 */
4006 __IO hw_sim_clkdiv2_t CLKDIV2; /*!< [0x1048] System Clock Divider Register 2 */
4007 __IO hw_sim_fcfg1_t FCFG1; /*!< [0x104C] Flash Configuration Register 1 */
4008 __I hw_sim_fcfg2_t FCFG2; /*!< [0x1050] Flash Configuration Register 2 */
4009 __I hw_sim_uidh_t UIDH; /*!< [0x1054] Unique Identification Register High */
4010 __I hw_sim_uidmh_t UIDMH; /*!< [0x1058] Unique Identification Register Mid-High */
4011 __I hw_sim_uidml_t UIDML; /*!< [0x105C] Unique Identification Register Mid Low */
4012 __I hw_sim_uidl_t UIDL; /*!< [0x1060] Unique Identification Register Low */
4016 /*! @brief Macro to access all SIM registers. */
4017 /*! @param x SIM module instance base address. */
4018 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
4019 * use the '&' operator, like <code>&HW_SIM(SIM_BASE)</code>. */
4020 #define HW_SIM(x) (*(hw_sim_t *)(x))
4022 #endif /* __HW_SIM_REGISTERS_H__ */