2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
9 ** Version: rev. 2.5, 2014-05-06
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-07-23)
49 ** - rev. 1.1 (2013-09-17)
50 ** RM rev. 0.4 update.
51 ** - rev. 2.0 (2013-10-29)
52 ** Register accessor macros added to the memory map.
53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
54 ** Startup file for gcc has been updated according to CMSIS 3.2.
55 ** System initialization updated.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-20)
59 ** Update according to reference manual rev. 0.6,
60 ** - rev. 2.3 (2014-01-13)
61 ** Update according to reference manual rev. 0.61,
62 ** - rev. 2.4 (2014-02-10)
63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
64 ** - rev. 2.5 (2014-05-06)
65 ** Update according to reference manual rev. 1.0,
66 ** Update of system and startup files.
67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
69 ** ###################################################################
73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
75 * This file was generated automatically and any changes may be lost.
77 #ifndef __HW_PORT_REGISTERS_H__
78 #define __HW_PORT_REGISTERS_H__
80 #include "MK22F51212.h"
81 #include "fsl_bitaccess.h"
86 * Pin Control and Interrupts
88 * Registers defined in this header file:
89 * - HW_PORT_PCRn - Pin Control Register n
90 * - HW_PORT_GPCLR - Global Pin Control Low Register
91 * - HW_PORT_GPCHR - Global Pin Control High Register
92 * - HW_PORT_ISFR - Interrupt Status Flag Register
93 * - HW_PORT_DFER - Digital Filter Enable Register
94 * - HW_PORT_DFCR - Digital Filter Clock Register
95 * - HW_PORT_DFWR - Digital Filter Width Register
97 * - hw_port_t - Struct containing all module registers.
100 #define HW_PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
101 #define HW_PORTA (0U) /*!< Instance number for PORTA. */
102 #define HW_PORTB (1U) /*!< Instance number for PORTB. */
103 #define HW_PORTC (2U) /*!< Instance number for PORTC. */
104 #define HW_PORTD (3U) /*!< Instance number for PORTD. */
105 #define HW_PORTE (4U) /*!< Instance number for PORTE. */
107 /*******************************************************************************
108 * HW_PORT_PCRn - Pin Control Register n
109 ******************************************************************************/
112 * @brief HW_PORT_PCRn - Pin Control Register n (RW)
114 * Reset value: 0x00000700U
116 * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
117 * this device. See the GPIO Configuration section for details on the available
118 * functions for each pin. Do not modify pin configuration registers associated
119 * with pins not available in your selected package. All unbonded pins not
120 * available in your package will default to DISABLE state for lowest power consumption.
122 typedef union _hw_port_pcrn
125 struct _hw_port_pcrn_bitfields
127 uint32_t PS : 1; /*!< [0] Pull Select */
128 uint32_t PE : 1; /*!< [1] Pull Enable */
129 uint32_t SRE : 1; /*!< [2] Slew Rate Enable */
130 uint32_t RESERVED0 : 1; /*!< [3] */
131 uint32_t PFE : 1; /*!< [4] Passive Filter Enable */
132 uint32_t ODE : 1; /*!< [5] Open Drain Enable */
133 uint32_t DSE : 1; /*!< [6] Drive Strength Enable */
134 uint32_t RESERVED1 : 1; /*!< [7] */
135 uint32_t MUX : 3; /*!< [10:8] Pin Mux Control */
136 uint32_t RESERVED2 : 4; /*!< [14:11] */
137 uint32_t LK : 1; /*!< [15] Lock Register */
138 uint32_t IRQC : 4; /*!< [19:16] Interrupt Configuration */
139 uint32_t RESERVED3 : 4; /*!< [23:20] */
140 uint32_t ISF : 1; /*!< [24] Interrupt Status Flag */
141 uint32_t RESERVED4 : 7; /*!< [31:25] */
146 * @name Constants and macros for entire PORT_PCRn register
149 #define HW_PORT_PCRn_COUNT (32U)
151 #define HW_PORT_PCRn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))
153 #define HW_PORT_PCRn(x, n) (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n))
154 #define HW_PORT_PCRn_RD(x, n) (HW_PORT_PCRn(x, n).U)
155 #define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v))
156 #define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) | (v)))
157 #define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v)))
158 #define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^ (v)))
162 * Constants & macros for individual PORT_PCRn bitfields
166 * @name Register PORT_PCRn, field PS[0] (RW)
168 * Pull configuration is valid in all digital pin muxing modes.
171 * - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
172 * corresponding PE field is set.
173 * - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
174 * corresponding PE field is set.
177 #define BP_PORT_PCRn_PS (0U) /*!< Bit position for PORT_PCRn_PS. */
178 #define BM_PORT_PCRn_PS (0x00000001U) /*!< Bit mask for PORT_PCRn_PS. */
179 #define BS_PORT_PCRn_PS (1U) /*!< Bit field size in bits for PORT_PCRn_PS. */
181 /*! @brief Read current value of the PORT_PCRn_PS field. */
182 #define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS))
184 /*! @brief Format value for bitfield PORT_PCRn_PS. */
185 #define BF_PORT_PCRn_PS(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PS) & BM_PORT_PCRn_PS)
187 /*! @brief Set the PS field to a new value. */
188 #define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v))
192 * @name Register PORT_PCRn, field PE[1] (RW)
194 * Pull configuration is valid in all digital pin muxing modes.
197 * - 0 - Internal pullup or pulldown resistor is not enabled on the
199 * - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
200 * pin, if the pin is configured as a digital input.
203 #define BP_PORT_PCRn_PE (1U) /*!< Bit position for PORT_PCRn_PE. */
204 #define BM_PORT_PCRn_PE (0x00000002U) /*!< Bit mask for PORT_PCRn_PE. */
205 #define BS_PORT_PCRn_PE (1U) /*!< Bit field size in bits for PORT_PCRn_PE. */
207 /*! @brief Read current value of the PORT_PCRn_PE field. */
208 #define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE))
210 /*! @brief Format value for bitfield PORT_PCRn_PE. */
211 #define BF_PORT_PCRn_PE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PE) & BM_PORT_PCRn_PE)
213 /*! @brief Set the PE field to a new value. */
214 #define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v))
218 * @name Register PORT_PCRn, field SRE[2] (RW)
220 * Slew rate configuration is valid in all digital pin muxing modes.
223 * - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
224 * configured as a digital output.
225 * - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
226 * configured as a digital output.
229 #define BP_PORT_PCRn_SRE (2U) /*!< Bit position for PORT_PCRn_SRE. */
230 #define BM_PORT_PCRn_SRE (0x00000004U) /*!< Bit mask for PORT_PCRn_SRE. */
231 #define BS_PORT_PCRn_SRE (1U) /*!< Bit field size in bits for PORT_PCRn_SRE. */
233 /*! @brief Read current value of the PORT_PCRn_SRE field. */
234 #define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE))
236 /*! @brief Format value for bitfield PORT_PCRn_SRE. */
237 #define BF_PORT_PCRn_SRE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_SRE) & BM_PORT_PCRn_SRE)
239 /*! @brief Set the SRE field to a new value. */
240 #define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v))
244 * @name Register PORT_PCRn, field PFE[4] (RW)
246 * Passive filter configuration is valid in all digital pin muxing modes.
249 * - 0 - Passive input filter is disabled on the corresponding pin.
250 * - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
251 * configured as a digital input. Refer to the device data sheet for filter
255 #define BP_PORT_PCRn_PFE (4U) /*!< Bit position for PORT_PCRn_PFE. */
256 #define BM_PORT_PCRn_PFE (0x00000010U) /*!< Bit mask for PORT_PCRn_PFE. */
257 #define BS_PORT_PCRn_PFE (1U) /*!< Bit field size in bits for PORT_PCRn_PFE. */
259 /*! @brief Read current value of the PORT_PCRn_PFE field. */
260 #define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE))
262 /*! @brief Format value for bitfield PORT_PCRn_PFE. */
263 #define BF_PORT_PCRn_PFE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PFE) & BM_PORT_PCRn_PFE)
265 /*! @brief Set the PFE field to a new value. */
266 #define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v))
270 * @name Register PORT_PCRn, field ODE[5] (RW)
272 * Open drain configuration is valid in all digital pin muxing modes.
275 * - 0 - Open drain output is disabled on the corresponding pin.
276 * - 1 - Open drain output is enabled on the corresponding pin, if the pin is
277 * configured as a digital output.
280 #define BP_PORT_PCRn_ODE (5U) /*!< Bit position for PORT_PCRn_ODE. */
281 #define BM_PORT_PCRn_ODE (0x00000020U) /*!< Bit mask for PORT_PCRn_ODE. */
282 #define BS_PORT_PCRn_ODE (1U) /*!< Bit field size in bits for PORT_PCRn_ODE. */
284 /*! @brief Read current value of the PORT_PCRn_ODE field. */
285 #define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE))
287 /*! @brief Format value for bitfield PORT_PCRn_ODE. */
288 #define BF_PORT_PCRn_ODE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ODE) & BM_PORT_PCRn_ODE)
290 /*! @brief Set the ODE field to a new value. */
291 #define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v))
295 * @name Register PORT_PCRn, field DSE[6] (RW)
297 * Drive strength configuration is valid in all digital pin muxing modes.
300 * - 0 - Low drive strength is configured on the corresponding pin, if pin is
301 * configured as a digital output.
302 * - 1 - High drive strength is configured on the corresponding pin, if pin is
303 * configured as a digital output.
306 #define BP_PORT_PCRn_DSE (6U) /*!< Bit position for PORT_PCRn_DSE. */
307 #define BM_PORT_PCRn_DSE (0x00000040U) /*!< Bit mask for PORT_PCRn_DSE. */
308 #define BS_PORT_PCRn_DSE (1U) /*!< Bit field size in bits for PORT_PCRn_DSE. */
310 /*! @brief Read current value of the PORT_PCRn_DSE field. */
311 #define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE))
313 /*! @brief Format value for bitfield PORT_PCRn_DSE. */
314 #define BF_PORT_PCRn_DSE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_DSE) & BM_PORT_PCRn_DSE)
316 /*! @brief Set the DSE field to a new value. */
317 #define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v))
321 * @name Register PORT_PCRn, field MUX[10:8] (RW)
323 * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
324 * reserved and may result in configuring the pin for a different pin muxing
325 * slot. The corresponding pin is configured in the following pin muxing slot as
329 * - 000 - Pin disabled (analog).
330 * - 001 - Alternative 1 (GPIO).
331 * - 010 - Alternative 2 (chip-specific).
332 * - 011 - Alternative 3 (chip-specific).
333 * - 100 - Alternative 4 (chip-specific).
334 * - 101 - Alternative 5 (chip-specific).
335 * - 110 - Alternative 6 (chip-specific).
336 * - 111 - Alternative 7 (chip-specific).
339 #define BP_PORT_PCRn_MUX (8U) /*!< Bit position for PORT_PCRn_MUX. */
340 #define BM_PORT_PCRn_MUX (0x00000700U) /*!< Bit mask for PORT_PCRn_MUX. */
341 #define BS_PORT_PCRn_MUX (3U) /*!< Bit field size in bits for PORT_PCRn_MUX. */
343 /*! @brief Read current value of the PORT_PCRn_MUX field. */
344 #define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX)
346 /*! @brief Format value for bitfield PORT_PCRn_MUX. */
347 #define BF_PORT_PCRn_MUX(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_MUX) & BM_PORT_PCRn_MUX)
349 /*! @brief Set the MUX field to a new value. */
350 #define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v)))
354 * @name Register PORT_PCRn, field LK[15] (RW)
357 * - 0 - Pin Control Register fields [15:0] are not locked.
358 * - 1 - Pin Control Register fields [15:0] are locked and cannot be updated
359 * until the next system reset.
362 #define BP_PORT_PCRn_LK (15U) /*!< Bit position for PORT_PCRn_LK. */
363 #define BM_PORT_PCRn_LK (0x00008000U) /*!< Bit mask for PORT_PCRn_LK. */
364 #define BS_PORT_PCRn_LK (1U) /*!< Bit field size in bits for PORT_PCRn_LK. */
366 /*! @brief Read current value of the PORT_PCRn_LK field. */
367 #define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK))
369 /*! @brief Format value for bitfield PORT_PCRn_LK. */
370 #define BF_PORT_PCRn_LK(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_LK) & BM_PORT_PCRn_LK)
372 /*! @brief Set the LK field to a new value. */
373 #define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v))
377 * @name Register PORT_PCRn, field IRQC[19:16] (RW)
379 * The pin interrupt configuration is valid in all digital pin muxing modes. The
380 * corresponding pin is configured to generate interrupt/DMA request as follows:
383 * - 0000 - Interrupt/DMA request disabled.
384 * - 0001 - DMA request on rising edge.
385 * - 0010 - DMA request on falling edge.
386 * - 0011 - DMA request on either edge.
387 * - 1000 - Interrupt when logic 0.
388 * - 1001 - Interrupt on rising-edge.
389 * - 1010 - Interrupt on falling-edge.
390 * - 1011 - Interrupt on either edge.
391 * - 1100 - Interrupt when logic 1.
394 #define BP_PORT_PCRn_IRQC (16U) /*!< Bit position for PORT_PCRn_IRQC. */
395 #define BM_PORT_PCRn_IRQC (0x000F0000U) /*!< Bit mask for PORT_PCRn_IRQC. */
396 #define BS_PORT_PCRn_IRQC (4U) /*!< Bit field size in bits for PORT_PCRn_IRQC. */
398 /*! @brief Read current value of the PORT_PCRn_IRQC field. */
399 #define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC)
401 /*! @brief Format value for bitfield PORT_PCRn_IRQC. */
402 #define BF_PORT_PCRn_IRQC(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_IRQC) & BM_PORT_PCRn_IRQC)
404 /*! @brief Set the IRQC field to a new value. */
405 #define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v)))
409 * @name Register PORT_PCRn, field ISF[24] (W1C)
411 * The pin interrupt configuration is valid in all digital pin muxing modes.
414 * - 0 - Configured interrupt is not detected.
415 * - 1 - Configured interrupt is detected. If the pin is configured to generate
416 * a DMA request, then the corresponding flag will be cleared automatically
417 * at the completion of the requested DMA transfer. Otherwise, the flag
418 * remains set until a logic 1 is written to the flag. If the pin is configured for
419 * a level sensitive interrupt and the pin remains asserted, then the flag
420 * is set again immediately after it is cleared.
423 #define BP_PORT_PCRn_ISF (24U) /*!< Bit position for PORT_PCRn_ISF. */
424 #define BM_PORT_PCRn_ISF (0x01000000U) /*!< Bit mask for PORT_PCRn_ISF. */
425 #define BS_PORT_PCRn_ISF (1U) /*!< Bit field size in bits for PORT_PCRn_ISF. */
427 /*! @brief Read current value of the PORT_PCRn_ISF field. */
428 #define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF))
430 /*! @brief Format value for bitfield PORT_PCRn_ISF. */
431 #define BF_PORT_PCRn_ISF(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ISF) & BM_PORT_PCRn_ISF)
433 /*! @brief Set the ISF field to a new value. */
434 #define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v))
437 /*******************************************************************************
438 * HW_PORT_GPCLR - Global Pin Control Low Register
439 ******************************************************************************/
442 * @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ)
444 * Reset value: 0x00000000U
446 * Only 32-bit writes are supported to this register.
448 typedef union _hw_port_gpclr
451 struct _hw_port_gpclr_bitfields
453 uint32_t GPWD : 16; /*!< [15:0] Global Pin Write Data */
454 uint32_t GPWE : 16; /*!< [31:16] Global Pin Write Enable */
459 * @name Constants and macros for entire PORT_GPCLR register
462 #define HW_PORT_GPCLR_ADDR(x) ((x) + 0x80U)
464 #define HW_PORT_GPCLR(x) (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x))
465 #define HW_PORT_GPCLR_RD(x) (HW_PORT_GPCLR(x).U)
466 #define HW_PORT_GPCLR_WR(x, v) (HW_PORT_GPCLR(x).U = (v))
470 * Constants & macros for individual PORT_GPCLR bitfields
474 * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
476 * Write value that is written to all Pin Control Registers bits [15:0] that are
480 #define BP_PORT_GPCLR_GPWD (0U) /*!< Bit position for PORT_GPCLR_GPWD. */
481 #define BM_PORT_GPCLR_GPWD (0x0000FFFFU) /*!< Bit mask for PORT_GPCLR_GPWD. */
482 #define BS_PORT_GPCLR_GPWD (16U) /*!< Bit field size in bits for PORT_GPCLR_GPWD. */
484 /*! @brief Format value for bitfield PORT_GPCLR_GPWD. */
485 #define BF_PORT_GPCLR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWD) & BM_PORT_GPCLR_GPWD)
487 /*! @brief Set the GPWD field to a new value. */
488 #define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v)))
492 * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
494 * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
495 * the value in GPWD. If a selected Pin Control Register is locked then the write
496 * to that register is ignored.
499 * - 0 - Corresponding Pin Control Register is not updated with the value in
501 * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
504 #define BP_PORT_GPCLR_GPWE (16U) /*!< Bit position for PORT_GPCLR_GPWE. */
505 #define BM_PORT_GPCLR_GPWE (0xFFFF0000U) /*!< Bit mask for PORT_GPCLR_GPWE. */
506 #define BS_PORT_GPCLR_GPWE (16U) /*!< Bit field size in bits for PORT_GPCLR_GPWE. */
508 /*! @brief Format value for bitfield PORT_GPCLR_GPWE. */
509 #define BF_PORT_GPCLR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWE) & BM_PORT_GPCLR_GPWE)
511 /*! @brief Set the GPWE field to a new value. */
512 #define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v)))
515 /*******************************************************************************
516 * HW_PORT_GPCHR - Global Pin Control High Register
517 ******************************************************************************/
520 * @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ)
522 * Reset value: 0x00000000U
524 * Only 32-bit writes are supported to this register.
526 typedef union _hw_port_gpchr
529 struct _hw_port_gpchr_bitfields
531 uint32_t GPWD : 16; /*!< [15:0] Global Pin Write Data */
532 uint32_t GPWE : 16; /*!< [31:16] Global Pin Write Enable */
537 * @name Constants and macros for entire PORT_GPCHR register
540 #define HW_PORT_GPCHR_ADDR(x) ((x) + 0x84U)
542 #define HW_PORT_GPCHR(x) (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x))
543 #define HW_PORT_GPCHR_RD(x) (HW_PORT_GPCHR(x).U)
544 #define HW_PORT_GPCHR_WR(x, v) (HW_PORT_GPCHR(x).U = (v))
548 * Constants & macros for individual PORT_GPCHR bitfields
552 * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
554 * Write value that is written to all Pin Control Registers bits [15:0] that are
558 #define BP_PORT_GPCHR_GPWD (0U) /*!< Bit position for PORT_GPCHR_GPWD. */
559 #define BM_PORT_GPCHR_GPWD (0x0000FFFFU) /*!< Bit mask for PORT_GPCHR_GPWD. */
560 #define BS_PORT_GPCHR_GPWD (16U) /*!< Bit field size in bits for PORT_GPCHR_GPWD. */
562 /*! @brief Format value for bitfield PORT_GPCHR_GPWD. */
563 #define BF_PORT_GPCHR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWD) & BM_PORT_GPCHR_GPWD)
565 /*! @brief Set the GPWD field to a new value. */
566 #define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v)))
570 * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
572 * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
573 * the value in GPWD. If a selected Pin Control Register is locked then the write
574 * to that register is ignored.
577 * - 0 - Corresponding Pin Control Register is not updated with the value in
579 * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
582 #define BP_PORT_GPCHR_GPWE (16U) /*!< Bit position for PORT_GPCHR_GPWE. */
583 #define BM_PORT_GPCHR_GPWE (0xFFFF0000U) /*!< Bit mask for PORT_GPCHR_GPWE. */
584 #define BS_PORT_GPCHR_GPWE (16U) /*!< Bit field size in bits for PORT_GPCHR_GPWE. */
586 /*! @brief Format value for bitfield PORT_GPCHR_GPWE. */
587 #define BF_PORT_GPCHR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWE) & BM_PORT_GPCHR_GPWE)
589 /*! @brief Set the GPWE field to a new value. */
590 #define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v)))
593 /*******************************************************************************
594 * HW_PORT_ISFR - Interrupt Status Flag Register
595 ******************************************************************************/
598 * @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C)
600 * Reset value: 0x00000000U
602 * The pin interrupt configuration is valid in all digital pin muxing modes. The
603 * Interrupt Status Flag for each pin is also visible in the corresponding Pin
604 * Control Register, and each flag can be cleared in either location.
606 typedef union _hw_port_isfr
609 struct _hw_port_isfr_bitfields
611 uint32_t ISF : 32; /*!< [31:0] Interrupt Status Flag */
616 * @name Constants and macros for entire PORT_ISFR register
619 #define HW_PORT_ISFR_ADDR(x) ((x) + 0xA0U)
621 #define HW_PORT_ISFR(x) (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x))
622 #define HW_PORT_ISFR_RD(x) (HW_PORT_ISFR(x).U)
623 #define HW_PORT_ISFR_WR(x, v) (HW_PORT_ISFR(x).U = (v))
624 #define HW_PORT_ISFR_SET(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) | (v)))
625 #define HW_PORT_ISFR_CLR(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v)))
626 #define HW_PORT_ISFR_TOG(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^ (v)))
630 * Constants & macros for individual PORT_ISFR bitfields
634 * @name Register PORT_ISFR, field ISF[31:0] (W1C)
636 * Each bit in the field indicates the detection of the configured interrupt of
637 * the same number as the field.
640 * - 0 - Configured interrupt is not detected.
641 * - 1 - Configured interrupt is detected. If the pin is configured to generate
642 * a DMA request, then the corresponding flag will be cleared automatically
643 * at the completion of the requested DMA transfer. Otherwise, the flag
644 * remains set until a logic 1 is written to the flag. If the pin is configured for
645 * a level sensitive interrupt and the pin remains asserted, then the flag
646 * is set again immediately after it is cleared.
649 #define BP_PORT_ISFR_ISF (0U) /*!< Bit position for PORT_ISFR_ISF. */
650 #define BM_PORT_ISFR_ISF (0xFFFFFFFFU) /*!< Bit mask for PORT_ISFR_ISF. */
651 #define BS_PORT_ISFR_ISF (32U) /*!< Bit field size in bits for PORT_ISFR_ISF. */
653 /*! @brief Read current value of the PORT_ISFR_ISF field. */
654 #define BR_PORT_ISFR_ISF(x) (HW_PORT_ISFR(x).U)
656 /*! @brief Format value for bitfield PORT_ISFR_ISF. */
657 #define BF_PORT_ISFR_ISF(v) ((uint32_t)((uint32_t)(v) << BP_PORT_ISFR_ISF) & BM_PORT_ISFR_ISF)
659 /*! @brief Set the ISF field to a new value. */
660 #define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v))
663 /*******************************************************************************
664 * HW_PORT_DFER - Digital Filter Enable Register
665 ******************************************************************************/
668 * @brief HW_PORT_DFER - Digital Filter Enable Register (RW)
670 * Reset value: 0x00000000U
672 * The corresponding bit is read only for pins that do not support a digital
673 * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
674 * the pins that support digital filter. The digital filter configuration is valid
675 * in all digital pin muxing modes.
677 typedef union _hw_port_dfer
680 struct _hw_port_dfer_bitfields
682 uint32_t DFE : 32; /*!< [31:0] Digital Filter Enable */
687 * @name Constants and macros for entire PORT_DFER register
690 #define HW_PORT_DFER_ADDR(x) ((x) + 0xC0U)
692 #define HW_PORT_DFER(x) (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x))
693 #define HW_PORT_DFER_RD(x) (HW_PORT_DFER(x).U)
694 #define HW_PORT_DFER_WR(x, v) (HW_PORT_DFER(x).U = (v))
695 #define HW_PORT_DFER_SET(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) | (v)))
696 #define HW_PORT_DFER_CLR(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v)))
697 #define HW_PORT_DFER_TOG(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^ (v)))
701 * Constants & macros for individual PORT_DFER bitfields
705 * @name Register PORT_DFER, field DFE[31:0] (RW)
707 * The digital filter configuration is valid in all digital pin muxing modes.
708 * The output of each digital filter is reset to zero at system reset and whenever
709 * the digital filter is disabled. Each bit in the field enables the digital
710 * filter of the same number as the field.
713 * - 0 - Digital filter is disabled on the corresponding pin and output of the
714 * digital filter is reset to zero.
715 * - 1 - Digital filter is enabled on the corresponding pin, if the pin is
716 * configured as a digital input.
719 #define BP_PORT_DFER_DFE (0U) /*!< Bit position for PORT_DFER_DFE. */
720 #define BM_PORT_DFER_DFE (0xFFFFFFFFU) /*!< Bit mask for PORT_DFER_DFE. */
721 #define BS_PORT_DFER_DFE (32U) /*!< Bit field size in bits for PORT_DFER_DFE. */
723 /*! @brief Read current value of the PORT_DFER_DFE field. */
724 #define BR_PORT_DFER_DFE(x) (HW_PORT_DFER(x).U)
726 /*! @brief Format value for bitfield PORT_DFER_DFE. */
727 #define BF_PORT_DFER_DFE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFER_DFE) & BM_PORT_DFER_DFE)
729 /*! @brief Set the DFE field to a new value. */
730 #define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v))
733 /*******************************************************************************
734 * HW_PORT_DFCR - Digital Filter Clock Register
735 ******************************************************************************/
738 * @brief HW_PORT_DFCR - Digital Filter Clock Register (RW)
740 * Reset value: 0x00000000U
742 * This register is read only for ports that do not support a digital filter.
743 * The digital filter configuration is valid in all digital pin muxing modes.
745 typedef union _hw_port_dfcr
748 struct _hw_port_dfcr_bitfields
750 uint32_t CS : 1; /*!< [0] Clock Source */
751 uint32_t RESERVED0 : 31; /*!< [31:1] */
756 * @name Constants and macros for entire PORT_DFCR register
759 #define HW_PORT_DFCR_ADDR(x) ((x) + 0xC4U)
761 #define HW_PORT_DFCR(x) (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x))
762 #define HW_PORT_DFCR_RD(x) (HW_PORT_DFCR(x).U)
763 #define HW_PORT_DFCR_WR(x, v) (HW_PORT_DFCR(x).U = (v))
764 #define HW_PORT_DFCR_SET(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) | (v)))
765 #define HW_PORT_DFCR_CLR(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v)))
766 #define HW_PORT_DFCR_TOG(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^ (v)))
770 * Constants & macros for individual PORT_DFCR bitfields
774 * @name Register PORT_DFCR, field CS[0] (RW)
776 * The digital filter configuration is valid in all digital pin muxing modes.
777 * Configures the clock source for the digital input filters. Changing the filter
778 * clock source must be done only when all digital filters are disabled.
781 * - 0 - Digital filters are clocked by the bus clock.
782 * - 1 - Digital filters are clocked by the 1 kHz LPO clock.
785 #define BP_PORT_DFCR_CS (0U) /*!< Bit position for PORT_DFCR_CS. */
786 #define BM_PORT_DFCR_CS (0x00000001U) /*!< Bit mask for PORT_DFCR_CS. */
787 #define BS_PORT_DFCR_CS (1U) /*!< Bit field size in bits for PORT_DFCR_CS. */
789 /*! @brief Read current value of the PORT_DFCR_CS field. */
790 #define BR_PORT_DFCR_CS(x) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS))
792 /*! @brief Format value for bitfield PORT_DFCR_CS. */
793 #define BF_PORT_DFCR_CS(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFCR_CS) & BM_PORT_DFCR_CS)
795 /*! @brief Set the CS field to a new value. */
796 #define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v))
799 /*******************************************************************************
800 * HW_PORT_DFWR - Digital Filter Width Register
801 ******************************************************************************/
804 * @brief HW_PORT_DFWR - Digital Filter Width Register (RW)
806 * Reset value: 0x00000000U
808 * This register is read only for ports that do not support a digital filter.
809 * The digital filter configuration is valid in all digital pin muxing modes.
811 typedef union _hw_port_dfwr
814 struct _hw_port_dfwr_bitfields
816 uint32_t FILT : 5; /*!< [4:0] Filter Length */
817 uint32_t RESERVED0 : 27; /*!< [31:5] */
822 * @name Constants and macros for entire PORT_DFWR register
825 #define HW_PORT_DFWR_ADDR(x) ((x) + 0xC8U)
827 #define HW_PORT_DFWR(x) (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x))
828 #define HW_PORT_DFWR_RD(x) (HW_PORT_DFWR(x).U)
829 #define HW_PORT_DFWR_WR(x, v) (HW_PORT_DFWR(x).U = (v))
830 #define HW_PORT_DFWR_SET(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) | (v)))
831 #define HW_PORT_DFWR_CLR(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v)))
832 #define HW_PORT_DFWR_TOG(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^ (v)))
836 * Constants & macros for individual PORT_DFWR bitfields
840 * @name Register PORT_DFWR, field FILT[4:0] (RW)
842 * The digital filter configuration is valid in all digital pin muxing modes.
843 * Configures the maximum size of the glitches, in clock cycles, that the digital
844 * filter absorbs for the enabled digital filters. Glitches that are longer than
845 * this register setting will pass through the digital filter, and glitches that
846 * are equal to or less than this register setting are filtered. Changing the
847 * filter length must be done only after all filters are disabled.
850 #define BP_PORT_DFWR_FILT (0U) /*!< Bit position for PORT_DFWR_FILT. */
851 #define BM_PORT_DFWR_FILT (0x0000001FU) /*!< Bit mask for PORT_DFWR_FILT. */
852 #define BS_PORT_DFWR_FILT (5U) /*!< Bit field size in bits for PORT_DFWR_FILT. */
854 /*! @brief Read current value of the PORT_DFWR_FILT field. */
855 #define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT)
857 /*! @brief Format value for bitfield PORT_DFWR_FILT. */
858 #define BF_PORT_DFWR_FILT(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFWR_FILT) & BM_PORT_DFWR_FILT)
860 /*! @brief Set the FILT field to a new value. */
861 #define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v)))
864 /*******************************************************************************
865 * hw_port_t - module struct
866 ******************************************************************************/
868 * @brief All PORT module registers.
871 typedef struct _hw_port
873 __IO hw_port_pcrn_t PCRn[32]; /*!< [0x0] Pin Control Register n */
874 __O hw_port_gpclr_t GPCLR; /*!< [0x80] Global Pin Control Low Register */
875 __O hw_port_gpchr_t GPCHR; /*!< [0x84] Global Pin Control High Register */
876 uint8_t _reserved0[24];
877 __IO hw_port_isfr_t ISFR; /*!< [0xA0] Interrupt Status Flag Register */
878 uint8_t _reserved1[28];
879 __IO hw_port_dfer_t DFER; /*!< [0xC0] Digital Filter Enable Register */
880 __IO hw_port_dfcr_t DFCR; /*!< [0xC4] Digital Filter Clock Register */
881 __IO hw_port_dfwr_t DFWR; /*!< [0xC8] Digital Filter Width Register */
885 /*! @brief Macro to access all PORT registers. */
886 /*! @param x PORT module instance base address. */
887 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
888 * use the '&' operator, like <code>&HW_PORT(PORTA_BASE)</code>. */
889 #define HW_PORT(x) (*(hw_port_t *)(x))
891 #endif /* __HW_PORT_REGISTERS_H__ */