2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
9 ** Version: rev. 2.5, 2014-05-06
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-07-23)
49 ** - rev. 1.1 (2013-09-17)
50 ** RM rev. 0.4 update.
51 ** - rev. 2.0 (2013-10-29)
52 ** Register accessor macros added to the memory map.
53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
54 ** Startup file for gcc has been updated according to CMSIS 3.2.
55 ** System initialization updated.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-20)
59 ** Update according to reference manual rev. 0.6,
60 ** - rev. 2.3 (2014-01-13)
61 ** Update according to reference manual rev. 0.61,
62 ** - rev. 2.4 (2014-02-10)
63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
64 ** - rev. 2.5 (2014-05-06)
65 ** Update according to reference manual rev. 1.0,
66 ** Update of system and startup files.
67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
69 ** ###################################################################
73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
75 * This file was generated automatically and any changes may be lost.
77 #ifndef __HW_PIT_REGISTERS_H__
78 #define __HW_PIT_REGISTERS_H__
80 #include "MK22F51212.h"
81 #include "fsl_bitaccess.h"
86 * Periodic Interrupt Timer
88 * Registers defined in this header file:
89 * - HW_PIT_MCR - PIT Module Control Register
90 * - HW_PIT_LDVALn - Timer Load Value Register
91 * - HW_PIT_CVALn - Current Timer Value Register
92 * - HW_PIT_TCTRLn - Timer Control Register
93 * - HW_PIT_TFLGn - Timer Flag Register
95 * - hw_pit_t - Struct containing all module registers.
98 #define HW_PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */
100 /*******************************************************************************
101 * HW_PIT_MCR - PIT Module Control Register
102 ******************************************************************************/
105 * @brief HW_PIT_MCR - PIT Module Control Register (RW)
107 * Reset value: 0x00000006U
109 * This register enables or disables the PIT timer clocks and controls the
110 * timers when the PIT enters the Debug mode.
112 typedef union _hw_pit_mcr
115 struct _hw_pit_mcr_bitfields
117 uint32_t FRZ : 1; /*!< [0] Freeze */
118 uint32_t MDIS : 1; /*!< [1] Module Disable - (PIT section) */
119 uint32_t RESERVED0 : 30; /*!< [31:2] */
124 * @name Constants and macros for entire PIT_MCR register
127 #define HW_PIT_MCR_ADDR(x) ((x) + 0x0U)
129 #define HW_PIT_MCR(x) (*(__IO hw_pit_mcr_t *) HW_PIT_MCR_ADDR(x))
130 #define HW_PIT_MCR_RD(x) (HW_PIT_MCR(x).U)
131 #define HW_PIT_MCR_WR(x, v) (HW_PIT_MCR(x).U = (v))
132 #define HW_PIT_MCR_SET(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) | (v)))
133 #define HW_PIT_MCR_CLR(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) & ~(v)))
134 #define HW_PIT_MCR_TOG(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) ^ (v)))
138 * Constants & macros for individual PIT_MCR bitfields
142 * @name Register PIT_MCR, field FRZ[0] (RW)
144 * Allows the timers to be stopped when the device enters the Debug mode.
147 * - 0 - Timers continue to run in Debug mode.
148 * - 1 - Timers are stopped in Debug mode.
151 #define BP_PIT_MCR_FRZ (0U) /*!< Bit position for PIT_MCR_FRZ. */
152 #define BM_PIT_MCR_FRZ (0x00000001U) /*!< Bit mask for PIT_MCR_FRZ. */
153 #define BS_PIT_MCR_FRZ (1U) /*!< Bit field size in bits for PIT_MCR_FRZ. */
155 /*! @brief Read current value of the PIT_MCR_FRZ field. */
156 #define BR_PIT_MCR_FRZ(x) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ))
158 /*! @brief Format value for bitfield PIT_MCR_FRZ. */
159 #define BF_PIT_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_FRZ) & BM_PIT_MCR_FRZ)
161 /*! @brief Set the FRZ field to a new value. */
162 #define BW_PIT_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ) = (v))
166 * @name Register PIT_MCR, field MDIS[1] (RW)
168 * Disables the standard timers. This field must be enabled before any other
172 * - 0 - Clock for standard PIT timers is enabled.
173 * - 1 - Clock for standard PIT timers is disabled.
176 #define BP_PIT_MCR_MDIS (1U) /*!< Bit position for PIT_MCR_MDIS. */
177 #define BM_PIT_MCR_MDIS (0x00000002U) /*!< Bit mask for PIT_MCR_MDIS. */
178 #define BS_PIT_MCR_MDIS (1U) /*!< Bit field size in bits for PIT_MCR_MDIS. */
180 /*! @brief Read current value of the PIT_MCR_MDIS field. */
181 #define BR_PIT_MCR_MDIS(x) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS))
183 /*! @brief Format value for bitfield PIT_MCR_MDIS. */
184 #define BF_PIT_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_MDIS) & BM_PIT_MCR_MDIS)
186 /*! @brief Set the MDIS field to a new value. */
187 #define BW_PIT_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS) = (v))
190 /*******************************************************************************
191 * HW_PIT_LDVALn - Timer Load Value Register
192 ******************************************************************************/
195 * @brief HW_PIT_LDVALn - Timer Load Value Register (RW)
197 * Reset value: 0x00000000U
199 * These registers select the timeout period for the timer interrupts.
201 typedef union _hw_pit_ldvaln
204 struct _hw_pit_ldvaln_bitfields
206 uint32_t TSV : 32; /*!< [31:0] Timer Start Value */
211 * @name Constants and macros for entire PIT_LDVALn register
214 #define HW_PIT_LDVALn_COUNT (4U)
216 #define HW_PIT_LDVALn_ADDR(x, n) ((x) + 0x100U + (0x10U * (n)))
218 #define HW_PIT_LDVALn(x, n) (*(__IO hw_pit_ldvaln_t *) HW_PIT_LDVALn_ADDR(x, n))
219 #define HW_PIT_LDVALn_RD(x, n) (HW_PIT_LDVALn(x, n).U)
220 #define HW_PIT_LDVALn_WR(x, n, v) (HW_PIT_LDVALn(x, n).U = (v))
221 #define HW_PIT_LDVALn_SET(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) | (v)))
222 #define HW_PIT_LDVALn_CLR(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) & ~(v)))
223 #define HW_PIT_LDVALn_TOG(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) ^ (v)))
227 * Constants & macros for individual PIT_LDVALn bitfields
231 * @name Register PIT_LDVALn, field TSV[31:0] (RW)
233 * Sets the timer start value. The timer will count down until it reaches 0,
234 * then it will generate an interrupt and load this register value again. Writing a
235 * new value to this register will not restart the timer; instead the value will
236 * be loaded after the timer expires. To abort the current cycle and start a
237 * timer period with the new value, the timer must be disabled and enabled again.
240 #define BP_PIT_LDVALn_TSV (0U) /*!< Bit position for PIT_LDVALn_TSV. */
241 #define BM_PIT_LDVALn_TSV (0xFFFFFFFFU) /*!< Bit mask for PIT_LDVALn_TSV. */
242 #define BS_PIT_LDVALn_TSV (32U) /*!< Bit field size in bits for PIT_LDVALn_TSV. */
244 /*! @brief Read current value of the PIT_LDVALn_TSV field. */
245 #define BR_PIT_LDVALn_TSV(x, n) (HW_PIT_LDVALn(x, n).U)
247 /*! @brief Format value for bitfield PIT_LDVALn_TSV. */
248 #define BF_PIT_LDVALn_TSV(v) ((uint32_t)((uint32_t)(v) << BP_PIT_LDVALn_TSV) & BM_PIT_LDVALn_TSV)
250 /*! @brief Set the TSV field to a new value. */
251 #define BW_PIT_LDVALn_TSV(x, n, v) (HW_PIT_LDVALn_WR(x, n, v))
253 /*******************************************************************************
254 * HW_PIT_CVALn - Current Timer Value Register
255 ******************************************************************************/
258 * @brief HW_PIT_CVALn - Current Timer Value Register (RO)
260 * Reset value: 0x00000000U
262 * These registers indicate the current timer position.
264 typedef union _hw_pit_cvaln
267 struct _hw_pit_cvaln_bitfields
269 uint32_t TVL : 32; /*!< [31:0] Current Timer Value */
274 * @name Constants and macros for entire PIT_CVALn register
277 #define HW_PIT_CVALn_COUNT (4U)
279 #define HW_PIT_CVALn_ADDR(x, n) ((x) + 0x104U + (0x10U * (n)))
281 #define HW_PIT_CVALn(x, n) (*(__I hw_pit_cvaln_t *) HW_PIT_CVALn_ADDR(x, n))
282 #define HW_PIT_CVALn_RD(x, n) (HW_PIT_CVALn(x, n).U)
286 * Constants & macros for individual PIT_CVALn bitfields
290 * @name Register PIT_CVALn, field TVL[31:0] (RO)
292 * Represents the current timer value, if the timer is enabled. If the timer is
293 * disabled, do not use this field as its value is unreliable. The timer uses a
294 * downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set.
297 #define BP_PIT_CVALn_TVL (0U) /*!< Bit position for PIT_CVALn_TVL. */
298 #define BM_PIT_CVALn_TVL (0xFFFFFFFFU) /*!< Bit mask for PIT_CVALn_TVL. */
299 #define BS_PIT_CVALn_TVL (32U) /*!< Bit field size in bits for PIT_CVALn_TVL. */
301 /*! @brief Read current value of the PIT_CVALn_TVL field. */
302 #define BR_PIT_CVALn_TVL(x, n) (HW_PIT_CVALn(x, n).U)
304 /*******************************************************************************
305 * HW_PIT_TCTRLn - Timer Control Register
306 ******************************************************************************/
309 * @brief HW_PIT_TCTRLn - Timer Control Register (RW)
311 * Reset value: 0x00000000U
313 * These registers contain the control bits for each timer.
315 typedef union _hw_pit_tctrln
318 struct _hw_pit_tctrln_bitfields
320 uint32_t TEN : 1; /*!< [0] Timer Enable */
321 uint32_t TIE : 1; /*!< [1] Timer Interrupt Enable */
322 uint32_t CHN : 1; /*!< [2] Chain Mode */
323 uint32_t RESERVED0 : 29; /*!< [31:3] */
328 * @name Constants and macros for entire PIT_TCTRLn register
331 #define HW_PIT_TCTRLn_COUNT (4U)
333 #define HW_PIT_TCTRLn_ADDR(x, n) ((x) + 0x108U + (0x10U * (n)))
335 #define HW_PIT_TCTRLn(x, n) (*(__IO hw_pit_tctrln_t *) HW_PIT_TCTRLn_ADDR(x, n))
336 #define HW_PIT_TCTRLn_RD(x, n) (HW_PIT_TCTRLn(x, n).U)
337 #define HW_PIT_TCTRLn_WR(x, n, v) (HW_PIT_TCTRLn(x, n).U = (v))
338 #define HW_PIT_TCTRLn_SET(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) | (v)))
339 #define HW_PIT_TCTRLn_CLR(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) & ~(v)))
340 #define HW_PIT_TCTRLn_TOG(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) ^ (v)))
344 * Constants & macros for individual PIT_TCTRLn bitfields
348 * @name Register PIT_TCTRLn, field TEN[0] (RW)
350 * Enables or disables the timer.
353 * - 0 - Timer n is disabled.
354 * - 1 - Timer n is enabled.
357 #define BP_PIT_TCTRLn_TEN (0U) /*!< Bit position for PIT_TCTRLn_TEN. */
358 #define BM_PIT_TCTRLn_TEN (0x00000001U) /*!< Bit mask for PIT_TCTRLn_TEN. */
359 #define BS_PIT_TCTRLn_TEN (1U) /*!< Bit field size in bits for PIT_TCTRLn_TEN. */
361 /*! @brief Read current value of the PIT_TCTRLn_TEN field. */
362 #define BR_PIT_TCTRLn_TEN(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN))
364 /*! @brief Format value for bitfield PIT_TCTRLn_TEN. */
365 #define BF_PIT_TCTRLn_TEN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TEN) & BM_PIT_TCTRLn_TEN)
367 /*! @brief Set the TEN field to a new value. */
368 #define BW_PIT_TCTRLn_TEN(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN) = (v))
372 * @name Register PIT_TCTRLn, field TIE[1] (RW)
374 * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
375 * will immediately cause an interrupt event. To avoid this, the associated
376 * TFLGn[TIF] must be cleared first.
379 * - 0 - Interrupt requests from Timer n are disabled.
380 * - 1 - Interrupt will be requested whenever TIF is set.
383 #define BP_PIT_TCTRLn_TIE (1U) /*!< Bit position for PIT_TCTRLn_TIE. */
384 #define BM_PIT_TCTRLn_TIE (0x00000002U) /*!< Bit mask for PIT_TCTRLn_TIE. */
385 #define BS_PIT_TCTRLn_TIE (1U) /*!< Bit field size in bits for PIT_TCTRLn_TIE. */
387 /*! @brief Read current value of the PIT_TCTRLn_TIE field. */
388 #define BR_PIT_TCTRLn_TIE(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE))
390 /*! @brief Format value for bitfield PIT_TCTRLn_TIE. */
391 #define BF_PIT_TCTRLn_TIE(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TIE) & BM_PIT_TCTRLn_TIE)
393 /*! @brief Set the TIE field to a new value. */
394 #define BW_PIT_TCTRLn_TIE(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE) = (v))
398 * @name Register PIT_TCTRLn, field CHN[2] (RW)
400 * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
401 * Timer 0 cannot be chained.
404 * - 0 - Timer is not chained.
405 * - 1 - Timer is chained to previous timer. For example, for Channel 2, if this
406 * field is set, Timer 2 is chained to Timer 1.
409 #define BP_PIT_TCTRLn_CHN (2U) /*!< Bit position for PIT_TCTRLn_CHN. */
410 #define BM_PIT_TCTRLn_CHN (0x00000004U) /*!< Bit mask for PIT_TCTRLn_CHN. */
411 #define BS_PIT_TCTRLn_CHN (1U) /*!< Bit field size in bits for PIT_TCTRLn_CHN. */
413 /*! @brief Read current value of the PIT_TCTRLn_CHN field. */
414 #define BR_PIT_TCTRLn_CHN(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN))
416 /*! @brief Format value for bitfield PIT_TCTRLn_CHN. */
417 #define BF_PIT_TCTRLn_CHN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_CHN) & BM_PIT_TCTRLn_CHN)
419 /*! @brief Set the CHN field to a new value. */
420 #define BW_PIT_TCTRLn_CHN(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN) = (v))
422 /*******************************************************************************
423 * HW_PIT_TFLGn - Timer Flag Register
424 ******************************************************************************/
427 * @brief HW_PIT_TFLGn - Timer Flag Register (RW)
429 * Reset value: 0x00000000U
431 * These registers hold the PIT interrupt flags.
433 typedef union _hw_pit_tflgn
436 struct _hw_pit_tflgn_bitfields
438 uint32_t TIF : 1; /*!< [0] Timer Interrupt Flag */
439 uint32_t RESERVED0 : 31; /*!< [31:1] */
444 * @name Constants and macros for entire PIT_TFLGn register
447 #define HW_PIT_TFLGn_COUNT (4U)
449 #define HW_PIT_TFLGn_ADDR(x, n) ((x) + 0x10CU + (0x10U * (n)))
451 #define HW_PIT_TFLGn(x, n) (*(__IO hw_pit_tflgn_t *) HW_PIT_TFLGn_ADDR(x, n))
452 #define HW_PIT_TFLGn_RD(x, n) (HW_PIT_TFLGn(x, n).U)
453 #define HW_PIT_TFLGn_WR(x, n, v) (HW_PIT_TFLGn(x, n).U = (v))
454 #define HW_PIT_TFLGn_SET(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) | (v)))
455 #define HW_PIT_TFLGn_CLR(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) & ~(v)))
456 #define HW_PIT_TFLGn_TOG(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) ^ (v)))
460 * Constants & macros for individual PIT_TFLGn bitfields
464 * @name Register PIT_TFLGn, field TIF[0] (W1C)
466 * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
467 * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
471 * - 0 - Timeout has not yet occurred.
472 * - 1 - Timeout has occurred.
475 #define BP_PIT_TFLGn_TIF (0U) /*!< Bit position for PIT_TFLGn_TIF. */
476 #define BM_PIT_TFLGn_TIF (0x00000001U) /*!< Bit mask for PIT_TFLGn_TIF. */
477 #define BS_PIT_TFLGn_TIF (1U) /*!< Bit field size in bits for PIT_TFLGn_TIF. */
479 /*! @brief Read current value of the PIT_TFLGn_TIF field. */
480 #define BR_PIT_TFLGn_TIF(x, n) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF))
482 /*! @brief Format value for bitfield PIT_TFLGn_TIF. */
483 #define BF_PIT_TFLGn_TIF(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TFLGn_TIF) & BM_PIT_TFLGn_TIF)
485 /*! @brief Set the TIF field to a new value. */
486 #define BW_PIT_TFLGn_TIF(x, n, v) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF) = (v))
489 /*******************************************************************************
490 * hw_pit_t - module struct
491 ******************************************************************************/
493 * @brief All PIT module registers.
496 typedef struct _hw_pit
498 __IO hw_pit_mcr_t MCR; /*!< [0x0] PIT Module Control Register */
499 uint8_t _reserved0[252];
501 __IO hw_pit_ldvaln_t LDVALn; /*!< [0x100] Timer Load Value Register */
502 __I hw_pit_cvaln_t CVALn; /*!< [0x104] Current Timer Value Register */
503 __IO hw_pit_tctrln_t TCTRLn; /*!< [0x108] Timer Control Register */
504 __IO hw_pit_tflgn_t TFLGn; /*!< [0x10C] Timer Flag Register */
509 /*! @brief Macro to access all PIT registers. */
510 /*! @param x PIT module instance base address. */
511 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
512 * use the '&' operator, like <code>&HW_PIT(PIT_BASE)</code>. */
513 #define HW_PIT(x) (*(hw_pit_t *)(x))
515 #endif /* __HW_PIT_REGISTERS_H__ */