2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
9 ** Version: rev. 2.5, 2014-05-06
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-07-23)
49 ** - rev. 1.1 (2013-09-17)
50 ** RM rev. 0.4 update.
51 ** - rev. 2.0 (2013-10-29)
52 ** Register accessor macros added to the memory map.
53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
54 ** Startup file for gcc has been updated according to CMSIS 3.2.
55 ** System initialization updated.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-20)
59 ** Update according to reference manual rev. 0.6,
60 ** - rev. 2.3 (2014-01-13)
61 ** Update according to reference manual rev. 0.61,
62 ** - rev. 2.4 (2014-02-10)
63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
64 ** - rev. 2.5 (2014-05-06)
65 ** Update according to reference manual rev. 1.0,
66 ** Update of system and startup files.
67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
69 ** ###################################################################
73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
75 * This file was generated automatically and any changes may be lost.
77 #ifndef __HW_DMA_REGISTERS_H__
78 #define __HW_DMA_REGISTERS_H__
80 #include "MK22F51212.h"
81 #include "fsl_bitaccess.h"
86 * Enhanced direct memory access controller
88 * Registers defined in this header file:
89 * - HW_DMA_CR - Control Register
90 * - HW_DMA_ES - Error Status Register
91 * - HW_DMA_ERQ - Enable Request Register
92 * - HW_DMA_EEI - Enable Error Interrupt Register
93 * - HW_DMA_CEEI - Clear Enable Error Interrupt Register
94 * - HW_DMA_SEEI - Set Enable Error Interrupt Register
95 * - HW_DMA_CERQ - Clear Enable Request Register
96 * - HW_DMA_SERQ - Set Enable Request Register
97 * - HW_DMA_CDNE - Clear DONE Status Bit Register
98 * - HW_DMA_SSRT - Set START Bit Register
99 * - HW_DMA_CERR - Clear Error Register
100 * - HW_DMA_CINT - Clear Interrupt Request Register
101 * - HW_DMA_INT - Interrupt Request Register
102 * - HW_DMA_ERR - Error Register
103 * - HW_DMA_HRS - Hardware Request Status Register
104 * - HW_DMA_EARS - Enable Asynchronous Request in Stop Register
105 * - HW_DMA_DCHPRIn - Channel n Priority Register
106 * - HW_DMA_TCDn_SADDR - TCD Source Address
107 * - HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
108 * - HW_DMA_TCDn_ATTR - TCD Transfer Attributes
109 * - HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
110 * - HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
111 * - HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
112 * - HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
113 * - HW_DMA_TCDn_DADDR - TCD Destination Address
114 * - HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
115 * - HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
116 * - HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
117 * - HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
118 * - HW_DMA_TCDn_CSR - TCD Control and Status
119 * - HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
120 * - HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
122 * - hw_dma_t - Struct containing all module registers.
125 #define HW_DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */
127 /*******************************************************************************
128 * HW_DMA_CR - Control Register
129 ******************************************************************************/
132 * @brief HW_DMA_CR - Control Register (RW)
134 * Reset value: 0x00000000U
136 * The CR defines the basic operating configuration of the DMA. Arbitration can
137 * be configured to use either a fixed-priority or a round-robin scheme. For
138 * fixed-priority arbitration, the highest priority channel requesting service is
139 * selected to execute. The channel priority registers assign the priorities; see
140 * the DCHPRIn registers. For round-robin arbitration, the channel priorities are
141 * ignored and channels are cycled through (from high to low channel number)
142 * without regard to priority. For proper operation, writes to the CR register must be
143 * performed only when the DMA channels are inactive; that is, when
144 * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
145 * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
146 * minor loop completion. When minor loop offsets are enabled, the minor loop
147 * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
148 * destination address (TCDn_DADDR), or to both prior to the addresses being
149 * written back into the TCD. If the major loop is complete, the minor loop offset is
150 * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
151 * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
152 * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
153 * is used to specify multiple fields: a source enable bit (SMLOE) to specify the
154 * minor loop offset should be applied to the source address (TCDn_SADDR) upon
155 * minor loop completion, a destination enable bit (DMLOE) to specify the minor
156 * loop offset should be applied to the destination address (TCDn_DADDR) upon minor
157 * loop completion, and the sign extended minor loop offset value (MLOFF). The
158 * same offset value (MLOFF) is used for both source and destination minor loop
159 * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
160 * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
161 * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
162 * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
163 * assigned to the NBYTES field.
165 typedef union _hw_dma_cr
168 struct _hw_dma_cr_bitfields
170 uint32_t RESERVED0 : 1; /*!< [0] Reserved. */
171 uint32_t EDBG : 1; /*!< [1] Enable Debug */
172 uint32_t ERCA : 1; /*!< [2] Enable Round Robin Channel Arbitration */
173 uint32_t RESERVED1 : 1; /*!< [3] Reserved. */
174 uint32_t HOE : 1; /*!< [4] Halt On Error */
175 uint32_t HALT : 1; /*!< [5] Halt DMA Operations */
176 uint32_t CLM : 1; /*!< [6] Continuous Link Mode */
177 uint32_t EMLM : 1; /*!< [7] Enable Minor Loop Mapping */
178 uint32_t RESERVED2 : 8; /*!< [15:8] */
179 uint32_t ECX : 1; /*!< [16] Error Cancel Transfer */
180 uint32_t CX : 1; /*!< [17] Cancel Transfer */
181 uint32_t RESERVED3 : 14; /*!< [31:18] */
186 * @name Constants and macros for entire DMA_CR register
189 #define HW_DMA_CR_ADDR(x) ((x) + 0x0U)
191 #define HW_DMA_CR(x) (*(__IO hw_dma_cr_t *) HW_DMA_CR_ADDR(x))
192 #define HW_DMA_CR_RD(x) (HW_DMA_CR(x).U)
193 #define HW_DMA_CR_WR(x, v) (HW_DMA_CR(x).U = (v))
194 #define HW_DMA_CR_SET(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) | (v)))
195 #define HW_DMA_CR_CLR(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) & ~(v)))
196 #define HW_DMA_CR_TOG(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) ^ (v)))
200 * Constants & macros for individual DMA_CR bitfields
204 * @name Register DMA_CR, field EDBG[1] (RW)
207 * - 0 - When in debug mode, the DMA continues to operate.
208 * - 1 - When in debug mode, the DMA stalls the start of a new channel.
209 * Executing channels are allowed to complete. Channel execution resumes when the
210 * system exits debug mode or the EDBG bit is cleared.
213 #define BP_DMA_CR_EDBG (1U) /*!< Bit position for DMA_CR_EDBG. */
214 #define BM_DMA_CR_EDBG (0x00000002U) /*!< Bit mask for DMA_CR_EDBG. */
215 #define BS_DMA_CR_EDBG (1U) /*!< Bit field size in bits for DMA_CR_EDBG. */
217 /*! @brief Read current value of the DMA_CR_EDBG field. */
218 #define BR_DMA_CR_EDBG(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG))
220 /*! @brief Format value for bitfield DMA_CR_EDBG. */
221 #define BF_DMA_CR_EDBG(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_EDBG) & BM_DMA_CR_EDBG)
223 /*! @brief Set the EDBG field to a new value. */
224 #define BW_DMA_CR_EDBG(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG) = (v))
228 * @name Register DMA_CR, field ERCA[2] (RW)
231 * - 0 - Fixed priority arbitration is used for channel selection .
232 * - 1 - Round robin arbitration is used for channel selection .
235 #define BP_DMA_CR_ERCA (2U) /*!< Bit position for DMA_CR_ERCA. */
236 #define BM_DMA_CR_ERCA (0x00000004U) /*!< Bit mask for DMA_CR_ERCA. */
237 #define BS_DMA_CR_ERCA (1U) /*!< Bit field size in bits for DMA_CR_ERCA. */
239 /*! @brief Read current value of the DMA_CR_ERCA field. */
240 #define BR_DMA_CR_ERCA(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA))
242 /*! @brief Format value for bitfield DMA_CR_ERCA. */
243 #define BF_DMA_CR_ERCA(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_ERCA) & BM_DMA_CR_ERCA)
245 /*! @brief Set the ERCA field to a new value. */
246 #define BW_DMA_CR_ERCA(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA) = (v))
250 * @name Register DMA_CR, field HOE[4] (RW)
253 * - 0 - Normal operation
254 * - 1 - Any error causes the HALT bit to set. Subsequently, all service
255 * requests are ignored until the HALT bit is cleared.
258 #define BP_DMA_CR_HOE (4U) /*!< Bit position for DMA_CR_HOE. */
259 #define BM_DMA_CR_HOE (0x00000010U) /*!< Bit mask for DMA_CR_HOE. */
260 #define BS_DMA_CR_HOE (1U) /*!< Bit field size in bits for DMA_CR_HOE. */
262 /*! @brief Read current value of the DMA_CR_HOE field. */
263 #define BR_DMA_CR_HOE(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE))
265 /*! @brief Format value for bitfield DMA_CR_HOE. */
266 #define BF_DMA_CR_HOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_HOE) & BM_DMA_CR_HOE)
268 /*! @brief Set the HOE field to a new value. */
269 #define BW_DMA_CR_HOE(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE) = (v))
273 * @name Register DMA_CR, field HALT[5] (RW)
276 * - 0 - Normal operation
277 * - 1 - Stall the start of any new channels. Executing channels are allowed to
278 * complete. Channel execution resumes when this bit is cleared.
281 #define BP_DMA_CR_HALT (5U) /*!< Bit position for DMA_CR_HALT. */
282 #define BM_DMA_CR_HALT (0x00000020U) /*!< Bit mask for DMA_CR_HALT. */
283 #define BS_DMA_CR_HALT (1U) /*!< Bit field size in bits for DMA_CR_HALT. */
285 /*! @brief Read current value of the DMA_CR_HALT field. */
286 #define BR_DMA_CR_HALT(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT))
288 /*! @brief Format value for bitfield DMA_CR_HALT. */
289 #define BF_DMA_CR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_HALT) & BM_DMA_CR_HALT)
291 /*! @brief Set the HALT field to a new value. */
292 #define BW_DMA_CR_HALT(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT) = (v))
296 * @name Register DMA_CR, field CLM[6] (RW)
299 * - 0 - A minor loop channel link made to itself goes through channel
300 * arbitration before being activated again.
301 * - 1 - A minor loop channel link made to itself does not go through channel
302 * arbitration before being activated again. Upon minor loop completion, the
303 * channel activates again if that channel has a minor loop channel link
304 * enabled and the link channel is itself. This effectively applies the minor loop
305 * offsets and restarts the next minor loop.
308 #define BP_DMA_CR_CLM (6U) /*!< Bit position for DMA_CR_CLM. */
309 #define BM_DMA_CR_CLM (0x00000040U) /*!< Bit mask for DMA_CR_CLM. */
310 #define BS_DMA_CR_CLM (1U) /*!< Bit field size in bits for DMA_CR_CLM. */
312 /*! @brief Read current value of the DMA_CR_CLM field. */
313 #define BR_DMA_CR_CLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM))
315 /*! @brief Format value for bitfield DMA_CR_CLM. */
316 #define BF_DMA_CR_CLM(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_CLM) & BM_DMA_CR_CLM)
318 /*! @brief Set the CLM field to a new value. */
319 #define BW_DMA_CR_CLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM) = (v))
323 * @name Register DMA_CR, field EMLM[7] (RW)
326 * - 0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
327 * - 1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
328 * an offset field, and the NBYTES field. The individual enable fields allow
329 * the minor loop offset to be applied to the source address, the destination
330 * address, or both. The NBYTES field is reduced when either offset is
334 #define BP_DMA_CR_EMLM (7U) /*!< Bit position for DMA_CR_EMLM. */
335 #define BM_DMA_CR_EMLM (0x00000080U) /*!< Bit mask for DMA_CR_EMLM. */
336 #define BS_DMA_CR_EMLM (1U) /*!< Bit field size in bits for DMA_CR_EMLM. */
338 /*! @brief Read current value of the DMA_CR_EMLM field. */
339 #define BR_DMA_CR_EMLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM))
341 /*! @brief Format value for bitfield DMA_CR_EMLM. */
342 #define BF_DMA_CR_EMLM(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_EMLM) & BM_DMA_CR_EMLM)
344 /*! @brief Set the EMLM field to a new value. */
345 #define BW_DMA_CR_EMLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM) = (v))
349 * @name Register DMA_CR, field ECX[16] (RW)
352 * - 0 - Normal operation
353 * - 1 - Cancel the remaining data transfer in the same fashion as the CX bit.
354 * Stop the executing channel and force the minor loop to finish. The cancel
355 * takes effect after the last write of the current read/write sequence. The
356 * ECX bit clears itself after the cancel is honored. In addition to
357 * cancelling the transfer, ECX treats the cancel as an error condition, thus updating
358 * the Error Status register (DMAx_ES) and generating an optional error
362 #define BP_DMA_CR_ECX (16U) /*!< Bit position for DMA_CR_ECX. */
363 #define BM_DMA_CR_ECX (0x00010000U) /*!< Bit mask for DMA_CR_ECX. */
364 #define BS_DMA_CR_ECX (1U) /*!< Bit field size in bits for DMA_CR_ECX. */
366 /*! @brief Read current value of the DMA_CR_ECX field. */
367 #define BR_DMA_CR_ECX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX))
369 /*! @brief Format value for bitfield DMA_CR_ECX. */
370 #define BF_DMA_CR_ECX(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_ECX) & BM_DMA_CR_ECX)
372 /*! @brief Set the ECX field to a new value. */
373 #define BW_DMA_CR_ECX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX) = (v))
377 * @name Register DMA_CR, field CX[17] (RW)
380 * - 0 - Normal operation
381 * - 1 - Cancel the remaining data transfer. Stop the executing channel and
382 * force the minor loop to finish. The cancel takes effect after the last write
383 * of the current read/write sequence. The CX bit clears itself after the
384 * cancel has been honored. This cancel retires the channel normally as if the
385 * minor loop was completed.
388 #define BP_DMA_CR_CX (17U) /*!< Bit position for DMA_CR_CX. */
389 #define BM_DMA_CR_CX (0x00020000U) /*!< Bit mask for DMA_CR_CX. */
390 #define BS_DMA_CR_CX (1U) /*!< Bit field size in bits for DMA_CR_CX. */
392 /*! @brief Read current value of the DMA_CR_CX field. */
393 #define BR_DMA_CR_CX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX))
395 /*! @brief Format value for bitfield DMA_CR_CX. */
396 #define BF_DMA_CR_CX(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_CX) & BM_DMA_CR_CX)
398 /*! @brief Set the CX field to a new value. */
399 #define BW_DMA_CR_CX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX) = (v))
402 /*******************************************************************************
403 * HW_DMA_ES - Error Status Register
404 ******************************************************************************/
407 * @brief HW_DMA_ES - Error Status Register (RO)
409 * Reset value: 0x00000000U
411 * The ES provides information concerning the last recorded channel error.
412 * Channel errors can be caused by: A configuration error, that is: An illegal setting
413 * in the transfer-control descriptor, or An illegal priority register setting
414 * in fixed-arbitration An error termination to a bus master read or write cycle
415 * See the Error Reporting and Handling section for more details.
417 typedef union _hw_dma_es
420 struct _hw_dma_es_bitfields
422 uint32_t DBE : 1; /*!< [0] Destination Bus Error */
423 uint32_t SBE : 1; /*!< [1] Source Bus Error */
424 uint32_t SGE : 1; /*!< [2] Scatter/Gather Configuration Error */
425 uint32_t NCE : 1; /*!< [3] NBYTES/CITER Configuration Error */
426 uint32_t DOE : 1; /*!< [4] Destination Offset Error */
427 uint32_t DAE : 1; /*!< [5] Destination Address Error */
428 uint32_t SOE : 1; /*!< [6] Source Offset Error */
429 uint32_t SAE : 1; /*!< [7] Source Address Error */
430 uint32_t ERRCHN : 4; /*!< [11:8] Error Channel Number or Canceled
432 uint32_t RESERVED0 : 2; /*!< [13:12] */
433 uint32_t CPE : 1; /*!< [14] Channel Priority Error */
434 uint32_t RESERVED1 : 1; /*!< [15] */
435 uint32_t ECX : 1; /*!< [16] Transfer Canceled */
436 uint32_t RESERVED2 : 14; /*!< [30:17] */
437 uint32_t VLD : 1; /*!< [31] */
442 * @name Constants and macros for entire DMA_ES register
445 #define HW_DMA_ES_ADDR(x) ((x) + 0x4U)
447 #define HW_DMA_ES(x) (*(__I hw_dma_es_t *) HW_DMA_ES_ADDR(x))
448 #define HW_DMA_ES_RD(x) (HW_DMA_ES(x).U)
452 * Constants & macros for individual DMA_ES bitfields
456 * @name Register DMA_ES, field DBE[0] (RO)
459 * - 0 - No destination bus error
460 * - 1 - The last recorded error was a bus error on a destination write
463 #define BP_DMA_ES_DBE (0U) /*!< Bit position for DMA_ES_DBE. */
464 #define BM_DMA_ES_DBE (0x00000001U) /*!< Bit mask for DMA_ES_DBE. */
465 #define BS_DMA_ES_DBE (1U) /*!< Bit field size in bits for DMA_ES_DBE. */
467 /*! @brief Read current value of the DMA_ES_DBE field. */
468 #define BR_DMA_ES_DBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DBE))
472 * @name Register DMA_ES, field SBE[1] (RO)
475 * - 0 - No source bus error
476 * - 1 - The last recorded error was a bus error on a source read
479 #define BP_DMA_ES_SBE (1U) /*!< Bit position for DMA_ES_SBE. */
480 #define BM_DMA_ES_SBE (0x00000002U) /*!< Bit mask for DMA_ES_SBE. */
481 #define BS_DMA_ES_SBE (1U) /*!< Bit field size in bits for DMA_ES_SBE. */
483 /*! @brief Read current value of the DMA_ES_SBE field. */
484 #define BR_DMA_ES_SBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SBE))
488 * @name Register DMA_ES, field SGE[2] (RO)
491 * - 0 - No scatter/gather configuration error
492 * - 1 - The last recorded error was a configuration error detected in the
493 * TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather
494 * operation after major loop completion if TCDn_CSR[ESG] is enabled.
495 * TCDn_DLASTSGA is not on a 32 byte boundary.
498 #define BP_DMA_ES_SGE (2U) /*!< Bit position for DMA_ES_SGE. */
499 #define BM_DMA_ES_SGE (0x00000004U) /*!< Bit mask for DMA_ES_SGE. */
500 #define BS_DMA_ES_SGE (1U) /*!< Bit field size in bits for DMA_ES_SGE. */
502 /*! @brief Read current value of the DMA_ES_SGE field. */
503 #define BR_DMA_ES_SGE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SGE))
507 * @name Register DMA_ES, field NCE[3] (RO)
510 * - 0 - No NBYTES/CITER configuration error
511 * - 1 - The last recorded error was a configuration error detected in the
512 * TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
513 * TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
514 * TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
517 #define BP_DMA_ES_NCE (3U) /*!< Bit position for DMA_ES_NCE. */
518 #define BM_DMA_ES_NCE (0x00000008U) /*!< Bit mask for DMA_ES_NCE. */
519 #define BS_DMA_ES_NCE (1U) /*!< Bit field size in bits for DMA_ES_NCE. */
521 /*! @brief Read current value of the DMA_ES_NCE field. */
522 #define BR_DMA_ES_NCE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_NCE))
526 * @name Register DMA_ES, field DOE[4] (RO)
529 * - 0 - No destination offset configuration error
530 * - 1 - The last recorded error was a configuration error detected in the
531 * TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
534 #define BP_DMA_ES_DOE (4U) /*!< Bit position for DMA_ES_DOE. */
535 #define BM_DMA_ES_DOE (0x00000010U) /*!< Bit mask for DMA_ES_DOE. */
536 #define BS_DMA_ES_DOE (1U) /*!< Bit field size in bits for DMA_ES_DOE. */
538 /*! @brief Read current value of the DMA_ES_DOE field. */
539 #define BR_DMA_ES_DOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DOE))
543 * @name Register DMA_ES, field DAE[5] (RO)
546 * - 0 - No destination address configuration error
547 * - 1 - The last recorded error was a configuration error detected in the
548 * TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
551 #define BP_DMA_ES_DAE (5U) /*!< Bit position for DMA_ES_DAE. */
552 #define BM_DMA_ES_DAE (0x00000020U) /*!< Bit mask for DMA_ES_DAE. */
553 #define BS_DMA_ES_DAE (1U) /*!< Bit field size in bits for DMA_ES_DAE. */
555 /*! @brief Read current value of the DMA_ES_DAE field. */
556 #define BR_DMA_ES_DAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DAE))
560 * @name Register DMA_ES, field SOE[6] (RO)
563 * - 0 - No source offset configuration error
564 * - 1 - The last recorded error was a configuration error detected in the
565 * TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
568 #define BP_DMA_ES_SOE (6U) /*!< Bit position for DMA_ES_SOE. */
569 #define BM_DMA_ES_SOE (0x00000040U) /*!< Bit mask for DMA_ES_SOE. */
570 #define BS_DMA_ES_SOE (1U) /*!< Bit field size in bits for DMA_ES_SOE. */
572 /*! @brief Read current value of the DMA_ES_SOE field. */
573 #define BR_DMA_ES_SOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SOE))
577 * @name Register DMA_ES, field SAE[7] (RO)
580 * - 0 - No source address configuration error.
581 * - 1 - The last recorded error was a configuration error detected in the
582 * TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
585 #define BP_DMA_ES_SAE (7U) /*!< Bit position for DMA_ES_SAE. */
586 #define BM_DMA_ES_SAE (0x00000080U) /*!< Bit mask for DMA_ES_SAE. */
587 #define BS_DMA_ES_SAE (1U) /*!< Bit field size in bits for DMA_ES_SAE. */
589 /*! @brief Read current value of the DMA_ES_SAE field. */
590 #define BR_DMA_ES_SAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SAE))
594 * @name Register DMA_ES, field ERRCHN[11:8] (RO)
596 * The channel number of the last recorded error (excluding CPE errors) or last
597 * recorded error canceled transfer.
600 #define BP_DMA_ES_ERRCHN (8U) /*!< Bit position for DMA_ES_ERRCHN. */
601 #define BM_DMA_ES_ERRCHN (0x00000F00U) /*!< Bit mask for DMA_ES_ERRCHN. */
602 #define BS_DMA_ES_ERRCHN (4U) /*!< Bit field size in bits for DMA_ES_ERRCHN. */
604 /*! @brief Read current value of the DMA_ES_ERRCHN field. */
605 #define BR_DMA_ES_ERRCHN(x) (HW_DMA_ES(x).B.ERRCHN)
609 * @name Register DMA_ES, field CPE[14] (RO)
612 * - 0 - No channel priority error
613 * - 1 - The last recorded error was a configuration error in the channel
614 * priorities . Channel priorities are not unique.
617 #define BP_DMA_ES_CPE (14U) /*!< Bit position for DMA_ES_CPE. */
618 #define BM_DMA_ES_CPE (0x00004000U) /*!< Bit mask for DMA_ES_CPE. */
619 #define BS_DMA_ES_CPE (1U) /*!< Bit field size in bits for DMA_ES_CPE. */
621 /*! @brief Read current value of the DMA_ES_CPE field. */
622 #define BR_DMA_ES_CPE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_CPE))
626 * @name Register DMA_ES, field ECX[16] (RO)
629 * - 0 - No canceled transfers
630 * - 1 - The last recorded entry was a canceled transfer by the error cancel
634 #define BP_DMA_ES_ECX (16U) /*!< Bit position for DMA_ES_ECX. */
635 #define BM_DMA_ES_ECX (0x00010000U) /*!< Bit mask for DMA_ES_ECX. */
636 #define BS_DMA_ES_ECX (1U) /*!< Bit field size in bits for DMA_ES_ECX. */
638 /*! @brief Read current value of the DMA_ES_ECX field. */
639 #define BR_DMA_ES_ECX(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_ECX))
643 * @name Register DMA_ES, field VLD[31] (RO)
645 * Logical OR of all ERR status bits
648 * - 0 - No ERR bits are set
649 * - 1 - At least one ERR bit is set indicating a valid error exists that has
653 #define BP_DMA_ES_VLD (31U) /*!< Bit position for DMA_ES_VLD. */
654 #define BM_DMA_ES_VLD (0x80000000U) /*!< Bit mask for DMA_ES_VLD. */
655 #define BS_DMA_ES_VLD (1U) /*!< Bit field size in bits for DMA_ES_VLD. */
657 /*! @brief Read current value of the DMA_ES_VLD field. */
658 #define BR_DMA_ES_VLD(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_VLD))
661 /*******************************************************************************
662 * HW_DMA_ERQ - Enable Request Register
663 ******************************************************************************/
666 * @brief HW_DMA_ERQ - Enable Request Register (RW)
668 * Reset value: 0x00000000U
670 * The ERQ register provides a bit map for the 16 implemented channels to enable
671 * the request signal for each channel. The state of any given channel enable is
672 * directly affected by writes to this register; it is also affected by writes
673 * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
674 * for a single channel can easily be modified without needing to perform a
675 * read-modify-write sequence to the ERQ. DMA request input signals and this enable
676 * request flag must be asserted before a channel's hardware service request is
677 * accepted. The state of the DMA enable request flag does not affect a channel
678 * service request made explicitly through software or a linked channel request.
680 typedef union _hw_dma_erq
683 struct _hw_dma_erq_bitfields
685 uint32_t ERQ0 : 1; /*!< [0] Enable DMA Request 0 */
686 uint32_t ERQ1 : 1; /*!< [1] Enable DMA Request 1 */
687 uint32_t ERQ2 : 1; /*!< [2] Enable DMA Request 2 */
688 uint32_t ERQ3 : 1; /*!< [3] Enable DMA Request 3 */
689 uint32_t ERQ4 : 1; /*!< [4] Enable DMA Request 4 */
690 uint32_t ERQ5 : 1; /*!< [5] Enable DMA Request 5 */
691 uint32_t ERQ6 : 1; /*!< [6] Enable DMA Request 6 */
692 uint32_t ERQ7 : 1; /*!< [7] Enable DMA Request 7 */
693 uint32_t ERQ8 : 1; /*!< [8] Enable DMA Request 8 */
694 uint32_t ERQ9 : 1; /*!< [9] Enable DMA Request 9 */
695 uint32_t ERQ10 : 1; /*!< [10] Enable DMA Request 10 */
696 uint32_t ERQ11 : 1; /*!< [11] Enable DMA Request 11 */
697 uint32_t ERQ12 : 1; /*!< [12] Enable DMA Request 12 */
698 uint32_t ERQ13 : 1; /*!< [13] Enable DMA Request 13 */
699 uint32_t ERQ14 : 1; /*!< [14] Enable DMA Request 14 */
700 uint32_t ERQ15 : 1; /*!< [15] Enable DMA Request 15 */
701 uint32_t RESERVED0 : 16; /*!< [31:16] */
706 * @name Constants and macros for entire DMA_ERQ register
709 #define HW_DMA_ERQ_ADDR(x) ((x) + 0xCU)
711 #define HW_DMA_ERQ(x) (*(__IO hw_dma_erq_t *) HW_DMA_ERQ_ADDR(x))
712 #define HW_DMA_ERQ_RD(x) (HW_DMA_ERQ(x).U)
713 #define HW_DMA_ERQ_WR(x, v) (HW_DMA_ERQ(x).U = (v))
714 #define HW_DMA_ERQ_SET(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) | (v)))
715 #define HW_DMA_ERQ_CLR(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) & ~(v)))
716 #define HW_DMA_ERQ_TOG(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) ^ (v)))
720 * Constants & macros for individual DMA_ERQ bitfields
724 * @name Register DMA_ERQ, field ERQ0[0] (RW)
727 * - 0 - The DMA request signal for the corresponding channel is disabled
728 * - 1 - The DMA request signal for the corresponding channel is enabled
731 #define BP_DMA_ERQ_ERQ0 (0U) /*!< Bit position for DMA_ERQ_ERQ0. */
732 #define BM_DMA_ERQ_ERQ0 (0x00000001U) /*!< Bit mask for DMA_ERQ_ERQ0. */
733 #define BS_DMA_ERQ_ERQ0 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ0. */
735 /*! @brief Read current value of the DMA_ERQ_ERQ0 field. */
736 #define BR_DMA_ERQ_ERQ0(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0))
738 /*! @brief Format value for bitfield DMA_ERQ_ERQ0. */
739 #define BF_DMA_ERQ_ERQ0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ0) & BM_DMA_ERQ_ERQ0)
741 /*! @brief Set the ERQ0 field to a new value. */
742 #define BW_DMA_ERQ_ERQ0(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0) = (v))
746 * @name Register DMA_ERQ, field ERQ1[1] (RW)
749 * - 0 - The DMA request signal for the corresponding channel is disabled
750 * - 1 - The DMA request signal for the corresponding channel is enabled
753 #define BP_DMA_ERQ_ERQ1 (1U) /*!< Bit position for DMA_ERQ_ERQ1. */
754 #define BM_DMA_ERQ_ERQ1 (0x00000002U) /*!< Bit mask for DMA_ERQ_ERQ1. */
755 #define BS_DMA_ERQ_ERQ1 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ1. */
757 /*! @brief Read current value of the DMA_ERQ_ERQ1 field. */
758 #define BR_DMA_ERQ_ERQ1(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1))
760 /*! @brief Format value for bitfield DMA_ERQ_ERQ1. */
761 #define BF_DMA_ERQ_ERQ1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ1) & BM_DMA_ERQ_ERQ1)
763 /*! @brief Set the ERQ1 field to a new value. */
764 #define BW_DMA_ERQ_ERQ1(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1) = (v))
768 * @name Register DMA_ERQ, field ERQ2[2] (RW)
771 * - 0 - The DMA request signal for the corresponding channel is disabled
772 * - 1 - The DMA request signal for the corresponding channel is enabled
775 #define BP_DMA_ERQ_ERQ2 (2U) /*!< Bit position for DMA_ERQ_ERQ2. */
776 #define BM_DMA_ERQ_ERQ2 (0x00000004U) /*!< Bit mask for DMA_ERQ_ERQ2. */
777 #define BS_DMA_ERQ_ERQ2 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ2. */
779 /*! @brief Read current value of the DMA_ERQ_ERQ2 field. */
780 #define BR_DMA_ERQ_ERQ2(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2))
782 /*! @brief Format value for bitfield DMA_ERQ_ERQ2. */
783 #define BF_DMA_ERQ_ERQ2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ2) & BM_DMA_ERQ_ERQ2)
785 /*! @brief Set the ERQ2 field to a new value. */
786 #define BW_DMA_ERQ_ERQ2(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2) = (v))
790 * @name Register DMA_ERQ, field ERQ3[3] (RW)
793 * - 0 - The DMA request signal for the corresponding channel is disabled
794 * - 1 - The DMA request signal for the corresponding channel is enabled
797 #define BP_DMA_ERQ_ERQ3 (3U) /*!< Bit position for DMA_ERQ_ERQ3. */
798 #define BM_DMA_ERQ_ERQ3 (0x00000008U) /*!< Bit mask for DMA_ERQ_ERQ3. */
799 #define BS_DMA_ERQ_ERQ3 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ3. */
801 /*! @brief Read current value of the DMA_ERQ_ERQ3 field. */
802 #define BR_DMA_ERQ_ERQ3(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3))
804 /*! @brief Format value for bitfield DMA_ERQ_ERQ3. */
805 #define BF_DMA_ERQ_ERQ3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ3) & BM_DMA_ERQ_ERQ3)
807 /*! @brief Set the ERQ3 field to a new value. */
808 #define BW_DMA_ERQ_ERQ3(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3) = (v))
812 * @name Register DMA_ERQ, field ERQ4[4] (RW)
815 * - 0 - The DMA request signal for the corresponding channel is disabled
816 * - 1 - The DMA request signal for the corresponding channel is enabled
819 #define BP_DMA_ERQ_ERQ4 (4U) /*!< Bit position for DMA_ERQ_ERQ4. */
820 #define BM_DMA_ERQ_ERQ4 (0x00000010U) /*!< Bit mask for DMA_ERQ_ERQ4. */
821 #define BS_DMA_ERQ_ERQ4 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ4. */
823 /*! @brief Read current value of the DMA_ERQ_ERQ4 field. */
824 #define BR_DMA_ERQ_ERQ4(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4))
826 /*! @brief Format value for bitfield DMA_ERQ_ERQ4. */
827 #define BF_DMA_ERQ_ERQ4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ4) & BM_DMA_ERQ_ERQ4)
829 /*! @brief Set the ERQ4 field to a new value. */
830 #define BW_DMA_ERQ_ERQ4(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4) = (v))
834 * @name Register DMA_ERQ, field ERQ5[5] (RW)
837 * - 0 - The DMA request signal for the corresponding channel is disabled
838 * - 1 - The DMA request signal for the corresponding channel is enabled
841 #define BP_DMA_ERQ_ERQ5 (5U) /*!< Bit position for DMA_ERQ_ERQ5. */
842 #define BM_DMA_ERQ_ERQ5 (0x00000020U) /*!< Bit mask for DMA_ERQ_ERQ5. */
843 #define BS_DMA_ERQ_ERQ5 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ5. */
845 /*! @brief Read current value of the DMA_ERQ_ERQ5 field. */
846 #define BR_DMA_ERQ_ERQ5(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5))
848 /*! @brief Format value for bitfield DMA_ERQ_ERQ5. */
849 #define BF_DMA_ERQ_ERQ5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ5) & BM_DMA_ERQ_ERQ5)
851 /*! @brief Set the ERQ5 field to a new value. */
852 #define BW_DMA_ERQ_ERQ5(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5) = (v))
856 * @name Register DMA_ERQ, field ERQ6[6] (RW)
859 * - 0 - The DMA request signal for the corresponding channel is disabled
860 * - 1 - The DMA request signal for the corresponding channel is enabled
863 #define BP_DMA_ERQ_ERQ6 (6U) /*!< Bit position for DMA_ERQ_ERQ6. */
864 #define BM_DMA_ERQ_ERQ6 (0x00000040U) /*!< Bit mask for DMA_ERQ_ERQ6. */
865 #define BS_DMA_ERQ_ERQ6 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ6. */
867 /*! @brief Read current value of the DMA_ERQ_ERQ6 field. */
868 #define BR_DMA_ERQ_ERQ6(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6))
870 /*! @brief Format value for bitfield DMA_ERQ_ERQ6. */
871 #define BF_DMA_ERQ_ERQ6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ6) & BM_DMA_ERQ_ERQ6)
873 /*! @brief Set the ERQ6 field to a new value. */
874 #define BW_DMA_ERQ_ERQ6(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6) = (v))
878 * @name Register DMA_ERQ, field ERQ7[7] (RW)
881 * - 0 - The DMA request signal for the corresponding channel is disabled
882 * - 1 - The DMA request signal for the corresponding channel is enabled
885 #define BP_DMA_ERQ_ERQ7 (7U) /*!< Bit position for DMA_ERQ_ERQ7. */
886 #define BM_DMA_ERQ_ERQ7 (0x00000080U) /*!< Bit mask for DMA_ERQ_ERQ7. */
887 #define BS_DMA_ERQ_ERQ7 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ7. */
889 /*! @brief Read current value of the DMA_ERQ_ERQ7 field. */
890 #define BR_DMA_ERQ_ERQ7(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7))
892 /*! @brief Format value for bitfield DMA_ERQ_ERQ7. */
893 #define BF_DMA_ERQ_ERQ7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ7) & BM_DMA_ERQ_ERQ7)
895 /*! @brief Set the ERQ7 field to a new value. */
896 #define BW_DMA_ERQ_ERQ7(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7) = (v))
900 * @name Register DMA_ERQ, field ERQ8[8] (RW)
903 * - 0 - The DMA request signal for the corresponding channel is disabled
904 * - 1 - The DMA request signal for the corresponding channel is enabled
907 #define BP_DMA_ERQ_ERQ8 (8U) /*!< Bit position for DMA_ERQ_ERQ8. */
908 #define BM_DMA_ERQ_ERQ8 (0x00000100U) /*!< Bit mask for DMA_ERQ_ERQ8. */
909 #define BS_DMA_ERQ_ERQ8 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ8. */
911 /*! @brief Read current value of the DMA_ERQ_ERQ8 field. */
912 #define BR_DMA_ERQ_ERQ8(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8))
914 /*! @brief Format value for bitfield DMA_ERQ_ERQ8. */
915 #define BF_DMA_ERQ_ERQ8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ8) & BM_DMA_ERQ_ERQ8)
917 /*! @brief Set the ERQ8 field to a new value. */
918 #define BW_DMA_ERQ_ERQ8(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8) = (v))
922 * @name Register DMA_ERQ, field ERQ9[9] (RW)
925 * - 0 - The DMA request signal for the corresponding channel is disabled
926 * - 1 - The DMA request signal for the corresponding channel is enabled
929 #define BP_DMA_ERQ_ERQ9 (9U) /*!< Bit position for DMA_ERQ_ERQ9. */
930 #define BM_DMA_ERQ_ERQ9 (0x00000200U) /*!< Bit mask for DMA_ERQ_ERQ9. */
931 #define BS_DMA_ERQ_ERQ9 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ9. */
933 /*! @brief Read current value of the DMA_ERQ_ERQ9 field. */
934 #define BR_DMA_ERQ_ERQ9(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9))
936 /*! @brief Format value for bitfield DMA_ERQ_ERQ9. */
937 #define BF_DMA_ERQ_ERQ9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ9) & BM_DMA_ERQ_ERQ9)
939 /*! @brief Set the ERQ9 field to a new value. */
940 #define BW_DMA_ERQ_ERQ9(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9) = (v))
944 * @name Register DMA_ERQ, field ERQ10[10] (RW)
947 * - 0 - The DMA request signal for the corresponding channel is disabled
948 * - 1 - The DMA request signal for the corresponding channel is enabled
951 #define BP_DMA_ERQ_ERQ10 (10U) /*!< Bit position for DMA_ERQ_ERQ10. */
952 #define BM_DMA_ERQ_ERQ10 (0x00000400U) /*!< Bit mask for DMA_ERQ_ERQ10. */
953 #define BS_DMA_ERQ_ERQ10 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ10. */
955 /*! @brief Read current value of the DMA_ERQ_ERQ10 field. */
956 #define BR_DMA_ERQ_ERQ10(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10))
958 /*! @brief Format value for bitfield DMA_ERQ_ERQ10. */
959 #define BF_DMA_ERQ_ERQ10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ10) & BM_DMA_ERQ_ERQ10)
961 /*! @brief Set the ERQ10 field to a new value. */
962 #define BW_DMA_ERQ_ERQ10(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10) = (v))
966 * @name Register DMA_ERQ, field ERQ11[11] (RW)
969 * - 0 - The DMA request signal for the corresponding channel is disabled
970 * - 1 - The DMA request signal for the corresponding channel is enabled
973 #define BP_DMA_ERQ_ERQ11 (11U) /*!< Bit position for DMA_ERQ_ERQ11. */
974 #define BM_DMA_ERQ_ERQ11 (0x00000800U) /*!< Bit mask for DMA_ERQ_ERQ11. */
975 #define BS_DMA_ERQ_ERQ11 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ11. */
977 /*! @brief Read current value of the DMA_ERQ_ERQ11 field. */
978 #define BR_DMA_ERQ_ERQ11(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11))
980 /*! @brief Format value for bitfield DMA_ERQ_ERQ11. */
981 #define BF_DMA_ERQ_ERQ11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ11) & BM_DMA_ERQ_ERQ11)
983 /*! @brief Set the ERQ11 field to a new value. */
984 #define BW_DMA_ERQ_ERQ11(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11) = (v))
988 * @name Register DMA_ERQ, field ERQ12[12] (RW)
991 * - 0 - The DMA request signal for the corresponding channel is disabled
992 * - 1 - The DMA request signal for the corresponding channel is enabled
995 #define BP_DMA_ERQ_ERQ12 (12U) /*!< Bit position for DMA_ERQ_ERQ12. */
996 #define BM_DMA_ERQ_ERQ12 (0x00001000U) /*!< Bit mask for DMA_ERQ_ERQ12. */
997 #define BS_DMA_ERQ_ERQ12 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ12. */
999 /*! @brief Read current value of the DMA_ERQ_ERQ12 field. */
1000 #define BR_DMA_ERQ_ERQ12(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12))
1002 /*! @brief Format value for bitfield DMA_ERQ_ERQ12. */
1003 #define BF_DMA_ERQ_ERQ12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ12) & BM_DMA_ERQ_ERQ12)
1005 /*! @brief Set the ERQ12 field to a new value. */
1006 #define BW_DMA_ERQ_ERQ12(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12) = (v))
1010 * @name Register DMA_ERQ, field ERQ13[13] (RW)
1013 * - 0 - The DMA request signal for the corresponding channel is disabled
1014 * - 1 - The DMA request signal for the corresponding channel is enabled
1017 #define BP_DMA_ERQ_ERQ13 (13U) /*!< Bit position for DMA_ERQ_ERQ13. */
1018 #define BM_DMA_ERQ_ERQ13 (0x00002000U) /*!< Bit mask for DMA_ERQ_ERQ13. */
1019 #define BS_DMA_ERQ_ERQ13 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ13. */
1021 /*! @brief Read current value of the DMA_ERQ_ERQ13 field. */
1022 #define BR_DMA_ERQ_ERQ13(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13))
1024 /*! @brief Format value for bitfield DMA_ERQ_ERQ13. */
1025 #define BF_DMA_ERQ_ERQ13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ13) & BM_DMA_ERQ_ERQ13)
1027 /*! @brief Set the ERQ13 field to a new value. */
1028 #define BW_DMA_ERQ_ERQ13(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13) = (v))
1032 * @name Register DMA_ERQ, field ERQ14[14] (RW)
1035 * - 0 - The DMA request signal for the corresponding channel is disabled
1036 * - 1 - The DMA request signal for the corresponding channel is enabled
1039 #define BP_DMA_ERQ_ERQ14 (14U) /*!< Bit position for DMA_ERQ_ERQ14. */
1040 #define BM_DMA_ERQ_ERQ14 (0x00004000U) /*!< Bit mask for DMA_ERQ_ERQ14. */
1041 #define BS_DMA_ERQ_ERQ14 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ14. */
1043 /*! @brief Read current value of the DMA_ERQ_ERQ14 field. */
1044 #define BR_DMA_ERQ_ERQ14(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14))
1046 /*! @brief Format value for bitfield DMA_ERQ_ERQ14. */
1047 #define BF_DMA_ERQ_ERQ14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ14) & BM_DMA_ERQ_ERQ14)
1049 /*! @brief Set the ERQ14 field to a new value. */
1050 #define BW_DMA_ERQ_ERQ14(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14) = (v))
1054 * @name Register DMA_ERQ, field ERQ15[15] (RW)
1057 * - 0 - The DMA request signal for the corresponding channel is disabled
1058 * - 1 - The DMA request signal for the corresponding channel is enabled
1061 #define BP_DMA_ERQ_ERQ15 (15U) /*!< Bit position for DMA_ERQ_ERQ15. */
1062 #define BM_DMA_ERQ_ERQ15 (0x00008000U) /*!< Bit mask for DMA_ERQ_ERQ15. */
1063 #define BS_DMA_ERQ_ERQ15 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ15. */
1065 /*! @brief Read current value of the DMA_ERQ_ERQ15 field. */
1066 #define BR_DMA_ERQ_ERQ15(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15))
1068 /*! @brief Format value for bitfield DMA_ERQ_ERQ15. */
1069 #define BF_DMA_ERQ_ERQ15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ15) & BM_DMA_ERQ_ERQ15)
1071 /*! @brief Set the ERQ15 field to a new value. */
1072 #define BW_DMA_ERQ_ERQ15(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15) = (v))
1075 /*******************************************************************************
1076 * HW_DMA_EEI - Enable Error Interrupt Register
1077 ******************************************************************************/
1080 * @brief HW_DMA_EEI - Enable Error Interrupt Register (RW)
1082 * Reset value: 0x00000000U
1084 * The EEI register provides a bit map for the 16 channels to enable the error
1085 * interrupt signal for each channel. The state of any given channel's error
1086 * interrupt enable is directly affected by writes to this register; it is also
1087 * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
1088 * interrupt enable for a single channel can easily be modified without the need to
1089 * perform a read-modify-write sequence to the EEI register. The DMA error
1090 * indicator and the error interrupt enable flag must be asserted before an error
1091 * interrupt request for a given channel is asserted to the interrupt controller.
1093 typedef union _hw_dma_eei
1096 struct _hw_dma_eei_bitfields
1098 uint32_t EEI0 : 1; /*!< [0] Enable Error Interrupt 0 */
1099 uint32_t EEI1 : 1; /*!< [1] Enable Error Interrupt 1 */
1100 uint32_t EEI2 : 1; /*!< [2] Enable Error Interrupt 2 */
1101 uint32_t EEI3 : 1; /*!< [3] Enable Error Interrupt 3 */
1102 uint32_t EEI4 : 1; /*!< [4] Enable Error Interrupt 4 */
1103 uint32_t EEI5 : 1; /*!< [5] Enable Error Interrupt 5 */
1104 uint32_t EEI6 : 1; /*!< [6] Enable Error Interrupt 6 */
1105 uint32_t EEI7 : 1; /*!< [7] Enable Error Interrupt 7 */
1106 uint32_t EEI8 : 1; /*!< [8] Enable Error Interrupt 8 */
1107 uint32_t EEI9 : 1; /*!< [9] Enable Error Interrupt 9 */
1108 uint32_t EEI10 : 1; /*!< [10] Enable Error Interrupt 10 */
1109 uint32_t EEI11 : 1; /*!< [11] Enable Error Interrupt 11 */
1110 uint32_t EEI12 : 1; /*!< [12] Enable Error Interrupt 12 */
1111 uint32_t EEI13 : 1; /*!< [13] Enable Error Interrupt 13 */
1112 uint32_t EEI14 : 1; /*!< [14] Enable Error Interrupt 14 */
1113 uint32_t EEI15 : 1; /*!< [15] Enable Error Interrupt 15 */
1114 uint32_t RESERVED0 : 16; /*!< [31:16] */
1119 * @name Constants and macros for entire DMA_EEI register
1122 #define HW_DMA_EEI_ADDR(x) ((x) + 0x14U)
1124 #define HW_DMA_EEI(x) (*(__IO hw_dma_eei_t *) HW_DMA_EEI_ADDR(x))
1125 #define HW_DMA_EEI_RD(x) (HW_DMA_EEI(x).U)
1126 #define HW_DMA_EEI_WR(x, v) (HW_DMA_EEI(x).U = (v))
1127 #define HW_DMA_EEI_SET(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) | (v)))
1128 #define HW_DMA_EEI_CLR(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) & ~(v)))
1129 #define HW_DMA_EEI_TOG(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) ^ (v)))
1133 * Constants & macros for individual DMA_EEI bitfields
1137 * @name Register DMA_EEI, field EEI0[0] (RW)
1140 * - 0 - The error signal for corresponding channel does not generate an error
1142 * - 1 - The assertion of the error signal for corresponding channel generates
1143 * an error interrupt request
1146 #define BP_DMA_EEI_EEI0 (0U) /*!< Bit position for DMA_EEI_EEI0. */
1147 #define BM_DMA_EEI_EEI0 (0x00000001U) /*!< Bit mask for DMA_EEI_EEI0. */
1148 #define BS_DMA_EEI_EEI0 (1U) /*!< Bit field size in bits for DMA_EEI_EEI0. */
1150 /*! @brief Read current value of the DMA_EEI_EEI0 field. */
1151 #define BR_DMA_EEI_EEI0(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0))
1153 /*! @brief Format value for bitfield DMA_EEI_EEI0. */
1154 #define BF_DMA_EEI_EEI0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI0) & BM_DMA_EEI_EEI0)
1156 /*! @brief Set the EEI0 field to a new value. */
1157 #define BW_DMA_EEI_EEI0(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0) = (v))
1161 * @name Register DMA_EEI, field EEI1[1] (RW)
1164 * - 0 - The error signal for corresponding channel does not generate an error
1166 * - 1 - The assertion of the error signal for corresponding channel generates
1167 * an error interrupt request
1170 #define BP_DMA_EEI_EEI1 (1U) /*!< Bit position for DMA_EEI_EEI1. */
1171 #define BM_DMA_EEI_EEI1 (0x00000002U) /*!< Bit mask for DMA_EEI_EEI1. */
1172 #define BS_DMA_EEI_EEI1 (1U) /*!< Bit field size in bits for DMA_EEI_EEI1. */
1174 /*! @brief Read current value of the DMA_EEI_EEI1 field. */
1175 #define BR_DMA_EEI_EEI1(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1))
1177 /*! @brief Format value for bitfield DMA_EEI_EEI1. */
1178 #define BF_DMA_EEI_EEI1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI1) & BM_DMA_EEI_EEI1)
1180 /*! @brief Set the EEI1 field to a new value. */
1181 #define BW_DMA_EEI_EEI1(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1) = (v))
1185 * @name Register DMA_EEI, field EEI2[2] (RW)
1188 * - 0 - The error signal for corresponding channel does not generate an error
1190 * - 1 - The assertion of the error signal for corresponding channel generates
1191 * an error interrupt request
1194 #define BP_DMA_EEI_EEI2 (2U) /*!< Bit position for DMA_EEI_EEI2. */
1195 #define BM_DMA_EEI_EEI2 (0x00000004U) /*!< Bit mask for DMA_EEI_EEI2. */
1196 #define BS_DMA_EEI_EEI2 (1U) /*!< Bit field size in bits for DMA_EEI_EEI2. */
1198 /*! @brief Read current value of the DMA_EEI_EEI2 field. */
1199 #define BR_DMA_EEI_EEI2(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2))
1201 /*! @brief Format value for bitfield DMA_EEI_EEI2. */
1202 #define BF_DMA_EEI_EEI2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI2) & BM_DMA_EEI_EEI2)
1204 /*! @brief Set the EEI2 field to a new value. */
1205 #define BW_DMA_EEI_EEI2(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2) = (v))
1209 * @name Register DMA_EEI, field EEI3[3] (RW)
1212 * - 0 - The error signal for corresponding channel does not generate an error
1214 * - 1 - The assertion of the error signal for corresponding channel generates
1215 * an error interrupt request
1218 #define BP_DMA_EEI_EEI3 (3U) /*!< Bit position for DMA_EEI_EEI3. */
1219 #define BM_DMA_EEI_EEI3 (0x00000008U) /*!< Bit mask for DMA_EEI_EEI3. */
1220 #define BS_DMA_EEI_EEI3 (1U) /*!< Bit field size in bits for DMA_EEI_EEI3. */
1222 /*! @brief Read current value of the DMA_EEI_EEI3 field. */
1223 #define BR_DMA_EEI_EEI3(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3))
1225 /*! @brief Format value for bitfield DMA_EEI_EEI3. */
1226 #define BF_DMA_EEI_EEI3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI3) & BM_DMA_EEI_EEI3)
1228 /*! @brief Set the EEI3 field to a new value. */
1229 #define BW_DMA_EEI_EEI3(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3) = (v))
1233 * @name Register DMA_EEI, field EEI4[4] (RW)
1236 * - 0 - The error signal for corresponding channel does not generate an error
1238 * - 1 - The assertion of the error signal for corresponding channel generates
1239 * an error interrupt request
1242 #define BP_DMA_EEI_EEI4 (4U) /*!< Bit position for DMA_EEI_EEI4. */
1243 #define BM_DMA_EEI_EEI4 (0x00000010U) /*!< Bit mask for DMA_EEI_EEI4. */
1244 #define BS_DMA_EEI_EEI4 (1U) /*!< Bit field size in bits for DMA_EEI_EEI4. */
1246 /*! @brief Read current value of the DMA_EEI_EEI4 field. */
1247 #define BR_DMA_EEI_EEI4(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4))
1249 /*! @brief Format value for bitfield DMA_EEI_EEI4. */
1250 #define BF_DMA_EEI_EEI4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI4) & BM_DMA_EEI_EEI4)
1252 /*! @brief Set the EEI4 field to a new value. */
1253 #define BW_DMA_EEI_EEI4(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4) = (v))
1257 * @name Register DMA_EEI, field EEI5[5] (RW)
1260 * - 0 - The error signal for corresponding channel does not generate an error
1262 * - 1 - The assertion of the error signal for corresponding channel generates
1263 * an error interrupt request
1266 #define BP_DMA_EEI_EEI5 (5U) /*!< Bit position for DMA_EEI_EEI5. */
1267 #define BM_DMA_EEI_EEI5 (0x00000020U) /*!< Bit mask for DMA_EEI_EEI5. */
1268 #define BS_DMA_EEI_EEI5 (1U) /*!< Bit field size in bits for DMA_EEI_EEI5. */
1270 /*! @brief Read current value of the DMA_EEI_EEI5 field. */
1271 #define BR_DMA_EEI_EEI5(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5))
1273 /*! @brief Format value for bitfield DMA_EEI_EEI5. */
1274 #define BF_DMA_EEI_EEI5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI5) & BM_DMA_EEI_EEI5)
1276 /*! @brief Set the EEI5 field to a new value. */
1277 #define BW_DMA_EEI_EEI5(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5) = (v))
1281 * @name Register DMA_EEI, field EEI6[6] (RW)
1284 * - 0 - The error signal for corresponding channel does not generate an error
1286 * - 1 - The assertion of the error signal for corresponding channel generates
1287 * an error interrupt request
1290 #define BP_DMA_EEI_EEI6 (6U) /*!< Bit position for DMA_EEI_EEI6. */
1291 #define BM_DMA_EEI_EEI6 (0x00000040U) /*!< Bit mask for DMA_EEI_EEI6. */
1292 #define BS_DMA_EEI_EEI6 (1U) /*!< Bit field size in bits for DMA_EEI_EEI6. */
1294 /*! @brief Read current value of the DMA_EEI_EEI6 field. */
1295 #define BR_DMA_EEI_EEI6(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6))
1297 /*! @brief Format value for bitfield DMA_EEI_EEI6. */
1298 #define BF_DMA_EEI_EEI6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI6) & BM_DMA_EEI_EEI6)
1300 /*! @brief Set the EEI6 field to a new value. */
1301 #define BW_DMA_EEI_EEI6(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6) = (v))
1305 * @name Register DMA_EEI, field EEI7[7] (RW)
1308 * - 0 - The error signal for corresponding channel does not generate an error
1310 * - 1 - The assertion of the error signal for corresponding channel generates
1311 * an error interrupt request
1314 #define BP_DMA_EEI_EEI7 (7U) /*!< Bit position for DMA_EEI_EEI7. */
1315 #define BM_DMA_EEI_EEI7 (0x00000080U) /*!< Bit mask for DMA_EEI_EEI7. */
1316 #define BS_DMA_EEI_EEI7 (1U) /*!< Bit field size in bits for DMA_EEI_EEI7. */
1318 /*! @brief Read current value of the DMA_EEI_EEI7 field. */
1319 #define BR_DMA_EEI_EEI7(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7))
1321 /*! @brief Format value for bitfield DMA_EEI_EEI7. */
1322 #define BF_DMA_EEI_EEI7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI7) & BM_DMA_EEI_EEI7)
1324 /*! @brief Set the EEI7 field to a new value. */
1325 #define BW_DMA_EEI_EEI7(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7) = (v))
1329 * @name Register DMA_EEI, field EEI8[8] (RW)
1332 * - 0 - The error signal for corresponding channel does not generate an error
1334 * - 1 - The assertion of the error signal for corresponding channel generates
1335 * an error interrupt request
1338 #define BP_DMA_EEI_EEI8 (8U) /*!< Bit position for DMA_EEI_EEI8. */
1339 #define BM_DMA_EEI_EEI8 (0x00000100U) /*!< Bit mask for DMA_EEI_EEI8. */
1340 #define BS_DMA_EEI_EEI8 (1U) /*!< Bit field size in bits for DMA_EEI_EEI8. */
1342 /*! @brief Read current value of the DMA_EEI_EEI8 field. */
1343 #define BR_DMA_EEI_EEI8(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8))
1345 /*! @brief Format value for bitfield DMA_EEI_EEI8. */
1346 #define BF_DMA_EEI_EEI8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI8) & BM_DMA_EEI_EEI8)
1348 /*! @brief Set the EEI8 field to a new value. */
1349 #define BW_DMA_EEI_EEI8(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8) = (v))
1353 * @name Register DMA_EEI, field EEI9[9] (RW)
1356 * - 0 - The error signal for corresponding channel does not generate an error
1358 * - 1 - The assertion of the error signal for corresponding channel generates
1359 * an error interrupt request
1362 #define BP_DMA_EEI_EEI9 (9U) /*!< Bit position for DMA_EEI_EEI9. */
1363 #define BM_DMA_EEI_EEI9 (0x00000200U) /*!< Bit mask for DMA_EEI_EEI9. */
1364 #define BS_DMA_EEI_EEI9 (1U) /*!< Bit field size in bits for DMA_EEI_EEI9. */
1366 /*! @brief Read current value of the DMA_EEI_EEI9 field. */
1367 #define BR_DMA_EEI_EEI9(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9))
1369 /*! @brief Format value for bitfield DMA_EEI_EEI9. */
1370 #define BF_DMA_EEI_EEI9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI9) & BM_DMA_EEI_EEI9)
1372 /*! @brief Set the EEI9 field to a new value. */
1373 #define BW_DMA_EEI_EEI9(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9) = (v))
1377 * @name Register DMA_EEI, field EEI10[10] (RW)
1380 * - 0 - The error signal for corresponding channel does not generate an error
1382 * - 1 - The assertion of the error signal for corresponding channel generates
1383 * an error interrupt request
1386 #define BP_DMA_EEI_EEI10 (10U) /*!< Bit position for DMA_EEI_EEI10. */
1387 #define BM_DMA_EEI_EEI10 (0x00000400U) /*!< Bit mask for DMA_EEI_EEI10. */
1388 #define BS_DMA_EEI_EEI10 (1U) /*!< Bit field size in bits for DMA_EEI_EEI10. */
1390 /*! @brief Read current value of the DMA_EEI_EEI10 field. */
1391 #define BR_DMA_EEI_EEI10(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10))
1393 /*! @brief Format value for bitfield DMA_EEI_EEI10. */
1394 #define BF_DMA_EEI_EEI10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI10) & BM_DMA_EEI_EEI10)
1396 /*! @brief Set the EEI10 field to a new value. */
1397 #define BW_DMA_EEI_EEI10(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10) = (v))
1401 * @name Register DMA_EEI, field EEI11[11] (RW)
1404 * - 0 - The error signal for corresponding channel does not generate an error
1406 * - 1 - The assertion of the error signal for corresponding channel generates
1407 * an error interrupt request
1410 #define BP_DMA_EEI_EEI11 (11U) /*!< Bit position for DMA_EEI_EEI11. */
1411 #define BM_DMA_EEI_EEI11 (0x00000800U) /*!< Bit mask for DMA_EEI_EEI11. */
1412 #define BS_DMA_EEI_EEI11 (1U) /*!< Bit field size in bits for DMA_EEI_EEI11. */
1414 /*! @brief Read current value of the DMA_EEI_EEI11 field. */
1415 #define BR_DMA_EEI_EEI11(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11))
1417 /*! @brief Format value for bitfield DMA_EEI_EEI11. */
1418 #define BF_DMA_EEI_EEI11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI11) & BM_DMA_EEI_EEI11)
1420 /*! @brief Set the EEI11 field to a new value. */
1421 #define BW_DMA_EEI_EEI11(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11) = (v))
1425 * @name Register DMA_EEI, field EEI12[12] (RW)
1428 * - 0 - The error signal for corresponding channel does not generate an error
1430 * - 1 - The assertion of the error signal for corresponding channel generates
1431 * an error interrupt request
1434 #define BP_DMA_EEI_EEI12 (12U) /*!< Bit position for DMA_EEI_EEI12. */
1435 #define BM_DMA_EEI_EEI12 (0x00001000U) /*!< Bit mask for DMA_EEI_EEI12. */
1436 #define BS_DMA_EEI_EEI12 (1U) /*!< Bit field size in bits for DMA_EEI_EEI12. */
1438 /*! @brief Read current value of the DMA_EEI_EEI12 field. */
1439 #define BR_DMA_EEI_EEI12(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12))
1441 /*! @brief Format value for bitfield DMA_EEI_EEI12. */
1442 #define BF_DMA_EEI_EEI12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI12) & BM_DMA_EEI_EEI12)
1444 /*! @brief Set the EEI12 field to a new value. */
1445 #define BW_DMA_EEI_EEI12(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12) = (v))
1449 * @name Register DMA_EEI, field EEI13[13] (RW)
1452 * - 0 - The error signal for corresponding channel does not generate an error
1454 * - 1 - The assertion of the error signal for corresponding channel generates
1455 * an error interrupt request
1458 #define BP_DMA_EEI_EEI13 (13U) /*!< Bit position for DMA_EEI_EEI13. */
1459 #define BM_DMA_EEI_EEI13 (0x00002000U) /*!< Bit mask for DMA_EEI_EEI13. */
1460 #define BS_DMA_EEI_EEI13 (1U) /*!< Bit field size in bits for DMA_EEI_EEI13. */
1462 /*! @brief Read current value of the DMA_EEI_EEI13 field. */
1463 #define BR_DMA_EEI_EEI13(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13))
1465 /*! @brief Format value for bitfield DMA_EEI_EEI13. */
1466 #define BF_DMA_EEI_EEI13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI13) & BM_DMA_EEI_EEI13)
1468 /*! @brief Set the EEI13 field to a new value. */
1469 #define BW_DMA_EEI_EEI13(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13) = (v))
1473 * @name Register DMA_EEI, field EEI14[14] (RW)
1476 * - 0 - The error signal for corresponding channel does not generate an error
1478 * - 1 - The assertion of the error signal for corresponding channel generates
1479 * an error interrupt request
1482 #define BP_DMA_EEI_EEI14 (14U) /*!< Bit position for DMA_EEI_EEI14. */
1483 #define BM_DMA_EEI_EEI14 (0x00004000U) /*!< Bit mask for DMA_EEI_EEI14. */
1484 #define BS_DMA_EEI_EEI14 (1U) /*!< Bit field size in bits for DMA_EEI_EEI14. */
1486 /*! @brief Read current value of the DMA_EEI_EEI14 field. */
1487 #define BR_DMA_EEI_EEI14(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14))
1489 /*! @brief Format value for bitfield DMA_EEI_EEI14. */
1490 #define BF_DMA_EEI_EEI14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI14) & BM_DMA_EEI_EEI14)
1492 /*! @brief Set the EEI14 field to a new value. */
1493 #define BW_DMA_EEI_EEI14(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14) = (v))
1497 * @name Register DMA_EEI, field EEI15[15] (RW)
1500 * - 0 - The error signal for corresponding channel does not generate an error
1502 * - 1 - The assertion of the error signal for corresponding channel generates
1503 * an error interrupt request
1506 #define BP_DMA_EEI_EEI15 (15U) /*!< Bit position for DMA_EEI_EEI15. */
1507 #define BM_DMA_EEI_EEI15 (0x00008000U) /*!< Bit mask for DMA_EEI_EEI15. */
1508 #define BS_DMA_EEI_EEI15 (1U) /*!< Bit field size in bits for DMA_EEI_EEI15. */
1510 /*! @brief Read current value of the DMA_EEI_EEI15 field. */
1511 #define BR_DMA_EEI_EEI15(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15))
1513 /*! @brief Format value for bitfield DMA_EEI_EEI15. */
1514 #define BF_DMA_EEI_EEI15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI15) & BM_DMA_EEI_EEI15)
1516 /*! @brief Set the EEI15 field to a new value. */
1517 #define BW_DMA_EEI_EEI15(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15) = (v))
1520 /*******************************************************************************
1521 * HW_DMA_CEEI - Clear Enable Error Interrupt Register
1522 ******************************************************************************/
1525 * @brief HW_DMA_CEEI - Clear Enable Error Interrupt Register (WO)
1527 * Reset value: 0x00U
1529 * The CEEI provides a simple memory-mapped mechanism to clear a given bit in
1530 * the EEI to disable the error interrupt for a given channel. The data value on a
1531 * register write causes the corresponding bit in the EEI to be cleared. Setting
1532 * the CAEE bit provides a global clear function, forcing the EEI contents to be
1533 * cleared, disabling all DMA request inputs. If the NOP bit is set, the command
1534 * is ignored. This allows you to write multiple-byte registers as a 32-bit word.
1535 * Reads of this register return all zeroes.
1537 typedef union _hw_dma_ceei
1540 struct _hw_dma_ceei_bitfields
1542 uint8_t CEEI : 4; /*!< [3:0] Clear Enable Error Interrupt */
1543 uint8_t RESERVED0 : 2; /*!< [5:4] */
1544 uint8_t CAEE : 1; /*!< [6] Clear All Enable Error Interrupts */
1545 uint8_t NOP : 1; /*!< [7] No Op enable */
1550 * @name Constants and macros for entire DMA_CEEI register
1553 #define HW_DMA_CEEI_ADDR(x) ((x) + 0x18U)
1555 #define HW_DMA_CEEI(x) (*(__O hw_dma_ceei_t *) HW_DMA_CEEI_ADDR(x))
1556 #define HW_DMA_CEEI_RD(x) (HW_DMA_CEEI(x).U)
1557 #define HW_DMA_CEEI_WR(x, v) (HW_DMA_CEEI(x).U = (v))
1561 * Constants & macros for individual DMA_CEEI bitfields
1565 * @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
1567 * Clears the corresponding bit in EEI
1570 #define BP_DMA_CEEI_CEEI (0U) /*!< Bit position for DMA_CEEI_CEEI. */
1571 #define BM_DMA_CEEI_CEEI (0x0FU) /*!< Bit mask for DMA_CEEI_CEEI. */
1572 #define BS_DMA_CEEI_CEEI (4U) /*!< Bit field size in bits for DMA_CEEI_CEEI. */
1574 /*! @brief Format value for bitfield DMA_CEEI_CEEI. */
1575 #define BF_DMA_CEEI_CEEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CEEI) & BM_DMA_CEEI_CEEI)
1577 /*! @brief Set the CEEI field to a new value. */
1578 #define BW_DMA_CEEI_CEEI(x, v) (HW_DMA_CEEI_WR(x, (HW_DMA_CEEI_RD(x) & ~BM_DMA_CEEI_CEEI) | BF_DMA_CEEI_CEEI(v)))
1582 * @name Register DMA_CEEI, field CAEE[6] (WORZ)
1585 * - 0 - Clear only the EEI bit specified in the CEEI field
1586 * - 1 - Clear all bits in EEI
1589 #define BP_DMA_CEEI_CAEE (6U) /*!< Bit position for DMA_CEEI_CAEE. */
1590 #define BM_DMA_CEEI_CAEE (0x40U) /*!< Bit mask for DMA_CEEI_CAEE. */
1591 #define BS_DMA_CEEI_CAEE (1U) /*!< Bit field size in bits for DMA_CEEI_CAEE. */
1593 /*! @brief Format value for bitfield DMA_CEEI_CAEE. */
1594 #define BF_DMA_CEEI_CAEE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CAEE) & BM_DMA_CEEI_CAEE)
1596 /*! @brief Set the CAEE field to a new value. */
1597 #define BW_DMA_CEEI_CAEE(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_CAEE) = (v))
1601 * @name Register DMA_CEEI, field NOP[7] (WORZ)
1604 * - 0 - Normal operation
1605 * - 1 - No operation, ignore the other bits in this register
1608 #define BP_DMA_CEEI_NOP (7U) /*!< Bit position for DMA_CEEI_NOP. */
1609 #define BM_DMA_CEEI_NOP (0x80U) /*!< Bit mask for DMA_CEEI_NOP. */
1610 #define BS_DMA_CEEI_NOP (1U) /*!< Bit field size in bits for DMA_CEEI_NOP. */
1612 /*! @brief Format value for bitfield DMA_CEEI_NOP. */
1613 #define BF_DMA_CEEI_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_NOP) & BM_DMA_CEEI_NOP)
1615 /*! @brief Set the NOP field to a new value. */
1616 #define BW_DMA_CEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_NOP) = (v))
1619 /*******************************************************************************
1620 * HW_DMA_SEEI - Set Enable Error Interrupt Register
1621 ******************************************************************************/
1624 * @brief HW_DMA_SEEI - Set Enable Error Interrupt Register (WO)
1626 * Reset value: 0x00U
1628 * The SEEI provides a simple memory-mapped mechanism to set a given bit in the
1629 * EEI to enable the error interrupt for a given channel. The data value on a
1630 * register write causes the corresponding bit in the EEI to be set. Setting the
1631 * SAEE bit provides a global set function, forcing the entire EEI contents to be
1632 * set. If the NOP bit is set, the command is ignored. This allows you to write
1633 * multiple-byte registers as a 32-bit word. Reads of this register return all
1636 typedef union _hw_dma_seei
1639 struct _hw_dma_seei_bitfields
1641 uint8_t SEEI : 4; /*!< [3:0] Set Enable Error Interrupt */
1642 uint8_t RESERVED0 : 2; /*!< [5:4] */
1643 uint8_t SAEE : 1; /*!< [6] Sets All Enable Error Interrupts */
1644 uint8_t NOP : 1; /*!< [7] No Op enable */
1649 * @name Constants and macros for entire DMA_SEEI register
1652 #define HW_DMA_SEEI_ADDR(x) ((x) + 0x19U)
1654 #define HW_DMA_SEEI(x) (*(__O hw_dma_seei_t *) HW_DMA_SEEI_ADDR(x))
1655 #define HW_DMA_SEEI_RD(x) (HW_DMA_SEEI(x).U)
1656 #define HW_DMA_SEEI_WR(x, v) (HW_DMA_SEEI(x).U = (v))
1660 * Constants & macros for individual DMA_SEEI bitfields
1664 * @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
1666 * Sets the corresponding bit in EEI
1669 #define BP_DMA_SEEI_SEEI (0U) /*!< Bit position for DMA_SEEI_SEEI. */
1670 #define BM_DMA_SEEI_SEEI (0x0FU) /*!< Bit mask for DMA_SEEI_SEEI. */
1671 #define BS_DMA_SEEI_SEEI (4U) /*!< Bit field size in bits for DMA_SEEI_SEEI. */
1673 /*! @brief Format value for bitfield DMA_SEEI_SEEI. */
1674 #define BF_DMA_SEEI_SEEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SEEI) & BM_DMA_SEEI_SEEI)
1676 /*! @brief Set the SEEI field to a new value. */
1677 #define BW_DMA_SEEI_SEEI(x, v) (HW_DMA_SEEI_WR(x, (HW_DMA_SEEI_RD(x) & ~BM_DMA_SEEI_SEEI) | BF_DMA_SEEI_SEEI(v)))
1681 * @name Register DMA_SEEI, field SAEE[6] (WORZ)
1684 * - 0 - Set only the EEI bit specified in the SEEI field.
1685 * - 1 - Sets all bits in EEI
1688 #define BP_DMA_SEEI_SAEE (6U) /*!< Bit position for DMA_SEEI_SAEE. */
1689 #define BM_DMA_SEEI_SAEE (0x40U) /*!< Bit mask for DMA_SEEI_SAEE. */
1690 #define BS_DMA_SEEI_SAEE (1U) /*!< Bit field size in bits for DMA_SEEI_SAEE. */
1692 /*! @brief Format value for bitfield DMA_SEEI_SAEE. */
1693 #define BF_DMA_SEEI_SAEE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SAEE) & BM_DMA_SEEI_SAEE)
1695 /*! @brief Set the SAEE field to a new value. */
1696 #define BW_DMA_SEEI_SAEE(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_SAEE) = (v))
1700 * @name Register DMA_SEEI, field NOP[7] (WORZ)
1703 * - 0 - Normal operation
1704 * - 1 - No operation, ignore the other bits in this register
1707 #define BP_DMA_SEEI_NOP (7U) /*!< Bit position for DMA_SEEI_NOP. */
1708 #define BM_DMA_SEEI_NOP (0x80U) /*!< Bit mask for DMA_SEEI_NOP. */
1709 #define BS_DMA_SEEI_NOP (1U) /*!< Bit field size in bits for DMA_SEEI_NOP. */
1711 /*! @brief Format value for bitfield DMA_SEEI_NOP. */
1712 #define BF_DMA_SEEI_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_NOP) & BM_DMA_SEEI_NOP)
1714 /*! @brief Set the NOP field to a new value. */
1715 #define BW_DMA_SEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_NOP) = (v))
1718 /*******************************************************************************
1719 * HW_DMA_CERQ - Clear Enable Request Register
1720 ******************************************************************************/
1723 * @brief HW_DMA_CERQ - Clear Enable Request Register (WO)
1725 * Reset value: 0x00U
1727 * The CERQ provides a simple memory-mapped mechanism to clear a given bit in
1728 * the ERQ to disable the DMA request for a given channel. The data value on a
1729 * register write causes the corresponding bit in the ERQ to be cleared. Setting the
1730 * CAER bit provides a global clear function, forcing the entire contents of the
1731 * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
1732 * command is ignored. This allows you to write multiple-byte registers as a 32-bit
1733 * word. Reads of this register return all zeroes.
1735 typedef union _hw_dma_cerq
1738 struct _hw_dma_cerq_bitfields
1740 uint8_t CERQ : 4; /*!< [3:0] Clear Enable Request */
1741 uint8_t RESERVED0 : 2; /*!< [5:4] */
1742 uint8_t CAER : 1; /*!< [6] Clear All Enable Requests */
1743 uint8_t NOP : 1; /*!< [7] No Op enable */
1748 * @name Constants and macros for entire DMA_CERQ register
1751 #define HW_DMA_CERQ_ADDR(x) ((x) + 0x1AU)
1753 #define HW_DMA_CERQ(x) (*(__O hw_dma_cerq_t *) HW_DMA_CERQ_ADDR(x))
1754 #define HW_DMA_CERQ_RD(x) (HW_DMA_CERQ(x).U)
1755 #define HW_DMA_CERQ_WR(x, v) (HW_DMA_CERQ(x).U = (v))
1759 * Constants & macros for individual DMA_CERQ bitfields
1763 * @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
1765 * Clears the corresponding bit in ERQ
1768 #define BP_DMA_CERQ_CERQ (0U) /*!< Bit position for DMA_CERQ_CERQ. */
1769 #define BM_DMA_CERQ_CERQ (0x0FU) /*!< Bit mask for DMA_CERQ_CERQ. */
1770 #define BS_DMA_CERQ_CERQ (4U) /*!< Bit field size in bits for DMA_CERQ_CERQ. */
1772 /*! @brief Format value for bitfield DMA_CERQ_CERQ. */
1773 #define BF_DMA_CERQ_CERQ(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CERQ) & BM_DMA_CERQ_CERQ)
1775 /*! @brief Set the CERQ field to a new value. */
1776 #define BW_DMA_CERQ_CERQ(x, v) (HW_DMA_CERQ_WR(x, (HW_DMA_CERQ_RD(x) & ~BM_DMA_CERQ_CERQ) | BF_DMA_CERQ_CERQ(v)))
1780 * @name Register DMA_CERQ, field CAER[6] (WORZ)
1783 * - 0 - Clear only the ERQ bit specified in the CERQ field
1784 * - 1 - Clear all bits in ERQ
1787 #define BP_DMA_CERQ_CAER (6U) /*!< Bit position for DMA_CERQ_CAER. */
1788 #define BM_DMA_CERQ_CAER (0x40U) /*!< Bit mask for DMA_CERQ_CAER. */
1789 #define BS_DMA_CERQ_CAER (1U) /*!< Bit field size in bits for DMA_CERQ_CAER. */
1791 /*! @brief Format value for bitfield DMA_CERQ_CAER. */
1792 #define BF_DMA_CERQ_CAER(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CAER) & BM_DMA_CERQ_CAER)
1794 /*! @brief Set the CAER field to a new value. */
1795 #define BW_DMA_CERQ_CAER(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_CAER) = (v))
1799 * @name Register DMA_CERQ, field NOP[7] (WORZ)
1802 * - 0 - Normal operation
1803 * - 1 - No operation, ignore the other bits in this register
1806 #define BP_DMA_CERQ_NOP (7U) /*!< Bit position for DMA_CERQ_NOP. */
1807 #define BM_DMA_CERQ_NOP (0x80U) /*!< Bit mask for DMA_CERQ_NOP. */
1808 #define BS_DMA_CERQ_NOP (1U) /*!< Bit field size in bits for DMA_CERQ_NOP. */
1810 /*! @brief Format value for bitfield DMA_CERQ_NOP. */
1811 #define BF_DMA_CERQ_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_NOP) & BM_DMA_CERQ_NOP)
1813 /*! @brief Set the NOP field to a new value. */
1814 #define BW_DMA_CERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_NOP) = (v))
1817 /*******************************************************************************
1818 * HW_DMA_SERQ - Set Enable Request Register
1819 ******************************************************************************/
1822 * @brief HW_DMA_SERQ - Set Enable Request Register (WO)
1824 * Reset value: 0x00U
1826 * The SERQ provides a simple memory-mapped mechanism to set a given bit in the
1827 * ERQ to enable the DMA request for a given channel. The data value on a
1828 * register write causes the corresponding bit in the ERQ to be set. Setting the SAER
1829 * bit provides a global set function, forcing the entire contents of ERQ to be
1830 * set. If the NOP bit is set, the command is ignored. This allows you to write
1831 * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
1833 typedef union _hw_dma_serq
1836 struct _hw_dma_serq_bitfields
1838 uint8_t SERQ : 4; /*!< [3:0] Set enable request */
1839 uint8_t RESERVED0 : 2; /*!< [5:4] */
1840 uint8_t SAER : 1; /*!< [6] Set All Enable Requests */
1841 uint8_t NOP : 1; /*!< [7] No Op enable */
1846 * @name Constants and macros for entire DMA_SERQ register
1849 #define HW_DMA_SERQ_ADDR(x) ((x) + 0x1BU)
1851 #define HW_DMA_SERQ(x) (*(__O hw_dma_serq_t *) HW_DMA_SERQ_ADDR(x))
1852 #define HW_DMA_SERQ_RD(x) (HW_DMA_SERQ(x).U)
1853 #define HW_DMA_SERQ_WR(x, v) (HW_DMA_SERQ(x).U = (v))
1857 * Constants & macros for individual DMA_SERQ bitfields
1861 * @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
1863 * Sets the corresponding bit in ERQ
1866 #define BP_DMA_SERQ_SERQ (0U) /*!< Bit position for DMA_SERQ_SERQ. */
1867 #define BM_DMA_SERQ_SERQ (0x0FU) /*!< Bit mask for DMA_SERQ_SERQ. */
1868 #define BS_DMA_SERQ_SERQ (4U) /*!< Bit field size in bits for DMA_SERQ_SERQ. */
1870 /*! @brief Format value for bitfield DMA_SERQ_SERQ. */
1871 #define BF_DMA_SERQ_SERQ(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SERQ) & BM_DMA_SERQ_SERQ)
1873 /*! @brief Set the SERQ field to a new value. */
1874 #define BW_DMA_SERQ_SERQ(x, v) (HW_DMA_SERQ_WR(x, (HW_DMA_SERQ_RD(x) & ~BM_DMA_SERQ_SERQ) | BF_DMA_SERQ_SERQ(v)))
1878 * @name Register DMA_SERQ, field SAER[6] (WORZ)
1881 * - 0 - Set only the ERQ bit specified in the SERQ field
1882 * - 1 - Set all bits in ERQ
1885 #define BP_DMA_SERQ_SAER (6U) /*!< Bit position for DMA_SERQ_SAER. */
1886 #define BM_DMA_SERQ_SAER (0x40U) /*!< Bit mask for DMA_SERQ_SAER. */
1887 #define BS_DMA_SERQ_SAER (1U) /*!< Bit field size in bits for DMA_SERQ_SAER. */
1889 /*! @brief Format value for bitfield DMA_SERQ_SAER. */
1890 #define BF_DMA_SERQ_SAER(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SAER) & BM_DMA_SERQ_SAER)
1892 /*! @brief Set the SAER field to a new value. */
1893 #define BW_DMA_SERQ_SAER(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_SAER) = (v))
1897 * @name Register DMA_SERQ, field NOP[7] (WORZ)
1900 * - 0 - Normal operation
1901 * - 1 - No operation, ignore the other bits in this register
1904 #define BP_DMA_SERQ_NOP (7U) /*!< Bit position for DMA_SERQ_NOP. */
1905 #define BM_DMA_SERQ_NOP (0x80U) /*!< Bit mask for DMA_SERQ_NOP. */
1906 #define BS_DMA_SERQ_NOP (1U) /*!< Bit field size in bits for DMA_SERQ_NOP. */
1908 /*! @brief Format value for bitfield DMA_SERQ_NOP. */
1909 #define BF_DMA_SERQ_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_NOP) & BM_DMA_SERQ_NOP)
1911 /*! @brief Set the NOP field to a new value. */
1912 #define BW_DMA_SERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_NOP) = (v))
1915 /*******************************************************************************
1916 * HW_DMA_CDNE - Clear DONE Status Bit Register
1917 ******************************************************************************/
1920 * @brief HW_DMA_CDNE - Clear DONE Status Bit Register (WO)
1922 * Reset value: 0x00U
1924 * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
1925 * the TCD of the given channel. The data value on a register write causes the
1926 * DONE bit in the corresponding transfer control descriptor to be cleared. Setting
1927 * the CADN bit provides a global clear function, forcing all DONE bits to be
1928 * cleared. If the NOP bit is set, the command is ignored. This allows you to write
1929 * multiple-byte registers as a 32-bit word. Reads of this register return all
1932 typedef union _hw_dma_cdne
1935 struct _hw_dma_cdne_bitfields
1937 uint8_t CDNE : 4; /*!< [3:0] Clear DONE Bit */
1938 uint8_t RESERVED0 : 2; /*!< [5:4] */
1939 uint8_t CADN : 1; /*!< [6] Clears All DONE Bits */
1940 uint8_t NOP : 1; /*!< [7] No Op enable */
1945 * @name Constants and macros for entire DMA_CDNE register
1948 #define HW_DMA_CDNE_ADDR(x) ((x) + 0x1CU)
1950 #define HW_DMA_CDNE(x) (*(__O hw_dma_cdne_t *) HW_DMA_CDNE_ADDR(x))
1951 #define HW_DMA_CDNE_RD(x) (HW_DMA_CDNE(x).U)
1952 #define HW_DMA_CDNE_WR(x, v) (HW_DMA_CDNE(x).U = (v))
1956 * Constants & macros for individual DMA_CDNE bitfields
1960 * @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
1962 * Clears the corresponding bit in TCDn_CSR[DONE]
1965 #define BP_DMA_CDNE_CDNE (0U) /*!< Bit position for DMA_CDNE_CDNE. */
1966 #define BM_DMA_CDNE_CDNE (0x0FU) /*!< Bit mask for DMA_CDNE_CDNE. */
1967 #define BS_DMA_CDNE_CDNE (4U) /*!< Bit field size in bits for DMA_CDNE_CDNE. */
1969 /*! @brief Format value for bitfield DMA_CDNE_CDNE. */
1970 #define BF_DMA_CDNE_CDNE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CDNE) & BM_DMA_CDNE_CDNE)
1972 /*! @brief Set the CDNE field to a new value. */
1973 #define BW_DMA_CDNE_CDNE(x, v) (HW_DMA_CDNE_WR(x, (HW_DMA_CDNE_RD(x) & ~BM_DMA_CDNE_CDNE) | BF_DMA_CDNE_CDNE(v)))
1977 * @name Register DMA_CDNE, field CADN[6] (WORZ)
1980 * - 0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
1981 * - 1 - Clears all bits in TCDn_CSR[DONE]
1984 #define BP_DMA_CDNE_CADN (6U) /*!< Bit position for DMA_CDNE_CADN. */
1985 #define BM_DMA_CDNE_CADN (0x40U) /*!< Bit mask for DMA_CDNE_CADN. */
1986 #define BS_DMA_CDNE_CADN (1U) /*!< Bit field size in bits for DMA_CDNE_CADN. */
1988 /*! @brief Format value for bitfield DMA_CDNE_CADN. */
1989 #define BF_DMA_CDNE_CADN(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CADN) & BM_DMA_CDNE_CADN)
1991 /*! @brief Set the CADN field to a new value. */
1992 #define BW_DMA_CDNE_CADN(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_CADN) = (v))
1996 * @name Register DMA_CDNE, field NOP[7] (WORZ)
1999 * - 0 - Normal operation
2000 * - 1 - No operation, ignore the other bits in this register
2003 #define BP_DMA_CDNE_NOP (7U) /*!< Bit position for DMA_CDNE_NOP. */
2004 #define BM_DMA_CDNE_NOP (0x80U) /*!< Bit mask for DMA_CDNE_NOP. */
2005 #define BS_DMA_CDNE_NOP (1U) /*!< Bit field size in bits for DMA_CDNE_NOP. */
2007 /*! @brief Format value for bitfield DMA_CDNE_NOP. */
2008 #define BF_DMA_CDNE_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_NOP) & BM_DMA_CDNE_NOP)
2010 /*! @brief Set the NOP field to a new value. */
2011 #define BW_DMA_CDNE_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_NOP) = (v))
2014 /*******************************************************************************
2015 * HW_DMA_SSRT - Set START Bit Register
2016 ******************************************************************************/
2019 * @brief HW_DMA_SSRT - Set START Bit Register (WO)
2021 * Reset value: 0x00U
2023 * The SSRT provides a simple memory-mapped mechanism to set the START bit in
2024 * the TCD of the given channel. The data value on a register write causes the
2025 * START bit in the corresponding transfer control descriptor to be set. Setting the
2026 * SAST bit provides a global set function, forcing all START bits to be set. If
2027 * the NOP bit is set, the command is ignored. This allows you to write
2028 * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
2030 typedef union _hw_dma_ssrt
2033 struct _hw_dma_ssrt_bitfields
2035 uint8_t SSRT : 4; /*!< [3:0] Set START Bit */
2036 uint8_t RESERVED0 : 2; /*!< [5:4] */
2037 uint8_t SAST : 1; /*!< [6] Set All START Bits (activates all
2039 uint8_t NOP : 1; /*!< [7] No Op enable */
2044 * @name Constants and macros for entire DMA_SSRT register
2047 #define HW_DMA_SSRT_ADDR(x) ((x) + 0x1DU)
2049 #define HW_DMA_SSRT(x) (*(__O hw_dma_ssrt_t *) HW_DMA_SSRT_ADDR(x))
2050 #define HW_DMA_SSRT_RD(x) (HW_DMA_SSRT(x).U)
2051 #define HW_DMA_SSRT_WR(x, v) (HW_DMA_SSRT(x).U = (v))
2055 * Constants & macros for individual DMA_SSRT bitfields
2059 * @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
2061 * Sets the corresponding bit in TCDn_CSR[START]
2064 #define BP_DMA_SSRT_SSRT (0U) /*!< Bit position for DMA_SSRT_SSRT. */
2065 #define BM_DMA_SSRT_SSRT (0x0FU) /*!< Bit mask for DMA_SSRT_SSRT. */
2066 #define BS_DMA_SSRT_SSRT (4U) /*!< Bit field size in bits for DMA_SSRT_SSRT. */
2068 /*! @brief Format value for bitfield DMA_SSRT_SSRT. */
2069 #define BF_DMA_SSRT_SSRT(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SSRT) & BM_DMA_SSRT_SSRT)
2071 /*! @brief Set the SSRT field to a new value. */
2072 #define BW_DMA_SSRT_SSRT(x, v) (HW_DMA_SSRT_WR(x, (HW_DMA_SSRT_RD(x) & ~BM_DMA_SSRT_SSRT) | BF_DMA_SSRT_SSRT(v)))
2076 * @name Register DMA_SSRT, field SAST[6] (WORZ)
2079 * - 0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
2080 * - 1 - Set all bits in TCDn_CSR[START]
2083 #define BP_DMA_SSRT_SAST (6U) /*!< Bit position for DMA_SSRT_SAST. */
2084 #define BM_DMA_SSRT_SAST (0x40U) /*!< Bit mask for DMA_SSRT_SAST. */
2085 #define BS_DMA_SSRT_SAST (1U) /*!< Bit field size in bits for DMA_SSRT_SAST. */
2087 /*! @brief Format value for bitfield DMA_SSRT_SAST. */
2088 #define BF_DMA_SSRT_SAST(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SAST) & BM_DMA_SSRT_SAST)
2090 /*! @brief Set the SAST field to a new value. */
2091 #define BW_DMA_SSRT_SAST(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_SAST) = (v))
2095 * @name Register DMA_SSRT, field NOP[7] (WORZ)
2098 * - 0 - Normal operation
2099 * - 1 - No operation, ignore the other bits in this register
2102 #define BP_DMA_SSRT_NOP (7U) /*!< Bit position for DMA_SSRT_NOP. */
2103 #define BM_DMA_SSRT_NOP (0x80U) /*!< Bit mask for DMA_SSRT_NOP. */
2104 #define BS_DMA_SSRT_NOP (1U) /*!< Bit field size in bits for DMA_SSRT_NOP. */
2106 /*! @brief Format value for bitfield DMA_SSRT_NOP. */
2107 #define BF_DMA_SSRT_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_NOP) & BM_DMA_SSRT_NOP)
2109 /*! @brief Set the NOP field to a new value. */
2110 #define BW_DMA_SSRT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_NOP) = (v))
2113 /*******************************************************************************
2114 * HW_DMA_CERR - Clear Error Register
2115 ******************************************************************************/
2118 * @brief HW_DMA_CERR - Clear Error Register (WO)
2120 * Reset value: 0x00U
2122 * The CERR provides a simple memory-mapped mechanism to clear a given bit in
2123 * the ERR to disable the error condition flag for a given channel. The given value
2124 * on a register write causes the corresponding bit in the ERR to be cleared.
2125 * Setting the CAEI bit provides a global clear function, forcing the ERR contents
2126 * to be cleared, clearing all channel error indicators. If the NOP bit is set,
2127 * the command is ignored. This allows you to write multiple-byte registers as a
2128 * 32-bit word. Reads of this register return all zeroes.
2130 typedef union _hw_dma_cerr
2133 struct _hw_dma_cerr_bitfields
2135 uint8_t CERR : 4; /*!< [3:0] Clear Error Indicator */
2136 uint8_t RESERVED0 : 2; /*!< [5:4] */
2137 uint8_t CAEI : 1; /*!< [6] Clear All Error Indicators */
2138 uint8_t NOP : 1; /*!< [7] No Op enable */
2143 * @name Constants and macros for entire DMA_CERR register
2146 #define HW_DMA_CERR_ADDR(x) ((x) + 0x1EU)
2148 #define HW_DMA_CERR(x) (*(__O hw_dma_cerr_t *) HW_DMA_CERR_ADDR(x))
2149 #define HW_DMA_CERR_RD(x) (HW_DMA_CERR(x).U)
2150 #define HW_DMA_CERR_WR(x, v) (HW_DMA_CERR(x).U = (v))
2154 * Constants & macros for individual DMA_CERR bitfields
2158 * @name Register DMA_CERR, field CERR[3:0] (WORZ)
2160 * Clears the corresponding bit in ERR
2163 #define BP_DMA_CERR_CERR (0U) /*!< Bit position for DMA_CERR_CERR. */
2164 #define BM_DMA_CERR_CERR (0x0FU) /*!< Bit mask for DMA_CERR_CERR. */
2165 #define BS_DMA_CERR_CERR (4U) /*!< Bit field size in bits for DMA_CERR_CERR. */
2167 /*! @brief Format value for bitfield DMA_CERR_CERR. */
2168 #define BF_DMA_CERR_CERR(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CERR) & BM_DMA_CERR_CERR)
2170 /*! @brief Set the CERR field to a new value. */
2171 #define BW_DMA_CERR_CERR(x, v) (HW_DMA_CERR_WR(x, (HW_DMA_CERR_RD(x) & ~BM_DMA_CERR_CERR) | BF_DMA_CERR_CERR(v)))
2175 * @name Register DMA_CERR, field CAEI[6] (WORZ)
2178 * - 0 - Clear only the ERR bit specified in the CERR field
2179 * - 1 - Clear all bits in ERR
2182 #define BP_DMA_CERR_CAEI (6U) /*!< Bit position for DMA_CERR_CAEI. */
2183 #define BM_DMA_CERR_CAEI (0x40U) /*!< Bit mask for DMA_CERR_CAEI. */
2184 #define BS_DMA_CERR_CAEI (1U) /*!< Bit field size in bits for DMA_CERR_CAEI. */
2186 /*! @brief Format value for bitfield DMA_CERR_CAEI. */
2187 #define BF_DMA_CERR_CAEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CAEI) & BM_DMA_CERR_CAEI)
2189 /*! @brief Set the CAEI field to a new value. */
2190 #define BW_DMA_CERR_CAEI(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_CAEI) = (v))
2194 * @name Register DMA_CERR, field NOP[7] (WORZ)
2197 * - 0 - Normal operation
2198 * - 1 - No operation, ignore the other bits in this register
2201 #define BP_DMA_CERR_NOP (7U) /*!< Bit position for DMA_CERR_NOP. */
2202 #define BM_DMA_CERR_NOP (0x80U) /*!< Bit mask for DMA_CERR_NOP. */
2203 #define BS_DMA_CERR_NOP (1U) /*!< Bit field size in bits for DMA_CERR_NOP. */
2205 /*! @brief Format value for bitfield DMA_CERR_NOP. */
2206 #define BF_DMA_CERR_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_NOP) & BM_DMA_CERR_NOP)
2208 /*! @brief Set the NOP field to a new value. */
2209 #define BW_DMA_CERR_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_NOP) = (v))
2212 /*******************************************************************************
2213 * HW_DMA_CINT - Clear Interrupt Request Register
2214 ******************************************************************************/
2217 * @brief HW_DMA_CINT - Clear Interrupt Request Register (WO)
2219 * Reset value: 0x00U
2221 * The CINT provides a simple, memory-mapped mechanism to clear a given bit in
2222 * the INT to disable the interrupt request for a given channel. The given value
2223 * on a register write causes the corresponding bit in the INT to be cleared.
2224 * Setting the CAIR bit provides a global clear function, forcing the entire contents
2225 * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
2226 * bit is set, the command is ignored. This allows you to write multiple-byte
2227 * registers as a 32-bit word. Reads of this register return all zeroes.
2229 typedef union _hw_dma_cint
2232 struct _hw_dma_cint_bitfields
2234 uint8_t CINT : 4; /*!< [3:0] Clear Interrupt Request */
2235 uint8_t RESERVED0 : 2; /*!< [5:4] */
2236 uint8_t CAIR : 1; /*!< [6] Clear All Interrupt Requests */
2237 uint8_t NOP : 1; /*!< [7] No Op enable */
2242 * @name Constants and macros for entire DMA_CINT register
2245 #define HW_DMA_CINT_ADDR(x) ((x) + 0x1FU)
2247 #define HW_DMA_CINT(x) (*(__O hw_dma_cint_t *) HW_DMA_CINT_ADDR(x))
2248 #define HW_DMA_CINT_RD(x) (HW_DMA_CINT(x).U)
2249 #define HW_DMA_CINT_WR(x, v) (HW_DMA_CINT(x).U = (v))
2253 * Constants & macros for individual DMA_CINT bitfields
2257 * @name Register DMA_CINT, field CINT[3:0] (WORZ)
2259 * Clears the corresponding bit in INT
2262 #define BP_DMA_CINT_CINT (0U) /*!< Bit position for DMA_CINT_CINT. */
2263 #define BM_DMA_CINT_CINT (0x0FU) /*!< Bit mask for DMA_CINT_CINT. */
2264 #define BS_DMA_CINT_CINT (4U) /*!< Bit field size in bits for DMA_CINT_CINT. */
2266 /*! @brief Format value for bitfield DMA_CINT_CINT. */
2267 #define BF_DMA_CINT_CINT(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CINT) & BM_DMA_CINT_CINT)
2269 /*! @brief Set the CINT field to a new value. */
2270 #define BW_DMA_CINT_CINT(x, v) (HW_DMA_CINT_WR(x, (HW_DMA_CINT_RD(x) & ~BM_DMA_CINT_CINT) | BF_DMA_CINT_CINT(v)))
2274 * @name Register DMA_CINT, field CAIR[6] (WORZ)
2277 * - 0 - Clear only the INT bit specified in the CINT field
2278 * - 1 - Clear all bits in INT
2281 #define BP_DMA_CINT_CAIR (6U) /*!< Bit position for DMA_CINT_CAIR. */
2282 #define BM_DMA_CINT_CAIR (0x40U) /*!< Bit mask for DMA_CINT_CAIR. */
2283 #define BS_DMA_CINT_CAIR (1U) /*!< Bit field size in bits for DMA_CINT_CAIR. */
2285 /*! @brief Format value for bitfield DMA_CINT_CAIR. */
2286 #define BF_DMA_CINT_CAIR(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CAIR) & BM_DMA_CINT_CAIR)
2288 /*! @brief Set the CAIR field to a new value. */
2289 #define BW_DMA_CINT_CAIR(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_CAIR) = (v))
2293 * @name Register DMA_CINT, field NOP[7] (WORZ)
2296 * - 0 - Normal operation
2297 * - 1 - No operation, ignore the other bits in this register
2300 #define BP_DMA_CINT_NOP (7U) /*!< Bit position for DMA_CINT_NOP. */
2301 #define BM_DMA_CINT_NOP (0x80U) /*!< Bit mask for DMA_CINT_NOP. */
2302 #define BS_DMA_CINT_NOP (1U) /*!< Bit field size in bits for DMA_CINT_NOP. */
2304 /*! @brief Format value for bitfield DMA_CINT_NOP. */
2305 #define BF_DMA_CINT_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_NOP) & BM_DMA_CINT_NOP)
2307 /*! @brief Set the NOP field to a new value. */
2308 #define BW_DMA_CINT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_NOP) = (v))
2311 /*******************************************************************************
2312 * HW_DMA_INT - Interrupt Request Register
2313 ******************************************************************************/
2316 * @brief HW_DMA_INT - Interrupt Request Register (RW)
2318 * Reset value: 0x00000000U
2320 * The INT register provides a bit map for the 16 channels signaling the
2321 * presence of an interrupt request for each channel. Depending on the appropriate bit
2322 * setting in the transfer-control descriptors, the eDMA engine generates an
2323 * interrupt on data transfer completion. The outputs of this register are directly
2324 * routed to the interrupt controller (INTC). During the interrupt-service routine
2325 * associated with any given channel, it is the software's responsibility to
2326 * clear the appropriate bit, negating the interrupt request. Typically, a write to
2327 * the CINT register in the interrupt service routine is used for this purpose.
2328 * The state of any given channel's interrupt request is directly affected by
2329 * writes to this register; it is also affected by writes to the CINT register. On
2330 * writes to INT, a 1 in any bit position clears the corresponding channel's
2331 * interrupt request. A zero in any bit position has no affect on the corresponding
2332 * channel's current interrupt status. The CINT register is provided so the interrupt
2333 * request for a single channel can easily be cleared without the need to
2334 * perform a read-modify-write sequence to the INT register.
2336 typedef union _hw_dma_int
2339 struct _hw_dma_int_bitfields
2341 uint32_t INT0 : 1; /*!< [0] Interrupt Request 0 */
2342 uint32_t INT1 : 1; /*!< [1] Interrupt Request 1 */
2343 uint32_t INT2 : 1; /*!< [2] Interrupt Request 2 */
2344 uint32_t INT3 : 1; /*!< [3] Interrupt Request 3 */
2345 uint32_t INT4 : 1; /*!< [4] Interrupt Request 4 */
2346 uint32_t INT5 : 1; /*!< [5] Interrupt Request 5 */
2347 uint32_t INT6 : 1; /*!< [6] Interrupt Request 6 */
2348 uint32_t INT7 : 1; /*!< [7] Interrupt Request 7 */
2349 uint32_t INT8 : 1; /*!< [8] Interrupt Request 8 */
2350 uint32_t INT9 : 1; /*!< [9] Interrupt Request 9 */
2351 uint32_t INT10 : 1; /*!< [10] Interrupt Request 10 */
2352 uint32_t INT11 : 1; /*!< [11] Interrupt Request 11 */
2353 uint32_t INT12 : 1; /*!< [12] Interrupt Request 12 */
2354 uint32_t INT13 : 1; /*!< [13] Interrupt Request 13 */
2355 uint32_t INT14 : 1; /*!< [14] Interrupt Request 14 */
2356 uint32_t INT15 : 1; /*!< [15] Interrupt Request 15 */
2357 uint32_t RESERVED0 : 16; /*!< [31:16] */
2362 * @name Constants and macros for entire DMA_INT register
2365 #define HW_DMA_INT_ADDR(x) ((x) + 0x24U)
2367 #define HW_DMA_INT(x) (*(__IO hw_dma_int_t *) HW_DMA_INT_ADDR(x))
2368 #define HW_DMA_INT_RD(x) (HW_DMA_INT(x).U)
2369 #define HW_DMA_INT_WR(x, v) (HW_DMA_INT(x).U = (v))
2370 #define HW_DMA_INT_SET(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) | (v)))
2371 #define HW_DMA_INT_CLR(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) & ~(v)))
2372 #define HW_DMA_INT_TOG(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) ^ (v)))
2376 * Constants & macros for individual DMA_INT bitfields
2380 * @name Register DMA_INT, field INT0[0] (W1C)
2383 * - 0 - The interrupt request for corresponding channel is cleared
2384 * - 1 - The interrupt request for corresponding channel is active
2387 #define BP_DMA_INT_INT0 (0U) /*!< Bit position for DMA_INT_INT0. */
2388 #define BM_DMA_INT_INT0 (0x00000001U) /*!< Bit mask for DMA_INT_INT0. */
2389 #define BS_DMA_INT_INT0 (1U) /*!< Bit field size in bits for DMA_INT_INT0. */
2391 /*! @brief Read current value of the DMA_INT_INT0 field. */
2392 #define BR_DMA_INT_INT0(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0))
2394 /*! @brief Format value for bitfield DMA_INT_INT0. */
2395 #define BF_DMA_INT_INT0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT0) & BM_DMA_INT_INT0)
2397 /*! @brief Set the INT0 field to a new value. */
2398 #define BW_DMA_INT_INT0(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0) = (v))
2402 * @name Register DMA_INT, field INT1[1] (W1C)
2405 * - 0 - The interrupt request for corresponding channel is cleared
2406 * - 1 - The interrupt request for corresponding channel is active
2409 #define BP_DMA_INT_INT1 (1U) /*!< Bit position for DMA_INT_INT1. */
2410 #define BM_DMA_INT_INT1 (0x00000002U) /*!< Bit mask for DMA_INT_INT1. */
2411 #define BS_DMA_INT_INT1 (1U) /*!< Bit field size in bits for DMA_INT_INT1. */
2413 /*! @brief Read current value of the DMA_INT_INT1 field. */
2414 #define BR_DMA_INT_INT1(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1))
2416 /*! @brief Format value for bitfield DMA_INT_INT1. */
2417 #define BF_DMA_INT_INT1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT1) & BM_DMA_INT_INT1)
2419 /*! @brief Set the INT1 field to a new value. */
2420 #define BW_DMA_INT_INT1(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1) = (v))
2424 * @name Register DMA_INT, field INT2[2] (W1C)
2427 * - 0 - The interrupt request for corresponding channel is cleared
2428 * - 1 - The interrupt request for corresponding channel is active
2431 #define BP_DMA_INT_INT2 (2U) /*!< Bit position for DMA_INT_INT2. */
2432 #define BM_DMA_INT_INT2 (0x00000004U) /*!< Bit mask for DMA_INT_INT2. */
2433 #define BS_DMA_INT_INT2 (1U) /*!< Bit field size in bits for DMA_INT_INT2. */
2435 /*! @brief Read current value of the DMA_INT_INT2 field. */
2436 #define BR_DMA_INT_INT2(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2))
2438 /*! @brief Format value for bitfield DMA_INT_INT2. */
2439 #define BF_DMA_INT_INT2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT2) & BM_DMA_INT_INT2)
2441 /*! @brief Set the INT2 field to a new value. */
2442 #define BW_DMA_INT_INT2(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2) = (v))
2446 * @name Register DMA_INT, field INT3[3] (W1C)
2449 * - 0 - The interrupt request for corresponding channel is cleared
2450 * - 1 - The interrupt request for corresponding channel is active
2453 #define BP_DMA_INT_INT3 (3U) /*!< Bit position for DMA_INT_INT3. */
2454 #define BM_DMA_INT_INT3 (0x00000008U) /*!< Bit mask for DMA_INT_INT3. */
2455 #define BS_DMA_INT_INT3 (1U) /*!< Bit field size in bits for DMA_INT_INT3. */
2457 /*! @brief Read current value of the DMA_INT_INT3 field. */
2458 #define BR_DMA_INT_INT3(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3))
2460 /*! @brief Format value for bitfield DMA_INT_INT3. */
2461 #define BF_DMA_INT_INT3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT3) & BM_DMA_INT_INT3)
2463 /*! @brief Set the INT3 field to a new value. */
2464 #define BW_DMA_INT_INT3(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3) = (v))
2468 * @name Register DMA_INT, field INT4[4] (W1C)
2471 * - 0 - The interrupt request for corresponding channel is cleared
2472 * - 1 - The interrupt request for corresponding channel is active
2475 #define BP_DMA_INT_INT4 (4U) /*!< Bit position for DMA_INT_INT4. */
2476 #define BM_DMA_INT_INT4 (0x00000010U) /*!< Bit mask for DMA_INT_INT4. */
2477 #define BS_DMA_INT_INT4 (1U) /*!< Bit field size in bits for DMA_INT_INT4. */
2479 /*! @brief Read current value of the DMA_INT_INT4 field. */
2480 #define BR_DMA_INT_INT4(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4))
2482 /*! @brief Format value for bitfield DMA_INT_INT4. */
2483 #define BF_DMA_INT_INT4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT4) & BM_DMA_INT_INT4)
2485 /*! @brief Set the INT4 field to a new value. */
2486 #define BW_DMA_INT_INT4(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4) = (v))
2490 * @name Register DMA_INT, field INT5[5] (W1C)
2493 * - 0 - The interrupt request for corresponding channel is cleared
2494 * - 1 - The interrupt request for corresponding channel is active
2497 #define BP_DMA_INT_INT5 (5U) /*!< Bit position for DMA_INT_INT5. */
2498 #define BM_DMA_INT_INT5 (0x00000020U) /*!< Bit mask for DMA_INT_INT5. */
2499 #define BS_DMA_INT_INT5 (1U) /*!< Bit field size in bits for DMA_INT_INT5. */
2501 /*! @brief Read current value of the DMA_INT_INT5 field. */
2502 #define BR_DMA_INT_INT5(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5))
2504 /*! @brief Format value for bitfield DMA_INT_INT5. */
2505 #define BF_DMA_INT_INT5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT5) & BM_DMA_INT_INT5)
2507 /*! @brief Set the INT5 field to a new value. */
2508 #define BW_DMA_INT_INT5(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5) = (v))
2512 * @name Register DMA_INT, field INT6[6] (W1C)
2515 * - 0 - The interrupt request for corresponding channel is cleared
2516 * - 1 - The interrupt request for corresponding channel is active
2519 #define BP_DMA_INT_INT6 (6U) /*!< Bit position for DMA_INT_INT6. */
2520 #define BM_DMA_INT_INT6 (0x00000040U) /*!< Bit mask for DMA_INT_INT6. */
2521 #define BS_DMA_INT_INT6 (1U) /*!< Bit field size in bits for DMA_INT_INT6. */
2523 /*! @brief Read current value of the DMA_INT_INT6 field. */
2524 #define BR_DMA_INT_INT6(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6))
2526 /*! @brief Format value for bitfield DMA_INT_INT6. */
2527 #define BF_DMA_INT_INT6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT6) & BM_DMA_INT_INT6)
2529 /*! @brief Set the INT6 field to a new value. */
2530 #define BW_DMA_INT_INT6(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6) = (v))
2534 * @name Register DMA_INT, field INT7[7] (W1C)
2537 * - 0 - The interrupt request for corresponding channel is cleared
2538 * - 1 - The interrupt request for corresponding channel is active
2541 #define BP_DMA_INT_INT7 (7U) /*!< Bit position for DMA_INT_INT7. */
2542 #define BM_DMA_INT_INT7 (0x00000080U) /*!< Bit mask for DMA_INT_INT7. */
2543 #define BS_DMA_INT_INT7 (1U) /*!< Bit field size in bits for DMA_INT_INT7. */
2545 /*! @brief Read current value of the DMA_INT_INT7 field. */
2546 #define BR_DMA_INT_INT7(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7))
2548 /*! @brief Format value for bitfield DMA_INT_INT7. */
2549 #define BF_DMA_INT_INT7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT7) & BM_DMA_INT_INT7)
2551 /*! @brief Set the INT7 field to a new value. */
2552 #define BW_DMA_INT_INT7(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7) = (v))
2556 * @name Register DMA_INT, field INT8[8] (W1C)
2559 * - 0 - The interrupt request for corresponding channel is cleared
2560 * - 1 - The interrupt request for corresponding channel is active
2563 #define BP_DMA_INT_INT8 (8U) /*!< Bit position for DMA_INT_INT8. */
2564 #define BM_DMA_INT_INT8 (0x00000100U) /*!< Bit mask for DMA_INT_INT8. */
2565 #define BS_DMA_INT_INT8 (1U) /*!< Bit field size in bits for DMA_INT_INT8. */
2567 /*! @brief Read current value of the DMA_INT_INT8 field. */
2568 #define BR_DMA_INT_INT8(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8))
2570 /*! @brief Format value for bitfield DMA_INT_INT8. */
2571 #define BF_DMA_INT_INT8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT8) & BM_DMA_INT_INT8)
2573 /*! @brief Set the INT8 field to a new value. */
2574 #define BW_DMA_INT_INT8(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8) = (v))
2578 * @name Register DMA_INT, field INT9[9] (W1C)
2581 * - 0 - The interrupt request for corresponding channel is cleared
2582 * - 1 - The interrupt request for corresponding channel is active
2585 #define BP_DMA_INT_INT9 (9U) /*!< Bit position for DMA_INT_INT9. */
2586 #define BM_DMA_INT_INT9 (0x00000200U) /*!< Bit mask for DMA_INT_INT9. */
2587 #define BS_DMA_INT_INT9 (1U) /*!< Bit field size in bits for DMA_INT_INT9. */
2589 /*! @brief Read current value of the DMA_INT_INT9 field. */
2590 #define BR_DMA_INT_INT9(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9))
2592 /*! @brief Format value for bitfield DMA_INT_INT9. */
2593 #define BF_DMA_INT_INT9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT9) & BM_DMA_INT_INT9)
2595 /*! @brief Set the INT9 field to a new value. */
2596 #define BW_DMA_INT_INT9(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9) = (v))
2600 * @name Register DMA_INT, field INT10[10] (W1C)
2603 * - 0 - The interrupt request for corresponding channel is cleared
2604 * - 1 - The interrupt request for corresponding channel is active
2607 #define BP_DMA_INT_INT10 (10U) /*!< Bit position for DMA_INT_INT10. */
2608 #define BM_DMA_INT_INT10 (0x00000400U) /*!< Bit mask for DMA_INT_INT10. */
2609 #define BS_DMA_INT_INT10 (1U) /*!< Bit field size in bits for DMA_INT_INT10. */
2611 /*! @brief Read current value of the DMA_INT_INT10 field. */
2612 #define BR_DMA_INT_INT10(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10))
2614 /*! @brief Format value for bitfield DMA_INT_INT10. */
2615 #define BF_DMA_INT_INT10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT10) & BM_DMA_INT_INT10)
2617 /*! @brief Set the INT10 field to a new value. */
2618 #define BW_DMA_INT_INT10(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10) = (v))
2622 * @name Register DMA_INT, field INT11[11] (W1C)
2625 * - 0 - The interrupt request for corresponding channel is cleared
2626 * - 1 - The interrupt request for corresponding channel is active
2629 #define BP_DMA_INT_INT11 (11U) /*!< Bit position for DMA_INT_INT11. */
2630 #define BM_DMA_INT_INT11 (0x00000800U) /*!< Bit mask for DMA_INT_INT11. */
2631 #define BS_DMA_INT_INT11 (1U) /*!< Bit field size in bits for DMA_INT_INT11. */
2633 /*! @brief Read current value of the DMA_INT_INT11 field. */
2634 #define BR_DMA_INT_INT11(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11))
2636 /*! @brief Format value for bitfield DMA_INT_INT11. */
2637 #define BF_DMA_INT_INT11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT11) & BM_DMA_INT_INT11)
2639 /*! @brief Set the INT11 field to a new value. */
2640 #define BW_DMA_INT_INT11(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11) = (v))
2644 * @name Register DMA_INT, field INT12[12] (W1C)
2647 * - 0 - The interrupt request for corresponding channel is cleared
2648 * - 1 - The interrupt request for corresponding channel is active
2651 #define BP_DMA_INT_INT12 (12U) /*!< Bit position for DMA_INT_INT12. */
2652 #define BM_DMA_INT_INT12 (0x00001000U) /*!< Bit mask for DMA_INT_INT12. */
2653 #define BS_DMA_INT_INT12 (1U) /*!< Bit field size in bits for DMA_INT_INT12. */
2655 /*! @brief Read current value of the DMA_INT_INT12 field. */
2656 #define BR_DMA_INT_INT12(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12))
2658 /*! @brief Format value for bitfield DMA_INT_INT12. */
2659 #define BF_DMA_INT_INT12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT12) & BM_DMA_INT_INT12)
2661 /*! @brief Set the INT12 field to a new value. */
2662 #define BW_DMA_INT_INT12(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12) = (v))
2666 * @name Register DMA_INT, field INT13[13] (W1C)
2669 * - 0 - The interrupt request for corresponding channel is cleared
2670 * - 1 - The interrupt request for corresponding channel is active
2673 #define BP_DMA_INT_INT13 (13U) /*!< Bit position for DMA_INT_INT13. */
2674 #define BM_DMA_INT_INT13 (0x00002000U) /*!< Bit mask for DMA_INT_INT13. */
2675 #define BS_DMA_INT_INT13 (1U) /*!< Bit field size in bits for DMA_INT_INT13. */
2677 /*! @brief Read current value of the DMA_INT_INT13 field. */
2678 #define BR_DMA_INT_INT13(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13))
2680 /*! @brief Format value for bitfield DMA_INT_INT13. */
2681 #define BF_DMA_INT_INT13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT13) & BM_DMA_INT_INT13)
2683 /*! @brief Set the INT13 field to a new value. */
2684 #define BW_DMA_INT_INT13(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13) = (v))
2688 * @name Register DMA_INT, field INT14[14] (W1C)
2691 * - 0 - The interrupt request for corresponding channel is cleared
2692 * - 1 - The interrupt request for corresponding channel is active
2695 #define BP_DMA_INT_INT14 (14U) /*!< Bit position for DMA_INT_INT14. */
2696 #define BM_DMA_INT_INT14 (0x00004000U) /*!< Bit mask for DMA_INT_INT14. */
2697 #define BS_DMA_INT_INT14 (1U) /*!< Bit field size in bits for DMA_INT_INT14. */
2699 /*! @brief Read current value of the DMA_INT_INT14 field. */
2700 #define BR_DMA_INT_INT14(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14))
2702 /*! @brief Format value for bitfield DMA_INT_INT14. */
2703 #define BF_DMA_INT_INT14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT14) & BM_DMA_INT_INT14)
2705 /*! @brief Set the INT14 field to a new value. */
2706 #define BW_DMA_INT_INT14(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14) = (v))
2710 * @name Register DMA_INT, field INT15[15] (W1C)
2713 * - 0 - The interrupt request for corresponding channel is cleared
2714 * - 1 - The interrupt request for corresponding channel is active
2717 #define BP_DMA_INT_INT15 (15U) /*!< Bit position for DMA_INT_INT15. */
2718 #define BM_DMA_INT_INT15 (0x00008000U) /*!< Bit mask for DMA_INT_INT15. */
2719 #define BS_DMA_INT_INT15 (1U) /*!< Bit field size in bits for DMA_INT_INT15. */
2721 /*! @brief Read current value of the DMA_INT_INT15 field. */
2722 #define BR_DMA_INT_INT15(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15))
2724 /*! @brief Format value for bitfield DMA_INT_INT15. */
2725 #define BF_DMA_INT_INT15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT15) & BM_DMA_INT_INT15)
2727 /*! @brief Set the INT15 field to a new value. */
2728 #define BW_DMA_INT_INT15(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15) = (v))
2731 /*******************************************************************************
2732 * HW_DMA_ERR - Error Register
2733 ******************************************************************************/
2736 * @brief HW_DMA_ERR - Error Register (RW)
2738 * Reset value: 0x00000000U
2740 * The ERR provides a bit map for the 16 channels, signaling the presence of an
2741 * error for each channel. The eDMA engine signals the occurrence of an error
2742 * condition by setting the appropriate bit in this register. The outputs of this
2743 * register are enabled by the contents of the EEI, and then routed to the
2744 * interrupt controller. During the execution of the interrupt-service routine associated
2745 * with any DMA errors, it is software's responsibility to clear the appropriate
2746 * bit, negating the error-interrupt request. Typically, a write to the CERR in
2747 * the interrupt-service routine is used for this purpose. The normal DMA channel
2748 * completion indicators (setting the transfer control descriptor DONE flag and
2749 * the possible assertion of an interrupt request) are not affected when an error
2750 * is detected. The contents of this register can also be polled because a
2751 * non-zero value indicates the presence of a channel error regardless of the state of
2752 * the EEI. The state of any given channel's error indicators is affected by
2753 * writes to this register; it is also affected by writes to the CERR. On writes to
2754 * the ERR, a one in any bit position clears the corresponding channel's error
2755 * status. A zero in any bit position has no affect on the corresponding channel's
2756 * current error status. The CERR is provided so the error indicator for a single
2757 * channel can easily be cleared.
2759 typedef union _hw_dma_err
2762 struct _hw_dma_err_bitfields
2764 uint32_t ERR0 : 1; /*!< [0] Error In Channel 0 */
2765 uint32_t ERR1 : 1; /*!< [1] Error In Channel 1 */
2766 uint32_t ERR2 : 1; /*!< [2] Error In Channel 2 */
2767 uint32_t ERR3 : 1; /*!< [3] Error In Channel 3 */
2768 uint32_t ERR4 : 1; /*!< [4] Error In Channel 4 */
2769 uint32_t ERR5 : 1; /*!< [5] Error In Channel 5 */
2770 uint32_t ERR6 : 1; /*!< [6] Error In Channel 6 */
2771 uint32_t ERR7 : 1; /*!< [7] Error In Channel 7 */
2772 uint32_t ERR8 : 1; /*!< [8] Error In Channel 8 */
2773 uint32_t ERR9 : 1; /*!< [9] Error In Channel 9 */
2774 uint32_t ERR10 : 1; /*!< [10] Error In Channel 10 */
2775 uint32_t ERR11 : 1; /*!< [11] Error In Channel 11 */
2776 uint32_t ERR12 : 1; /*!< [12] Error In Channel 12 */
2777 uint32_t ERR13 : 1; /*!< [13] Error In Channel 13 */
2778 uint32_t ERR14 : 1; /*!< [14] Error In Channel 14 */
2779 uint32_t ERR15 : 1; /*!< [15] Error In Channel 15 */
2780 uint32_t RESERVED0 : 16; /*!< [31:16] */
2785 * @name Constants and macros for entire DMA_ERR register
2788 #define HW_DMA_ERR_ADDR(x) ((x) + 0x2CU)
2790 #define HW_DMA_ERR(x) (*(__IO hw_dma_err_t *) HW_DMA_ERR_ADDR(x))
2791 #define HW_DMA_ERR_RD(x) (HW_DMA_ERR(x).U)
2792 #define HW_DMA_ERR_WR(x, v) (HW_DMA_ERR(x).U = (v))
2793 #define HW_DMA_ERR_SET(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) | (v)))
2794 #define HW_DMA_ERR_CLR(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) & ~(v)))
2795 #define HW_DMA_ERR_TOG(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) ^ (v)))
2799 * Constants & macros for individual DMA_ERR bitfields
2803 * @name Register DMA_ERR, field ERR0[0] (W1C)
2806 * - 0 - An error in the corresponding channel has not occurred
2807 * - 1 - An error in the corresponding channel has occurred
2810 #define BP_DMA_ERR_ERR0 (0U) /*!< Bit position for DMA_ERR_ERR0. */
2811 #define BM_DMA_ERR_ERR0 (0x00000001U) /*!< Bit mask for DMA_ERR_ERR0. */
2812 #define BS_DMA_ERR_ERR0 (1U) /*!< Bit field size in bits for DMA_ERR_ERR0. */
2814 /*! @brief Read current value of the DMA_ERR_ERR0 field. */
2815 #define BR_DMA_ERR_ERR0(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0))
2817 /*! @brief Format value for bitfield DMA_ERR_ERR0. */
2818 #define BF_DMA_ERR_ERR0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR0) & BM_DMA_ERR_ERR0)
2820 /*! @brief Set the ERR0 field to a new value. */
2821 #define BW_DMA_ERR_ERR0(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0) = (v))
2825 * @name Register DMA_ERR, field ERR1[1] (W1C)
2828 * - 0 - An error in the corresponding channel has not occurred
2829 * - 1 - An error in the corresponding channel has occurred
2832 #define BP_DMA_ERR_ERR1 (1U) /*!< Bit position for DMA_ERR_ERR1. */
2833 #define BM_DMA_ERR_ERR1 (0x00000002U) /*!< Bit mask for DMA_ERR_ERR1. */
2834 #define BS_DMA_ERR_ERR1 (1U) /*!< Bit field size in bits for DMA_ERR_ERR1. */
2836 /*! @brief Read current value of the DMA_ERR_ERR1 field. */
2837 #define BR_DMA_ERR_ERR1(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1))
2839 /*! @brief Format value for bitfield DMA_ERR_ERR1. */
2840 #define BF_DMA_ERR_ERR1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR1) & BM_DMA_ERR_ERR1)
2842 /*! @brief Set the ERR1 field to a new value. */
2843 #define BW_DMA_ERR_ERR1(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1) = (v))
2847 * @name Register DMA_ERR, field ERR2[2] (W1C)
2850 * - 0 - An error in the corresponding channel has not occurred
2851 * - 1 - An error in the corresponding channel has occurred
2854 #define BP_DMA_ERR_ERR2 (2U) /*!< Bit position for DMA_ERR_ERR2. */
2855 #define BM_DMA_ERR_ERR2 (0x00000004U) /*!< Bit mask for DMA_ERR_ERR2. */
2856 #define BS_DMA_ERR_ERR2 (1U) /*!< Bit field size in bits for DMA_ERR_ERR2. */
2858 /*! @brief Read current value of the DMA_ERR_ERR2 field. */
2859 #define BR_DMA_ERR_ERR2(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2))
2861 /*! @brief Format value for bitfield DMA_ERR_ERR2. */
2862 #define BF_DMA_ERR_ERR2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR2) & BM_DMA_ERR_ERR2)
2864 /*! @brief Set the ERR2 field to a new value. */
2865 #define BW_DMA_ERR_ERR2(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2) = (v))
2869 * @name Register DMA_ERR, field ERR3[3] (W1C)
2872 * - 0 - An error in the corresponding channel has not occurred
2873 * - 1 - An error in the corresponding channel has occurred
2876 #define BP_DMA_ERR_ERR3 (3U) /*!< Bit position for DMA_ERR_ERR3. */
2877 #define BM_DMA_ERR_ERR3 (0x00000008U) /*!< Bit mask for DMA_ERR_ERR3. */
2878 #define BS_DMA_ERR_ERR3 (1U) /*!< Bit field size in bits for DMA_ERR_ERR3. */
2880 /*! @brief Read current value of the DMA_ERR_ERR3 field. */
2881 #define BR_DMA_ERR_ERR3(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3))
2883 /*! @brief Format value for bitfield DMA_ERR_ERR3. */
2884 #define BF_DMA_ERR_ERR3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR3) & BM_DMA_ERR_ERR3)
2886 /*! @brief Set the ERR3 field to a new value. */
2887 #define BW_DMA_ERR_ERR3(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3) = (v))
2891 * @name Register DMA_ERR, field ERR4[4] (W1C)
2894 * - 0 - An error in the corresponding channel has not occurred
2895 * - 1 - An error in the corresponding channel has occurred
2898 #define BP_DMA_ERR_ERR4 (4U) /*!< Bit position for DMA_ERR_ERR4. */
2899 #define BM_DMA_ERR_ERR4 (0x00000010U) /*!< Bit mask for DMA_ERR_ERR4. */
2900 #define BS_DMA_ERR_ERR4 (1U) /*!< Bit field size in bits for DMA_ERR_ERR4. */
2902 /*! @brief Read current value of the DMA_ERR_ERR4 field. */
2903 #define BR_DMA_ERR_ERR4(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4))
2905 /*! @brief Format value for bitfield DMA_ERR_ERR4. */
2906 #define BF_DMA_ERR_ERR4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR4) & BM_DMA_ERR_ERR4)
2908 /*! @brief Set the ERR4 field to a new value. */
2909 #define BW_DMA_ERR_ERR4(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4) = (v))
2913 * @name Register DMA_ERR, field ERR5[5] (W1C)
2916 * - 0 - An error in the corresponding channel has not occurred
2917 * - 1 - An error in the corresponding channel has occurred
2920 #define BP_DMA_ERR_ERR5 (5U) /*!< Bit position for DMA_ERR_ERR5. */
2921 #define BM_DMA_ERR_ERR5 (0x00000020U) /*!< Bit mask for DMA_ERR_ERR5. */
2922 #define BS_DMA_ERR_ERR5 (1U) /*!< Bit field size in bits for DMA_ERR_ERR5. */
2924 /*! @brief Read current value of the DMA_ERR_ERR5 field. */
2925 #define BR_DMA_ERR_ERR5(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5))
2927 /*! @brief Format value for bitfield DMA_ERR_ERR5. */
2928 #define BF_DMA_ERR_ERR5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR5) & BM_DMA_ERR_ERR5)
2930 /*! @brief Set the ERR5 field to a new value. */
2931 #define BW_DMA_ERR_ERR5(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5) = (v))
2935 * @name Register DMA_ERR, field ERR6[6] (W1C)
2938 * - 0 - An error in the corresponding channel has not occurred
2939 * - 1 - An error in the corresponding channel has occurred
2942 #define BP_DMA_ERR_ERR6 (6U) /*!< Bit position for DMA_ERR_ERR6. */
2943 #define BM_DMA_ERR_ERR6 (0x00000040U) /*!< Bit mask for DMA_ERR_ERR6. */
2944 #define BS_DMA_ERR_ERR6 (1U) /*!< Bit field size in bits for DMA_ERR_ERR6. */
2946 /*! @brief Read current value of the DMA_ERR_ERR6 field. */
2947 #define BR_DMA_ERR_ERR6(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6))
2949 /*! @brief Format value for bitfield DMA_ERR_ERR6. */
2950 #define BF_DMA_ERR_ERR6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR6) & BM_DMA_ERR_ERR6)
2952 /*! @brief Set the ERR6 field to a new value. */
2953 #define BW_DMA_ERR_ERR6(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6) = (v))
2957 * @name Register DMA_ERR, field ERR7[7] (W1C)
2960 * - 0 - An error in the corresponding channel has not occurred
2961 * - 1 - An error in the corresponding channel has occurred
2964 #define BP_DMA_ERR_ERR7 (7U) /*!< Bit position for DMA_ERR_ERR7. */
2965 #define BM_DMA_ERR_ERR7 (0x00000080U) /*!< Bit mask for DMA_ERR_ERR7. */
2966 #define BS_DMA_ERR_ERR7 (1U) /*!< Bit field size in bits for DMA_ERR_ERR7. */
2968 /*! @brief Read current value of the DMA_ERR_ERR7 field. */
2969 #define BR_DMA_ERR_ERR7(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7))
2971 /*! @brief Format value for bitfield DMA_ERR_ERR7. */
2972 #define BF_DMA_ERR_ERR7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR7) & BM_DMA_ERR_ERR7)
2974 /*! @brief Set the ERR7 field to a new value. */
2975 #define BW_DMA_ERR_ERR7(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7) = (v))
2979 * @name Register DMA_ERR, field ERR8[8] (W1C)
2982 * - 0 - An error in the corresponding channel has not occurred
2983 * - 1 - An error in the corresponding channel has occurred
2986 #define BP_DMA_ERR_ERR8 (8U) /*!< Bit position for DMA_ERR_ERR8. */
2987 #define BM_DMA_ERR_ERR8 (0x00000100U) /*!< Bit mask for DMA_ERR_ERR8. */
2988 #define BS_DMA_ERR_ERR8 (1U) /*!< Bit field size in bits for DMA_ERR_ERR8. */
2990 /*! @brief Read current value of the DMA_ERR_ERR8 field. */
2991 #define BR_DMA_ERR_ERR8(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8))
2993 /*! @brief Format value for bitfield DMA_ERR_ERR8. */
2994 #define BF_DMA_ERR_ERR8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR8) & BM_DMA_ERR_ERR8)
2996 /*! @brief Set the ERR8 field to a new value. */
2997 #define BW_DMA_ERR_ERR8(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8) = (v))
3001 * @name Register DMA_ERR, field ERR9[9] (W1C)
3004 * - 0 - An error in the corresponding channel has not occurred
3005 * - 1 - An error in the corresponding channel has occurred
3008 #define BP_DMA_ERR_ERR9 (9U) /*!< Bit position for DMA_ERR_ERR9. */
3009 #define BM_DMA_ERR_ERR9 (0x00000200U) /*!< Bit mask for DMA_ERR_ERR9. */
3010 #define BS_DMA_ERR_ERR9 (1U) /*!< Bit field size in bits for DMA_ERR_ERR9. */
3012 /*! @brief Read current value of the DMA_ERR_ERR9 field. */
3013 #define BR_DMA_ERR_ERR9(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9))
3015 /*! @brief Format value for bitfield DMA_ERR_ERR9. */
3016 #define BF_DMA_ERR_ERR9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR9) & BM_DMA_ERR_ERR9)
3018 /*! @brief Set the ERR9 field to a new value. */
3019 #define BW_DMA_ERR_ERR9(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9) = (v))
3023 * @name Register DMA_ERR, field ERR10[10] (W1C)
3026 * - 0 - An error in the corresponding channel has not occurred
3027 * - 1 - An error in the corresponding channel has occurred
3030 #define BP_DMA_ERR_ERR10 (10U) /*!< Bit position for DMA_ERR_ERR10. */
3031 #define BM_DMA_ERR_ERR10 (0x00000400U) /*!< Bit mask for DMA_ERR_ERR10. */
3032 #define BS_DMA_ERR_ERR10 (1U) /*!< Bit field size in bits for DMA_ERR_ERR10. */
3034 /*! @brief Read current value of the DMA_ERR_ERR10 field. */
3035 #define BR_DMA_ERR_ERR10(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10))
3037 /*! @brief Format value for bitfield DMA_ERR_ERR10. */
3038 #define BF_DMA_ERR_ERR10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR10) & BM_DMA_ERR_ERR10)
3040 /*! @brief Set the ERR10 field to a new value. */
3041 #define BW_DMA_ERR_ERR10(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10) = (v))
3045 * @name Register DMA_ERR, field ERR11[11] (W1C)
3048 * - 0 - An error in the corresponding channel has not occurred
3049 * - 1 - An error in the corresponding channel has occurred
3052 #define BP_DMA_ERR_ERR11 (11U) /*!< Bit position for DMA_ERR_ERR11. */
3053 #define BM_DMA_ERR_ERR11 (0x00000800U) /*!< Bit mask for DMA_ERR_ERR11. */
3054 #define BS_DMA_ERR_ERR11 (1U) /*!< Bit field size in bits for DMA_ERR_ERR11. */
3056 /*! @brief Read current value of the DMA_ERR_ERR11 field. */
3057 #define BR_DMA_ERR_ERR11(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11))
3059 /*! @brief Format value for bitfield DMA_ERR_ERR11. */
3060 #define BF_DMA_ERR_ERR11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR11) & BM_DMA_ERR_ERR11)
3062 /*! @brief Set the ERR11 field to a new value. */
3063 #define BW_DMA_ERR_ERR11(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11) = (v))
3067 * @name Register DMA_ERR, field ERR12[12] (W1C)
3070 * - 0 - An error in the corresponding channel has not occurred
3071 * - 1 - An error in the corresponding channel has occurred
3074 #define BP_DMA_ERR_ERR12 (12U) /*!< Bit position for DMA_ERR_ERR12. */
3075 #define BM_DMA_ERR_ERR12 (0x00001000U) /*!< Bit mask for DMA_ERR_ERR12. */
3076 #define BS_DMA_ERR_ERR12 (1U) /*!< Bit field size in bits for DMA_ERR_ERR12. */
3078 /*! @brief Read current value of the DMA_ERR_ERR12 field. */
3079 #define BR_DMA_ERR_ERR12(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12))
3081 /*! @brief Format value for bitfield DMA_ERR_ERR12. */
3082 #define BF_DMA_ERR_ERR12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR12) & BM_DMA_ERR_ERR12)
3084 /*! @brief Set the ERR12 field to a new value. */
3085 #define BW_DMA_ERR_ERR12(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12) = (v))
3089 * @name Register DMA_ERR, field ERR13[13] (W1C)
3092 * - 0 - An error in the corresponding channel has not occurred
3093 * - 1 - An error in the corresponding channel has occurred
3096 #define BP_DMA_ERR_ERR13 (13U) /*!< Bit position for DMA_ERR_ERR13. */
3097 #define BM_DMA_ERR_ERR13 (0x00002000U) /*!< Bit mask for DMA_ERR_ERR13. */
3098 #define BS_DMA_ERR_ERR13 (1U) /*!< Bit field size in bits for DMA_ERR_ERR13. */
3100 /*! @brief Read current value of the DMA_ERR_ERR13 field. */
3101 #define BR_DMA_ERR_ERR13(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13))
3103 /*! @brief Format value for bitfield DMA_ERR_ERR13. */
3104 #define BF_DMA_ERR_ERR13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR13) & BM_DMA_ERR_ERR13)
3106 /*! @brief Set the ERR13 field to a new value. */
3107 #define BW_DMA_ERR_ERR13(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13) = (v))
3111 * @name Register DMA_ERR, field ERR14[14] (W1C)
3114 * - 0 - An error in the corresponding channel has not occurred
3115 * - 1 - An error in the corresponding channel has occurred
3118 #define BP_DMA_ERR_ERR14 (14U) /*!< Bit position for DMA_ERR_ERR14. */
3119 #define BM_DMA_ERR_ERR14 (0x00004000U) /*!< Bit mask for DMA_ERR_ERR14. */
3120 #define BS_DMA_ERR_ERR14 (1U) /*!< Bit field size in bits for DMA_ERR_ERR14. */
3122 /*! @brief Read current value of the DMA_ERR_ERR14 field. */
3123 #define BR_DMA_ERR_ERR14(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14))
3125 /*! @brief Format value for bitfield DMA_ERR_ERR14. */
3126 #define BF_DMA_ERR_ERR14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR14) & BM_DMA_ERR_ERR14)
3128 /*! @brief Set the ERR14 field to a new value. */
3129 #define BW_DMA_ERR_ERR14(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14) = (v))
3133 * @name Register DMA_ERR, field ERR15[15] (W1C)
3136 * - 0 - An error in the corresponding channel has not occurred
3137 * - 1 - An error in the corresponding channel has occurred
3140 #define BP_DMA_ERR_ERR15 (15U) /*!< Bit position for DMA_ERR_ERR15. */
3141 #define BM_DMA_ERR_ERR15 (0x00008000U) /*!< Bit mask for DMA_ERR_ERR15. */
3142 #define BS_DMA_ERR_ERR15 (1U) /*!< Bit field size in bits for DMA_ERR_ERR15. */
3144 /*! @brief Read current value of the DMA_ERR_ERR15 field. */
3145 #define BR_DMA_ERR_ERR15(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15))
3147 /*! @brief Format value for bitfield DMA_ERR_ERR15. */
3148 #define BF_DMA_ERR_ERR15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR15) & BM_DMA_ERR_ERR15)
3150 /*! @brief Set the ERR15 field to a new value. */
3151 #define BW_DMA_ERR_ERR15(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15) = (v))
3154 /*******************************************************************************
3155 * HW_DMA_HRS - Hardware Request Status Register
3156 ******************************************************************************/
3159 * @brief HW_DMA_HRS - Hardware Request Status Register (RO)
3161 * Reset value: 0x00000000U
3163 * The HRS register provides a bit map for the DMA channels, signaling the
3164 * presence of a hardware request for each channel. The hardware request status bits
3165 * reflect the current state of the register and qualified (via the ERQ fields)
3166 * DMA request signals as seen by the DMA's arbitration logic. This view into the
3167 * hardware request signals may be used for debug purposes. These bits reflect the
3168 * state of the request as seen by the arbitration logic. Therefore, this status
3169 * is affected by the ERQ bits.
3171 typedef union _hw_dma_hrs
3174 struct _hw_dma_hrs_bitfields
3176 uint32_t HRS0 : 1; /*!< [0] Hardware Request Status Channel 0 */
3177 uint32_t HRS1 : 1; /*!< [1] Hardware Request Status Channel 1 */
3178 uint32_t HRS2 : 1; /*!< [2] Hardware Request Status Channel 2 */
3179 uint32_t HRS3 : 1; /*!< [3] Hardware Request Status Channel 3 */
3180 uint32_t HRS4 : 1; /*!< [4] Hardware Request Status Channel 4 */
3181 uint32_t HRS5 : 1; /*!< [5] Hardware Request Status Channel 5 */
3182 uint32_t HRS6 : 1; /*!< [6] Hardware Request Status Channel 6 */
3183 uint32_t HRS7 : 1; /*!< [7] Hardware Request Status Channel 7 */
3184 uint32_t HRS8 : 1; /*!< [8] Hardware Request Status Channel 8 */
3185 uint32_t HRS9 : 1; /*!< [9] Hardware Request Status Channel 9 */
3186 uint32_t HRS10 : 1; /*!< [10] Hardware Request Status Channel 10 */
3187 uint32_t HRS11 : 1; /*!< [11] Hardware Request Status Channel 11 */
3188 uint32_t HRS12 : 1; /*!< [12] Hardware Request Status Channel 12 */
3189 uint32_t HRS13 : 1; /*!< [13] Hardware Request Status Channel 13 */
3190 uint32_t HRS14 : 1; /*!< [14] Hardware Request Status Channel 14 */
3191 uint32_t HRS15 : 1; /*!< [15] Hardware Request Status Channel 15 */
3192 uint32_t RESERVED0 : 16; /*!< [31:16] Reserved */
3197 * @name Constants and macros for entire DMA_HRS register
3200 #define HW_DMA_HRS_ADDR(x) ((x) + 0x34U)
3202 #define HW_DMA_HRS(x) (*(__I hw_dma_hrs_t *) HW_DMA_HRS_ADDR(x))
3203 #define HW_DMA_HRS_RD(x) (HW_DMA_HRS(x).U)
3207 * Constants & macros for individual DMA_HRS bitfields
3211 * @name Register DMA_HRS, field HRS0[0] (RO)
3213 * The HRS bit for its respective channel remains asserted for the period when a
3214 * Hardware Request is Present on the Channel. After the Request is completed
3215 * and Channel is free , the HRS bit is automatically cleared by hardware.
3218 * - 0 - A hardware service request for channel 0 is not present
3219 * - 1 - A hardware service request for channel 0 is present
3222 #define BP_DMA_HRS_HRS0 (0U) /*!< Bit position for DMA_HRS_HRS0. */
3223 #define BM_DMA_HRS_HRS0 (0x00000001U) /*!< Bit mask for DMA_HRS_HRS0. */
3224 #define BS_DMA_HRS_HRS0 (1U) /*!< Bit field size in bits for DMA_HRS_HRS0. */
3226 /*! @brief Read current value of the DMA_HRS_HRS0 field. */
3227 #define BR_DMA_HRS_HRS0(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS0))
3231 * @name Register DMA_HRS, field HRS1[1] (RO)
3233 * The HRS bit for its respective channel remains asserted for the period when a
3234 * Hardware Request is Present on the Channel. After the Request is completed
3235 * and Channel is free , the HRS bit is automatically cleared by hardware.
3238 * - 0 - A hardware service request for channel 1 is not present
3239 * - 1 - A hardware service request for channel 1 is present
3242 #define BP_DMA_HRS_HRS1 (1U) /*!< Bit position for DMA_HRS_HRS1. */
3243 #define BM_DMA_HRS_HRS1 (0x00000002U) /*!< Bit mask for DMA_HRS_HRS1. */
3244 #define BS_DMA_HRS_HRS1 (1U) /*!< Bit field size in bits for DMA_HRS_HRS1. */
3246 /*! @brief Read current value of the DMA_HRS_HRS1 field. */
3247 #define BR_DMA_HRS_HRS1(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS1))
3251 * @name Register DMA_HRS, field HRS2[2] (RO)
3253 * The HRS bit for its respective channel remains asserted for the period when a
3254 * Hardware Request is Present on the Channel. After the Request is completed
3255 * and Channel is free , the HRS bit is automatically cleared by hardware.
3258 * - 0 - A hardware service request for channel 2 is not present
3259 * - 1 - A hardware service request for channel 2 is present
3262 #define BP_DMA_HRS_HRS2 (2U) /*!< Bit position for DMA_HRS_HRS2. */
3263 #define BM_DMA_HRS_HRS2 (0x00000004U) /*!< Bit mask for DMA_HRS_HRS2. */
3264 #define BS_DMA_HRS_HRS2 (1U) /*!< Bit field size in bits for DMA_HRS_HRS2. */
3266 /*! @brief Read current value of the DMA_HRS_HRS2 field. */
3267 #define BR_DMA_HRS_HRS2(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS2))
3271 * @name Register DMA_HRS, field HRS3[3] (RO)
3273 * The HRS bit for its respective channel remains asserted for the period when a
3274 * Hardware Request is Present on the Channel. After the Request is completed
3275 * and Channel is free , the HRS bit is automatically cleared by hardware.
3278 * - 0 - A hardware service request for channel 3 is not present
3279 * - 1 - A hardware service request for channel 3 is present
3282 #define BP_DMA_HRS_HRS3 (3U) /*!< Bit position for DMA_HRS_HRS3. */
3283 #define BM_DMA_HRS_HRS3 (0x00000008U) /*!< Bit mask for DMA_HRS_HRS3. */
3284 #define BS_DMA_HRS_HRS3 (1U) /*!< Bit field size in bits for DMA_HRS_HRS3. */
3286 /*! @brief Read current value of the DMA_HRS_HRS3 field. */
3287 #define BR_DMA_HRS_HRS3(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS3))
3291 * @name Register DMA_HRS, field HRS4[4] (RO)
3293 * The HRS bit for its respective channel remains asserted for the period when a
3294 * Hardware Request is Present on the Channel. After the Request is completed
3295 * and Channel is free , the HRS bit is automatically cleared by hardware.
3298 * - 0 - A hardware service request for channel 4 is not present
3299 * - 1 - A hardware service request for channel 4 is present
3302 #define BP_DMA_HRS_HRS4 (4U) /*!< Bit position for DMA_HRS_HRS4. */
3303 #define BM_DMA_HRS_HRS4 (0x00000010U) /*!< Bit mask for DMA_HRS_HRS4. */
3304 #define BS_DMA_HRS_HRS4 (1U) /*!< Bit field size in bits for DMA_HRS_HRS4. */
3306 /*! @brief Read current value of the DMA_HRS_HRS4 field. */
3307 #define BR_DMA_HRS_HRS4(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS4))
3311 * @name Register DMA_HRS, field HRS5[5] (RO)
3313 * The HRS bit for its respective channel remains asserted for the period when a
3314 * Hardware Request is Present on the Channel. After the Request is completed
3315 * and Channel is free , the HRS bit is automatically cleared by hardware.
3318 * - 0 - A hardware service request for channel 5 is not present
3319 * - 1 - A hardware service request for channel 5 is present
3322 #define BP_DMA_HRS_HRS5 (5U) /*!< Bit position for DMA_HRS_HRS5. */
3323 #define BM_DMA_HRS_HRS5 (0x00000020U) /*!< Bit mask for DMA_HRS_HRS5. */
3324 #define BS_DMA_HRS_HRS5 (1U) /*!< Bit field size in bits for DMA_HRS_HRS5. */
3326 /*! @brief Read current value of the DMA_HRS_HRS5 field. */
3327 #define BR_DMA_HRS_HRS5(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS5))
3331 * @name Register DMA_HRS, field HRS6[6] (RO)
3333 * The HRS bit for its respective channel remains asserted for the period when a
3334 * Hardware Request is Present on the Channel. After the Request is completed
3335 * and Channel is free , the HRS bit is automatically cleared by hardware.
3338 * - 0 - A hardware service request for channel 6 is not present
3339 * - 1 - A hardware service request for channel 6 is present
3342 #define BP_DMA_HRS_HRS6 (6U) /*!< Bit position for DMA_HRS_HRS6. */
3343 #define BM_DMA_HRS_HRS6 (0x00000040U) /*!< Bit mask for DMA_HRS_HRS6. */
3344 #define BS_DMA_HRS_HRS6 (1U) /*!< Bit field size in bits for DMA_HRS_HRS6. */
3346 /*! @brief Read current value of the DMA_HRS_HRS6 field. */
3347 #define BR_DMA_HRS_HRS6(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS6))
3351 * @name Register DMA_HRS, field HRS7[7] (RO)
3353 * The HRS bit for its respective channel remains asserted for the period when a
3354 * Hardware Request is Present on the Channel. After the Request is completed
3355 * and Channel is free , the HRS bit is automatically cleared by hardware.
3358 * - 0 - A hardware service request for channel 7 is not present
3359 * - 1 - A hardware service request for channel 7 is present
3362 #define BP_DMA_HRS_HRS7 (7U) /*!< Bit position for DMA_HRS_HRS7. */
3363 #define BM_DMA_HRS_HRS7 (0x00000080U) /*!< Bit mask for DMA_HRS_HRS7. */
3364 #define BS_DMA_HRS_HRS7 (1U) /*!< Bit field size in bits for DMA_HRS_HRS7. */
3366 /*! @brief Read current value of the DMA_HRS_HRS7 field. */
3367 #define BR_DMA_HRS_HRS7(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS7))
3371 * @name Register DMA_HRS, field HRS8[8] (RO)
3373 * The HRS bit for its respective channel remains asserted for the period when a
3374 * Hardware Request is Present on the Channel. After the Request is completed
3375 * and Channel is free , the HRS bit is automatically cleared by hardware.
3378 * - 0 - A hardware service request for channel 8 is not present
3379 * - 1 - A hardware service request for channel 8 is present
3382 #define BP_DMA_HRS_HRS8 (8U) /*!< Bit position for DMA_HRS_HRS8. */
3383 #define BM_DMA_HRS_HRS8 (0x00000100U) /*!< Bit mask for DMA_HRS_HRS8. */
3384 #define BS_DMA_HRS_HRS8 (1U) /*!< Bit field size in bits for DMA_HRS_HRS8. */
3386 /*! @brief Read current value of the DMA_HRS_HRS8 field. */
3387 #define BR_DMA_HRS_HRS8(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS8))
3391 * @name Register DMA_HRS, field HRS9[9] (RO)
3393 * The HRS bit for its respective channel remains asserted for the period when a
3394 * Hardware Request is Present on the Channel. After the Request is completed
3395 * and Channel is free , the HRS bit is automatically cleared by hardware.
3398 * - 0 - A hardware service request for channel 9 is not present
3399 * - 1 - A hardware service request for channel 9 is present
3402 #define BP_DMA_HRS_HRS9 (9U) /*!< Bit position for DMA_HRS_HRS9. */
3403 #define BM_DMA_HRS_HRS9 (0x00000200U) /*!< Bit mask for DMA_HRS_HRS9. */
3404 #define BS_DMA_HRS_HRS9 (1U) /*!< Bit field size in bits for DMA_HRS_HRS9. */
3406 /*! @brief Read current value of the DMA_HRS_HRS9 field. */
3407 #define BR_DMA_HRS_HRS9(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS9))
3411 * @name Register DMA_HRS, field HRS10[10] (RO)
3413 * The HRS bit for its respective channel remains asserted for the period when a
3414 * Hardware Request is Present on the Channel. After the Request is completed
3415 * and Channel is free , the HRS bit is automatically cleared by hardware.
3418 * - 0 - A hardware service request for channel 10 is not present
3419 * - 1 - A hardware service request for channel 10 is present
3422 #define BP_DMA_HRS_HRS10 (10U) /*!< Bit position for DMA_HRS_HRS10. */
3423 #define BM_DMA_HRS_HRS10 (0x00000400U) /*!< Bit mask for DMA_HRS_HRS10. */
3424 #define BS_DMA_HRS_HRS10 (1U) /*!< Bit field size in bits for DMA_HRS_HRS10. */
3426 /*! @brief Read current value of the DMA_HRS_HRS10 field. */
3427 #define BR_DMA_HRS_HRS10(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS10))
3431 * @name Register DMA_HRS, field HRS11[11] (RO)
3433 * The HRS bit for its respective channel remains asserted for the period when a
3434 * Hardware Request is Present on the Channel. After the Request is completed
3435 * and Channel is free , the HRS bit is automatically cleared by hardware.
3438 * - 0 - A hardware service request for channel 11 is not present
3439 * - 1 - A hardware service request for channel 11 is present
3442 #define BP_DMA_HRS_HRS11 (11U) /*!< Bit position for DMA_HRS_HRS11. */
3443 #define BM_DMA_HRS_HRS11 (0x00000800U) /*!< Bit mask for DMA_HRS_HRS11. */
3444 #define BS_DMA_HRS_HRS11 (1U) /*!< Bit field size in bits for DMA_HRS_HRS11. */
3446 /*! @brief Read current value of the DMA_HRS_HRS11 field. */
3447 #define BR_DMA_HRS_HRS11(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS11))
3451 * @name Register DMA_HRS, field HRS12[12] (RO)
3453 * The HRS bit for its respective channel remains asserted for the period when a
3454 * Hardware Request is Present on the Channel. After the Request is completed
3455 * and Channel is free , the HRS bit is automatically cleared by hardware.
3458 * - 0 - A hardware service request for channel 12 is not present
3459 * - 1 - A hardware service request for channel 12 is present
3462 #define BP_DMA_HRS_HRS12 (12U) /*!< Bit position for DMA_HRS_HRS12. */
3463 #define BM_DMA_HRS_HRS12 (0x00001000U) /*!< Bit mask for DMA_HRS_HRS12. */
3464 #define BS_DMA_HRS_HRS12 (1U) /*!< Bit field size in bits for DMA_HRS_HRS12. */
3466 /*! @brief Read current value of the DMA_HRS_HRS12 field. */
3467 #define BR_DMA_HRS_HRS12(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS12))
3471 * @name Register DMA_HRS, field HRS13[13] (RO)
3473 * The HRS bit for its respective channel remains asserted for the period when a
3474 * Hardware Request is Present on the Channel. After the Request is completed
3475 * and Channel is free , the HRS bit is automatically cleared by hardware.
3478 * - 0 - A hardware service request for channel 13 is not present
3479 * - 1 - A hardware service request for channel 13 is present
3482 #define BP_DMA_HRS_HRS13 (13U) /*!< Bit position for DMA_HRS_HRS13. */
3483 #define BM_DMA_HRS_HRS13 (0x00002000U) /*!< Bit mask for DMA_HRS_HRS13. */
3484 #define BS_DMA_HRS_HRS13 (1U) /*!< Bit field size in bits for DMA_HRS_HRS13. */
3486 /*! @brief Read current value of the DMA_HRS_HRS13 field. */
3487 #define BR_DMA_HRS_HRS13(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS13))
3491 * @name Register DMA_HRS, field HRS14[14] (RO)
3493 * The HRS bit for its respective channel remains asserted for the period when a
3494 * Hardware Request is Present on the Channel. After the Request is completed
3495 * and Channel is free , the HRS bit is automatically cleared by hardware.
3498 * - 0 - A hardware service request for channel 14 is not present
3499 * - 1 - A hardware service request for channel 14 is present
3502 #define BP_DMA_HRS_HRS14 (14U) /*!< Bit position for DMA_HRS_HRS14. */
3503 #define BM_DMA_HRS_HRS14 (0x00004000U) /*!< Bit mask for DMA_HRS_HRS14. */
3504 #define BS_DMA_HRS_HRS14 (1U) /*!< Bit field size in bits for DMA_HRS_HRS14. */
3506 /*! @brief Read current value of the DMA_HRS_HRS14 field. */
3507 #define BR_DMA_HRS_HRS14(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS14))
3511 * @name Register DMA_HRS, field HRS15[15] (RO)
3513 * The HRS bit for its respective channel remains asserted for the period when a
3514 * Hardware Request is Present on the Channel. After the Request is completed
3515 * and Channel is free , the HRS bit is automatically cleared by hardware.
3518 * - 0 - A hardware service request for channel 15 is not present
3519 * - 1 - A hardware service request for channel 15 is present
3522 #define BP_DMA_HRS_HRS15 (15U) /*!< Bit position for DMA_HRS_HRS15. */
3523 #define BM_DMA_HRS_HRS15 (0x00008000U) /*!< Bit mask for DMA_HRS_HRS15. */
3524 #define BS_DMA_HRS_HRS15 (1U) /*!< Bit field size in bits for DMA_HRS_HRS15. */
3526 /*! @brief Read current value of the DMA_HRS_HRS15 field. */
3527 #define BR_DMA_HRS_HRS15(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS15))
3530 /*******************************************************************************
3531 * HW_DMA_EARS - Enable Asynchronous Request in Stop Register
3532 ******************************************************************************/
3535 * @brief HW_DMA_EARS - Enable Asynchronous Request in Stop Register (RW)
3537 * Reset value: 0x00000000U
3539 typedef union _hw_dma_ears
3542 struct _hw_dma_ears_bitfields
3544 uint32_t EDREQ_0 : 1; /*!< [0] Enable asynchronous DMA request in
3545 * stop for channel 0. */
3546 uint32_t EDREQ_1 : 1; /*!< [1] Enable asynchronous DMA request in
3547 * stop for channel 1. */
3548 uint32_t EDREQ_2 : 1; /*!< [2] Enable asynchronous DMA request in
3549 * stop for channel 2. */
3550 uint32_t EDREQ_3 : 1; /*!< [3] Enable asynchronous DMA request in
3551 * stop for channel 3. */
3552 uint32_t EDREQ_4 : 1; /*!< [4] Enable asynchronous DMA request in
3553 * stop for channel 4 */
3554 uint32_t EDREQ_5 : 1; /*!< [5] Enable asynchronous DMA request in
3555 * stop for channel 5 */
3556 uint32_t EDREQ_6 : 1; /*!< [6] Enable asynchronous DMA request in
3557 * stop for channel 6 */
3558 uint32_t EDREQ_7 : 1; /*!< [7] Enable asynchronous DMA request in
3559 * stop for channel 7 */
3560 uint32_t EDREQ_8 : 1; /*!< [8] Enable asynchronous DMA request in
3561 * stop for channel 8 */
3562 uint32_t EDREQ_9 : 1; /*!< [9] Enable asynchronous DMA request in
3563 * stop for channel 9 */
3564 uint32_t EDREQ_10 : 1; /*!< [10] Enable asynchronous DMA request in
3565 * stop for channel 10 */
3566 uint32_t EDREQ_11 : 1; /*!< [11] Enable asynchronous DMA request in
3567 * stop for channel 11 */
3568 uint32_t EDREQ_12 : 1; /*!< [12] Enable asynchronous DMA request in
3569 * stop for channel 12 */
3570 uint32_t EDREQ_13 : 1; /*!< [13] Enable asynchronous DMA request in
3571 * stop for channel 13 */
3572 uint32_t EDREQ_14 : 1; /*!< [14] Enable asynchronous DMA request in
3573 * stop for channel 14 */
3574 uint32_t EDREQ_15 : 1; /*!< [15] Enable asynchronous DMA request in
3575 * stop for channel 15 */
3576 uint32_t RESERVED0 : 16; /*!< [31:16] Reserved. */
3581 * @name Constants and macros for entire DMA_EARS register
3584 #define HW_DMA_EARS_ADDR(x) ((x) + 0x44U)
3586 #define HW_DMA_EARS(x) (*(__IO hw_dma_ears_t *) HW_DMA_EARS_ADDR(x))
3587 #define HW_DMA_EARS_RD(x) (HW_DMA_EARS(x).U)
3588 #define HW_DMA_EARS_WR(x, v) (HW_DMA_EARS(x).U = (v))
3589 #define HW_DMA_EARS_SET(x, v) (HW_DMA_EARS_WR(x, HW_DMA_EARS_RD(x) | (v)))
3590 #define HW_DMA_EARS_CLR(x, v) (HW_DMA_EARS_WR(x, HW_DMA_EARS_RD(x) & ~(v)))
3591 #define HW_DMA_EARS_TOG(x, v) (HW_DMA_EARS_WR(x, HW_DMA_EARS_RD(x) ^ (v)))
3595 * Constants & macros for individual DMA_EARS bitfields
3599 * @name Register DMA_EARS, field EDREQ_0[0] (RW)
3602 * - 0 - Disable asynchronous DMA request for channel 0.
3603 * - 1 - Enable asynchronous DMA request for channel 0.
3606 #define BP_DMA_EARS_EDREQ_0 (0U) /*!< Bit position for DMA_EARS_EDREQ_0. */
3607 #define BM_DMA_EARS_EDREQ_0 (0x00000001U) /*!< Bit mask for DMA_EARS_EDREQ_0. */
3608 #define BS_DMA_EARS_EDREQ_0 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_0. */
3610 /*! @brief Read current value of the DMA_EARS_EDREQ_0 field. */
3611 #define BR_DMA_EARS_EDREQ_0(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_0))
3613 /*! @brief Format value for bitfield DMA_EARS_EDREQ_0. */
3614 #define BF_DMA_EARS_EDREQ_0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_0) & BM_DMA_EARS_EDREQ_0)
3616 /*! @brief Set the EDREQ_0 field to a new value. */
3617 #define BW_DMA_EARS_EDREQ_0(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_0) = (v))
3621 * @name Register DMA_EARS, field EDREQ_1[1] (RW)
3624 * - 0 - Disable asynchronous DMA request for channel 1
3625 * - 1 - Enable asynchronous DMA request for channel 1.
3628 #define BP_DMA_EARS_EDREQ_1 (1U) /*!< Bit position for DMA_EARS_EDREQ_1. */
3629 #define BM_DMA_EARS_EDREQ_1 (0x00000002U) /*!< Bit mask for DMA_EARS_EDREQ_1. */
3630 #define BS_DMA_EARS_EDREQ_1 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_1. */
3632 /*! @brief Read current value of the DMA_EARS_EDREQ_1 field. */
3633 #define BR_DMA_EARS_EDREQ_1(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_1))
3635 /*! @brief Format value for bitfield DMA_EARS_EDREQ_1. */
3636 #define BF_DMA_EARS_EDREQ_1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_1) & BM_DMA_EARS_EDREQ_1)
3638 /*! @brief Set the EDREQ_1 field to a new value. */
3639 #define BW_DMA_EARS_EDREQ_1(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_1) = (v))
3643 * @name Register DMA_EARS, field EDREQ_2[2] (RW)
3646 * - 0 - Disable asynchronous DMA request for channel 2.
3647 * - 1 - Enable asynchronous DMA request for channel 2.
3650 #define BP_DMA_EARS_EDREQ_2 (2U) /*!< Bit position for DMA_EARS_EDREQ_2. */
3651 #define BM_DMA_EARS_EDREQ_2 (0x00000004U) /*!< Bit mask for DMA_EARS_EDREQ_2. */
3652 #define BS_DMA_EARS_EDREQ_2 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_2. */
3654 /*! @brief Read current value of the DMA_EARS_EDREQ_2 field. */
3655 #define BR_DMA_EARS_EDREQ_2(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_2))
3657 /*! @brief Format value for bitfield DMA_EARS_EDREQ_2. */
3658 #define BF_DMA_EARS_EDREQ_2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_2) & BM_DMA_EARS_EDREQ_2)
3660 /*! @brief Set the EDREQ_2 field to a new value. */
3661 #define BW_DMA_EARS_EDREQ_2(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_2) = (v))
3665 * @name Register DMA_EARS, field EDREQ_3[3] (RW)
3668 * - 0 - Disable asynchronous DMA request for channel 3.
3669 * - 1 - Enable asynchronous DMA request for channel 3.
3672 #define BP_DMA_EARS_EDREQ_3 (3U) /*!< Bit position for DMA_EARS_EDREQ_3. */
3673 #define BM_DMA_EARS_EDREQ_3 (0x00000008U) /*!< Bit mask for DMA_EARS_EDREQ_3. */
3674 #define BS_DMA_EARS_EDREQ_3 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_3. */
3676 /*! @brief Read current value of the DMA_EARS_EDREQ_3 field. */
3677 #define BR_DMA_EARS_EDREQ_3(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_3))
3679 /*! @brief Format value for bitfield DMA_EARS_EDREQ_3. */
3680 #define BF_DMA_EARS_EDREQ_3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_3) & BM_DMA_EARS_EDREQ_3)
3682 /*! @brief Set the EDREQ_3 field to a new value. */
3683 #define BW_DMA_EARS_EDREQ_3(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_3) = (v))
3687 * @name Register DMA_EARS, field EDREQ_4[4] (RW)
3690 * - 0 - Disable asynchronous DMA request for channel 4.
3691 * - 1 - Enable asynchronous DMA request for channel 4.
3694 #define BP_DMA_EARS_EDREQ_4 (4U) /*!< Bit position for DMA_EARS_EDREQ_4. */
3695 #define BM_DMA_EARS_EDREQ_4 (0x00000010U) /*!< Bit mask for DMA_EARS_EDREQ_4. */
3696 #define BS_DMA_EARS_EDREQ_4 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_4. */
3698 /*! @brief Read current value of the DMA_EARS_EDREQ_4 field. */
3699 #define BR_DMA_EARS_EDREQ_4(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_4))
3701 /*! @brief Format value for bitfield DMA_EARS_EDREQ_4. */
3702 #define BF_DMA_EARS_EDREQ_4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_4) & BM_DMA_EARS_EDREQ_4)
3704 /*! @brief Set the EDREQ_4 field to a new value. */
3705 #define BW_DMA_EARS_EDREQ_4(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_4) = (v))
3709 * @name Register DMA_EARS, field EDREQ_5[5] (RW)
3712 * - 0 - Disable asynchronous DMA request for channel 5.
3713 * - 1 - Enable asynchronous DMA request for channel 5.
3716 #define BP_DMA_EARS_EDREQ_5 (5U) /*!< Bit position for DMA_EARS_EDREQ_5. */
3717 #define BM_DMA_EARS_EDREQ_5 (0x00000020U) /*!< Bit mask for DMA_EARS_EDREQ_5. */
3718 #define BS_DMA_EARS_EDREQ_5 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_5. */
3720 /*! @brief Read current value of the DMA_EARS_EDREQ_5 field. */
3721 #define BR_DMA_EARS_EDREQ_5(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_5))
3723 /*! @brief Format value for bitfield DMA_EARS_EDREQ_5. */
3724 #define BF_DMA_EARS_EDREQ_5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_5) & BM_DMA_EARS_EDREQ_5)
3726 /*! @brief Set the EDREQ_5 field to a new value. */
3727 #define BW_DMA_EARS_EDREQ_5(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_5) = (v))
3731 * @name Register DMA_EARS, field EDREQ_6[6] (RW)
3734 * - 0 - Disable asynchronous DMA request for channel 6.
3735 * - 1 - Enable asynchronous DMA request for channel 6.
3738 #define BP_DMA_EARS_EDREQ_6 (6U) /*!< Bit position for DMA_EARS_EDREQ_6. */
3739 #define BM_DMA_EARS_EDREQ_6 (0x00000040U) /*!< Bit mask for DMA_EARS_EDREQ_6. */
3740 #define BS_DMA_EARS_EDREQ_6 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_6. */
3742 /*! @brief Read current value of the DMA_EARS_EDREQ_6 field. */
3743 #define BR_DMA_EARS_EDREQ_6(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_6))
3745 /*! @brief Format value for bitfield DMA_EARS_EDREQ_6. */
3746 #define BF_DMA_EARS_EDREQ_6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_6) & BM_DMA_EARS_EDREQ_6)
3748 /*! @brief Set the EDREQ_6 field to a new value. */
3749 #define BW_DMA_EARS_EDREQ_6(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_6) = (v))
3753 * @name Register DMA_EARS, field EDREQ_7[7] (RW)
3756 * - 0 - Disable asynchronous DMA request for channel 7.
3757 * - 1 - Enable asynchronous DMA request for channel 7.
3760 #define BP_DMA_EARS_EDREQ_7 (7U) /*!< Bit position for DMA_EARS_EDREQ_7. */
3761 #define BM_DMA_EARS_EDREQ_7 (0x00000080U) /*!< Bit mask for DMA_EARS_EDREQ_7. */
3762 #define BS_DMA_EARS_EDREQ_7 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_7. */
3764 /*! @brief Read current value of the DMA_EARS_EDREQ_7 field. */
3765 #define BR_DMA_EARS_EDREQ_7(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_7))
3767 /*! @brief Format value for bitfield DMA_EARS_EDREQ_7. */
3768 #define BF_DMA_EARS_EDREQ_7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_7) & BM_DMA_EARS_EDREQ_7)
3770 /*! @brief Set the EDREQ_7 field to a new value. */
3771 #define BW_DMA_EARS_EDREQ_7(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_7) = (v))
3775 * @name Register DMA_EARS, field EDREQ_8[8] (RW)
3778 * - 0 - Disable asynchronous DMA request for channel 8.
3779 * - 1 - Enable asynchronous DMA request for channel 8.
3782 #define BP_DMA_EARS_EDREQ_8 (8U) /*!< Bit position for DMA_EARS_EDREQ_8. */
3783 #define BM_DMA_EARS_EDREQ_8 (0x00000100U) /*!< Bit mask for DMA_EARS_EDREQ_8. */
3784 #define BS_DMA_EARS_EDREQ_8 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_8. */
3786 /*! @brief Read current value of the DMA_EARS_EDREQ_8 field. */
3787 #define BR_DMA_EARS_EDREQ_8(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_8))
3789 /*! @brief Format value for bitfield DMA_EARS_EDREQ_8. */
3790 #define BF_DMA_EARS_EDREQ_8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_8) & BM_DMA_EARS_EDREQ_8)
3792 /*! @brief Set the EDREQ_8 field to a new value. */
3793 #define BW_DMA_EARS_EDREQ_8(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_8) = (v))
3797 * @name Register DMA_EARS, field EDREQ_9[9] (RW)
3800 * - 0 - Disable asynchronous DMA request for channel 9.
3801 * - 1 - Enable asynchronous DMA request for channel 9.
3804 #define BP_DMA_EARS_EDREQ_9 (9U) /*!< Bit position for DMA_EARS_EDREQ_9. */
3805 #define BM_DMA_EARS_EDREQ_9 (0x00000200U) /*!< Bit mask for DMA_EARS_EDREQ_9. */
3806 #define BS_DMA_EARS_EDREQ_9 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_9. */
3808 /*! @brief Read current value of the DMA_EARS_EDREQ_9 field. */
3809 #define BR_DMA_EARS_EDREQ_9(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_9))
3811 /*! @brief Format value for bitfield DMA_EARS_EDREQ_9. */
3812 #define BF_DMA_EARS_EDREQ_9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_9) & BM_DMA_EARS_EDREQ_9)
3814 /*! @brief Set the EDREQ_9 field to a new value. */
3815 #define BW_DMA_EARS_EDREQ_9(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_9) = (v))
3819 * @name Register DMA_EARS, field EDREQ_10[10] (RW)
3822 * - 0 - Disable asynchronous DMA request for channel 10.
3823 * - 1 - Enable asynchronous DMA request for channel 10.
3826 #define BP_DMA_EARS_EDREQ_10 (10U) /*!< Bit position for DMA_EARS_EDREQ_10. */
3827 #define BM_DMA_EARS_EDREQ_10 (0x00000400U) /*!< Bit mask for DMA_EARS_EDREQ_10. */
3828 #define BS_DMA_EARS_EDREQ_10 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_10. */
3830 /*! @brief Read current value of the DMA_EARS_EDREQ_10 field. */
3831 #define BR_DMA_EARS_EDREQ_10(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_10))
3833 /*! @brief Format value for bitfield DMA_EARS_EDREQ_10. */
3834 #define BF_DMA_EARS_EDREQ_10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_10) & BM_DMA_EARS_EDREQ_10)
3836 /*! @brief Set the EDREQ_10 field to a new value. */
3837 #define BW_DMA_EARS_EDREQ_10(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_10) = (v))
3841 * @name Register DMA_EARS, field EDREQ_11[11] (RW)
3844 * - 0 - Disable asynchronous DMA request for channel 11.
3845 * - 1 - Enable asynchronous DMA request for channel 11.
3848 #define BP_DMA_EARS_EDREQ_11 (11U) /*!< Bit position for DMA_EARS_EDREQ_11. */
3849 #define BM_DMA_EARS_EDREQ_11 (0x00000800U) /*!< Bit mask for DMA_EARS_EDREQ_11. */
3850 #define BS_DMA_EARS_EDREQ_11 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_11. */
3852 /*! @brief Read current value of the DMA_EARS_EDREQ_11 field. */
3853 #define BR_DMA_EARS_EDREQ_11(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_11))
3855 /*! @brief Format value for bitfield DMA_EARS_EDREQ_11. */
3856 #define BF_DMA_EARS_EDREQ_11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_11) & BM_DMA_EARS_EDREQ_11)
3858 /*! @brief Set the EDREQ_11 field to a new value. */
3859 #define BW_DMA_EARS_EDREQ_11(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_11) = (v))
3863 * @name Register DMA_EARS, field EDREQ_12[12] (RW)
3866 * - 0 - Disable asynchronous DMA request for channel 12.
3867 * - 1 - Enable asynchronous DMA request for channel 12.
3870 #define BP_DMA_EARS_EDREQ_12 (12U) /*!< Bit position for DMA_EARS_EDREQ_12. */
3871 #define BM_DMA_EARS_EDREQ_12 (0x00001000U) /*!< Bit mask for DMA_EARS_EDREQ_12. */
3872 #define BS_DMA_EARS_EDREQ_12 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_12. */
3874 /*! @brief Read current value of the DMA_EARS_EDREQ_12 field. */
3875 #define BR_DMA_EARS_EDREQ_12(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_12))
3877 /*! @brief Format value for bitfield DMA_EARS_EDREQ_12. */
3878 #define BF_DMA_EARS_EDREQ_12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_12) & BM_DMA_EARS_EDREQ_12)
3880 /*! @brief Set the EDREQ_12 field to a new value. */
3881 #define BW_DMA_EARS_EDREQ_12(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_12) = (v))
3885 * @name Register DMA_EARS, field EDREQ_13[13] (RW)
3888 * - 0 - Disable asynchronous DMA request for channel 13.
3889 * - 1 - Enable asynchronous DMA request for channel 13.
3892 #define BP_DMA_EARS_EDREQ_13 (13U) /*!< Bit position for DMA_EARS_EDREQ_13. */
3893 #define BM_DMA_EARS_EDREQ_13 (0x00002000U) /*!< Bit mask for DMA_EARS_EDREQ_13. */
3894 #define BS_DMA_EARS_EDREQ_13 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_13. */
3896 /*! @brief Read current value of the DMA_EARS_EDREQ_13 field. */
3897 #define BR_DMA_EARS_EDREQ_13(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_13))
3899 /*! @brief Format value for bitfield DMA_EARS_EDREQ_13. */
3900 #define BF_DMA_EARS_EDREQ_13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_13) & BM_DMA_EARS_EDREQ_13)
3902 /*! @brief Set the EDREQ_13 field to a new value. */
3903 #define BW_DMA_EARS_EDREQ_13(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_13) = (v))
3907 * @name Register DMA_EARS, field EDREQ_14[14] (RW)
3910 * - 0 - Disable asynchronous DMA request for channel 14.
3911 * - 1 - Enable asynchronous DMA request for channel 14.
3914 #define BP_DMA_EARS_EDREQ_14 (14U) /*!< Bit position for DMA_EARS_EDREQ_14. */
3915 #define BM_DMA_EARS_EDREQ_14 (0x00004000U) /*!< Bit mask for DMA_EARS_EDREQ_14. */
3916 #define BS_DMA_EARS_EDREQ_14 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_14. */
3918 /*! @brief Read current value of the DMA_EARS_EDREQ_14 field. */
3919 #define BR_DMA_EARS_EDREQ_14(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_14))
3921 /*! @brief Format value for bitfield DMA_EARS_EDREQ_14. */
3922 #define BF_DMA_EARS_EDREQ_14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_14) & BM_DMA_EARS_EDREQ_14)
3924 /*! @brief Set the EDREQ_14 field to a new value. */
3925 #define BW_DMA_EARS_EDREQ_14(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_14) = (v))
3929 * @name Register DMA_EARS, field EDREQ_15[15] (RW)
3932 * - 0 - Disable asynchronous DMA request for channel 15.
3933 * - 1 - Enable asynchronous DMA request for channel 15.
3936 #define BP_DMA_EARS_EDREQ_15 (15U) /*!< Bit position for DMA_EARS_EDREQ_15. */
3937 #define BM_DMA_EARS_EDREQ_15 (0x00008000U) /*!< Bit mask for DMA_EARS_EDREQ_15. */
3938 #define BS_DMA_EARS_EDREQ_15 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_15. */
3940 /*! @brief Read current value of the DMA_EARS_EDREQ_15 field. */
3941 #define BR_DMA_EARS_EDREQ_15(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_15))
3943 /*! @brief Format value for bitfield DMA_EARS_EDREQ_15. */
3944 #define BF_DMA_EARS_EDREQ_15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_15) & BM_DMA_EARS_EDREQ_15)
3946 /*! @brief Set the EDREQ_15 field to a new value. */
3947 #define BW_DMA_EARS_EDREQ_15(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_15) = (v))
3950 /*******************************************************************************
3951 * HW_DMA_DCHPRIn - Channel n Priority Register
3952 ******************************************************************************/
3955 * @brief HW_DMA_DCHPRIn - Channel n Priority Register (RW)
3957 * Reset value: 0x00U
3959 * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
3960 * contents of these registers define the unique priorities associated with each
3961 * channel . The channel priorities are evaluated by numeric value; for example, 0 is
3962 * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
3963 * program the channel priorities with unique values; otherwise, a configuration
3964 * error is reported. The range of the priority value is limited to the values of 0
3967 typedef union _hw_dma_dchprin
3970 struct _hw_dma_dchprin_bitfields
3972 uint8_t CHPRI : 4; /*!< [3:0] Channel n Arbitration Priority */
3973 uint8_t RESERVED0 : 2; /*!< [5:4] */
3974 uint8_t DPA : 1; /*!< [6] Disable Preempt Ability */
3975 uint8_t ECP : 1; /*!< [7] Enable Channel Preemption */
3980 * @name Constants and macros for entire DMA_DCHPRIn register
3983 #define HW_DMA_DCHPRIn_COUNT (16U)
3985 #define HW_DMA_DCHPRIn_ADDR(x, n) ((x) + 0x100U + (0x1U * (n)))
3987 /* DMA channel index to DMA channel priority register array index conversion macro */
3988 #define HW_DMA_DCHPRIn_CHANNEL(n) (((n) & ~0x03U) | (3 - ((n) & 0x03U)))
3990 #define HW_DMA_DCHPRIn(x, n) (*(__IO hw_dma_dchprin_t *) HW_DMA_DCHPRIn_ADDR(x, n))
3991 #define HW_DMA_DCHPRIn_RD(x, n) (HW_DMA_DCHPRIn(x, n).U)
3992 #define HW_DMA_DCHPRIn_WR(x, n, v) (HW_DMA_DCHPRIn(x, n).U = (v))
3993 #define HW_DMA_DCHPRIn_SET(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) | (v)))
3994 #define HW_DMA_DCHPRIn_CLR(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) & ~(v)))
3995 #define HW_DMA_DCHPRIn_TOG(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) ^ (v)))
3999 * Constants & macros for individual DMA_DCHPRIn bitfields
4003 * @name Register DMA_DCHPRIn, field CHPRI[3:0] (RW)
4005 * Channel priority when fixed-priority arbitration is enabled Reset value for
4006 * the channel priority fields, CHPRI, is equal to the corresponding channel
4007 * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
4010 #define BP_DMA_DCHPRIn_CHPRI (0U) /*!< Bit position for DMA_DCHPRIn_CHPRI. */
4011 #define BM_DMA_DCHPRIn_CHPRI (0x0FU) /*!< Bit mask for DMA_DCHPRIn_CHPRI. */
4012 #define BS_DMA_DCHPRIn_CHPRI (4U) /*!< Bit field size in bits for DMA_DCHPRIn_CHPRI. */
4014 /*! @brief Read current value of the DMA_DCHPRIn_CHPRI field. */
4015 #define BR_DMA_DCHPRIn_CHPRI(x, n) (HW_DMA_DCHPRIn(x, n).B.CHPRI)
4017 /*! @brief Format value for bitfield DMA_DCHPRIn_CHPRI. */
4018 #define BF_DMA_DCHPRIn_CHPRI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_CHPRI) & BM_DMA_DCHPRIn_CHPRI)
4020 /*! @brief Set the CHPRI field to a new value. */
4021 #define BW_DMA_DCHPRIn_CHPRI(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, (HW_DMA_DCHPRIn_RD(x, n) & ~BM_DMA_DCHPRIn_CHPRI) | BF_DMA_DCHPRIn_CHPRI(v)))
4025 * @name Register DMA_DCHPRIn, field DPA[6] (RW)
4028 * - 0 - Channel n can suspend a lower priority channel
4029 * - 1 - Channel n cannot suspend any channel, regardless of channel priority
4032 #define BP_DMA_DCHPRIn_DPA (6U) /*!< Bit position for DMA_DCHPRIn_DPA. */
4033 #define BM_DMA_DCHPRIn_DPA (0x40U) /*!< Bit mask for DMA_DCHPRIn_DPA. */
4034 #define BS_DMA_DCHPRIn_DPA (1U) /*!< Bit field size in bits for DMA_DCHPRIn_DPA. */
4036 /*! @brief Read current value of the DMA_DCHPRIn_DPA field. */
4037 #define BR_DMA_DCHPRIn_DPA(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA))
4039 /*! @brief Format value for bitfield DMA_DCHPRIn_DPA. */
4040 #define BF_DMA_DCHPRIn_DPA(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_DPA) & BM_DMA_DCHPRIn_DPA)
4042 /*! @brief Set the DPA field to a new value. */
4043 #define BW_DMA_DCHPRIn_DPA(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA) = (v))
4047 * @name Register DMA_DCHPRIn, field ECP[7] (RW)
4050 * - 0 - Channel n cannot be suspended by a higher priority channel's service
4052 * - 1 - Channel n can be temporarily suspended by the service request of a
4053 * higher priority channel
4056 #define BP_DMA_DCHPRIn_ECP (7U) /*!< Bit position for DMA_DCHPRIn_ECP. */
4057 #define BM_DMA_DCHPRIn_ECP (0x80U) /*!< Bit mask for DMA_DCHPRIn_ECP. */
4058 #define BS_DMA_DCHPRIn_ECP (1U) /*!< Bit field size in bits for DMA_DCHPRIn_ECP. */
4060 /*! @brief Read current value of the DMA_DCHPRIn_ECP field. */
4061 #define BR_DMA_DCHPRIn_ECP(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP))
4063 /*! @brief Format value for bitfield DMA_DCHPRIn_ECP. */
4064 #define BF_DMA_DCHPRIn_ECP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_ECP) & BM_DMA_DCHPRIn_ECP)
4066 /*! @brief Set the ECP field to a new value. */
4067 #define BW_DMA_DCHPRIn_ECP(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP) = (v))
4070 /*******************************************************************************
4071 * HW_DMA_TCDn_SADDR - TCD Source Address
4072 ******************************************************************************/
4075 * @brief HW_DMA_TCDn_SADDR - TCD Source Address (RW)
4077 * Reset value: 0x00000000U
4079 typedef union _hw_dma_tcdn_saddr
4082 struct _hw_dma_tcdn_saddr_bitfields
4084 uint32_t SADDR : 32; /*!< [31:0] Source Address */
4086 } hw_dma_tcdn_saddr_t;
4089 * @name Constants and macros for entire DMA_TCDn_SADDR register
4092 #define HW_DMA_TCDn_SADDR_COUNT (16U)
4094 #define HW_DMA_TCDn_SADDR_ADDR(x, n) ((x) + 0x1000U + (0x20U * (n)))
4096 #define HW_DMA_TCDn_SADDR(x, n) (*(__IO hw_dma_tcdn_saddr_t *) HW_DMA_TCDn_SADDR_ADDR(x, n))
4097 #define HW_DMA_TCDn_SADDR_RD(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
4098 #define HW_DMA_TCDn_SADDR_WR(x, n, v) (HW_DMA_TCDn_SADDR(x, n).U = (v))
4099 #define HW_DMA_TCDn_SADDR_SET(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) | (v)))
4100 #define HW_DMA_TCDn_SADDR_CLR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) & ~(v)))
4101 #define HW_DMA_TCDn_SADDR_TOG(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) ^ (v)))
4105 * Constants & macros for individual DMA_TCDn_SADDR bitfields
4109 * @name Register DMA_TCDn_SADDR, field SADDR[31:0] (RW)
4111 * Memory address pointing to the source data.
4114 #define BP_DMA_TCDn_SADDR_SADDR (0U) /*!< Bit position for DMA_TCDn_SADDR_SADDR. */
4115 #define BM_DMA_TCDn_SADDR_SADDR (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_SADDR_SADDR. */
4116 #define BS_DMA_TCDn_SADDR_SADDR (32U) /*!< Bit field size in bits for DMA_TCDn_SADDR_SADDR. */
4118 /*! @brief Read current value of the DMA_TCDn_SADDR_SADDR field. */
4119 #define BR_DMA_TCDn_SADDR_SADDR(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
4121 /*! @brief Format value for bitfield DMA_TCDn_SADDR_SADDR. */
4122 #define BF_DMA_TCDn_SADDR_SADDR(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_SADDR_SADDR) & BM_DMA_TCDn_SADDR_SADDR)
4124 /*! @brief Set the SADDR field to a new value. */
4125 #define BW_DMA_TCDn_SADDR_SADDR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, v))
4127 /*******************************************************************************
4128 * HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
4129 ******************************************************************************/
4132 * @brief HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset (RW)
4134 * Reset value: 0x0000U
4136 typedef union _hw_dma_tcdn_soff
4139 struct _hw_dma_tcdn_soff_bitfields
4141 uint16_t SOFF : 16; /*!< [15:0] Source address signed offset */
4143 } hw_dma_tcdn_soff_t;
4146 * @name Constants and macros for entire DMA_TCDn_SOFF register
4149 #define HW_DMA_TCDn_SOFF_COUNT (16U)
4151 #define HW_DMA_TCDn_SOFF_ADDR(x, n) ((x) + 0x1004U + (0x20U * (n)))
4153 #define HW_DMA_TCDn_SOFF(x, n) (*(__IO hw_dma_tcdn_soff_t *) HW_DMA_TCDn_SOFF_ADDR(x, n))
4154 #define HW_DMA_TCDn_SOFF_RD(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
4155 #define HW_DMA_TCDn_SOFF_WR(x, n, v) (HW_DMA_TCDn_SOFF(x, n).U = (v))
4156 #define HW_DMA_TCDn_SOFF_SET(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) | (v)))
4157 #define HW_DMA_TCDn_SOFF_CLR(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) & ~(v)))
4158 #define HW_DMA_TCDn_SOFF_TOG(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) ^ (v)))
4162 * Constants & macros for individual DMA_TCDn_SOFF bitfields
4166 * @name Register DMA_TCDn_SOFF, field SOFF[15:0] (RW)
4168 * Sign-extended offset applied to the current source address to form the
4169 * next-state value as each source read is completed.
4172 #define BP_DMA_TCDn_SOFF_SOFF (0U) /*!< Bit position for DMA_TCDn_SOFF_SOFF. */
4173 #define BM_DMA_TCDn_SOFF_SOFF (0xFFFFU) /*!< Bit mask for DMA_TCDn_SOFF_SOFF. */
4174 #define BS_DMA_TCDn_SOFF_SOFF (16U) /*!< Bit field size in bits for DMA_TCDn_SOFF_SOFF. */
4176 /*! @brief Read current value of the DMA_TCDn_SOFF_SOFF field. */
4177 #define BR_DMA_TCDn_SOFF_SOFF(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
4179 /*! @brief Format value for bitfield DMA_TCDn_SOFF_SOFF. */
4180 #define BF_DMA_TCDn_SOFF_SOFF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_SOFF_SOFF) & BM_DMA_TCDn_SOFF_SOFF)
4182 /*! @brief Set the SOFF field to a new value. */
4183 #define BW_DMA_TCDn_SOFF_SOFF(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, v))
4185 /*******************************************************************************
4186 * HW_DMA_TCDn_ATTR - TCD Transfer Attributes
4187 ******************************************************************************/
4190 * @brief HW_DMA_TCDn_ATTR - TCD Transfer Attributes (RW)
4192 * Reset value: 0x0000U
4194 typedef union _hw_dma_tcdn_attr
4197 struct _hw_dma_tcdn_attr_bitfields
4199 uint16_t DSIZE : 3; /*!< [2:0] Destination Data Transfer Size */
4200 uint16_t DMOD : 5; /*!< [7:3] Destination Address Modulo */
4201 uint16_t SSIZE : 3; /*!< [10:8] Source data transfer size */
4202 uint16_t SMOD : 5; /*!< [15:11] Source Address Modulo. */
4204 } hw_dma_tcdn_attr_t;
4207 * @name Constants and macros for entire DMA_TCDn_ATTR register
4210 #define HW_DMA_TCDn_ATTR_COUNT (16U)
4212 #define HW_DMA_TCDn_ATTR_ADDR(x, n) ((x) + 0x1006U + (0x20U * (n)))
4214 #define HW_DMA_TCDn_ATTR(x, n) (*(__IO hw_dma_tcdn_attr_t *) HW_DMA_TCDn_ATTR_ADDR(x, n))
4215 #define HW_DMA_TCDn_ATTR_RD(x, n) (HW_DMA_TCDn_ATTR(x, n).U)
4216 #define HW_DMA_TCDn_ATTR_WR(x, n, v) (HW_DMA_TCDn_ATTR(x, n).U = (v))
4217 #define HW_DMA_TCDn_ATTR_SET(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) | (v)))
4218 #define HW_DMA_TCDn_ATTR_CLR(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) & ~(v)))
4219 #define HW_DMA_TCDn_ATTR_TOG(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) ^ (v)))
4223 * Constants & macros for individual DMA_TCDn_ATTR bitfields
4227 * @name Register DMA_TCDn_ATTR, field DSIZE[2:0] (RW)
4229 * See the SSIZE definition
4232 #define BP_DMA_TCDn_ATTR_DSIZE (0U) /*!< Bit position for DMA_TCDn_ATTR_DSIZE. */
4233 #define BM_DMA_TCDn_ATTR_DSIZE (0x0007U) /*!< Bit mask for DMA_TCDn_ATTR_DSIZE. */
4234 #define BS_DMA_TCDn_ATTR_DSIZE (3U) /*!< Bit field size in bits for DMA_TCDn_ATTR_DSIZE. */
4236 /*! @brief Read current value of the DMA_TCDn_ATTR_DSIZE field. */
4237 #define BR_DMA_TCDn_ATTR_DSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DSIZE)
4239 /*! @brief Format value for bitfield DMA_TCDn_ATTR_DSIZE. */
4240 #define BF_DMA_TCDn_ATTR_DSIZE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_DSIZE) & BM_DMA_TCDn_ATTR_DSIZE)
4242 /*! @brief Set the DSIZE field to a new value. */
4243 #define BW_DMA_TCDn_ATTR_DSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DSIZE) | BF_DMA_TCDn_ATTR_DSIZE(v)))
4247 * @name Register DMA_TCDn_ATTR, field DMOD[7:3] (RW)
4249 * See the SMOD definition
4252 #define BP_DMA_TCDn_ATTR_DMOD (3U) /*!< Bit position for DMA_TCDn_ATTR_DMOD. */
4253 #define BM_DMA_TCDn_ATTR_DMOD (0x00F8U) /*!< Bit mask for DMA_TCDn_ATTR_DMOD. */
4254 #define BS_DMA_TCDn_ATTR_DMOD (5U) /*!< Bit field size in bits for DMA_TCDn_ATTR_DMOD. */
4256 /*! @brief Read current value of the DMA_TCDn_ATTR_DMOD field. */
4257 #define BR_DMA_TCDn_ATTR_DMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DMOD)
4259 /*! @brief Format value for bitfield DMA_TCDn_ATTR_DMOD. */
4260 #define BF_DMA_TCDn_ATTR_DMOD(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_DMOD) & BM_DMA_TCDn_ATTR_DMOD)
4262 /*! @brief Set the DMOD field to a new value. */
4263 #define BW_DMA_TCDn_ATTR_DMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DMOD) | BF_DMA_TCDn_ATTR_DMOD(v)))
4267 * @name Register DMA_TCDn_ATTR, field SSIZE[10:8] (RW)
4269 * The attempted use of a Reserved encoding causes a configuration error.
4282 #define BP_DMA_TCDn_ATTR_SSIZE (8U) /*!< Bit position for DMA_TCDn_ATTR_SSIZE. */
4283 #define BM_DMA_TCDn_ATTR_SSIZE (0x0700U) /*!< Bit mask for DMA_TCDn_ATTR_SSIZE. */
4284 #define BS_DMA_TCDn_ATTR_SSIZE (3U) /*!< Bit field size in bits for DMA_TCDn_ATTR_SSIZE. */
4286 /*! @brief Read current value of the DMA_TCDn_ATTR_SSIZE field. */
4287 #define BR_DMA_TCDn_ATTR_SSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SSIZE)
4289 /*! @brief Format value for bitfield DMA_TCDn_ATTR_SSIZE. */
4290 #define BF_DMA_TCDn_ATTR_SSIZE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_SSIZE) & BM_DMA_TCDn_ATTR_SSIZE)
4292 /*! @brief Set the SSIZE field to a new value. */
4293 #define BW_DMA_TCDn_ATTR_SSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SSIZE) | BF_DMA_TCDn_ATTR_SSIZE(v)))
4297 * @name Register DMA_TCDn_ATTR, field SMOD[15:11] (RW)
4300 * - 0 - Source address modulo feature is disabled
4303 #define BP_DMA_TCDn_ATTR_SMOD (11U) /*!< Bit position for DMA_TCDn_ATTR_SMOD. */
4304 #define BM_DMA_TCDn_ATTR_SMOD (0xF800U) /*!< Bit mask for DMA_TCDn_ATTR_SMOD. */
4305 #define BS_DMA_TCDn_ATTR_SMOD (5U) /*!< Bit field size in bits for DMA_TCDn_ATTR_SMOD. */
4307 /*! @brief Read current value of the DMA_TCDn_ATTR_SMOD field. */
4308 #define BR_DMA_TCDn_ATTR_SMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SMOD)
4310 /*! @brief Format value for bitfield DMA_TCDn_ATTR_SMOD. */
4311 #define BF_DMA_TCDn_ATTR_SMOD(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_SMOD) & BM_DMA_TCDn_ATTR_SMOD)
4313 /*! @brief Set the SMOD field to a new value. */
4314 #define BW_DMA_TCDn_ATTR_SMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SMOD) | BF_DMA_TCDn_ATTR_SMOD(v)))
4316 /*******************************************************************************
4317 * HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
4318 ******************************************************************************/
4321 * @brief HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
4323 * Reset value: 0x00000000U
4325 * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
4326 * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
4327 * register to use depends on whether minor loop mapping is disabled, enabled but not
4328 * used for this channel, or enabled and used. TCD word 2 is defined as follows
4329 * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
4330 * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
4331 * for TCD word 2's definition.
4333 typedef union _hw_dma_tcdn_nbytes_mlno
4336 struct _hw_dma_tcdn_nbytes_mlno_bitfields
4338 uint32_t NBYTES : 32; /*!< [31:0] Minor Byte Transfer Count */
4340 } hw_dma_tcdn_nbytes_mlno_t;
4343 * @name Constants and macros for entire DMA_TCDn_NBYTES_MLNO register
4346 #define HW_DMA_TCDn_NBYTES_MLNO_COUNT (16U)
4348 #define HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
4350 #define HW_DMA_TCDn_NBYTES_MLNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mlno_t *) HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n))
4351 #define HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
4352 #define HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U = (v))
4353 #define HW_DMA_TCDn_NBYTES_MLNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) | (v)))
4354 #define HW_DMA_TCDn_NBYTES_MLNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) & ~(v)))
4355 #define HW_DMA_TCDn_NBYTES_MLNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) ^ (v)))
4359 * Constants & macros for individual DMA_TCDn_NBYTES_MLNO bitfields
4363 * @name Register DMA_TCDn_NBYTES_MLNO, field NBYTES[31:0] (RW)
4365 * Number of bytes to be transferred in each service request of the channel. As
4366 * a channel activates, the appropriate TCD contents load into the eDMA engine,
4367 * and the appropriate reads and writes perform until the minor byte transfer
4368 * count has transferred. This is an indivisible operation and cannot be halted.
4369 * (Although, it may be stalled by using the bandwidth control field, or via
4370 * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
4371 * written back into the TCD memory, the major iteration count is decremented and
4372 * restored to the TCD memory. If the major iteration count is completed, additional
4373 * processing is performed. An NBYTES value of 0x0000_0000 is interpreted as a 4
4377 #define BP_DMA_TCDn_NBYTES_MLNO_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLNO_NBYTES. */
4378 #define BM_DMA_TCDn_NBYTES_MLNO_NBYTES (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLNO_NBYTES. */
4379 #define BS_DMA_TCDn_NBYTES_MLNO_NBYTES (32U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLNO_NBYTES. */
4381 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLNO_NBYTES field. */
4382 #define BR_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
4384 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLNO_NBYTES. */
4385 #define BF_DMA_TCDn_NBYTES_MLNO_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLNO_NBYTES) & BM_DMA_TCDn_NBYTES_MLNO_NBYTES)
4387 /*! @brief Set the NBYTES field to a new value. */
4388 #define BW_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v))
4390 /*******************************************************************************
4391 * HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
4392 ******************************************************************************/
4395 * @brief HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
4397 * Reset value: 0x00000000U
4399 * One of three registers (this register, TCD_NBYTES_MLNO, or
4400 * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
4401 * depends on whether minor loop mapping is disabled, enabled but not used for
4402 * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
4403 * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
4404 * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
4405 * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
4406 * the TCD_NBYTES_MLNO register description.
4408 typedef union _hw_dma_tcdn_nbytes_mloffno
4411 struct _hw_dma_tcdn_nbytes_mloffno_bitfields
4413 uint32_t NBYTES : 30; /*!< [29:0] Minor Byte Transfer Count */
4414 uint32_t DMLOE : 1; /*!< [30] Destination Minor Loop Offset enable */
4415 uint32_t SMLOE : 1; /*!< [31] Source Minor Loop Offset Enable */
4417 } hw_dma_tcdn_nbytes_mloffno_t;
4420 * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFNO register
4423 #define HW_DMA_TCDn_NBYTES_MLOFFNO_COUNT (16U)
4425 #define HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
4427 #define HW_DMA_TCDn_NBYTES_MLOFFNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffno_t *) HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n))
4428 #define HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U)
4429 #define HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U = (v))
4430 #define HW_DMA_TCDn_NBYTES_MLOFFNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) | (v)))
4431 #define HW_DMA_TCDn_NBYTES_MLOFFNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~(v)))
4432 #define HW_DMA_TCDn_NBYTES_MLOFFNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) ^ (v)))
4436 * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFNO bitfields
4440 * @name Register DMA_TCDn_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
4442 * Number of bytes to be transferred in each service request of the channel. As
4443 * a channel activates, the appropriate TCD contents load into the eDMA engine,
4444 * and the appropriate reads and writes perform until the minor byte transfer
4445 * count has transferred. This is an indivisible operation and cannot be halted;
4446 * although, it may be stalled by using the bandwidth control field, or via
4447 * preemption. After the minor count is exhausted, the SADDR and DADDR values are written
4448 * back into the TCD memory, the major iteration count is decremented and
4449 * restored to the TCD memory. If the major iteration count is completed, additional
4450 * processing is performed.
4453 #define BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
4454 #define BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0x3FFFFFFFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
4455 #define BS_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (30U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
4457 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_NBYTES field. */
4458 #define BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).B.NBYTES)
4460 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
4461 #define BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) & BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES)
4463 /*! @brief Set the NBYTES field to a new value. */
4464 #define BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v)))
4468 * @name Register DMA_TCDn_NBYTES_MLOFFNO, field DMLOE[30] (RW)
4470 * Selects whether the minor loop offset is applied to the destination address
4471 * upon minor loop completion.
4474 * - 0 - The minor loop offset is not applied to the DADDR
4475 * - 1 - The minor loop offset is applied to the DADDR
4478 #define BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (30U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
4479 #define BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (0x40000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
4480 #define BS_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
4482 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_DMLOE field. */
4483 #define BR_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE))
4485 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
4486 #define BF_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) & BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE)
4488 /*! @brief Set the DMLOE field to a new value. */
4489 #define BW_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) = (v))
4493 * @name Register DMA_TCDn_NBYTES_MLOFFNO, field SMLOE[31] (RW)
4495 * Selects whether the minor loop offset is applied to the source address upon
4496 * minor loop completion.
4499 * - 0 - The minor loop offset is not applied to the SADDR
4500 * - 1 - The minor loop offset is applied to the SADDR
4503 #define BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (31U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
4504 #define BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (0x80000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
4505 #define BS_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
4507 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_SMLOE field. */
4508 #define BR_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE))
4510 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
4511 #define BF_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) & BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE)
4513 /*! @brief Set the SMLOE field to a new value. */
4514 #define BW_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) = (v))
4516 /*******************************************************************************
4517 * HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
4518 ******************************************************************************/
4521 * @brief HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
4523 * Reset value: 0x00000000U
4525 * One of three registers (this register, TCD_NBYTES_MLNO, or
4526 * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
4527 * depends on whether minor loop mapping is disabled, enabled but not used for
4528 * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
4529 * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
4530 * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
4531 * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
4532 * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
4534 typedef union _hw_dma_tcdn_nbytes_mloffyes
4537 struct _hw_dma_tcdn_nbytes_mloffyes_bitfields
4539 uint32_t NBYTES : 10; /*!< [9:0] Minor Byte Transfer Count */
4540 uint32_t MLOFF : 20; /*!< [29:10] If SMLOE or DMLOE is set, this
4541 * field represents a sign-extended offset applied to the source or destination
4542 * address to form the next-state value after the minor loop completes. */
4543 uint32_t DMLOE : 1; /*!< [30] Destination Minor Loop Offset enable */
4544 uint32_t SMLOE : 1; /*!< [31] Source Minor Loop Offset Enable */
4546 } hw_dma_tcdn_nbytes_mloffyes_t;
4549 * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFYES register
4552 #define HW_DMA_TCDn_NBYTES_MLOFFYES_COUNT (16U)
4554 #define HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
4556 #define HW_DMA_TCDn_NBYTES_MLOFFYES(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffyes_t *) HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n))
4557 #define HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U)
4558 #define HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U = (v))
4559 #define HW_DMA_TCDn_NBYTES_MLOFFYES_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) | (v)))
4560 #define HW_DMA_TCDn_NBYTES_MLOFFYES_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~(v)))
4561 #define HW_DMA_TCDn_NBYTES_MLOFFYES_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) ^ (v)))
4565 * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFYES bitfields
4569 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
4571 * Number of bytes to be transferred in each service request of the channel. As
4572 * a channel activates, the appropriate TCD contents load into the eDMA engine,
4573 * and the appropriate reads and writes perform until the minor byte transfer
4574 * count has transferred. This is an indivisible operation and cannot be halted.
4575 * (Although, it may be stalled by using the bandwidth control field, or via
4576 * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
4577 * written back into the TCD memory, the major iteration count is decremented and
4578 * restored to the TCD memory. If the major iteration count is completed, additional
4579 * processing is performed.
4582 #define BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
4583 #define BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0x000003FFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
4584 #define BS_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (10U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
4586 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_NBYTES field. */
4587 #define BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.NBYTES)
4589 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
4590 #define BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) & BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES)
4592 /*! @brief Set the NBYTES field to a new value. */
4593 #define BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v)))
4597 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
4600 #define BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (10U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
4601 #define BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (0x3FFFFC00U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
4602 #define BS_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (20U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
4604 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_MLOFF field. */
4605 #define BR_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.MLOFF)
4607 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
4608 #define BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) & BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF)
4610 /*! @brief Set the MLOFF field to a new value. */
4611 #define BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) | BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v)))
4615 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field DMLOE[30] (RW)
4617 * Selects whether the minor loop offset is applied to the destination address
4618 * upon minor loop completion.
4621 * - 0 - The minor loop offset is not applied to the DADDR
4622 * - 1 - The minor loop offset is applied to the DADDR
4625 #define BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (30U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
4626 #define BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (0x40000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
4627 #define BS_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
4629 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_DMLOE field. */
4630 #define BR_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE))
4632 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
4633 #define BF_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) & BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE)
4635 /*! @brief Set the DMLOE field to a new value. */
4636 #define BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) = (v))
4640 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field SMLOE[31] (RW)
4642 * Selects whether the minor loop offset is applied to the source address upon
4643 * minor loop completion.
4646 * - 0 - The minor loop offset is not applied to the SADDR
4647 * - 1 - The minor loop offset is applied to the SADDR
4650 #define BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (31U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
4651 #define BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (0x80000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
4652 #define BS_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
4654 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_SMLOE field. */
4655 #define BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE))
4657 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
4658 #define BF_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) & BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE)
4660 /*! @brief Set the SMLOE field to a new value. */
4661 #define BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) = (v))
4663 /*******************************************************************************
4664 * HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
4665 ******************************************************************************/
4668 * @brief HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment (RW)
4670 * Reset value: 0x00000000U
4672 typedef union _hw_dma_tcdn_slast
4675 struct _hw_dma_tcdn_slast_bitfields
4677 uint32_t SLAST : 32; /*!< [31:0] Last source Address Adjustment */
4679 } hw_dma_tcdn_slast_t;
4682 * @name Constants and macros for entire DMA_TCDn_SLAST register
4685 #define HW_DMA_TCDn_SLAST_COUNT (16U)
4687 #define HW_DMA_TCDn_SLAST_ADDR(x, n) ((x) + 0x100CU + (0x20U * (n)))
4689 #define HW_DMA_TCDn_SLAST(x, n) (*(__IO hw_dma_tcdn_slast_t *) HW_DMA_TCDn_SLAST_ADDR(x, n))
4690 #define HW_DMA_TCDn_SLAST_RD(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
4691 #define HW_DMA_TCDn_SLAST_WR(x, n, v) (HW_DMA_TCDn_SLAST(x, n).U = (v))
4692 #define HW_DMA_TCDn_SLAST_SET(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) | (v)))
4693 #define HW_DMA_TCDn_SLAST_CLR(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) & ~(v)))
4694 #define HW_DMA_TCDn_SLAST_TOG(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) ^ (v)))
4698 * Constants & macros for individual DMA_TCDn_SLAST bitfields
4702 * @name Register DMA_TCDn_SLAST, field SLAST[31:0] (RW)
4704 * Adjustment value added to the source address at the completion of the major
4705 * iteration count. This value can be applied to restore the source address to the
4706 * initial value, or adjust the address to reference the next data structure.
4707 * This register uses two's complement notation; the overflow bit is discarded.
4710 #define BP_DMA_TCDn_SLAST_SLAST (0U) /*!< Bit position for DMA_TCDn_SLAST_SLAST. */
4711 #define BM_DMA_TCDn_SLAST_SLAST (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_SLAST_SLAST. */
4712 #define BS_DMA_TCDn_SLAST_SLAST (32U) /*!< Bit field size in bits for DMA_TCDn_SLAST_SLAST. */
4714 /*! @brief Read current value of the DMA_TCDn_SLAST_SLAST field. */
4715 #define BR_DMA_TCDn_SLAST_SLAST(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
4717 /*! @brief Format value for bitfield DMA_TCDn_SLAST_SLAST. */
4718 #define BF_DMA_TCDn_SLAST_SLAST(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_SLAST_SLAST) & BM_DMA_TCDn_SLAST_SLAST)
4720 /*! @brief Set the SLAST field to a new value. */
4721 #define BW_DMA_TCDn_SLAST_SLAST(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, v))
4723 /*******************************************************************************
4724 * HW_DMA_TCDn_DADDR - TCD Destination Address
4725 ******************************************************************************/
4728 * @brief HW_DMA_TCDn_DADDR - TCD Destination Address (RW)
4730 * Reset value: 0x00000000U
4732 typedef union _hw_dma_tcdn_daddr
4735 struct _hw_dma_tcdn_daddr_bitfields
4737 uint32_t DADDR : 32; /*!< [31:0] Destination Address */
4739 } hw_dma_tcdn_daddr_t;
4742 * @name Constants and macros for entire DMA_TCDn_DADDR register
4745 #define HW_DMA_TCDn_DADDR_COUNT (16U)
4747 #define HW_DMA_TCDn_DADDR_ADDR(x, n) ((x) + 0x1010U + (0x20U * (n)))
4749 #define HW_DMA_TCDn_DADDR(x, n) (*(__IO hw_dma_tcdn_daddr_t *) HW_DMA_TCDn_DADDR_ADDR(x, n))
4750 #define HW_DMA_TCDn_DADDR_RD(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
4751 #define HW_DMA_TCDn_DADDR_WR(x, n, v) (HW_DMA_TCDn_DADDR(x, n).U = (v))
4752 #define HW_DMA_TCDn_DADDR_SET(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) | (v)))
4753 #define HW_DMA_TCDn_DADDR_CLR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) & ~(v)))
4754 #define HW_DMA_TCDn_DADDR_TOG(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) ^ (v)))
4758 * Constants & macros for individual DMA_TCDn_DADDR bitfields
4762 * @name Register DMA_TCDn_DADDR, field DADDR[31:0] (RW)
4764 * Memory address pointing to the destination data.
4767 #define BP_DMA_TCDn_DADDR_DADDR (0U) /*!< Bit position for DMA_TCDn_DADDR_DADDR. */
4768 #define BM_DMA_TCDn_DADDR_DADDR (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_DADDR_DADDR. */
4769 #define BS_DMA_TCDn_DADDR_DADDR (32U) /*!< Bit field size in bits for DMA_TCDn_DADDR_DADDR. */
4771 /*! @brief Read current value of the DMA_TCDn_DADDR_DADDR field. */
4772 #define BR_DMA_TCDn_DADDR_DADDR(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
4774 /*! @brief Format value for bitfield DMA_TCDn_DADDR_DADDR. */
4775 #define BF_DMA_TCDn_DADDR_DADDR(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_DADDR_DADDR) & BM_DMA_TCDn_DADDR_DADDR)
4777 /*! @brief Set the DADDR field to a new value. */
4778 #define BW_DMA_TCDn_DADDR_DADDR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, v))
4780 /*******************************************************************************
4781 * HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
4782 ******************************************************************************/
4785 * @brief HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset (RW)
4787 * Reset value: 0x0000U
4789 typedef union _hw_dma_tcdn_doff
4792 struct _hw_dma_tcdn_doff_bitfields
4794 uint16_t DOFF : 16; /*!< [15:0] Destination Address Signed offset */
4796 } hw_dma_tcdn_doff_t;
4799 * @name Constants and macros for entire DMA_TCDn_DOFF register
4802 #define HW_DMA_TCDn_DOFF_COUNT (16U)
4804 #define HW_DMA_TCDn_DOFF_ADDR(x, n) ((x) + 0x1014U + (0x20U * (n)))
4806 #define HW_DMA_TCDn_DOFF(x, n) (*(__IO hw_dma_tcdn_doff_t *) HW_DMA_TCDn_DOFF_ADDR(x, n))
4807 #define HW_DMA_TCDn_DOFF_RD(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
4808 #define HW_DMA_TCDn_DOFF_WR(x, n, v) (HW_DMA_TCDn_DOFF(x, n).U = (v))
4809 #define HW_DMA_TCDn_DOFF_SET(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) | (v)))
4810 #define HW_DMA_TCDn_DOFF_CLR(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) & ~(v)))
4811 #define HW_DMA_TCDn_DOFF_TOG(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) ^ (v)))
4815 * Constants & macros for individual DMA_TCDn_DOFF bitfields
4819 * @name Register DMA_TCDn_DOFF, field DOFF[15:0] (RW)
4821 * Sign-extended offset applied to the current destination address to form the
4822 * next-state value as each destination write is completed.
4825 #define BP_DMA_TCDn_DOFF_DOFF (0U) /*!< Bit position for DMA_TCDn_DOFF_DOFF. */
4826 #define BM_DMA_TCDn_DOFF_DOFF (0xFFFFU) /*!< Bit mask for DMA_TCDn_DOFF_DOFF. */
4827 #define BS_DMA_TCDn_DOFF_DOFF (16U) /*!< Bit field size in bits for DMA_TCDn_DOFF_DOFF. */
4829 /*! @brief Read current value of the DMA_TCDn_DOFF_DOFF field. */
4830 #define BR_DMA_TCDn_DOFF_DOFF(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
4832 /*! @brief Format value for bitfield DMA_TCDn_DOFF_DOFF. */
4833 #define BF_DMA_TCDn_DOFF_DOFF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_DOFF_DOFF) & BM_DMA_TCDn_DOFF_DOFF)
4835 /*! @brief Set the DOFF field to a new value. */
4836 #define BW_DMA_TCDn_DOFF_DOFF(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, v))
4838 /*******************************************************************************
4839 * HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
4840 ******************************************************************************/
4843 * @brief HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
4845 * Reset value: 0x0000U
4847 * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
4850 typedef union _hw_dma_tcdn_citer_elinkno
4853 struct _hw_dma_tcdn_citer_elinkno_bitfields
4855 uint16_t CITER : 15; /*!< [14:0] Current Major Iteration Count */
4856 uint16_t ELINK : 1; /*!< [15] Enable channel-to-channel linking on
4857 * minor-loop complete */
4859 } hw_dma_tcdn_citer_elinkno_t;
4862 * @name Constants and macros for entire DMA_TCDn_CITER_ELINKNO register
4865 #define HW_DMA_TCDn_CITER_ELINKNO_COUNT (16U)
4867 #define HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n)))
4869 #define HW_DMA_TCDn_CITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_citer_elinkno_t *) HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n))
4870 #define HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U)
4871 #define HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U = (v))
4872 #define HW_DMA_TCDn_CITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) | (v)))
4873 #define HW_DMA_TCDn_CITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~(v)))
4874 #define HW_DMA_TCDn_CITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) ^ (v)))
4878 * Constants & macros for individual DMA_TCDn_CITER_ELINKNO bitfields
4882 * @name Register DMA_TCDn_CITER_ELINKNO, field CITER[14:0] (RW)
4884 * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
4885 * major loop count for the channel. It is decremented each time the minor loop is
4886 * completed and updated in the transfer control descriptor memory. After the
4887 * major iteration count is exhausted, the channel performs a number of operations
4888 * (e.g., final source and destination address calculations), optionally generating
4889 * an interrupt to signal channel completion before reloading the CITER field
4890 * from the beginning iteration count (BITER) field. When the CITER field is
4891 * initially loaded by software, it must be set to the same value as that contained in
4892 * the BITER field. If the channel is configured to execute a single service
4893 * request, the initial values of BITER and CITER should be 0x0001.
4896 #define BP_DMA_TCDn_CITER_ELINKNO_CITER (0U) /*!< Bit position for DMA_TCDn_CITER_ELINKNO_CITER. */
4897 #define BM_DMA_TCDn_CITER_ELINKNO_CITER (0x7FFFU) /*!< Bit mask for DMA_TCDn_CITER_ELINKNO_CITER. */
4898 #define BS_DMA_TCDn_CITER_ELINKNO_CITER (15U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_CITER. */
4900 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_CITER field. */
4901 #define BR_DMA_TCDn_CITER_ELINKNO_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).B.CITER)
4903 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_CITER. */
4904 #define BF_DMA_TCDn_CITER_ELINKNO_CITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKNO_CITER) & BM_DMA_TCDn_CITER_ELINKNO_CITER)
4906 /*! @brief Set the CITER field to a new value. */
4907 #define BW_DMA_TCDn_CITER_ELINKNO_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKNO_CITER) | BF_DMA_TCDn_CITER_ELINKNO_CITER(v)))
4911 * @name Register DMA_TCDn_CITER_ELINKNO, field ELINK[15] (RW)
4913 * As the channel completes the minor loop, this flag enables linking to another
4914 * channel, defined by the LINKCH field. The link target channel initiates a
4915 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
4916 * bit of the specified channel. If channel linking is disabled, the CITER value
4917 * is extended to 15 bits in place of a link channel number. If the major loop is
4918 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
4919 * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
4920 * configuration error is reported.
4923 * - 0 - The channel-to-channel linking is disabled
4924 * - 1 - The channel-to-channel linking is enabled
4927 #define BP_DMA_TCDn_CITER_ELINKNO_ELINK (15U) /*!< Bit position for DMA_TCDn_CITER_ELINKNO_ELINK. */
4928 #define BM_DMA_TCDn_CITER_ELINKNO_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_CITER_ELINKNO_ELINK. */
4929 #define BS_DMA_TCDn_CITER_ELINKNO_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_ELINK. */
4931 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_ELINK field. */
4932 #define BR_DMA_TCDn_CITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK))
4934 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_ELINK. */
4935 #define BF_DMA_TCDn_CITER_ELINKNO_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKNO_ELINK) & BM_DMA_TCDn_CITER_ELINKNO_ELINK)
4937 /*! @brief Set the ELINK field to a new value. */
4938 #define BW_DMA_TCDn_CITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK) = (v))
4940 /*******************************************************************************
4941 * HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
4942 ******************************************************************************/
4945 * @brief HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
4947 * Reset value: 0x0000U
4949 * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
4951 typedef union _hw_dma_tcdn_citer_elinkyes
4954 struct _hw_dma_tcdn_citer_elinkyes_bitfields
4956 uint16_t CITER : 9; /*!< [8:0] Current Major Iteration Count */
4957 uint16_t LINKCH : 4; /*!< [12:9] Link Channel Number */
4958 uint16_t RESERVED0 : 2; /*!< [14:13] */
4959 uint16_t ELINK : 1; /*!< [15] Enable channel-to-channel linking on
4960 * minor-loop complete */
4962 } hw_dma_tcdn_citer_elinkyes_t;
4965 * @name Constants and macros for entire DMA_TCDn_CITER_ELINKYES register
4968 #define HW_DMA_TCDn_CITER_ELINKYES_COUNT (16U)
4970 #define HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n)))
4972 #define HW_DMA_TCDn_CITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_citer_elinkyes_t *) HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n))
4973 #define HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U)
4974 #define HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U = (v))
4975 #define HW_DMA_TCDn_CITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) | (v)))
4976 #define HW_DMA_TCDn_CITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~(v)))
4977 #define HW_DMA_TCDn_CITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) ^ (v)))
4981 * Constants & macros for individual DMA_TCDn_CITER_ELINKYES bitfields
4985 * @name Register DMA_TCDn_CITER_ELINKYES, field CITER[8:0] (RW)
4987 * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
4988 * major loop count for the channel. It is decremented each time the minor loop is
4989 * completed and updated in the transfer control descriptor memory. After the
4990 * major iteration count is exhausted, the channel performs a number of operations
4991 * (e.g., final source and destination address calculations), optionally generating
4992 * an interrupt to signal channel completion before reloading the CITER field
4993 * from the beginning iteration count (BITER) field. When the CITER field is
4994 * initially loaded by software, it must be set to the same value as that contained in
4995 * the BITER field. If the channel is configured to execute a single service
4996 * request, the initial values of BITER and CITER should be 0x0001.
4999 #define BP_DMA_TCDn_CITER_ELINKYES_CITER (0U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_CITER. */
5000 #define BM_DMA_TCDn_CITER_ELINKYES_CITER (0x01FFU) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_CITER. */
5001 #define BS_DMA_TCDn_CITER_ELINKYES_CITER (9U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_CITER. */
5003 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_CITER field. */
5004 #define BR_DMA_TCDn_CITER_ELINKYES_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.CITER)
5006 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_CITER. */
5007 #define BF_DMA_TCDn_CITER_ELINKYES_CITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_CITER) & BM_DMA_TCDn_CITER_ELINKYES_CITER)
5009 /*! @brief Set the CITER field to a new value. */
5010 #define BW_DMA_TCDn_CITER_ELINKYES_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_CITER) | BF_DMA_TCDn_CITER_ELINKYES_CITER(v)))
5014 * @name Register DMA_TCDn_CITER_ELINKYES, field LINKCH[12:9] (RW)
5016 * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
5017 * loop is exhausted, the eDMA engine initiates a channel service request to the
5018 * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
5021 #define BP_DMA_TCDn_CITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_LINKCH. */
5022 #define BM_DMA_TCDn_CITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_LINKCH. */
5023 #define BS_DMA_TCDn_CITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_LINKCH. */
5025 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_LINKCH field. */
5026 #define BR_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.LINKCH)
5028 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_LINKCH. */
5029 #define BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_LINKCH) & BM_DMA_TCDn_CITER_ELINKYES_LINKCH)
5031 /*! @brief Set the LINKCH field to a new value. */
5032 #define BW_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_LINKCH) | BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v)))
5036 * @name Register DMA_TCDn_CITER_ELINKYES, field ELINK[15] (RW)
5038 * As the channel completes the minor loop, this flag enables linking to another
5039 * channel, defined by the LINKCH field. The link target channel initiates a
5040 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
5041 * bit of the specified channel. If channel linking is disabled, the CITER value
5042 * is extended to 15 bits in place of a link channel number. If the major loop is
5043 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
5044 * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
5045 * configuration error is reported.
5048 * - 0 - The channel-to-channel linking is disabled
5049 * - 1 - The channel-to-channel linking is enabled
5052 #define BP_DMA_TCDn_CITER_ELINKYES_ELINK (15U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_ELINK. */
5053 #define BM_DMA_TCDn_CITER_ELINKYES_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_ELINK. */
5054 #define BS_DMA_TCDn_CITER_ELINKYES_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_ELINK. */
5056 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_ELINK field. */
5057 #define BR_DMA_TCDn_CITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK))
5059 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_ELINK. */
5060 #define BF_DMA_TCDn_CITER_ELINKYES_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_ELINK) & BM_DMA_TCDn_CITER_ELINKYES_ELINK)
5062 /*! @brief Set the ELINK field to a new value. */
5063 #define BW_DMA_TCDn_CITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK) = (v))
5065 /*******************************************************************************
5066 * HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
5067 ******************************************************************************/
5070 * @brief HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
5072 * Reset value: 0x00000000U
5074 typedef union _hw_dma_tcdn_dlastsga
5077 struct _hw_dma_tcdn_dlastsga_bitfields
5079 uint32_t DLASTSGA : 32; /*!< [31:0] */
5081 } hw_dma_tcdn_dlastsga_t;
5084 * @name Constants and macros for entire DMA_TCDn_DLASTSGA register
5087 #define HW_DMA_TCDn_DLASTSGA_COUNT (16U)
5089 #define HW_DMA_TCDn_DLASTSGA_ADDR(x, n) ((x) + 0x1018U + (0x20U * (n)))
5091 #define HW_DMA_TCDn_DLASTSGA(x, n) (*(__IO hw_dma_tcdn_dlastsga_t *) HW_DMA_TCDn_DLASTSGA_ADDR(x, n))
5092 #define HW_DMA_TCDn_DLASTSGA_RD(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
5093 #define HW_DMA_TCDn_DLASTSGA_WR(x, n, v) (HW_DMA_TCDn_DLASTSGA(x, n).U = (v))
5094 #define HW_DMA_TCDn_DLASTSGA_SET(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) | (v)))
5095 #define HW_DMA_TCDn_DLASTSGA_CLR(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) & ~(v)))
5096 #define HW_DMA_TCDn_DLASTSGA_TOG(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) ^ (v)))
5100 * Constants & macros for individual DMA_TCDn_DLASTSGA bitfields
5104 * @name Register DMA_TCDn_DLASTSGA, field DLASTSGA[31:0] (RW)
5106 * Destination last address adjustment or the memory address for the next
5107 * transfer control descriptor to be loaded into this channel (scatter/gather). If
5108 * (TCDn_CSR[ESG] = 0), then: Adjustment value added to the destination address at
5109 * the completion of the major iteration count. This value can apply to restore the
5110 * destination address to the initial value or adjust the address to reference
5111 * the next data structure. This field uses two's complement notation for the
5112 * final destination address adjustment. Otherwise: This address points to the
5113 * beginning of a 0-modulo-32-byte region containing the next transfer control
5114 * descriptor to be loaded into this channel. This channel reload is performed as the
5115 * major iteration count completes. The scatter/gather address must be
5116 * 0-modulo-32-byte, else a configuration error is reported.
5119 #define BP_DMA_TCDn_DLASTSGA_DLASTSGA (0U) /*!< Bit position for DMA_TCDn_DLASTSGA_DLASTSGA. */
5120 #define BM_DMA_TCDn_DLASTSGA_DLASTSGA (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_DLASTSGA_DLASTSGA. */
5121 #define BS_DMA_TCDn_DLASTSGA_DLASTSGA (32U) /*!< Bit field size in bits for DMA_TCDn_DLASTSGA_DLASTSGA. */
5123 /*! @brief Read current value of the DMA_TCDn_DLASTSGA_DLASTSGA field. */
5124 #define BR_DMA_TCDn_DLASTSGA_DLASTSGA(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
5126 /*! @brief Format value for bitfield DMA_TCDn_DLASTSGA_DLASTSGA. */
5127 #define BF_DMA_TCDn_DLASTSGA_DLASTSGA(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_DLASTSGA_DLASTSGA) & BM_DMA_TCDn_DLASTSGA_DLASTSGA)
5129 /*! @brief Set the DLASTSGA field to a new value. */
5130 #define BW_DMA_TCDn_DLASTSGA_DLASTSGA(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, v))
5132 /*******************************************************************************
5133 * HW_DMA_TCDn_CSR - TCD Control and Status
5134 ******************************************************************************/
5137 * @brief HW_DMA_TCDn_CSR - TCD Control and Status (RW)
5139 * Reset value: 0x0000U
5141 typedef union _hw_dma_tcdn_csr
5144 struct _hw_dma_tcdn_csr_bitfields
5146 uint16_t START : 1; /*!< [0] Channel Start */
5147 uint16_t INTMAJOR : 1; /*!< [1] Enable an interrupt when major
5148 * iteration count completes */
5149 uint16_t INTHALF : 1; /*!< [2] Enable an interrupt when major counter
5150 * is half complete. */
5151 uint16_t DREQ : 1; /*!< [3] Disable Request */
5152 uint16_t ESG : 1; /*!< [4] Enable Scatter/Gather Processing */
5153 uint16_t MAJORELINK : 1; /*!< [5] Enable channel-to-channel linking
5154 * on major loop complete */
5155 uint16_t ACTIVE : 1; /*!< [6] Channel Active */
5156 uint16_t DONE : 1; /*!< [7] Channel Done */
5157 uint16_t MAJORLINKCH : 4; /*!< [11:8] Link Channel Number */
5158 uint16_t RESERVED0 : 2; /*!< [13:12] */
5159 uint16_t BWC : 2; /*!< [15:14] Bandwidth Control */
5161 } hw_dma_tcdn_csr_t;
5164 * @name Constants and macros for entire DMA_TCDn_CSR register
5167 #define HW_DMA_TCDn_CSR_COUNT (16U)
5169 #define HW_DMA_TCDn_CSR_ADDR(x, n) ((x) + 0x101CU + (0x20U * (n)))
5171 #define HW_DMA_TCDn_CSR(x, n) (*(__IO hw_dma_tcdn_csr_t *) HW_DMA_TCDn_CSR_ADDR(x, n))
5172 #define HW_DMA_TCDn_CSR_RD(x, n) (HW_DMA_TCDn_CSR(x, n).U)
5173 #define HW_DMA_TCDn_CSR_WR(x, n, v) (HW_DMA_TCDn_CSR(x, n).U = (v))
5174 #define HW_DMA_TCDn_CSR_SET(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) | (v)))
5175 #define HW_DMA_TCDn_CSR_CLR(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) & ~(v)))
5176 #define HW_DMA_TCDn_CSR_TOG(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) ^ (v)))
5180 * Constants & macros for individual DMA_TCDn_CSR bitfields
5184 * @name Register DMA_TCDn_CSR, field START[0] (RW)
5186 * If this flag is set, the channel is requesting service. The eDMA hardware
5187 * automatically clears this flag after the channel begins execution.
5190 * - 0 - The channel is not explicitly started
5191 * - 1 - The channel is explicitly started via a software initiated service
5195 #define BP_DMA_TCDn_CSR_START (0U) /*!< Bit position for DMA_TCDn_CSR_START. */
5196 #define BM_DMA_TCDn_CSR_START (0x0001U) /*!< Bit mask for DMA_TCDn_CSR_START. */
5197 #define BS_DMA_TCDn_CSR_START (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_START. */
5199 /*! @brief Read current value of the DMA_TCDn_CSR_START field. */
5200 #define BR_DMA_TCDn_CSR_START(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START))
5202 /*! @brief Format value for bitfield DMA_TCDn_CSR_START. */
5203 #define BF_DMA_TCDn_CSR_START(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_START) & BM_DMA_TCDn_CSR_START)
5205 /*! @brief Set the START field to a new value. */
5206 #define BW_DMA_TCDn_CSR_START(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START) = (v))
5210 * @name Register DMA_TCDn_CSR, field INTMAJOR[1] (RW)
5212 * If this flag is set, the channel generates an interrupt request by setting
5213 * the appropriate bit in the INT when the current major iteration count reaches
5217 * - 0 - The end-of-major loop interrupt is disabled
5218 * - 1 - The end-of-major loop interrupt is enabled
5221 #define BP_DMA_TCDn_CSR_INTMAJOR (1U) /*!< Bit position for DMA_TCDn_CSR_INTMAJOR. */
5222 #define BM_DMA_TCDn_CSR_INTMAJOR (0x0002U) /*!< Bit mask for DMA_TCDn_CSR_INTMAJOR. */
5223 #define BS_DMA_TCDn_CSR_INTMAJOR (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_INTMAJOR. */
5225 /*! @brief Read current value of the DMA_TCDn_CSR_INTMAJOR field. */
5226 #define BR_DMA_TCDn_CSR_INTMAJOR(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR))
5228 /*! @brief Format value for bitfield DMA_TCDn_CSR_INTMAJOR. */
5229 #define BF_DMA_TCDn_CSR_INTMAJOR(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_INTMAJOR) & BM_DMA_TCDn_CSR_INTMAJOR)
5231 /*! @brief Set the INTMAJOR field to a new value. */
5232 #define BW_DMA_TCDn_CSR_INTMAJOR(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR) = (v))
5236 * @name Register DMA_TCDn_CSR, field INTHALF[2] (RW)
5238 * If this flag is set, the channel generates an interrupt request by setting
5239 * the appropriate bit in the INT register when the current major iteration count
5240 * reaches the halfway point. Specifically, the comparison performed by the eDMA
5241 * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
5242 * provided to support double-buffered (aka ping-pong) schemes or other types of data
5243 * movement where the processor needs an early indication of the transfer's
5244 * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
5247 * - 0 - The half-point interrupt is disabled
5248 * - 1 - The half-point interrupt is enabled
5251 #define BP_DMA_TCDn_CSR_INTHALF (2U) /*!< Bit position for DMA_TCDn_CSR_INTHALF. */
5252 #define BM_DMA_TCDn_CSR_INTHALF (0x0004U) /*!< Bit mask for DMA_TCDn_CSR_INTHALF. */
5253 #define BS_DMA_TCDn_CSR_INTHALF (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_INTHALF. */
5255 /*! @brief Read current value of the DMA_TCDn_CSR_INTHALF field. */
5256 #define BR_DMA_TCDn_CSR_INTHALF(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF))
5258 /*! @brief Format value for bitfield DMA_TCDn_CSR_INTHALF. */
5259 #define BF_DMA_TCDn_CSR_INTHALF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_INTHALF) & BM_DMA_TCDn_CSR_INTHALF)
5261 /*! @brief Set the INTHALF field to a new value. */
5262 #define BW_DMA_TCDn_CSR_INTHALF(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF) = (v))
5266 * @name Register DMA_TCDn_CSR, field DREQ[3] (RW)
5268 * If this flag is set, the eDMA hardware automatically clears the corresponding
5269 * ERQ bit when the current major iteration count reaches zero.
5272 * - 0 - The channel's ERQ bit is not affected
5273 * - 1 - The channel's ERQ bit is cleared when the major loop is complete
5276 #define BP_DMA_TCDn_CSR_DREQ (3U) /*!< Bit position for DMA_TCDn_CSR_DREQ. */
5277 #define BM_DMA_TCDn_CSR_DREQ (0x0008U) /*!< Bit mask for DMA_TCDn_CSR_DREQ. */
5278 #define BS_DMA_TCDn_CSR_DREQ (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_DREQ. */
5280 /*! @brief Read current value of the DMA_TCDn_CSR_DREQ field. */
5281 #define BR_DMA_TCDn_CSR_DREQ(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ))
5283 /*! @brief Format value for bitfield DMA_TCDn_CSR_DREQ. */
5284 #define BF_DMA_TCDn_CSR_DREQ(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_DREQ) & BM_DMA_TCDn_CSR_DREQ)
5286 /*! @brief Set the DREQ field to a new value. */
5287 #define BW_DMA_TCDn_CSR_DREQ(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ) = (v))
5291 * @name Register DMA_TCDn_CSR, field ESG[4] (RW)
5293 * As the channel completes the major loop, this flag enables scatter/gather
5294 * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
5295 * memory pointer to a 0-modulo-32 address containing a 32-byte data structure
5296 * loaded as the transfer control descriptor into the local memory. To support the
5297 * dynamic scatter/gather coherency model, this field is forced to zero when
5298 * written to while the TCDn_CSR[DONE] bit is set.
5301 * - 0 - The current channel's TCD is normal format.
5302 * - 1 - The current channel's TCD specifies a scatter gather format. The
5303 * DLASTSGA field provides a memory pointer to the next TCD to be loaded into this
5304 * channel after the major loop completes its execution.
5307 #define BP_DMA_TCDn_CSR_ESG (4U) /*!< Bit position for DMA_TCDn_CSR_ESG. */
5308 #define BM_DMA_TCDn_CSR_ESG (0x0010U) /*!< Bit mask for DMA_TCDn_CSR_ESG. */
5309 #define BS_DMA_TCDn_CSR_ESG (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_ESG. */
5311 /*! @brief Read current value of the DMA_TCDn_CSR_ESG field. */
5312 #define BR_DMA_TCDn_CSR_ESG(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG))
5314 /*! @brief Format value for bitfield DMA_TCDn_CSR_ESG. */
5315 #define BF_DMA_TCDn_CSR_ESG(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_ESG) & BM_DMA_TCDn_CSR_ESG)
5317 /*! @brief Set the ESG field to a new value. */
5318 #define BW_DMA_TCDn_CSR_ESG(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG) = (v))
5322 * @name Register DMA_TCDn_CSR, field MAJORELINK[5] (RW)
5324 * As the channel completes the major loop, this flag enables the linking to
5325 * another channel, defined by MAJORLINKCH. The link target channel initiates a
5326 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
5327 * bit of the specified channel. To support the dynamic linking coherency model,
5328 * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
5331 * - 0 - The channel-to-channel linking is disabled
5332 * - 1 - The channel-to-channel linking is enabled
5335 #define BP_DMA_TCDn_CSR_MAJORELINK (5U) /*!< Bit position for DMA_TCDn_CSR_MAJORELINK. */
5336 #define BM_DMA_TCDn_CSR_MAJORELINK (0x0020U) /*!< Bit mask for DMA_TCDn_CSR_MAJORELINK. */
5337 #define BS_DMA_TCDn_CSR_MAJORELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORELINK. */
5339 /*! @brief Read current value of the DMA_TCDn_CSR_MAJORELINK field. */
5340 #define BR_DMA_TCDn_CSR_MAJORELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK))
5342 /*! @brief Format value for bitfield DMA_TCDn_CSR_MAJORELINK. */
5343 #define BF_DMA_TCDn_CSR_MAJORELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_MAJORELINK) & BM_DMA_TCDn_CSR_MAJORELINK)
5345 /*! @brief Set the MAJORELINK field to a new value. */
5346 #define BW_DMA_TCDn_CSR_MAJORELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK) = (v))
5350 * @name Register DMA_TCDn_CSR, field ACTIVE[6] (RW)
5352 * This flag signals the channel is currently in execution. It is set when
5353 * channel service begins, and the eDMA clears it as the minor loop completes or if
5354 * any error condition is detected. This bit resets to zero.
5357 #define BP_DMA_TCDn_CSR_ACTIVE (6U) /*!< Bit position for DMA_TCDn_CSR_ACTIVE. */
5358 #define BM_DMA_TCDn_CSR_ACTIVE (0x0040U) /*!< Bit mask for DMA_TCDn_CSR_ACTIVE. */
5359 #define BS_DMA_TCDn_CSR_ACTIVE (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_ACTIVE. */
5361 /*! @brief Read current value of the DMA_TCDn_CSR_ACTIVE field. */
5362 #define BR_DMA_TCDn_CSR_ACTIVE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE))
5364 /*! @brief Format value for bitfield DMA_TCDn_CSR_ACTIVE. */
5365 #define BF_DMA_TCDn_CSR_ACTIVE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_ACTIVE) & BM_DMA_TCDn_CSR_ACTIVE)
5367 /*! @brief Set the ACTIVE field to a new value. */
5368 #define BW_DMA_TCDn_CSR_ACTIVE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE) = (v))
5372 * @name Register DMA_TCDn_CSR, field DONE[7] (RW)
5374 * This flag indicates the eDMA has completed the major loop. The eDMA engine
5375 * sets it as the CITER count reaches zero; The software clears it, or the hardware
5376 * when the channel is activated. This bit must be cleared to write the
5377 * MAJORELINK or ESG bits.
5380 #define BP_DMA_TCDn_CSR_DONE (7U) /*!< Bit position for DMA_TCDn_CSR_DONE. */
5381 #define BM_DMA_TCDn_CSR_DONE (0x0080U) /*!< Bit mask for DMA_TCDn_CSR_DONE. */
5382 #define BS_DMA_TCDn_CSR_DONE (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_DONE. */
5384 /*! @brief Read current value of the DMA_TCDn_CSR_DONE field. */
5385 #define BR_DMA_TCDn_CSR_DONE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE))
5387 /*! @brief Format value for bitfield DMA_TCDn_CSR_DONE. */
5388 #define BF_DMA_TCDn_CSR_DONE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_DONE) & BM_DMA_TCDn_CSR_DONE)
5390 /*! @brief Set the DONE field to a new value. */
5391 #define BW_DMA_TCDn_CSR_DONE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE) = (v))
5395 * @name Register DMA_TCDn_CSR, field MAJORLINKCH[11:8] (RW)
5397 * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
5398 * performed after the major loop counter is exhausted. else After the major loop
5399 * counter is exhausted, the eDMA engine initiates a channel service request at the
5400 * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
5403 #define BP_DMA_TCDn_CSR_MAJORLINKCH (8U) /*!< Bit position for DMA_TCDn_CSR_MAJORLINKCH. */
5404 #define BM_DMA_TCDn_CSR_MAJORLINKCH (0x0F00U) /*!< Bit mask for DMA_TCDn_CSR_MAJORLINKCH. */
5405 #define BS_DMA_TCDn_CSR_MAJORLINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORLINKCH. */
5407 /*! @brief Read current value of the DMA_TCDn_CSR_MAJORLINKCH field. */
5408 #define BR_DMA_TCDn_CSR_MAJORLINKCH(x, n) (HW_DMA_TCDn_CSR(x, n).B.MAJORLINKCH)
5410 /*! @brief Format value for bitfield DMA_TCDn_CSR_MAJORLINKCH. */
5411 #define BF_DMA_TCDn_CSR_MAJORLINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_MAJORLINKCH) & BM_DMA_TCDn_CSR_MAJORLINKCH)
5413 /*! @brief Set the MAJORLINKCH field to a new value. */
5414 #define BW_DMA_TCDn_CSR_MAJORLINKCH(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_MAJORLINKCH) | BF_DMA_TCDn_CSR_MAJORLINKCH(v)))
5418 * @name Register DMA_TCDn_CSR, field BWC[15:14] (RW)
5420 * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
5421 * the eDMA processes the minor loop, it continuously generates read/write
5422 * sequences until the minor count is exhausted. This field forces the eDMA to stall
5423 * after the completion of each read/write access to control the bus request
5424 * bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
5425 * this field is ignored between the first and second transfers and after the
5426 * last write of each minor loop. This behavior is a side effect of reducing
5430 * - 00 - No eDMA engine stalls
5432 * - 10 - eDMA engine stalls for 4 cycles after each r/w
5433 * - 11 - eDMA engine stalls for 8 cycles after each r/w
5436 #define BP_DMA_TCDn_CSR_BWC (14U) /*!< Bit position for DMA_TCDn_CSR_BWC. */
5437 #define BM_DMA_TCDn_CSR_BWC (0xC000U) /*!< Bit mask for DMA_TCDn_CSR_BWC. */
5438 #define BS_DMA_TCDn_CSR_BWC (2U) /*!< Bit field size in bits for DMA_TCDn_CSR_BWC. */
5440 /*! @brief Read current value of the DMA_TCDn_CSR_BWC field. */
5441 #define BR_DMA_TCDn_CSR_BWC(x, n) (HW_DMA_TCDn_CSR(x, n).B.BWC)
5443 /*! @brief Format value for bitfield DMA_TCDn_CSR_BWC. */
5444 #define BF_DMA_TCDn_CSR_BWC(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_BWC) & BM_DMA_TCDn_CSR_BWC)
5446 /*! @brief Set the BWC field to a new value. */
5447 #define BW_DMA_TCDn_CSR_BWC(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_BWC) | BF_DMA_TCDn_CSR_BWC(v)))
5449 /*******************************************************************************
5450 * HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
5451 ******************************************************************************/
5454 * @brief HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
5456 * Reset value: 0x0000U
5458 * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
5461 typedef union _hw_dma_tcdn_biter_elinkno
5464 struct _hw_dma_tcdn_biter_elinkno_bitfields
5466 uint16_t BITER : 15; /*!< [14:0] Starting Major Iteration Count */
5467 uint16_t ELINK : 1; /*!< [15] Enables channel-to-channel linking on
5468 * minor loop complete */
5470 } hw_dma_tcdn_biter_elinkno_t;
5473 * @name Constants and macros for entire DMA_TCDn_BITER_ELINKNO register
5476 #define HW_DMA_TCDn_BITER_ELINKNO_COUNT (16U)
5478 #define HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n)))
5480 #define HW_DMA_TCDn_BITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_biter_elinkno_t *) HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n))
5481 #define HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U)
5482 #define HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U = (v))
5483 #define HW_DMA_TCDn_BITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) | (v)))
5484 #define HW_DMA_TCDn_BITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~(v)))
5485 #define HW_DMA_TCDn_BITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) ^ (v)))
5489 * Constants & macros for individual DMA_TCDn_BITER_ELINKNO bitfields
5493 * @name Register DMA_TCDn_BITER_ELINKNO, field BITER[14:0] (RW)
5495 * As the transfer control descriptor is first loaded by software, this 9-bit
5496 * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
5497 * field. As the major iteration count is exhausted, the contents of this field
5498 * are reloaded into the CITER field. When the software loads the TCD, this field
5499 * must be set equal to the corresponding CITER field; otherwise, a configuration
5500 * error is reported. As the major iteration count is exhausted, the contents of
5501 * this field is reloaded into the CITER field. If the channel is configured to
5502 * execute a single service request, the initial values of BITER and CITER should
5506 #define BP_DMA_TCDn_BITER_ELINKNO_BITER (0U) /*!< Bit position for DMA_TCDn_BITER_ELINKNO_BITER. */
5507 #define BM_DMA_TCDn_BITER_ELINKNO_BITER (0x7FFFU) /*!< Bit mask for DMA_TCDn_BITER_ELINKNO_BITER. */
5508 #define BS_DMA_TCDn_BITER_ELINKNO_BITER (15U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_BITER. */
5510 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_BITER field. */
5511 #define BR_DMA_TCDn_BITER_ELINKNO_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).B.BITER)
5513 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_BITER. */
5514 #define BF_DMA_TCDn_BITER_ELINKNO_BITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKNO_BITER) & BM_DMA_TCDn_BITER_ELINKNO_BITER)
5516 /*! @brief Set the BITER field to a new value. */
5517 #define BW_DMA_TCDn_BITER_ELINKNO_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKNO_BITER) | BF_DMA_TCDn_BITER_ELINKNO_BITER(v)))
5521 * @name Register DMA_TCDn_BITER_ELINKNO, field ELINK[15] (RW)
5523 * As the channel completes the minor loop, this flag enables the linking to
5524 * another channel, defined by BITER[LINKCH]. The link target channel initiates a
5525 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
5526 * bit of the specified channel. If channel linking is disabled, the BITER value
5527 * extends to 15 bits in place of a link channel number. If the major loop is
5528 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
5529 * linking. When the software loads the TCD, this field must be set equal to the
5530 * corresponding CITER field; otherwise, a configuration error is reported. As the
5531 * major iteration count is exhausted, the contents of this field is reloaded
5532 * into the CITER field.
5535 * - 0 - The channel-to-channel linking is disabled
5536 * - 1 - The channel-to-channel linking is enabled
5539 #define BP_DMA_TCDn_BITER_ELINKNO_ELINK (15U) /*!< Bit position for DMA_TCDn_BITER_ELINKNO_ELINK. */
5540 #define BM_DMA_TCDn_BITER_ELINKNO_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_BITER_ELINKNO_ELINK. */
5541 #define BS_DMA_TCDn_BITER_ELINKNO_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_ELINK. */
5543 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_ELINK field. */
5544 #define BR_DMA_TCDn_BITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK))
5546 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_ELINK. */
5547 #define BF_DMA_TCDn_BITER_ELINKNO_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKNO_ELINK) & BM_DMA_TCDn_BITER_ELINKNO_ELINK)
5549 /*! @brief Set the ELINK field to a new value. */
5550 #define BW_DMA_TCDn_BITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK) = (v))
5552 /*******************************************************************************
5553 * HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
5554 ******************************************************************************/
5557 * @brief HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
5559 * Reset value: 0x0000U
5561 * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
5564 typedef union _hw_dma_tcdn_biter_elinkyes
5567 struct _hw_dma_tcdn_biter_elinkyes_bitfields
5569 uint16_t BITER : 9; /*!< [8:0] Starting Major Iteration Count */
5570 uint16_t LINKCH : 4; /*!< [12:9] Link Channel Number */
5571 uint16_t RESERVED0 : 2; /*!< [14:13] */
5572 uint16_t ELINK : 1; /*!< [15] Enables channel-to-channel linking on
5573 * minor loop complete */
5575 } hw_dma_tcdn_biter_elinkyes_t;
5578 * @name Constants and macros for entire DMA_TCDn_BITER_ELINKYES register
5581 #define HW_DMA_TCDn_BITER_ELINKYES_COUNT (16U)
5583 #define HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n)))
5585 #define HW_DMA_TCDn_BITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_biter_elinkyes_t *) HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n))
5586 #define HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U)
5587 #define HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U = (v))
5588 #define HW_DMA_TCDn_BITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) | (v)))
5589 #define HW_DMA_TCDn_BITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~(v)))
5590 #define HW_DMA_TCDn_BITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) ^ (v)))
5594 * Constants & macros for individual DMA_TCDn_BITER_ELINKYES bitfields
5598 * @name Register DMA_TCDn_BITER_ELINKYES, field BITER[8:0] (RW)
5600 * As the transfer control descriptor is first loaded by software, this 9-bit
5601 * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
5602 * field. As the major iteration count is exhausted, the contents of this field
5603 * are reloaded into the CITER field. When the software loads the TCD, this field
5604 * must be set equal to the corresponding CITER field; otherwise, a configuration
5605 * error is reported. As the major iteration count is exhausted, the contents of
5606 * this field is reloaded into the CITER field. If the channel is configured to
5607 * execute a single service request, the initial values of BITER and CITER should
5611 #define BP_DMA_TCDn_BITER_ELINKYES_BITER (0U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_BITER. */
5612 #define BM_DMA_TCDn_BITER_ELINKYES_BITER (0x01FFU) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_BITER. */
5613 #define BS_DMA_TCDn_BITER_ELINKYES_BITER (9U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_BITER. */
5615 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_BITER field. */
5616 #define BR_DMA_TCDn_BITER_ELINKYES_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.BITER)
5618 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_BITER. */
5619 #define BF_DMA_TCDn_BITER_ELINKYES_BITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_BITER) & BM_DMA_TCDn_BITER_ELINKYES_BITER)
5621 /*! @brief Set the BITER field to a new value. */
5622 #define BW_DMA_TCDn_BITER_ELINKYES_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_BITER) | BF_DMA_TCDn_BITER_ELINKYES_BITER(v)))
5626 * @name Register DMA_TCDn_BITER_ELINKYES, field LINKCH[12:9] (RW)
5628 * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
5629 * loop is exhausted, the eDMA engine initiates a channel service request at the
5630 * channel defined by these four bits by setting that channel's TCDn_CSR[START]
5631 * bit. When the software loads the TCD, this field must be set equal to the
5632 * corresponding CITER field; otherwise, a configuration error is reported. As the major
5633 * iteration count is exhausted, the contents of this field is reloaded into the
5637 #define BP_DMA_TCDn_BITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_LINKCH. */
5638 #define BM_DMA_TCDn_BITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_LINKCH. */
5639 #define BS_DMA_TCDn_BITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_LINKCH. */
5641 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_LINKCH field. */
5642 #define BR_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.LINKCH)
5644 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_LINKCH. */
5645 #define BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_LINKCH) & BM_DMA_TCDn_BITER_ELINKYES_LINKCH)
5647 /*! @brief Set the LINKCH field to a new value. */
5648 #define BW_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_LINKCH) | BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v)))
5652 * @name Register DMA_TCDn_BITER_ELINKYES, field ELINK[15] (RW)
5654 * As the channel completes the minor loop, this flag enables the linking to
5655 * another channel, defined by BITER[LINKCH]. The link target channel initiates a
5656 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
5657 * bit of the specified channel. If channel linking disables, the BITER value
5658 * extends to 15 bits in place of a link channel number. If the major loop is
5659 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
5660 * linking. When the software loads the TCD, this field must be set equal to the
5661 * corresponding CITER field; otherwise, a configuration error is reported. As the
5662 * major iteration count is exhausted, the contents of this field is reloaded into
5666 * - 0 - The channel-to-channel linking is disabled
5667 * - 1 - The channel-to-channel linking is enabled
5670 #define BP_DMA_TCDn_BITER_ELINKYES_ELINK (15U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_ELINK. */
5671 #define BM_DMA_TCDn_BITER_ELINKYES_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_ELINK. */
5672 #define BS_DMA_TCDn_BITER_ELINKYES_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_ELINK. */
5674 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_ELINK field. */
5675 #define BR_DMA_TCDn_BITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK))
5677 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_ELINK. */
5678 #define BF_DMA_TCDn_BITER_ELINKYES_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_ELINK) & BM_DMA_TCDn_BITER_ELINKYES_ELINK)
5680 /*! @brief Set the ELINK field to a new value. */
5681 #define BW_DMA_TCDn_BITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK) = (v))
5685 ** Start of section using anonymous unions
5688 #if defined(__ARMCC_VERSION)
5691 #elif defined(__CWCC__)
5693 #pragma cpp_extensions on
5694 #elif defined(__GNUC__)
5695 /* anonymous unions are enabled by default */
5696 #elif defined(__IAR_SYSTEMS_ICC__)
5697 #pragma language=extended
5699 #error Not supported compiler type
5702 /*******************************************************************************
5703 * hw_dma_t - module struct
5704 ******************************************************************************/
5706 * @brief All DMA module registers.
5709 typedef struct _hw_dma
5711 __IO hw_dma_cr_t CR; /*!< [0x0] Control Register */
5712 __I hw_dma_es_t ES; /*!< [0x4] Error Status Register */
5713 uint8_t _reserved0[4];
5714 __IO hw_dma_erq_t ERQ; /*!< [0xC] Enable Request Register */
5715 uint8_t _reserved1[4];
5716 __IO hw_dma_eei_t EEI; /*!< [0x14] Enable Error Interrupt Register */
5717 __O hw_dma_ceei_t CEEI; /*!< [0x18] Clear Enable Error Interrupt Register */
5718 __O hw_dma_seei_t SEEI; /*!< [0x19] Set Enable Error Interrupt Register */
5719 __O hw_dma_cerq_t CERQ; /*!< [0x1A] Clear Enable Request Register */
5720 __O hw_dma_serq_t SERQ; /*!< [0x1B] Set Enable Request Register */
5721 __O hw_dma_cdne_t CDNE; /*!< [0x1C] Clear DONE Status Bit Register */
5722 __O hw_dma_ssrt_t SSRT; /*!< [0x1D] Set START Bit Register */
5723 __O hw_dma_cerr_t CERR; /*!< [0x1E] Clear Error Register */
5724 __O hw_dma_cint_t CINT; /*!< [0x1F] Clear Interrupt Request Register */
5725 uint8_t _reserved2[4];
5726 __IO hw_dma_int_t INT; /*!< [0x24] Interrupt Request Register */
5727 uint8_t _reserved3[4];
5728 __IO hw_dma_err_t ERR; /*!< [0x2C] Error Register */
5729 uint8_t _reserved4[4];
5730 __I hw_dma_hrs_t HRS; /*!< [0x34] Hardware Request Status Register */
5731 uint8_t _reserved5[12];
5732 __IO hw_dma_ears_t EARS; /*!< [0x44] Enable Asynchronous Request in Stop Register */
5733 uint8_t _reserved6[184];
5734 __IO hw_dma_dchprin_t DCHPRIn[16]; /*!< [0x100] Channel n Priority Register */
5735 uint8_t _reserved7[3824];
5737 __IO hw_dma_tcdn_saddr_t TCDn_SADDR; /*!< [0x1000] TCD Source Address */
5738 __IO hw_dma_tcdn_soff_t TCDn_SOFF; /*!< [0x1004] TCD Signed Source Address Offset */
5739 __IO hw_dma_tcdn_attr_t TCDn_ATTR; /*!< [0x1006] TCD Transfer Attributes */
5741 __IO hw_dma_tcdn_nbytes_mlno_t TCDn_NBYTES_MLNO; /*!< [0x1008] TCD Minor Byte Count (Minor Loop Disabled) */
5742 __IO hw_dma_tcdn_nbytes_mloffno_t TCDn_NBYTES_MLOFFNO; /*!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
5743 __IO hw_dma_tcdn_nbytes_mloffyes_t TCDn_NBYTES_MLOFFYES; /*!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
5745 __IO hw_dma_tcdn_slast_t TCDn_SLAST; /*!< [0x100C] TCD Last Source Address Adjustment */
5746 __IO hw_dma_tcdn_daddr_t TCDn_DADDR; /*!< [0x1010] TCD Destination Address */
5747 __IO hw_dma_tcdn_doff_t TCDn_DOFF; /*!< [0x1014] TCD Signed Destination Address Offset */
5749 __IO hw_dma_tcdn_citer_elinkno_t TCDn_CITER_ELINKNO; /*!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
5750 __IO hw_dma_tcdn_citer_elinkyes_t TCDn_CITER_ELINKYES; /*!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
5752 __IO hw_dma_tcdn_dlastsga_t TCDn_DLASTSGA; /*!< [0x1018] TCD Last Destination Address Adjustment/Scatter Gather Address */
5753 __IO hw_dma_tcdn_csr_t TCDn_CSR; /*!< [0x101C] TCD Control and Status */
5755 __IO hw_dma_tcdn_biter_elinkno_t TCDn_BITER_ELINKNO; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
5756 __IO hw_dma_tcdn_biter_elinkyes_t TCDn_BITER_ELINKYES; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
5762 /*! @brief Macro to access all DMA registers. */
5763 /*! @param x DMA module instance base address. */
5764 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
5765 * use the '&' operator, like <code>&HW_DMA(DMA_BASE)</code>. */
5766 #define HW_DMA(x) (*(hw_dma_t *)(x))
5769 ** End of section using anonymous unions
5772 #if defined(__ARMCC_VERSION)
5774 #elif defined(__CWCC__)
5776 #elif defined(__GNUC__)
5777 /* leave anonymous unions enabled */
5778 #elif defined(__IAR_SYSTEMS_ICC__)
5779 #pragma language=default
5781 #error Not supported compiler type
5784 #endif /* __HW_DMA_REGISTERS_H__ */