2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
9 ** Version: rev. 2.5, 2014-05-06
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-07-23)
49 ** - rev. 1.1 (2013-09-17)
50 ** RM rev. 0.4 update.
51 ** - rev. 2.0 (2013-10-29)
52 ** Register accessor macros added to the memory map.
53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
54 ** Startup file for gcc has been updated according to CMSIS 3.2.
55 ** System initialization updated.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-20)
59 ** Update according to reference manual rev. 0.6,
60 ** - rev. 2.3 (2014-01-13)
61 ** Update according to reference manual rev. 0.61,
62 ** - rev. 2.4 (2014-02-10)
63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
64 ** - rev. 2.5 (2014-05-06)
65 ** Update according to reference manual rev. 1.0,
66 ** Update of system and startup files.
67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
69 ** ###################################################################
73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
75 * This file was generated automatically and any changes may be lost.
77 #ifndef __HW_CRC_REGISTERS_H__
78 #define __HW_CRC_REGISTERS_H__
80 #include "MK22F51212.h"
81 #include "fsl_bitaccess.h"
86 * Cyclic Redundancy Check
88 * Registers defined in this header file:
89 * - HW_CRC_DATAL - CRC_DATAL register.
90 * - HW_CRC_DATAH - CRC_DATAH register.
91 * - HW_CRC_DATALL - CRC_DATALL register.
92 * - HW_CRC_DATALU - CRC_DATALU register.
93 * - HW_CRC_DATAHL - CRC_DATAHL register.
94 * - HW_CRC_DATAHU - CRC_DATAHU register.
95 * - HW_CRC_DATA - CRC Data register
96 * - HW_CRC_GPOLY - CRC Polynomial register
97 * - HW_CRC_GPOLYL - CRC_GPOLYL register.
98 * - HW_CRC_GPOLYH - CRC_GPOLYH register.
99 * - HW_CRC_GPOLYLL - CRC_GPOLYLL register.
100 * - HW_CRC_GPOLYLU - CRC_GPOLYLU register.
101 * - HW_CRC_GPOLYHL - CRC_GPOLYHL register.
102 * - HW_CRC_GPOLYHU - CRC_GPOLYHU register.
103 * - HW_CRC_CTRL - CRC Control register
104 * - HW_CRC_CTRLHU - CRC_CTRLHU register.
106 * - hw_crc_t - Struct containing all module registers.
109 #define HW_CRC_INSTANCE_COUNT (1U) /*!< Number of instances of the CRC module. */
111 /*******************************************************************************
112 * HW_CRC_DATAL - CRC_DATAL register.
113 ******************************************************************************/
116 * @brief HW_CRC_DATAL - CRC_DATAL register. (RW)
118 * Reset value: 0xFFFFU
120 typedef union _hw_crc_datal
123 struct _hw_crc_datal_bitfields
125 uint16_t DATAL : 16; /*!< [15:0] DATAL stores the lower 16 bits of
126 * the 16/32 bit CRC */
131 * @name Constants and macros for entire CRC_DATAL register
134 #define HW_CRC_DATAL_ADDR(x) ((x) + 0x0U)
136 #define HW_CRC_DATAL(x) (*(__IO hw_crc_datal_t *) HW_CRC_DATAL_ADDR(x))
137 #define HW_CRC_DATAL_RD(x) (HW_CRC_DATAL(x).U)
138 #define HW_CRC_DATAL_WR(x, v) (HW_CRC_DATAL(x).U = (v))
139 #define HW_CRC_DATAL_SET(x, v) (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) | (v)))
140 #define HW_CRC_DATAL_CLR(x, v) (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) & ~(v)))
141 #define HW_CRC_DATAL_TOG(x, v) (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) ^ (v)))
145 * Constants & macros for individual CRC_DATAL bitfields
149 * @name Register CRC_DATAL, field DATAL[15:0] (RW)
152 #define BP_CRC_DATAL_DATAL (0U) /*!< Bit position for CRC_DATAL_DATAL. */
153 #define BM_CRC_DATAL_DATAL (0xFFFFU) /*!< Bit mask for CRC_DATAL_DATAL. */
154 #define BS_CRC_DATAL_DATAL (16U) /*!< Bit field size in bits for CRC_DATAL_DATAL. */
156 /*! @brief Read current value of the CRC_DATAL_DATAL field. */
157 #define BR_CRC_DATAL_DATAL(x) (HW_CRC_DATAL(x).U)
159 /*! @brief Format value for bitfield CRC_DATAL_DATAL. */
160 #define BF_CRC_DATAL_DATAL(v) ((uint16_t)((uint16_t)(v) << BP_CRC_DATAL_DATAL) & BM_CRC_DATAL_DATAL)
162 /*! @brief Set the DATAL field to a new value. */
163 #define BW_CRC_DATAL_DATAL(x, v) (HW_CRC_DATAL_WR(x, v))
165 /*******************************************************************************
166 * HW_CRC_DATAH - CRC_DATAH register.
167 ******************************************************************************/
170 * @brief HW_CRC_DATAH - CRC_DATAH register. (RW)
172 * Reset value: 0xFFFFU
174 typedef union _hw_crc_datah
177 struct _hw_crc_datah_bitfields
179 uint16_t DATAH : 16; /*!< [15:0] DATAH stores the high 16 bits of the
185 * @name Constants and macros for entire CRC_DATAH register
188 #define HW_CRC_DATAH_ADDR(x) ((x) + 0x2U)
190 #define HW_CRC_DATAH(x) (*(__IO hw_crc_datah_t *) HW_CRC_DATAH_ADDR(x))
191 #define HW_CRC_DATAH_RD(x) (HW_CRC_DATAH(x).U)
192 #define HW_CRC_DATAH_WR(x, v) (HW_CRC_DATAH(x).U = (v))
193 #define HW_CRC_DATAH_SET(x, v) (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) | (v)))
194 #define HW_CRC_DATAH_CLR(x, v) (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) & ~(v)))
195 #define HW_CRC_DATAH_TOG(x, v) (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) ^ (v)))
199 * Constants & macros for individual CRC_DATAH bitfields
203 * @name Register CRC_DATAH, field DATAH[15:0] (RW)
206 #define BP_CRC_DATAH_DATAH (0U) /*!< Bit position for CRC_DATAH_DATAH. */
207 #define BM_CRC_DATAH_DATAH (0xFFFFU) /*!< Bit mask for CRC_DATAH_DATAH. */
208 #define BS_CRC_DATAH_DATAH (16U) /*!< Bit field size in bits for CRC_DATAH_DATAH. */
210 /*! @brief Read current value of the CRC_DATAH_DATAH field. */
211 #define BR_CRC_DATAH_DATAH(x) (HW_CRC_DATAH(x).U)
213 /*! @brief Format value for bitfield CRC_DATAH_DATAH. */
214 #define BF_CRC_DATAH_DATAH(v) ((uint16_t)((uint16_t)(v) << BP_CRC_DATAH_DATAH) & BM_CRC_DATAH_DATAH)
216 /*! @brief Set the DATAH field to a new value. */
217 #define BW_CRC_DATAH_DATAH(x, v) (HW_CRC_DATAH_WR(x, v))
219 /*******************************************************************************
220 * HW_CRC_DATALL - CRC_DATALL register.
221 ******************************************************************************/
224 * @brief HW_CRC_DATALL - CRC_DATALL register. (RW)
228 typedef union _hw_crc_datall
231 struct _hw_crc_datall_bitfields
233 uint8_t DATALL : 8; /*!< [7:0] CRCLL stores the first 8 bits of the
239 * @name Constants and macros for entire CRC_DATALL register
242 #define HW_CRC_DATALL_ADDR(x) ((x) + 0x0U)
244 #define HW_CRC_DATALL(x) (*(__IO hw_crc_datall_t *) HW_CRC_DATALL_ADDR(x))
245 #define HW_CRC_DATALL_RD(x) (HW_CRC_DATALL(x).U)
246 #define HW_CRC_DATALL_WR(x, v) (HW_CRC_DATALL(x).U = (v))
247 #define HW_CRC_DATALL_SET(x, v) (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) | (v)))
248 #define HW_CRC_DATALL_CLR(x, v) (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) & ~(v)))
249 #define HW_CRC_DATALL_TOG(x, v) (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) ^ (v)))
253 * Constants & macros for individual CRC_DATALL bitfields
257 * @name Register CRC_DATALL, field DATALL[7:0] (RW)
260 #define BP_CRC_DATALL_DATALL (0U) /*!< Bit position for CRC_DATALL_DATALL. */
261 #define BM_CRC_DATALL_DATALL (0xFFU) /*!< Bit mask for CRC_DATALL_DATALL. */
262 #define BS_CRC_DATALL_DATALL (8U) /*!< Bit field size in bits for CRC_DATALL_DATALL. */
264 /*! @brief Read current value of the CRC_DATALL_DATALL field. */
265 #define BR_CRC_DATALL_DATALL(x) (HW_CRC_DATALL(x).U)
267 /*! @brief Format value for bitfield CRC_DATALL_DATALL. */
268 #define BF_CRC_DATALL_DATALL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATALL_DATALL) & BM_CRC_DATALL_DATALL)
270 /*! @brief Set the DATALL field to a new value. */
271 #define BW_CRC_DATALL_DATALL(x, v) (HW_CRC_DATALL_WR(x, v))
273 /*******************************************************************************
274 * HW_CRC_DATALU - CRC_DATALU register.
275 ******************************************************************************/
278 * @brief HW_CRC_DATALU - CRC_DATALU register. (RW)
282 typedef union _hw_crc_datalu
285 struct _hw_crc_datalu_bitfields
287 uint8_t DATALU : 8; /*!< [7:0] DATALL stores the second 8 bits of the
293 * @name Constants and macros for entire CRC_DATALU register
296 #define HW_CRC_DATALU_ADDR(x) ((x) + 0x1U)
298 #define HW_CRC_DATALU(x) (*(__IO hw_crc_datalu_t *) HW_CRC_DATALU_ADDR(x))
299 #define HW_CRC_DATALU_RD(x) (HW_CRC_DATALU(x).U)
300 #define HW_CRC_DATALU_WR(x, v) (HW_CRC_DATALU(x).U = (v))
301 #define HW_CRC_DATALU_SET(x, v) (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) | (v)))
302 #define HW_CRC_DATALU_CLR(x, v) (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) & ~(v)))
303 #define HW_CRC_DATALU_TOG(x, v) (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) ^ (v)))
307 * Constants & macros for individual CRC_DATALU bitfields
311 * @name Register CRC_DATALU, field DATALU[7:0] (RW)
314 #define BP_CRC_DATALU_DATALU (0U) /*!< Bit position for CRC_DATALU_DATALU. */
315 #define BM_CRC_DATALU_DATALU (0xFFU) /*!< Bit mask for CRC_DATALU_DATALU. */
316 #define BS_CRC_DATALU_DATALU (8U) /*!< Bit field size in bits for CRC_DATALU_DATALU. */
318 /*! @brief Read current value of the CRC_DATALU_DATALU field. */
319 #define BR_CRC_DATALU_DATALU(x) (HW_CRC_DATALU(x).U)
321 /*! @brief Format value for bitfield CRC_DATALU_DATALU. */
322 #define BF_CRC_DATALU_DATALU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATALU_DATALU) & BM_CRC_DATALU_DATALU)
324 /*! @brief Set the DATALU field to a new value. */
325 #define BW_CRC_DATALU_DATALU(x, v) (HW_CRC_DATALU_WR(x, v))
327 /*******************************************************************************
328 * HW_CRC_DATAHL - CRC_DATAHL register.
329 ******************************************************************************/
332 * @brief HW_CRC_DATAHL - CRC_DATAHL register. (RW)
336 typedef union _hw_crc_datahl
339 struct _hw_crc_datahl_bitfields
341 uint8_t DATAHL : 8; /*!< [7:0] DATAHL stores the third 8 bits of the
347 * @name Constants and macros for entire CRC_DATAHL register
350 #define HW_CRC_DATAHL_ADDR(x) ((x) + 0x2U)
352 #define HW_CRC_DATAHL(x) (*(__IO hw_crc_datahl_t *) HW_CRC_DATAHL_ADDR(x))
353 #define HW_CRC_DATAHL_RD(x) (HW_CRC_DATAHL(x).U)
354 #define HW_CRC_DATAHL_WR(x, v) (HW_CRC_DATAHL(x).U = (v))
355 #define HW_CRC_DATAHL_SET(x, v) (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) | (v)))
356 #define HW_CRC_DATAHL_CLR(x, v) (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) & ~(v)))
357 #define HW_CRC_DATAHL_TOG(x, v) (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) ^ (v)))
361 * Constants & macros for individual CRC_DATAHL bitfields
365 * @name Register CRC_DATAHL, field DATAHL[7:0] (RW)
368 #define BP_CRC_DATAHL_DATAHL (0U) /*!< Bit position for CRC_DATAHL_DATAHL. */
369 #define BM_CRC_DATAHL_DATAHL (0xFFU) /*!< Bit mask for CRC_DATAHL_DATAHL. */
370 #define BS_CRC_DATAHL_DATAHL (8U) /*!< Bit field size in bits for CRC_DATAHL_DATAHL. */
372 /*! @brief Read current value of the CRC_DATAHL_DATAHL field. */
373 #define BR_CRC_DATAHL_DATAHL(x) (HW_CRC_DATAHL(x).U)
375 /*! @brief Format value for bitfield CRC_DATAHL_DATAHL. */
376 #define BF_CRC_DATAHL_DATAHL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATAHL_DATAHL) & BM_CRC_DATAHL_DATAHL)
378 /*! @brief Set the DATAHL field to a new value. */
379 #define BW_CRC_DATAHL_DATAHL(x, v) (HW_CRC_DATAHL_WR(x, v))
381 /*******************************************************************************
382 * HW_CRC_DATAHU - CRC_DATAHU register.
383 ******************************************************************************/
386 * @brief HW_CRC_DATAHU - CRC_DATAHU register. (RW)
390 typedef union _hw_crc_datahu
393 struct _hw_crc_datahu_bitfields
395 uint8_t DATAHU : 8; /*!< [7:0] DATAHU stores the fourth 8 bits of the
401 * @name Constants and macros for entire CRC_DATAHU register
404 #define HW_CRC_DATAHU_ADDR(x) ((x) + 0x3U)
406 #define HW_CRC_DATAHU(x) (*(__IO hw_crc_datahu_t *) HW_CRC_DATAHU_ADDR(x))
407 #define HW_CRC_DATAHU_RD(x) (HW_CRC_DATAHU(x).U)
408 #define HW_CRC_DATAHU_WR(x, v) (HW_CRC_DATAHU(x).U = (v))
409 #define HW_CRC_DATAHU_SET(x, v) (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) | (v)))
410 #define HW_CRC_DATAHU_CLR(x, v) (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) & ~(v)))
411 #define HW_CRC_DATAHU_TOG(x, v) (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) ^ (v)))
415 * Constants & macros for individual CRC_DATAHU bitfields
419 * @name Register CRC_DATAHU, field DATAHU[7:0] (RW)
422 #define BP_CRC_DATAHU_DATAHU (0U) /*!< Bit position for CRC_DATAHU_DATAHU. */
423 #define BM_CRC_DATAHU_DATAHU (0xFFU) /*!< Bit mask for CRC_DATAHU_DATAHU. */
424 #define BS_CRC_DATAHU_DATAHU (8U) /*!< Bit field size in bits for CRC_DATAHU_DATAHU. */
426 /*! @brief Read current value of the CRC_DATAHU_DATAHU field. */
427 #define BR_CRC_DATAHU_DATAHU(x) (HW_CRC_DATAHU(x).U)
429 /*! @brief Format value for bitfield CRC_DATAHU_DATAHU. */
430 #define BF_CRC_DATAHU_DATAHU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATAHU_DATAHU) & BM_CRC_DATAHU_DATAHU)
432 /*! @brief Set the DATAHU field to a new value. */
433 #define BW_CRC_DATAHU_DATAHU(x, v) (HW_CRC_DATAHU_WR(x, v))
435 /*******************************************************************************
436 * HW_CRC_DATA - CRC Data register
437 ******************************************************************************/
440 * @brief HW_CRC_DATA - CRC Data register (RW)
442 * Reset value: 0xFFFFFFFFU
444 * The CRC Data register contains the value of the seed, data, and checksum.
445 * When CTRL[WAS] is set, any write to the data register is regarded as the seed
446 * value. When CTRL[WAS] is cleared, any write to the data register is regarded as
447 * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are
448 * not used for programming the seed value, and reads of these fields return an
449 * indeterminate value. In 32-bit CRC mode, all fields are used for programming
450 * the seed value. When programming data values, the values can be written 8 bits,
451 * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of
452 * data value written first. After all data values are written, the CRC result
453 * can be read from this data register. In 16-bit CRC mode, the CRC result is
454 * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the
455 * result. Reads of this register at any time return the intermediate CRC value,
456 * provided the CRC module is configured.
458 typedef union _hw_crc_data
461 struct _hw_crc_data_bitfields
463 uint32_t LL : 8; /*!< [7:0] CRC Low Lower Byte */
464 uint32_t LU : 8; /*!< [15:8] CRC Low Upper Byte */
465 uint32_t HL : 8; /*!< [23:16] CRC High Lower Byte */
466 uint32_t HU : 8; /*!< [31:24] CRC High Upper Byte */
471 * @name Constants and macros for entire CRC_DATA register
474 #define HW_CRC_DATA_ADDR(x) ((x) + 0x0U)
476 #define HW_CRC_DATA(x) (*(__IO hw_crc_data_t *) HW_CRC_DATA_ADDR(x))
477 #define HW_CRC_DATA_RD(x) (HW_CRC_DATA(x).U)
478 #define HW_CRC_DATA_WR(x, v) (HW_CRC_DATA(x).U = (v))
479 #define HW_CRC_DATA_SET(x, v) (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) | (v)))
480 #define HW_CRC_DATA_CLR(x, v) (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) & ~(v)))
481 #define HW_CRC_DATA_TOG(x, v) (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) ^ (v)))
485 * Constants & macros for individual CRC_DATA bitfields
489 * @name Register CRC_DATA, field LL[7:0] (RW)
491 * When CTRL[WAS] is 1, values written to this field are part of the seed value.
492 * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
496 #define BP_CRC_DATA_LL (0U) /*!< Bit position for CRC_DATA_LL. */
497 #define BM_CRC_DATA_LL (0x000000FFU) /*!< Bit mask for CRC_DATA_LL. */
498 #define BS_CRC_DATA_LL (8U) /*!< Bit field size in bits for CRC_DATA_LL. */
500 /*! @brief Read current value of the CRC_DATA_LL field. */
501 #define BR_CRC_DATA_LL(x) (HW_CRC_DATA(x).B.LL)
503 /*! @brief Format value for bitfield CRC_DATA_LL. */
504 #define BF_CRC_DATA_LL(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_LL) & BM_CRC_DATA_LL)
506 /*! @brief Set the LL field to a new value. */
507 #define BW_CRC_DATA_LL(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_LL) | BF_CRC_DATA_LL(v)))
511 * @name Register CRC_DATA, field LU[15:8] (RW)
513 * When CTRL[WAS] is 1, values written to this field are part of the seed value.
514 * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
518 #define BP_CRC_DATA_LU (8U) /*!< Bit position for CRC_DATA_LU. */
519 #define BM_CRC_DATA_LU (0x0000FF00U) /*!< Bit mask for CRC_DATA_LU. */
520 #define BS_CRC_DATA_LU (8U) /*!< Bit field size in bits for CRC_DATA_LU. */
522 /*! @brief Read current value of the CRC_DATA_LU field. */
523 #define BR_CRC_DATA_LU(x) (HW_CRC_DATA(x).B.LU)
525 /*! @brief Format value for bitfield CRC_DATA_LU. */
526 #define BF_CRC_DATA_LU(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_LU) & BM_CRC_DATA_LU)
528 /*! @brief Set the LU field to a new value. */
529 #define BW_CRC_DATA_LU(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_LU) | BF_CRC_DATA_LU(v)))
533 * @name Register CRC_DATA, field HL[23:16] (RW)
535 * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
536 * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
537 * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
538 * written to this field is used for CRC checksum generation in both 16-bit and
542 #define BP_CRC_DATA_HL (16U) /*!< Bit position for CRC_DATA_HL. */
543 #define BM_CRC_DATA_HL (0x00FF0000U) /*!< Bit mask for CRC_DATA_HL. */
544 #define BS_CRC_DATA_HL (8U) /*!< Bit field size in bits for CRC_DATA_HL. */
546 /*! @brief Read current value of the CRC_DATA_HL field. */
547 #define BR_CRC_DATA_HL(x) (HW_CRC_DATA(x).B.HL)
549 /*! @brief Format value for bitfield CRC_DATA_HL. */
550 #define BF_CRC_DATA_HL(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_HL) & BM_CRC_DATA_HL)
552 /*! @brief Set the HL field to a new value. */
553 #define BW_CRC_DATA_HL(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_HL) | BF_CRC_DATA_HL(v)))
557 * @name Register CRC_DATA, field HU[31:24] (RW)
559 * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
560 * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
561 * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
562 * written to this field is used for CRC checksum generation in both 16-bit and
566 #define BP_CRC_DATA_HU (24U) /*!< Bit position for CRC_DATA_HU. */
567 #define BM_CRC_DATA_HU (0xFF000000U) /*!< Bit mask for CRC_DATA_HU. */
568 #define BS_CRC_DATA_HU (8U) /*!< Bit field size in bits for CRC_DATA_HU. */
570 /*! @brief Read current value of the CRC_DATA_HU field. */
571 #define BR_CRC_DATA_HU(x) (HW_CRC_DATA(x).B.HU)
573 /*! @brief Format value for bitfield CRC_DATA_HU. */
574 #define BF_CRC_DATA_HU(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_HU) & BM_CRC_DATA_HU)
576 /*! @brief Set the HU field to a new value. */
577 #define BW_CRC_DATA_HU(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_HU) | BF_CRC_DATA_HU(v)))
580 /*******************************************************************************
581 * HW_CRC_GPOLY - CRC Polynomial register
582 ******************************************************************************/
585 * @brief HW_CRC_GPOLY - CRC Polynomial register (RW)
587 * Reset value: 0x00001021U
589 * This register contains the value of the polynomial for the CRC calculation.
590 * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used
591 * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC
592 * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are
593 * used in both 16- and 32-bit CRC modes.
595 typedef union _hw_crc_gpoly
598 struct _hw_crc_gpoly_bitfields
600 uint32_t LOW : 16; /*!< [15:0] Low Polynominal Half-word */
601 uint32_t HIGH : 16; /*!< [31:16] High Polynominal Half-word */
606 * @name Constants and macros for entire CRC_GPOLY register
609 #define HW_CRC_GPOLY_ADDR(x) ((x) + 0x4U)
611 #define HW_CRC_GPOLY(x) (*(__IO hw_crc_gpoly_t *) HW_CRC_GPOLY_ADDR(x))
612 #define HW_CRC_GPOLY_RD(x) (HW_CRC_GPOLY(x).U)
613 #define HW_CRC_GPOLY_WR(x, v) (HW_CRC_GPOLY(x).U = (v))
614 #define HW_CRC_GPOLY_SET(x, v) (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) | (v)))
615 #define HW_CRC_GPOLY_CLR(x, v) (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) & ~(v)))
616 #define HW_CRC_GPOLY_TOG(x, v) (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) ^ (v)))
620 * Constants & macros for individual CRC_GPOLY bitfields
624 * @name Register CRC_GPOLY, field LOW[15:0] (RW)
626 * Writable and readable in both 32-bit and 16-bit CRC modes.
629 #define BP_CRC_GPOLY_LOW (0U) /*!< Bit position for CRC_GPOLY_LOW. */
630 #define BM_CRC_GPOLY_LOW (0x0000FFFFU) /*!< Bit mask for CRC_GPOLY_LOW. */
631 #define BS_CRC_GPOLY_LOW (16U) /*!< Bit field size in bits for CRC_GPOLY_LOW. */
633 /*! @brief Read current value of the CRC_GPOLY_LOW field. */
634 #define BR_CRC_GPOLY_LOW(x) (HW_CRC_GPOLY(x).B.LOW)
636 /*! @brief Format value for bitfield CRC_GPOLY_LOW. */
637 #define BF_CRC_GPOLY_LOW(v) ((uint32_t)((uint32_t)(v) << BP_CRC_GPOLY_LOW) & BM_CRC_GPOLY_LOW)
639 /*! @brief Set the LOW field to a new value. */
640 #define BW_CRC_GPOLY_LOW(x, v) (HW_CRC_GPOLY_WR(x, (HW_CRC_GPOLY_RD(x) & ~BM_CRC_GPOLY_LOW) | BF_CRC_GPOLY_LOW(v)))
644 * @name Register CRC_GPOLY, field HIGH[31:16] (RW)
646 * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not
647 * writable in 16-bit CRC mode (CTRL[TCRC] is 0).
650 #define BP_CRC_GPOLY_HIGH (16U) /*!< Bit position for CRC_GPOLY_HIGH. */
651 #define BM_CRC_GPOLY_HIGH (0xFFFF0000U) /*!< Bit mask for CRC_GPOLY_HIGH. */
652 #define BS_CRC_GPOLY_HIGH (16U) /*!< Bit field size in bits for CRC_GPOLY_HIGH. */
654 /*! @brief Read current value of the CRC_GPOLY_HIGH field. */
655 #define BR_CRC_GPOLY_HIGH(x) (HW_CRC_GPOLY(x).B.HIGH)
657 /*! @brief Format value for bitfield CRC_GPOLY_HIGH. */
658 #define BF_CRC_GPOLY_HIGH(v) ((uint32_t)((uint32_t)(v) << BP_CRC_GPOLY_HIGH) & BM_CRC_GPOLY_HIGH)
660 /*! @brief Set the HIGH field to a new value. */
661 #define BW_CRC_GPOLY_HIGH(x, v) (HW_CRC_GPOLY_WR(x, (HW_CRC_GPOLY_RD(x) & ~BM_CRC_GPOLY_HIGH) | BF_CRC_GPOLY_HIGH(v)))
663 /*******************************************************************************
664 * HW_CRC_GPOLYL - CRC_GPOLYL register.
665 ******************************************************************************/
668 * @brief HW_CRC_GPOLYL - CRC_GPOLYL register. (RW)
670 * Reset value: 0xFFFFU
672 typedef union _hw_crc_gpolyl
675 struct _hw_crc_gpolyl_bitfields
677 uint16_t GPOLYL : 16; /*!< [15:0] POLYL stores the lower 16 bits of
678 * the 16/32 bit CRC polynomial value */
683 * @name Constants and macros for entire CRC_GPOLYL register
686 #define HW_CRC_GPOLYL_ADDR(x) ((x) + 0x4U)
688 #define HW_CRC_GPOLYL(x) (*(__IO hw_crc_gpolyl_t *) HW_CRC_GPOLYL_ADDR(x))
689 #define HW_CRC_GPOLYL_RD(x) (HW_CRC_GPOLYL(x).U)
690 #define HW_CRC_GPOLYL_WR(x, v) (HW_CRC_GPOLYL(x).U = (v))
691 #define HW_CRC_GPOLYL_SET(x, v) (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) | (v)))
692 #define HW_CRC_GPOLYL_CLR(x, v) (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) & ~(v)))
693 #define HW_CRC_GPOLYL_TOG(x, v) (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) ^ (v)))
697 * Constants & macros for individual CRC_GPOLYL bitfields
701 * @name Register CRC_GPOLYL, field GPOLYL[15:0] (RW)
704 #define BP_CRC_GPOLYL_GPOLYL (0U) /*!< Bit position for CRC_GPOLYL_GPOLYL. */
705 #define BM_CRC_GPOLYL_GPOLYL (0xFFFFU) /*!< Bit mask for CRC_GPOLYL_GPOLYL. */
706 #define BS_CRC_GPOLYL_GPOLYL (16U) /*!< Bit field size in bits for CRC_GPOLYL_GPOLYL. */
708 /*! @brief Read current value of the CRC_GPOLYL_GPOLYL field. */
709 #define BR_CRC_GPOLYL_GPOLYL(x) (HW_CRC_GPOLYL(x).U)
711 /*! @brief Format value for bitfield CRC_GPOLYL_GPOLYL. */
712 #define BF_CRC_GPOLYL_GPOLYL(v) ((uint16_t)((uint16_t)(v) << BP_CRC_GPOLYL_GPOLYL) & BM_CRC_GPOLYL_GPOLYL)
714 /*! @brief Set the GPOLYL field to a new value. */
715 #define BW_CRC_GPOLYL_GPOLYL(x, v) (HW_CRC_GPOLYL_WR(x, v))
717 /*******************************************************************************
718 * HW_CRC_GPOLYH - CRC_GPOLYH register.
719 ******************************************************************************/
722 * @brief HW_CRC_GPOLYH - CRC_GPOLYH register. (RW)
724 * Reset value: 0xFFFFU
726 typedef union _hw_crc_gpolyh
729 struct _hw_crc_gpolyh_bitfields
731 uint16_t GPOLYH : 16; /*!< [15:0] POLYH stores the high 16 bits of
732 * the 16/32 bit CRC polynomial value */
737 * @name Constants and macros for entire CRC_GPOLYH register
740 #define HW_CRC_GPOLYH_ADDR(x) ((x) + 0x6U)
742 #define HW_CRC_GPOLYH(x) (*(__IO hw_crc_gpolyh_t *) HW_CRC_GPOLYH_ADDR(x))
743 #define HW_CRC_GPOLYH_RD(x) (HW_CRC_GPOLYH(x).U)
744 #define HW_CRC_GPOLYH_WR(x, v) (HW_CRC_GPOLYH(x).U = (v))
745 #define HW_CRC_GPOLYH_SET(x, v) (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) | (v)))
746 #define HW_CRC_GPOLYH_CLR(x, v) (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) & ~(v)))
747 #define HW_CRC_GPOLYH_TOG(x, v) (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) ^ (v)))
751 * Constants & macros for individual CRC_GPOLYH bitfields
755 * @name Register CRC_GPOLYH, field GPOLYH[15:0] (RW)
758 #define BP_CRC_GPOLYH_GPOLYH (0U) /*!< Bit position for CRC_GPOLYH_GPOLYH. */
759 #define BM_CRC_GPOLYH_GPOLYH (0xFFFFU) /*!< Bit mask for CRC_GPOLYH_GPOLYH. */
760 #define BS_CRC_GPOLYH_GPOLYH (16U) /*!< Bit field size in bits for CRC_GPOLYH_GPOLYH. */
762 /*! @brief Read current value of the CRC_GPOLYH_GPOLYH field. */
763 #define BR_CRC_GPOLYH_GPOLYH(x) (HW_CRC_GPOLYH(x).U)
765 /*! @brief Format value for bitfield CRC_GPOLYH_GPOLYH. */
766 #define BF_CRC_GPOLYH_GPOLYH(v) ((uint16_t)((uint16_t)(v) << BP_CRC_GPOLYH_GPOLYH) & BM_CRC_GPOLYH_GPOLYH)
768 /*! @brief Set the GPOLYH field to a new value. */
769 #define BW_CRC_GPOLYH_GPOLYH(x, v) (HW_CRC_GPOLYH_WR(x, v))
771 /*******************************************************************************
772 * HW_CRC_GPOLYLL - CRC_GPOLYLL register.
773 ******************************************************************************/
776 * @brief HW_CRC_GPOLYLL - CRC_GPOLYLL register. (RW)
780 typedef union _hw_crc_gpolyll
783 struct _hw_crc_gpolyll_bitfields
785 uint8_t GPOLYLL : 8; /*!< [7:0] POLYLL stores the first 8 bits of the
791 * @name Constants and macros for entire CRC_GPOLYLL register
794 #define HW_CRC_GPOLYLL_ADDR(x) ((x) + 0x4U)
796 #define HW_CRC_GPOLYLL(x) (*(__IO hw_crc_gpolyll_t *) HW_CRC_GPOLYLL_ADDR(x))
797 #define HW_CRC_GPOLYLL_RD(x) (HW_CRC_GPOLYLL(x).U)
798 #define HW_CRC_GPOLYLL_WR(x, v) (HW_CRC_GPOLYLL(x).U = (v))
799 #define HW_CRC_GPOLYLL_SET(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) | (v)))
800 #define HW_CRC_GPOLYLL_CLR(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) & ~(v)))
801 #define HW_CRC_GPOLYLL_TOG(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) ^ (v)))
805 * Constants & macros for individual CRC_GPOLYLL bitfields
809 * @name Register CRC_GPOLYLL, field GPOLYLL[7:0] (RW)
812 #define BP_CRC_GPOLYLL_GPOLYLL (0U) /*!< Bit position for CRC_GPOLYLL_GPOLYLL. */
813 #define BM_CRC_GPOLYLL_GPOLYLL (0xFFU) /*!< Bit mask for CRC_GPOLYLL_GPOLYLL. */
814 #define BS_CRC_GPOLYLL_GPOLYLL (8U) /*!< Bit field size in bits for CRC_GPOLYLL_GPOLYLL. */
816 /*! @brief Read current value of the CRC_GPOLYLL_GPOLYLL field. */
817 #define BR_CRC_GPOLYLL_GPOLYLL(x) (HW_CRC_GPOLYLL(x).U)
819 /*! @brief Format value for bitfield CRC_GPOLYLL_GPOLYLL. */
820 #define BF_CRC_GPOLYLL_GPOLYLL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYLL_GPOLYLL) & BM_CRC_GPOLYLL_GPOLYLL)
822 /*! @brief Set the GPOLYLL field to a new value. */
823 #define BW_CRC_GPOLYLL_GPOLYLL(x, v) (HW_CRC_GPOLYLL_WR(x, v))
825 /*******************************************************************************
826 * HW_CRC_GPOLYLU - CRC_GPOLYLU register.
827 ******************************************************************************/
830 * @brief HW_CRC_GPOLYLU - CRC_GPOLYLU register. (RW)
834 typedef union _hw_crc_gpolylu
837 struct _hw_crc_gpolylu_bitfields
839 uint8_t GPOLYLU : 8; /*!< [7:0] POLYLL stores the second 8 bits of
845 * @name Constants and macros for entire CRC_GPOLYLU register
848 #define HW_CRC_GPOLYLU_ADDR(x) ((x) + 0x5U)
850 #define HW_CRC_GPOLYLU(x) (*(__IO hw_crc_gpolylu_t *) HW_CRC_GPOLYLU_ADDR(x))
851 #define HW_CRC_GPOLYLU_RD(x) (HW_CRC_GPOLYLU(x).U)
852 #define HW_CRC_GPOLYLU_WR(x, v) (HW_CRC_GPOLYLU(x).U = (v))
853 #define HW_CRC_GPOLYLU_SET(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) | (v)))
854 #define HW_CRC_GPOLYLU_CLR(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) & ~(v)))
855 #define HW_CRC_GPOLYLU_TOG(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) ^ (v)))
859 * Constants & macros for individual CRC_GPOLYLU bitfields
863 * @name Register CRC_GPOLYLU, field GPOLYLU[7:0] (RW)
866 #define BP_CRC_GPOLYLU_GPOLYLU (0U) /*!< Bit position for CRC_GPOLYLU_GPOLYLU. */
867 #define BM_CRC_GPOLYLU_GPOLYLU (0xFFU) /*!< Bit mask for CRC_GPOLYLU_GPOLYLU. */
868 #define BS_CRC_GPOLYLU_GPOLYLU (8U) /*!< Bit field size in bits for CRC_GPOLYLU_GPOLYLU. */
870 /*! @brief Read current value of the CRC_GPOLYLU_GPOLYLU field. */
871 #define BR_CRC_GPOLYLU_GPOLYLU(x) (HW_CRC_GPOLYLU(x).U)
873 /*! @brief Format value for bitfield CRC_GPOLYLU_GPOLYLU. */
874 #define BF_CRC_GPOLYLU_GPOLYLU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYLU_GPOLYLU) & BM_CRC_GPOLYLU_GPOLYLU)
876 /*! @brief Set the GPOLYLU field to a new value. */
877 #define BW_CRC_GPOLYLU_GPOLYLU(x, v) (HW_CRC_GPOLYLU_WR(x, v))
879 /*******************************************************************************
880 * HW_CRC_GPOLYHL - CRC_GPOLYHL register.
881 ******************************************************************************/
884 * @brief HW_CRC_GPOLYHL - CRC_GPOLYHL register. (RW)
888 typedef union _hw_crc_gpolyhl
891 struct _hw_crc_gpolyhl_bitfields
893 uint8_t GPOLYHL : 8; /*!< [7:0] POLYHL stores the third 8 bits of the
899 * @name Constants and macros for entire CRC_GPOLYHL register
902 #define HW_CRC_GPOLYHL_ADDR(x) ((x) + 0x6U)
904 #define HW_CRC_GPOLYHL(x) (*(__IO hw_crc_gpolyhl_t *) HW_CRC_GPOLYHL_ADDR(x))
905 #define HW_CRC_GPOLYHL_RD(x) (HW_CRC_GPOLYHL(x).U)
906 #define HW_CRC_GPOLYHL_WR(x, v) (HW_CRC_GPOLYHL(x).U = (v))
907 #define HW_CRC_GPOLYHL_SET(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) | (v)))
908 #define HW_CRC_GPOLYHL_CLR(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) & ~(v)))
909 #define HW_CRC_GPOLYHL_TOG(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) ^ (v)))
913 * Constants & macros for individual CRC_GPOLYHL bitfields
917 * @name Register CRC_GPOLYHL, field GPOLYHL[7:0] (RW)
920 #define BP_CRC_GPOLYHL_GPOLYHL (0U) /*!< Bit position for CRC_GPOLYHL_GPOLYHL. */
921 #define BM_CRC_GPOLYHL_GPOLYHL (0xFFU) /*!< Bit mask for CRC_GPOLYHL_GPOLYHL. */
922 #define BS_CRC_GPOLYHL_GPOLYHL (8U) /*!< Bit field size in bits for CRC_GPOLYHL_GPOLYHL. */
924 /*! @brief Read current value of the CRC_GPOLYHL_GPOLYHL field. */
925 #define BR_CRC_GPOLYHL_GPOLYHL(x) (HW_CRC_GPOLYHL(x).U)
927 /*! @brief Format value for bitfield CRC_GPOLYHL_GPOLYHL. */
928 #define BF_CRC_GPOLYHL_GPOLYHL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYHL_GPOLYHL) & BM_CRC_GPOLYHL_GPOLYHL)
930 /*! @brief Set the GPOLYHL field to a new value. */
931 #define BW_CRC_GPOLYHL_GPOLYHL(x, v) (HW_CRC_GPOLYHL_WR(x, v))
933 /*******************************************************************************
934 * HW_CRC_GPOLYHU - CRC_GPOLYHU register.
935 ******************************************************************************/
938 * @brief HW_CRC_GPOLYHU - CRC_GPOLYHU register. (RW)
942 typedef union _hw_crc_gpolyhu
945 struct _hw_crc_gpolyhu_bitfields
947 uint8_t GPOLYHU : 8; /*!< [7:0] POLYHU stores the fourth 8 bits of
953 * @name Constants and macros for entire CRC_GPOLYHU register
956 #define HW_CRC_GPOLYHU_ADDR(x) ((x) + 0x7U)
958 #define HW_CRC_GPOLYHU(x) (*(__IO hw_crc_gpolyhu_t *) HW_CRC_GPOLYHU_ADDR(x))
959 #define HW_CRC_GPOLYHU_RD(x) (HW_CRC_GPOLYHU(x).U)
960 #define HW_CRC_GPOLYHU_WR(x, v) (HW_CRC_GPOLYHU(x).U = (v))
961 #define HW_CRC_GPOLYHU_SET(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) | (v)))
962 #define HW_CRC_GPOLYHU_CLR(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) & ~(v)))
963 #define HW_CRC_GPOLYHU_TOG(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) ^ (v)))
967 * Constants & macros for individual CRC_GPOLYHU bitfields
971 * @name Register CRC_GPOLYHU, field GPOLYHU[7:0] (RW)
974 #define BP_CRC_GPOLYHU_GPOLYHU (0U) /*!< Bit position for CRC_GPOLYHU_GPOLYHU. */
975 #define BM_CRC_GPOLYHU_GPOLYHU (0xFFU) /*!< Bit mask for CRC_GPOLYHU_GPOLYHU. */
976 #define BS_CRC_GPOLYHU_GPOLYHU (8U) /*!< Bit field size in bits for CRC_GPOLYHU_GPOLYHU. */
978 /*! @brief Read current value of the CRC_GPOLYHU_GPOLYHU field. */
979 #define BR_CRC_GPOLYHU_GPOLYHU(x) (HW_CRC_GPOLYHU(x).U)
981 /*! @brief Format value for bitfield CRC_GPOLYHU_GPOLYHU. */
982 #define BF_CRC_GPOLYHU_GPOLYHU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYHU_GPOLYHU) & BM_CRC_GPOLYHU_GPOLYHU)
984 /*! @brief Set the GPOLYHU field to a new value. */
985 #define BW_CRC_GPOLYHU_GPOLYHU(x, v) (HW_CRC_GPOLYHU_WR(x, v))
988 /*******************************************************************************
989 * HW_CRC_CTRL - CRC Control register
990 ******************************************************************************/
993 * @brief HW_CRC_CTRL - CRC Control register (RW)
995 * Reset value: 0x00000000U
997 * This register controls the configuration and working of the CRC module.
998 * Appropriate bits must be set before starting a new CRC calculation. A new CRC
999 * calculation is initialized by asserting CTRL[WAS] and then writing the seed into
1000 * the CRC data register.
1002 typedef union _hw_crc_ctrl
1005 struct _hw_crc_ctrl_bitfields
1007 uint32_t RESERVED0 : 24; /*!< [23:0] */
1008 uint32_t TCRC : 1; /*!< [24] */
1009 uint32_t WAS : 1; /*!< [25] Write CRC Data Register As Seed */
1010 uint32_t FXOR : 1; /*!< [26] Complement Read Of CRC Data Register */
1011 uint32_t RESERVED1 : 1; /*!< [27] */
1012 uint32_t TOTR : 2; /*!< [29:28] Type Of Transpose For Read */
1013 uint32_t TOT : 2; /*!< [31:30] Type Of Transpose For Writes */
1018 * @name Constants and macros for entire CRC_CTRL register
1021 #define HW_CRC_CTRL_ADDR(x) ((x) + 0x8U)
1023 #define HW_CRC_CTRL(x) (*(__IO hw_crc_ctrl_t *) HW_CRC_CTRL_ADDR(x))
1024 #define HW_CRC_CTRL_RD(x) (HW_CRC_CTRL(x).U)
1025 #define HW_CRC_CTRL_WR(x, v) (HW_CRC_CTRL(x).U = (v))
1026 #define HW_CRC_CTRL_SET(x, v) (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) | (v)))
1027 #define HW_CRC_CTRL_CLR(x, v) (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) & ~(v)))
1028 #define HW_CRC_CTRL_TOG(x, v) (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) ^ (v)))
1032 * Constants & macros for individual CRC_CTRL bitfields
1036 * @name Register CRC_CTRL, field TCRC[24] (RW)
1038 * Width of CRC protocol.
1041 * - 0 - 16-bit CRC protocol.
1042 * - 1 - 32-bit CRC protocol.
1045 #define BP_CRC_CTRL_TCRC (24U) /*!< Bit position for CRC_CTRL_TCRC. */
1046 #define BM_CRC_CTRL_TCRC (0x01000000U) /*!< Bit mask for CRC_CTRL_TCRC. */
1047 #define BS_CRC_CTRL_TCRC (1U) /*!< Bit field size in bits for CRC_CTRL_TCRC. */
1049 /*! @brief Read current value of the CRC_CTRL_TCRC field. */
1050 #define BR_CRC_CTRL_TCRC(x) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_TCRC))
1052 /*! @brief Format value for bitfield CRC_CTRL_TCRC. */
1053 #define BF_CRC_CTRL_TCRC(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TCRC) & BM_CRC_CTRL_TCRC)
1055 /*! @brief Set the TCRC field to a new value. */
1056 #define BW_CRC_CTRL_TCRC(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_TCRC) = (v))
1060 * @name Register CRC_CTRL, field WAS[25] (RW)
1062 * When asserted, a value written to the CRC data register is considered a seed
1063 * value. When deasserted, a value written to the CRC data register is taken as
1064 * data for CRC computation.
1067 * - 0 - Writes to the CRC data register are data values.
1068 * - 1 - Writes to the CRC data register are seed values.
1071 #define BP_CRC_CTRL_WAS (25U) /*!< Bit position for CRC_CTRL_WAS. */
1072 #define BM_CRC_CTRL_WAS (0x02000000U) /*!< Bit mask for CRC_CTRL_WAS. */
1073 #define BS_CRC_CTRL_WAS (1U) /*!< Bit field size in bits for CRC_CTRL_WAS. */
1075 /*! @brief Read current value of the CRC_CTRL_WAS field. */
1076 #define BR_CRC_CTRL_WAS(x) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_WAS))
1078 /*! @brief Format value for bitfield CRC_CTRL_WAS. */
1079 #define BF_CRC_CTRL_WAS(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_WAS) & BM_CRC_CTRL_WAS)
1081 /*! @brief Set the WAS field to a new value. */
1082 #define BW_CRC_CTRL_WAS(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_WAS) = (v))
1086 * @name Register CRC_CTRL, field FXOR[26] (RW)
1088 * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or
1089 * 0xFFFF. Asserting this bit enables on the fly complementing of read data.
1092 * - 0 - No XOR on reading.
1093 * - 1 - Invert or complement the read value of the CRC Data register.
1096 #define BP_CRC_CTRL_FXOR (26U) /*!< Bit position for CRC_CTRL_FXOR. */
1097 #define BM_CRC_CTRL_FXOR (0x04000000U) /*!< Bit mask for CRC_CTRL_FXOR. */
1098 #define BS_CRC_CTRL_FXOR (1U) /*!< Bit field size in bits for CRC_CTRL_FXOR. */
1100 /*! @brief Read current value of the CRC_CTRL_FXOR field. */
1101 #define BR_CRC_CTRL_FXOR(x) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_FXOR))
1103 /*! @brief Format value for bitfield CRC_CTRL_FXOR. */
1104 #define BF_CRC_CTRL_FXOR(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_FXOR) & BM_CRC_CTRL_FXOR)
1106 /*! @brief Set the FXOR field to a new value. */
1107 #define BW_CRC_CTRL_FXOR(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_FXOR) = (v))
1111 * @name Register CRC_CTRL, field TOTR[29:28] (RW)
1113 * Identifies the transpose configuration of the value read from the CRC Data
1114 * register. See the description of the transpose feature for the available
1115 * transpose options.
1118 * - 00 - No transposition.
1119 * - 01 - Bits in bytes are transposed; bytes are not transposed.
1120 * - 10 - Both bits in bytes and bytes are transposed.
1121 * - 11 - Only bytes are transposed; no bits in a byte are transposed.
1124 #define BP_CRC_CTRL_TOTR (28U) /*!< Bit position for CRC_CTRL_TOTR. */
1125 #define BM_CRC_CTRL_TOTR (0x30000000U) /*!< Bit mask for CRC_CTRL_TOTR. */
1126 #define BS_CRC_CTRL_TOTR (2U) /*!< Bit field size in bits for CRC_CTRL_TOTR. */
1128 /*! @brief Read current value of the CRC_CTRL_TOTR field. */
1129 #define BR_CRC_CTRL_TOTR(x) (HW_CRC_CTRL(x).B.TOTR)
1131 /*! @brief Format value for bitfield CRC_CTRL_TOTR. */
1132 #define BF_CRC_CTRL_TOTR(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TOTR) & BM_CRC_CTRL_TOTR)
1134 /*! @brief Set the TOTR field to a new value. */
1135 #define BW_CRC_CTRL_TOTR(x, v) (HW_CRC_CTRL_WR(x, (HW_CRC_CTRL_RD(x) & ~BM_CRC_CTRL_TOTR) | BF_CRC_CTRL_TOTR(v)))
1139 * @name Register CRC_CTRL, field TOT[31:30] (RW)
1141 * Defines the transpose configuration of the data written to the CRC data
1142 * register. See the description of the transpose feature for the available transpose
1146 * - 00 - No transposition.
1147 * - 01 - Bits in bytes are transposed; bytes are not transposed.
1148 * - 10 - Both bits in bytes and bytes are transposed.
1149 * - 11 - Only bytes are transposed; no bits in a byte are transposed.
1152 #define BP_CRC_CTRL_TOT (30U) /*!< Bit position for CRC_CTRL_TOT. */
1153 #define BM_CRC_CTRL_TOT (0xC0000000U) /*!< Bit mask for CRC_CTRL_TOT. */
1154 #define BS_CRC_CTRL_TOT (2U) /*!< Bit field size in bits for CRC_CTRL_TOT. */
1156 /*! @brief Read current value of the CRC_CTRL_TOT field. */
1157 #define BR_CRC_CTRL_TOT(x) (HW_CRC_CTRL(x).B.TOT)
1159 /*! @brief Format value for bitfield CRC_CTRL_TOT. */
1160 #define BF_CRC_CTRL_TOT(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TOT) & BM_CRC_CTRL_TOT)
1162 /*! @brief Set the TOT field to a new value. */
1163 #define BW_CRC_CTRL_TOT(x, v) (HW_CRC_CTRL_WR(x, (HW_CRC_CTRL_RD(x) & ~BM_CRC_CTRL_TOT) | BF_CRC_CTRL_TOT(v)))
1165 /*******************************************************************************
1166 * HW_CRC_CTRLHU - CRC_CTRLHU register.
1167 ******************************************************************************/
1170 * @brief HW_CRC_CTRLHU - CRC_CTRLHU register. (RW)
1172 * Reset value: 0x00U
1174 typedef union _hw_crc_ctrlhu
1177 struct _hw_crc_ctrlhu_bitfields
1179 uint8_t TCRC : 1; /*!< [0] */
1180 uint8_t WAS : 1; /*!< [1] */
1181 uint8_t FXOR : 1; /*!< [2] */
1182 uint8_t RESERVED0 : 1; /*!< [3] */
1183 uint8_t TOTR : 2; /*!< [5:4] */
1184 uint8_t TOT : 2; /*!< [7:6] */
1189 * @name Constants and macros for entire CRC_CTRLHU register
1192 #define HW_CRC_CTRLHU_ADDR(x) ((x) + 0xBU)
1194 #define HW_CRC_CTRLHU(x) (*(__IO hw_crc_ctrlhu_t *) HW_CRC_CTRLHU_ADDR(x))
1195 #define HW_CRC_CTRLHU_RD(x) (HW_CRC_CTRLHU(x).U)
1196 #define HW_CRC_CTRLHU_WR(x, v) (HW_CRC_CTRLHU(x).U = (v))
1197 #define HW_CRC_CTRLHU_SET(x, v) (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) | (v)))
1198 #define HW_CRC_CTRLHU_CLR(x, v) (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) & ~(v)))
1199 #define HW_CRC_CTRLHU_TOG(x, v) (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) ^ (v)))
1203 * Constants & macros for individual CRC_CTRLHU bitfields
1207 * @name Register CRC_CTRLHU, field TCRC[0] (RW)
1210 * - 0 - 16-bit CRC protocol.
1211 * - 1 - 32-bit CRC protocol.
1214 #define BP_CRC_CTRLHU_TCRC (0U) /*!< Bit position for CRC_CTRLHU_TCRC. */
1215 #define BM_CRC_CTRLHU_TCRC (0x01U) /*!< Bit mask for CRC_CTRLHU_TCRC. */
1216 #define BS_CRC_CTRLHU_TCRC (1U) /*!< Bit field size in bits for CRC_CTRLHU_TCRC. */
1218 /*! @brief Read current value of the CRC_CTRLHU_TCRC field. */
1219 #define BR_CRC_CTRLHU_TCRC(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_TCRC))
1221 /*! @brief Format value for bitfield CRC_CTRLHU_TCRC. */
1222 #define BF_CRC_CTRLHU_TCRC(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TCRC) & BM_CRC_CTRLHU_TCRC)
1224 /*! @brief Set the TCRC field to a new value. */
1225 #define BW_CRC_CTRLHU_TCRC(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_TCRC) = (v))
1229 * @name Register CRC_CTRLHU, field WAS[1] (RW)
1232 * - 0 - Writes to CRC data register are data values.
1233 * - 1 - Writes to CRC data reguster are seed values.
1236 #define BP_CRC_CTRLHU_WAS (1U) /*!< Bit position for CRC_CTRLHU_WAS. */
1237 #define BM_CRC_CTRLHU_WAS (0x02U) /*!< Bit mask for CRC_CTRLHU_WAS. */
1238 #define BS_CRC_CTRLHU_WAS (1U) /*!< Bit field size in bits for CRC_CTRLHU_WAS. */
1240 /*! @brief Read current value of the CRC_CTRLHU_WAS field. */
1241 #define BR_CRC_CTRLHU_WAS(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_WAS))
1243 /*! @brief Format value for bitfield CRC_CTRLHU_WAS. */
1244 #define BF_CRC_CTRLHU_WAS(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_WAS) & BM_CRC_CTRLHU_WAS)
1246 /*! @brief Set the WAS field to a new value. */
1247 #define BW_CRC_CTRLHU_WAS(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_WAS) = (v))
1251 * @name Register CRC_CTRLHU, field FXOR[2] (RW)
1254 * - 0 - No XOR on reading.
1255 * - 1 - Invert or complement the read value of CRC data register.
1258 #define BP_CRC_CTRLHU_FXOR (2U) /*!< Bit position for CRC_CTRLHU_FXOR. */
1259 #define BM_CRC_CTRLHU_FXOR (0x04U) /*!< Bit mask for CRC_CTRLHU_FXOR. */
1260 #define BS_CRC_CTRLHU_FXOR (1U) /*!< Bit field size in bits for CRC_CTRLHU_FXOR. */
1262 /*! @brief Read current value of the CRC_CTRLHU_FXOR field. */
1263 #define BR_CRC_CTRLHU_FXOR(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_FXOR))
1265 /*! @brief Format value for bitfield CRC_CTRLHU_FXOR. */
1266 #define BF_CRC_CTRLHU_FXOR(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_FXOR) & BM_CRC_CTRLHU_FXOR)
1268 /*! @brief Set the FXOR field to a new value. */
1269 #define BW_CRC_CTRLHU_FXOR(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_FXOR) = (v))
1273 * @name Register CRC_CTRLHU, field TOTR[5:4] (RW)
1276 * - 00 - No Transposition.
1277 * - 01 - Bits in bytes are transposed, bytes are not transposed.
1278 * - 10 - Both bits in bytes and bytes are transposed.
1279 * - 11 - Only bytes are transposed; no bits in a byte are transposed.
1282 #define BP_CRC_CTRLHU_TOTR (4U) /*!< Bit position for CRC_CTRLHU_TOTR. */
1283 #define BM_CRC_CTRLHU_TOTR (0x30U) /*!< Bit mask for CRC_CTRLHU_TOTR. */
1284 #define BS_CRC_CTRLHU_TOTR (2U) /*!< Bit field size in bits for CRC_CTRLHU_TOTR. */
1286 /*! @brief Read current value of the CRC_CTRLHU_TOTR field. */
1287 #define BR_CRC_CTRLHU_TOTR(x) (HW_CRC_CTRLHU(x).B.TOTR)
1289 /*! @brief Format value for bitfield CRC_CTRLHU_TOTR. */
1290 #define BF_CRC_CTRLHU_TOTR(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TOTR) & BM_CRC_CTRLHU_TOTR)
1292 /*! @brief Set the TOTR field to a new value. */
1293 #define BW_CRC_CTRLHU_TOTR(x, v) (HW_CRC_CTRLHU_WR(x, (HW_CRC_CTRLHU_RD(x) & ~BM_CRC_CTRLHU_TOTR) | BF_CRC_CTRLHU_TOTR(v)))
1297 * @name Register CRC_CTRLHU, field TOT[7:6] (RW)
1300 * - 00 - No Transposition.
1301 * - 01 - Bits in bytes are transposed, bytes are not transposed.
1302 * - 10 - Both bits in bytes and bytes are transposed.
1303 * - 11 - Only bytes are transposed; no bits in a byte are transposed.
1306 #define BP_CRC_CTRLHU_TOT (6U) /*!< Bit position for CRC_CTRLHU_TOT. */
1307 #define BM_CRC_CTRLHU_TOT (0xC0U) /*!< Bit mask for CRC_CTRLHU_TOT. */
1308 #define BS_CRC_CTRLHU_TOT (2U) /*!< Bit field size in bits for CRC_CTRLHU_TOT. */
1310 /*! @brief Read current value of the CRC_CTRLHU_TOT field. */
1311 #define BR_CRC_CTRLHU_TOT(x) (HW_CRC_CTRLHU(x).B.TOT)
1313 /*! @brief Format value for bitfield CRC_CTRLHU_TOT. */
1314 #define BF_CRC_CTRLHU_TOT(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TOT) & BM_CRC_CTRLHU_TOT)
1316 /*! @brief Set the TOT field to a new value. */
1317 #define BW_CRC_CTRLHU_TOT(x, v) (HW_CRC_CTRLHU_WR(x, (HW_CRC_CTRLHU_RD(x) & ~BM_CRC_CTRLHU_TOT) | BF_CRC_CTRLHU_TOT(v)))
1321 ** Start of section using anonymous unions
1324 #if defined(__ARMCC_VERSION)
1327 #elif defined(__CWCC__)
1329 #pragma cpp_extensions on
1330 #elif defined(__GNUC__)
1331 /* anonymous unions are enabled by default */
1332 #elif defined(__IAR_SYSTEMS_ICC__)
1333 #pragma language=extended
1335 #error Not supported compiler type
1338 /*******************************************************************************
1339 * hw_crc_t - module struct
1340 ******************************************************************************/
1342 * @brief All CRC module registers.
1345 typedef struct _hw_crc
1349 __IO hw_crc_datal_t DATAL; /*!< [0x0] CRC_DATAL register. */
1350 __IO hw_crc_datah_t DATAH; /*!< [0x2] CRC_DATAH register. */
1353 __IO hw_crc_datall_t DATALL; /*!< [0x0] CRC_DATALL register. */
1354 __IO hw_crc_datalu_t DATALU; /*!< [0x1] CRC_DATALU register. */
1355 __IO hw_crc_datahl_t DATAHL; /*!< [0x2] CRC_DATAHL register. */
1356 __IO hw_crc_datahu_t DATAHU; /*!< [0x3] CRC_DATAHU register. */
1358 __IO hw_crc_data_t DATA; /*!< [0x0] CRC Data register */
1361 __IO hw_crc_gpoly_t GPOLY; /*!< [0x4] CRC Polynomial register */
1363 __IO hw_crc_gpolyl_t GPOLYL; /*!< [0x4] CRC_GPOLYL register. */
1364 __IO hw_crc_gpolyh_t GPOLYH; /*!< [0x6] CRC_GPOLYH register. */
1365 } GPOLY_ACCESS16BIT;
1367 __IO hw_crc_gpolyll_t GPOLYLL; /*!< [0x4] CRC_GPOLYLL register. */
1368 __IO hw_crc_gpolylu_t GPOLYLU; /*!< [0x5] CRC_GPOLYLU register. */
1369 __IO hw_crc_gpolyhl_t GPOLYHL; /*!< [0x6] CRC_GPOLYHL register. */
1370 __IO hw_crc_gpolyhu_t GPOLYHU; /*!< [0x7] CRC_GPOLYHU register. */
1374 __IO hw_crc_ctrl_t CTRL; /*!< [0x8] CRC Control register */
1376 uint8_t _reserved0[3];
1377 __IO hw_crc_ctrlhu_t CTRLHU; /*!< [0xB] CRC_CTRLHU register. */
1383 /*! @brief Macro to access all CRC registers. */
1384 /*! @param x CRC module instance base address. */
1385 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1386 * use the '&' operator, like <code>&HW_CRC(CRC_BASE)</code>. */
1387 #define HW_CRC(x) (*(hw_crc_t *)(x))
1390 ** End of section using anonymous unions
1393 #if defined(__ARMCC_VERSION)
1395 #elif defined(__CWCC__)
1397 #elif defined(__GNUC__)
1398 /* leave anonymous unions enabled */
1399 #elif defined(__IAR_SYSTEMS_ICC__)
1400 #pragma language=default
1402 #error Not supported compiler type
1405 #endif /* __HW_CRC_REGISTERS_H__ */