2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** GNU C Compiler - CodeSourcery Sourcery G++
7 ** IAR ANSI C/C++ Compiler for ARM
9 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
10 ** Version: rev. 2.5, 2014-05-06
14 ** CMSIS Peripheral Access Layer for MK22F51212
16 ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
17 ** All rights reserved.
19 ** Redistribution and use in source and binary forms, with or without modification,
20 ** are permitted provided that the following conditions are met:
22 ** o Redistributions of source code must retain the above copyright notice, this list
23 ** of conditions and the following disclaimer.
25 ** o Redistributions in binary form must reproduce the above copyright notice, this
26 ** list of conditions and the following disclaimer in the documentation and/or
27 ** other materials provided with the distribution.
29 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
30 ** contributors may be used to endorse or promote products derived from this
31 ** software without specific prior written permission.
33 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
37 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
40 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 ** http: www.freescale.com
45 ** mail: support@freescale.com
48 ** - rev. 1.0 (2013-07-23)
50 ** - rev. 1.1 (2013-09-17)
51 ** RM rev. 0.4 update.
52 ** - rev. 2.0 (2013-10-29)
53 ** Register accessor macros added to the memory map.
54 ** Symbols for Processor Expert memory map compatibility added to the memory map.
55 ** Startup file for gcc has been updated according to CMSIS 3.2.
56 ** System initialization updated.
57 ** - rev. 2.1 (2013-10-30)
58 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
59 ** - rev. 2.2 (2013-12-20)
60 ** Update according to reference manual rev. 0.6,
61 ** - rev. 2.3 (2014-01-13)
62 ** Update according to reference manual rev. 0.61,
63 ** - rev. 2.4 (2014-02-10)
64 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
65 ** - rev. 2.5 (2014-05-06)
66 ** Update according to reference manual rev. 1.0,
67 ** Update of system and startup files.
68 ** Module access macro module_BASES replaced by module_BASE_PTRS.
70 ** ###################################################################
77 * @brief CMSIS Peripheral Access Layer for MK22F51212
79 * CMSIS Peripheral Access Layer for MK22F51212
83 /* ----------------------------------------------------------------------------
85 ---------------------------------------------------------------------------- */
87 /* Prevention from multiple including the same memory map */
88 #if !defined(MK22F51212_H_) /* Check if memory map has not been already included */
90 #define MCU_MK22F51212
92 /* Check if another memory map has not been also included */
93 #if (defined(MCU_ACTIVE))
94 #error MK22F51212 memory map: There is already included another memory map. Only one memory map can be included.
95 #endif /* (defined(MCU_ACTIVE)) */
100 /** Memory map major version (memory maps with equal major version number are
102 #define MCU_MEM_MAP_VERSION 0x0200u
103 /** Memory map minor version */
104 #define MCU_MEM_MAP_VERSION_MINOR 0x0005u
107 * @brief Macro to calculate address of an aliased word in the peripheral
108 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
110 * @param Reg Register to access.
111 * @param Bit Bit number to access.
112 * @return Address of the aliased word in the peripheral bitband area.
114 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
116 * @brief Macro to access a single bit of a peripheral register (bit band region
117 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
118 * be used for peripherals with 32bit access allowed.
119 * @param Reg Register to access.
120 * @param Bit Bit number to access.
121 * @return Value of the targeted bit in the bit band region.
123 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
124 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
126 * @brief Macro to access a single bit of a peripheral register (bit band region
127 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
128 * be used for peripherals with 16bit access allowed.
129 * @param Reg Register to access.
130 * @param Bit Bit number to access.
131 * @return Value of the targeted bit in the bit band region.
133 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
135 * @brief Macro to access a single bit of a peripheral register (bit band region
136 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
137 * be used for peripherals with 8bit access allowed.
138 * @param Reg Register to access.
139 * @param Bit Bit number to access.
140 * @return Value of the targeted bit in the bit band region.
142 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
144 /* ----------------------------------------------------------------------------
145 -- Interrupt vector numbers
146 ---------------------------------------------------------------------------- */
149 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
153 /** Interrupt Number Definitions */
154 #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
157 /* Core interrupts */
158 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
159 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
160 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
161 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
162 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
163 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
164 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
165 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
166 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
168 /* Device specific interrupts */
169 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
170 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
171 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
172 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
173 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
174 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
175 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
176 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
177 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
178 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
179 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
180 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
181 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
182 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
183 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
184 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
185 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
186 MCM_IRQn = 17, /**< Normal Interrupt */
187 FTF_IRQn = 18, /**< FTFA Command complete interrupt */
188 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
189 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
190 LLW_IRQn = 21, /**< Low Leakage Wakeup */
191 Watchdog_IRQn = 22, /**< WDOG Interrupt */
192 RNG_IRQn = 23, /**< RNG Interrupt */
193 I2C0_IRQn = 24, /**< I2C0 interrupt */
194 I2C1_IRQn = 25, /**< I2C1 interrupt */
195 SPI0_IRQn = 26, /**< SPI0 Interrupt */
196 SPI1_IRQn = 27, /**< SPI1 Interrupt */
197 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
198 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
199 LPUART0_IRQn = 30, /**< LPUART0 status/error interrupt */
200 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
201 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
202 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
203 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
204 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
205 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
206 Reserved53_IRQn = 37, /**< Reserved interrupt 53 */
207 Reserved54_IRQn = 38, /**< Reserved interrupt 54 */
208 ADC0_IRQn = 39, /**< ADC0 interrupt */
209 CMP0_IRQn = 40, /**< CMP0 interrupt */
210 CMP1_IRQn = 41, /**< CMP1 interrupt */
211 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
212 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
213 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
214 Reserved61_IRQn = 45, /**< Reserved interrupt 61 */
215 RTC_IRQn = 46, /**< RTC interrupt */
216 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
217 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
218 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
219 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
220 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
221 PDB0_IRQn = 52, /**< PDB0 Interrupt */
222 USB0_IRQn = 53, /**< USB0 interrupt */
223 Reserved70_IRQn = 54, /**< Reserved interrupt 70 */
224 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
225 DAC0_IRQn = 56, /**< DAC0 interrupt */
226 MCG_IRQn = 57, /**< MCG Interrupt */
227 LPTimer_IRQn = 58, /**< LPTimer interrupt */
228 PORTA_IRQn = 59, /**< Port A interrupt */
229 PORTB_IRQn = 60, /**< Port B interrupt */
230 PORTC_IRQn = 61, /**< Port C interrupt */
231 PORTD_IRQn = 62, /**< Port D interrupt */
232 PORTE_IRQn = 63, /**< Port E interrupt */
233 SWI_IRQn = 64, /**< Software interrupt */
234 Reserved81_IRQn = 65, /**< Reserved interrupt 81 */
235 Reserved82_IRQn = 66, /**< Reserved interrupt 82 */
236 Reserved83_IRQn = 67, /**< Reserved interrupt 83 */
237 Reserved84_IRQn = 68, /**< Reserved interrupt 84 */
238 Reserved85_IRQn = 69, /**< Reserved interrupt 85 */
239 Reserved86_IRQn = 70, /**< Reserved interrupt 86 */
240 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
241 DAC1_IRQn = 72, /**< DAC1 interrupt */
242 ADC1_IRQn = 73, /**< ADC1 interrupt */
243 Reserved90_IRQn = 74, /**< Reserved Interrupt 90 */
244 Reserved91_IRQn = 75, /**< Reserved Interrupt 91 */
245 Reserved92_IRQn = 76, /**< Reserved Interrupt 92 */
246 Reserved93_IRQn = 77, /**< Reserved Interrupt 93 */
247 Reserved94_IRQn = 78, /**< Reserved Interrupt 94 */
248 Reserved95_IRQn = 79, /**< Reserved Interrupt 95 */
249 Reserved96_IRQn = 80, /**< Reserved Interrupt 96 */
250 Reserved97_IRQn = 81, /**< Reserved Interrupt 97 */
251 Reserved98_IRQn = 82, /**< Reserved Interrupt 98 */
252 Reserved99_IRQn = 83, /**< Reserved Interrupt 99 */
253 Reserved100_IRQn = 84, /**< Reserved Interrupt 100 */
254 Reserved101_IRQn = 85 /**< Reserved Interrupt 101 */
259 */ /* end of group Interrupt_vector_numbers */
262 /* ----------------------------------------------------------------------------
263 -- Cortex M4 Core Configuration
264 ---------------------------------------------------------------------------- */
267 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
271 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
272 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
273 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
274 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
276 #include "core_cm4.h" /* Core Peripheral Access Layer */
277 #include "system_MK22F51212.h" /* Device specific configuration file */
281 */ /* end of group Cortex_Core_Configuration */
284 /* ----------------------------------------------------------------------------
285 -- Device Peripheral Access Layer
286 ---------------------------------------------------------------------------- */
289 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
295 ** Start of section using anonymous unions
298 #if defined(__ARMCC_VERSION)
301 #elif defined(__CWCC__)
303 #pragma cpp_extensions on
304 #elif defined(__GNUC__)
305 /* anonymous unions are enabled by default */
306 #elif defined(__IAR_SYSTEMS_ICC__)
307 #pragma language=extended
309 #error Not supported compiler type
312 /* ----------------------------------------------------------------------------
313 -- ADC Peripheral Access Layer
314 ---------------------------------------------------------------------------- */
317 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
321 /** ADC - Register Layout Typedef */
323 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
324 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
325 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
326 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
327 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
328 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
329 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
330 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
331 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
332 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
333 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
334 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
335 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
336 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
337 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
338 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
339 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
340 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
341 uint8_t RESERVED_0[4];
342 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
343 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
344 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
345 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
346 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
347 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
348 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
349 } ADC_Type, *ADC_MemMapPtr;
351 /* ----------------------------------------------------------------------------
352 -- ADC - Register accessor macros
353 ---------------------------------------------------------------------------- */
356 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
361 /* ADC - Register accessors */
362 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
363 #define ADC_CFG1_REG(base) ((base)->CFG1)
364 #define ADC_CFG2_REG(base) ((base)->CFG2)
365 #define ADC_R_REG(base,index) ((base)->R[index])
366 #define ADC_CV1_REG(base) ((base)->CV1)
367 #define ADC_CV2_REG(base) ((base)->CV2)
368 #define ADC_SC2_REG(base) ((base)->SC2)
369 #define ADC_SC3_REG(base) ((base)->SC3)
370 #define ADC_OFS_REG(base) ((base)->OFS)
371 #define ADC_PG_REG(base) ((base)->PG)
372 #define ADC_MG_REG(base) ((base)->MG)
373 #define ADC_CLPD_REG(base) ((base)->CLPD)
374 #define ADC_CLPS_REG(base) ((base)->CLPS)
375 #define ADC_CLP4_REG(base) ((base)->CLP4)
376 #define ADC_CLP3_REG(base) ((base)->CLP3)
377 #define ADC_CLP2_REG(base) ((base)->CLP2)
378 #define ADC_CLP1_REG(base) ((base)->CLP1)
379 #define ADC_CLP0_REG(base) ((base)->CLP0)
380 #define ADC_CLMD_REG(base) ((base)->CLMD)
381 #define ADC_CLMS_REG(base) ((base)->CLMS)
382 #define ADC_CLM4_REG(base) ((base)->CLM4)
383 #define ADC_CLM3_REG(base) ((base)->CLM3)
384 #define ADC_CLM2_REG(base) ((base)->CLM2)
385 #define ADC_CLM1_REG(base) ((base)->CLM1)
386 #define ADC_CLM0_REG(base) ((base)->CLM0)
390 */ /* end of group ADC_Register_Accessor_Macros */
393 /* ----------------------------------------------------------------------------
394 -- ADC Register Masks
395 ---------------------------------------------------------------------------- */
398 * @addtogroup ADC_Register_Masks ADC Register Masks
403 #define ADC_SC1_ADCH_MASK 0x1Fu
404 #define ADC_SC1_ADCH_SHIFT 0
405 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
406 #define ADC_SC1_DIFF_MASK 0x20u
407 #define ADC_SC1_DIFF_SHIFT 5
408 #define ADC_SC1_AIEN_MASK 0x40u
409 #define ADC_SC1_AIEN_SHIFT 6
410 #define ADC_SC1_COCO_MASK 0x80u
411 #define ADC_SC1_COCO_SHIFT 7
412 /* CFG1 Bit Fields */
413 #define ADC_CFG1_ADICLK_MASK 0x3u
414 #define ADC_CFG1_ADICLK_SHIFT 0
415 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
416 #define ADC_CFG1_MODE_MASK 0xCu
417 #define ADC_CFG1_MODE_SHIFT 2
418 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
419 #define ADC_CFG1_ADLSMP_MASK 0x10u
420 #define ADC_CFG1_ADLSMP_SHIFT 4
421 #define ADC_CFG1_ADIV_MASK 0x60u
422 #define ADC_CFG1_ADIV_SHIFT 5
423 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
424 #define ADC_CFG1_ADLPC_MASK 0x80u
425 #define ADC_CFG1_ADLPC_SHIFT 7
426 /* CFG2 Bit Fields */
427 #define ADC_CFG2_ADLSTS_MASK 0x3u
428 #define ADC_CFG2_ADLSTS_SHIFT 0
429 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
430 #define ADC_CFG2_ADHSC_MASK 0x4u
431 #define ADC_CFG2_ADHSC_SHIFT 2
432 #define ADC_CFG2_ADACKEN_MASK 0x8u
433 #define ADC_CFG2_ADACKEN_SHIFT 3
434 #define ADC_CFG2_MUXSEL_MASK 0x10u
435 #define ADC_CFG2_MUXSEL_SHIFT 4
437 #define ADC_R_D_MASK 0xFFFFu
438 #define ADC_R_D_SHIFT 0
439 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
441 #define ADC_CV1_CV_MASK 0xFFFFu
442 #define ADC_CV1_CV_SHIFT 0
443 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
445 #define ADC_CV2_CV_MASK 0xFFFFu
446 #define ADC_CV2_CV_SHIFT 0
447 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
449 #define ADC_SC2_REFSEL_MASK 0x3u
450 #define ADC_SC2_REFSEL_SHIFT 0
451 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
452 #define ADC_SC2_DMAEN_MASK 0x4u
453 #define ADC_SC2_DMAEN_SHIFT 2
454 #define ADC_SC2_ACREN_MASK 0x8u
455 #define ADC_SC2_ACREN_SHIFT 3
456 #define ADC_SC2_ACFGT_MASK 0x10u
457 #define ADC_SC2_ACFGT_SHIFT 4
458 #define ADC_SC2_ACFE_MASK 0x20u
459 #define ADC_SC2_ACFE_SHIFT 5
460 #define ADC_SC2_ADTRG_MASK 0x40u
461 #define ADC_SC2_ADTRG_SHIFT 6
462 #define ADC_SC2_ADACT_MASK 0x80u
463 #define ADC_SC2_ADACT_SHIFT 7
465 #define ADC_SC3_AVGS_MASK 0x3u
466 #define ADC_SC3_AVGS_SHIFT 0
467 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
468 #define ADC_SC3_AVGE_MASK 0x4u
469 #define ADC_SC3_AVGE_SHIFT 2
470 #define ADC_SC3_ADCO_MASK 0x8u
471 #define ADC_SC3_ADCO_SHIFT 3
472 #define ADC_SC3_CALF_MASK 0x40u
473 #define ADC_SC3_CALF_SHIFT 6
474 #define ADC_SC3_CAL_MASK 0x80u
475 #define ADC_SC3_CAL_SHIFT 7
477 #define ADC_OFS_OFS_MASK 0xFFFFu
478 #define ADC_OFS_OFS_SHIFT 0
479 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
481 #define ADC_PG_PG_MASK 0xFFFFu
482 #define ADC_PG_PG_SHIFT 0
483 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
485 #define ADC_MG_MG_MASK 0xFFFFu
486 #define ADC_MG_MG_SHIFT 0
487 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
488 /* CLPD Bit Fields */
489 #define ADC_CLPD_CLPD_MASK 0x3Fu
490 #define ADC_CLPD_CLPD_SHIFT 0
491 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
492 /* CLPS Bit Fields */
493 #define ADC_CLPS_CLPS_MASK 0x3Fu
494 #define ADC_CLPS_CLPS_SHIFT 0
495 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
496 /* CLP4 Bit Fields */
497 #define ADC_CLP4_CLP4_MASK 0x3FFu
498 #define ADC_CLP4_CLP4_SHIFT 0
499 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
500 /* CLP3 Bit Fields */
501 #define ADC_CLP3_CLP3_MASK 0x1FFu
502 #define ADC_CLP3_CLP3_SHIFT 0
503 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
504 /* CLP2 Bit Fields */
505 #define ADC_CLP2_CLP2_MASK 0xFFu
506 #define ADC_CLP2_CLP2_SHIFT 0
507 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
508 /* CLP1 Bit Fields */
509 #define ADC_CLP1_CLP1_MASK 0x7Fu
510 #define ADC_CLP1_CLP1_SHIFT 0
511 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
512 /* CLP0 Bit Fields */
513 #define ADC_CLP0_CLP0_MASK 0x3Fu
514 #define ADC_CLP0_CLP0_SHIFT 0
515 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
516 /* CLMD Bit Fields */
517 #define ADC_CLMD_CLMD_MASK 0x3Fu
518 #define ADC_CLMD_CLMD_SHIFT 0
519 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
520 /* CLMS Bit Fields */
521 #define ADC_CLMS_CLMS_MASK 0x3Fu
522 #define ADC_CLMS_CLMS_SHIFT 0
523 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
524 /* CLM4 Bit Fields */
525 #define ADC_CLM4_CLM4_MASK 0x3FFu
526 #define ADC_CLM4_CLM4_SHIFT 0
527 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
528 /* CLM3 Bit Fields */
529 #define ADC_CLM3_CLM3_MASK 0x1FFu
530 #define ADC_CLM3_CLM3_SHIFT 0
531 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
532 /* CLM2 Bit Fields */
533 #define ADC_CLM2_CLM2_MASK 0xFFu
534 #define ADC_CLM2_CLM2_SHIFT 0
535 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
536 /* CLM1 Bit Fields */
537 #define ADC_CLM1_CLM1_MASK 0x7Fu
538 #define ADC_CLM1_CLM1_SHIFT 0
539 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
540 /* CLM0 Bit Fields */
541 #define ADC_CLM0_CLM0_MASK 0x3Fu
542 #define ADC_CLM0_CLM0_SHIFT 0
543 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
547 */ /* end of group ADC_Register_Masks */
550 /* ADC - Peripheral instance base addresses */
551 /** Peripheral ADC0 base address */
552 #define ADC0_BASE (0x4003B000u)
553 /** Peripheral ADC0 base pointer */
554 #define ADC0 ((ADC_Type *)ADC0_BASE)
555 #define ADC0_BASE_PTR (ADC0)
556 /** Peripheral ADC1 base address */
557 #define ADC1_BASE (0x40027000u)
558 /** Peripheral ADC1 base pointer */
559 #define ADC1 ((ADC_Type *)ADC1_BASE)
560 #define ADC1_BASE_PTR (ADC1)
561 /** Array initializer of ADC peripheral base addresses */
562 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
563 /** Array initializer of ADC peripheral base pointers */
564 #define ADC_BASE_PTRS { ADC0, ADC1 }
565 /** Interrupt vectors for the ADC peripheral type */
566 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
568 /* ----------------------------------------------------------------------------
569 -- ADC - Register accessor macros
570 ---------------------------------------------------------------------------- */
573 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
578 /* ADC - Register instance definitions */
580 #define ADC0_SC1A ADC_SC1_REG(ADC0,0)
581 #define ADC0_SC1B ADC_SC1_REG(ADC0,1)
582 #define ADC0_CFG1 ADC_CFG1_REG(ADC0)
583 #define ADC0_CFG2 ADC_CFG2_REG(ADC0)
584 #define ADC0_RA ADC_R_REG(ADC0,0)
585 #define ADC0_RB ADC_R_REG(ADC0,1)
586 #define ADC0_CV1 ADC_CV1_REG(ADC0)
587 #define ADC0_CV2 ADC_CV2_REG(ADC0)
588 #define ADC0_SC2 ADC_SC2_REG(ADC0)
589 #define ADC0_SC3 ADC_SC3_REG(ADC0)
590 #define ADC0_OFS ADC_OFS_REG(ADC0)
591 #define ADC0_PG ADC_PG_REG(ADC0)
592 #define ADC0_MG ADC_MG_REG(ADC0)
593 #define ADC0_CLPD ADC_CLPD_REG(ADC0)
594 #define ADC0_CLPS ADC_CLPS_REG(ADC0)
595 #define ADC0_CLP4 ADC_CLP4_REG(ADC0)
596 #define ADC0_CLP3 ADC_CLP3_REG(ADC0)
597 #define ADC0_CLP2 ADC_CLP2_REG(ADC0)
598 #define ADC0_CLP1 ADC_CLP1_REG(ADC0)
599 #define ADC0_CLP0 ADC_CLP0_REG(ADC0)
600 #define ADC0_CLMD ADC_CLMD_REG(ADC0)
601 #define ADC0_CLMS ADC_CLMS_REG(ADC0)
602 #define ADC0_CLM4 ADC_CLM4_REG(ADC0)
603 #define ADC0_CLM3 ADC_CLM3_REG(ADC0)
604 #define ADC0_CLM2 ADC_CLM2_REG(ADC0)
605 #define ADC0_CLM1 ADC_CLM1_REG(ADC0)
606 #define ADC0_CLM0 ADC_CLM0_REG(ADC0)
608 #define ADC1_SC1A ADC_SC1_REG(ADC1,0)
609 #define ADC1_SC1B ADC_SC1_REG(ADC1,1)
610 #define ADC1_CFG1 ADC_CFG1_REG(ADC1)
611 #define ADC1_CFG2 ADC_CFG2_REG(ADC1)
612 #define ADC1_RA ADC_R_REG(ADC1,0)
613 #define ADC1_RB ADC_R_REG(ADC1,1)
614 #define ADC1_CV1 ADC_CV1_REG(ADC1)
615 #define ADC1_CV2 ADC_CV2_REG(ADC1)
616 #define ADC1_SC2 ADC_SC2_REG(ADC1)
617 #define ADC1_SC3 ADC_SC3_REG(ADC1)
618 #define ADC1_OFS ADC_OFS_REG(ADC1)
619 #define ADC1_PG ADC_PG_REG(ADC1)
620 #define ADC1_MG ADC_MG_REG(ADC1)
621 #define ADC1_CLPD ADC_CLPD_REG(ADC1)
622 #define ADC1_CLPS ADC_CLPS_REG(ADC1)
623 #define ADC1_CLP4 ADC_CLP4_REG(ADC1)
624 #define ADC1_CLP3 ADC_CLP3_REG(ADC1)
625 #define ADC1_CLP2 ADC_CLP2_REG(ADC1)
626 #define ADC1_CLP1 ADC_CLP1_REG(ADC1)
627 #define ADC1_CLP0 ADC_CLP0_REG(ADC1)
628 #define ADC1_CLMD ADC_CLMD_REG(ADC1)
629 #define ADC1_CLMS ADC_CLMS_REG(ADC1)
630 #define ADC1_CLM4 ADC_CLM4_REG(ADC1)
631 #define ADC1_CLM3 ADC_CLM3_REG(ADC1)
632 #define ADC1_CLM2 ADC_CLM2_REG(ADC1)
633 #define ADC1_CLM1 ADC_CLM1_REG(ADC1)
634 #define ADC1_CLM0 ADC_CLM0_REG(ADC1)
636 /* ADC - Register array accessors */
637 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
638 #define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
639 #define ADC0_R(index) ADC_R_REG(ADC0,index)
640 #define ADC1_R(index) ADC_R_REG(ADC1,index)
644 */ /* end of group ADC_Register_Accessor_Macros */
649 */ /* end of group ADC_Peripheral_Access_Layer */
652 /* ----------------------------------------------------------------------------
653 -- CMP Peripheral Access Layer
654 ---------------------------------------------------------------------------- */
657 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
661 /** CMP - Register Layout Typedef */
663 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
664 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
665 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
666 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
667 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
668 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
669 } CMP_Type, *CMP_MemMapPtr;
671 /* ----------------------------------------------------------------------------
672 -- CMP - Register accessor macros
673 ---------------------------------------------------------------------------- */
676 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
681 /* CMP - Register accessors */
682 #define CMP_CR0_REG(base) ((base)->CR0)
683 #define CMP_CR1_REG(base) ((base)->CR1)
684 #define CMP_FPR_REG(base) ((base)->FPR)
685 #define CMP_SCR_REG(base) ((base)->SCR)
686 #define CMP_DACCR_REG(base) ((base)->DACCR)
687 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
691 */ /* end of group CMP_Register_Accessor_Macros */
694 /* ----------------------------------------------------------------------------
695 -- CMP Register Masks
696 ---------------------------------------------------------------------------- */
699 * @addtogroup CMP_Register_Masks CMP Register Masks
704 #define CMP_CR0_HYSTCTR_MASK 0x3u
705 #define CMP_CR0_HYSTCTR_SHIFT 0
706 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
707 #define CMP_CR0_FILTER_CNT_MASK 0x70u
708 #define CMP_CR0_FILTER_CNT_SHIFT 4
709 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
711 #define CMP_CR1_EN_MASK 0x1u
712 #define CMP_CR1_EN_SHIFT 0
713 #define CMP_CR1_OPE_MASK 0x2u
714 #define CMP_CR1_OPE_SHIFT 1
715 #define CMP_CR1_COS_MASK 0x4u
716 #define CMP_CR1_COS_SHIFT 2
717 #define CMP_CR1_INV_MASK 0x8u
718 #define CMP_CR1_INV_SHIFT 3
719 #define CMP_CR1_PMODE_MASK 0x10u
720 #define CMP_CR1_PMODE_SHIFT 4
721 #define CMP_CR1_TRIGM_MASK 0x20u
722 #define CMP_CR1_TRIGM_SHIFT 5
723 #define CMP_CR1_WE_MASK 0x40u
724 #define CMP_CR1_WE_SHIFT 6
725 #define CMP_CR1_SE_MASK 0x80u
726 #define CMP_CR1_SE_SHIFT 7
728 #define CMP_FPR_FILT_PER_MASK 0xFFu
729 #define CMP_FPR_FILT_PER_SHIFT 0
730 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
732 #define CMP_SCR_COUT_MASK 0x1u
733 #define CMP_SCR_COUT_SHIFT 0
734 #define CMP_SCR_CFF_MASK 0x2u
735 #define CMP_SCR_CFF_SHIFT 1
736 #define CMP_SCR_CFR_MASK 0x4u
737 #define CMP_SCR_CFR_SHIFT 2
738 #define CMP_SCR_IEF_MASK 0x8u
739 #define CMP_SCR_IEF_SHIFT 3
740 #define CMP_SCR_IER_MASK 0x10u
741 #define CMP_SCR_IER_SHIFT 4
742 #define CMP_SCR_DMAEN_MASK 0x40u
743 #define CMP_SCR_DMAEN_SHIFT 6
744 /* DACCR Bit Fields */
745 #define CMP_DACCR_VOSEL_MASK 0x3Fu
746 #define CMP_DACCR_VOSEL_SHIFT 0
747 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
748 #define CMP_DACCR_VRSEL_MASK 0x40u
749 #define CMP_DACCR_VRSEL_SHIFT 6
750 #define CMP_DACCR_DACEN_MASK 0x80u
751 #define CMP_DACCR_DACEN_SHIFT 7
752 /* MUXCR Bit Fields */
753 #define CMP_MUXCR_MSEL_MASK 0x7u
754 #define CMP_MUXCR_MSEL_SHIFT 0
755 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
756 #define CMP_MUXCR_PSEL_MASK 0x38u
757 #define CMP_MUXCR_PSEL_SHIFT 3
758 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
762 */ /* end of group CMP_Register_Masks */
765 /* CMP - Peripheral instance base addresses */
766 /** Peripheral CMP0 base address */
767 #define CMP0_BASE (0x40073000u)
768 /** Peripheral CMP0 base pointer */
769 #define CMP0 ((CMP_Type *)CMP0_BASE)
770 #define CMP0_BASE_PTR (CMP0)
771 /** Peripheral CMP1 base address */
772 #define CMP1_BASE (0x40073008u)
773 /** Peripheral CMP1 base pointer */
774 #define CMP1 ((CMP_Type *)CMP1_BASE)
775 #define CMP1_BASE_PTR (CMP1)
776 /** Array initializer of CMP peripheral base addresses */
777 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
778 /** Array initializer of CMP peripheral base pointers */
779 #define CMP_BASE_PTRS { CMP0, CMP1 }
780 /** Interrupt vectors for the CMP peripheral type */
781 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
783 /* ----------------------------------------------------------------------------
784 -- CMP - Register accessor macros
785 ---------------------------------------------------------------------------- */
788 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
793 /* CMP - Register instance definitions */
795 #define CMP0_CR0 CMP_CR0_REG(CMP0)
796 #define CMP0_CR1 CMP_CR1_REG(CMP0)
797 #define CMP0_FPR CMP_FPR_REG(CMP0)
798 #define CMP0_SCR CMP_SCR_REG(CMP0)
799 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
800 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
802 #define CMP1_CR0 CMP_CR0_REG(CMP1)
803 #define CMP1_CR1 CMP_CR1_REG(CMP1)
804 #define CMP1_FPR CMP_FPR_REG(CMP1)
805 #define CMP1_SCR CMP_SCR_REG(CMP1)
806 #define CMP1_DACCR CMP_DACCR_REG(CMP1)
807 #define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
811 */ /* end of group CMP_Register_Accessor_Macros */
816 */ /* end of group CMP_Peripheral_Access_Layer */
819 /* ----------------------------------------------------------------------------
820 -- CRC Peripheral Access Layer
821 ---------------------------------------------------------------------------- */
824 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
828 /** CRC - Register Layout Typedef */
830 union { /* offset: 0x0 */
831 struct { /* offset: 0x0 */
832 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
833 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
835 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
836 struct { /* offset: 0x0 */
837 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
838 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
839 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
840 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
843 union { /* offset: 0x4 */
844 struct { /* offset: 0x4 */
845 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
846 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
848 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
849 struct { /* offset: 0x4 */
850 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
851 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
852 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
853 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
856 union { /* offset: 0x8 */
857 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
858 struct { /* offset: 0x8 */
859 uint8_t RESERVED_0[3];
860 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
863 } CRC_Type, *CRC_MemMapPtr;
865 /* ----------------------------------------------------------------------------
866 -- CRC - Register accessor macros
867 ---------------------------------------------------------------------------- */
870 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
875 /* CRC - Register accessors */
876 #define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
877 #define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
878 #define CRC_DATA_REG(base) ((base)->DATA)
879 #define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
880 #define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
881 #define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
882 #define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
883 #define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
884 #define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
885 #define CRC_GPOLY_REG(base) ((base)->GPOLY)
886 #define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
887 #define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
888 #define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
889 #define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
890 #define CRC_CTRL_REG(base) ((base)->CTRL)
891 #define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
895 */ /* end of group CRC_Register_Accessor_Macros */
898 /* ----------------------------------------------------------------------------
899 -- CRC Register Masks
900 ---------------------------------------------------------------------------- */
903 * @addtogroup CRC_Register_Masks CRC Register Masks
907 /* DATAL Bit Fields */
908 #define CRC_DATAL_DATAL_MASK 0xFFFFu
909 #define CRC_DATAL_DATAL_SHIFT 0
910 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
911 /* DATAH Bit Fields */
912 #define CRC_DATAH_DATAH_MASK 0xFFFFu
913 #define CRC_DATAH_DATAH_SHIFT 0
914 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
915 /* DATA Bit Fields */
916 #define CRC_DATA_LL_MASK 0xFFu
917 #define CRC_DATA_LL_SHIFT 0
918 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
919 #define CRC_DATA_LU_MASK 0xFF00u
920 #define CRC_DATA_LU_SHIFT 8
921 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
922 #define CRC_DATA_HL_MASK 0xFF0000u
923 #define CRC_DATA_HL_SHIFT 16
924 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
925 #define CRC_DATA_HU_MASK 0xFF000000u
926 #define CRC_DATA_HU_SHIFT 24
927 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
928 /* DATALL Bit Fields */
929 #define CRC_DATALL_DATALL_MASK 0xFFu
930 #define CRC_DATALL_DATALL_SHIFT 0
931 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
932 /* DATALU Bit Fields */
933 #define CRC_DATALU_DATALU_MASK 0xFFu
934 #define CRC_DATALU_DATALU_SHIFT 0
935 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
936 /* DATAHL Bit Fields */
937 #define CRC_DATAHL_DATAHL_MASK 0xFFu
938 #define CRC_DATAHL_DATAHL_SHIFT 0
939 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
940 /* DATAHU Bit Fields */
941 #define CRC_DATAHU_DATAHU_MASK 0xFFu
942 #define CRC_DATAHU_DATAHU_SHIFT 0
943 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
944 /* GPOLYL Bit Fields */
945 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
946 #define CRC_GPOLYL_GPOLYL_SHIFT 0
947 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
948 /* GPOLYH Bit Fields */
949 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
950 #define CRC_GPOLYH_GPOLYH_SHIFT 0
951 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
952 /* GPOLY Bit Fields */
953 #define CRC_GPOLY_LOW_MASK 0xFFFFu
954 #define CRC_GPOLY_LOW_SHIFT 0
955 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
956 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
957 #define CRC_GPOLY_HIGH_SHIFT 16
958 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
959 /* GPOLYLL Bit Fields */
960 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
961 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
962 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
963 /* GPOLYLU Bit Fields */
964 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
965 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
966 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
967 /* GPOLYHL Bit Fields */
968 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
969 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
970 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
971 /* GPOLYHU Bit Fields */
972 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
973 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
974 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
975 /* CTRL Bit Fields */
976 #define CRC_CTRL_TCRC_MASK 0x1000000u
977 #define CRC_CTRL_TCRC_SHIFT 24
978 #define CRC_CTRL_WAS_MASK 0x2000000u
979 #define CRC_CTRL_WAS_SHIFT 25
980 #define CRC_CTRL_FXOR_MASK 0x4000000u
981 #define CRC_CTRL_FXOR_SHIFT 26
982 #define CRC_CTRL_TOTR_MASK 0x30000000u
983 #define CRC_CTRL_TOTR_SHIFT 28
984 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
985 #define CRC_CTRL_TOT_MASK 0xC0000000u
986 #define CRC_CTRL_TOT_SHIFT 30
987 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
988 /* CTRLHU Bit Fields */
989 #define CRC_CTRLHU_TCRC_MASK 0x1u
990 #define CRC_CTRLHU_TCRC_SHIFT 0
991 #define CRC_CTRLHU_WAS_MASK 0x2u
992 #define CRC_CTRLHU_WAS_SHIFT 1
993 #define CRC_CTRLHU_FXOR_MASK 0x4u
994 #define CRC_CTRLHU_FXOR_SHIFT 2
995 #define CRC_CTRLHU_TOTR_MASK 0x30u
996 #define CRC_CTRLHU_TOTR_SHIFT 4
997 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
998 #define CRC_CTRLHU_TOT_MASK 0xC0u
999 #define CRC_CTRLHU_TOT_SHIFT 6
1000 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
1004 */ /* end of group CRC_Register_Masks */
1007 /* CRC - Peripheral instance base addresses */
1008 /** Peripheral CRC base address */
1009 #define CRC_BASE (0x40032000u)
1010 /** Peripheral CRC base pointer */
1011 #define CRC0 ((CRC_Type *)CRC_BASE)
1012 #define CRC_BASE_PTR (CRC0)
1013 /** Array initializer of CRC peripheral base addresses */
1014 #define CRC_BASE_ADDRS { CRC_BASE }
1015 /** Array initializer of CRC peripheral base pointers */
1016 #define CRC_BASE_PTRS { CRC0 }
1018 /* ----------------------------------------------------------------------------
1019 -- CRC - Register accessor macros
1020 ---------------------------------------------------------------------------- */
1023 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
1028 /* CRC - Register instance definitions */
1030 #define CRC_DATA CRC_DATA_REG(CRC0)
1031 #define CRC_DATAL CRC_DATAL_REG(CRC0)
1032 #define CRC_DATALL CRC_DATALL_REG(CRC0)
1033 #define CRC_DATALU CRC_DATALU_REG(CRC0)
1034 #define CRC_DATAH CRC_DATAH_REG(CRC0)
1035 #define CRC_DATAHL CRC_DATAHL_REG(CRC0)
1036 #define CRC_DATAHU CRC_DATAHU_REG(CRC0)
1037 #define CRC_GPOLY CRC_GPOLY_REG(CRC0)
1038 #define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
1039 #define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
1040 #define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
1041 #define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
1042 #define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
1043 #define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
1044 #define CRC_CTRL CRC_CTRL_REG(CRC0)
1045 #define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
1049 */ /* end of group CRC_Register_Accessor_Macros */
1054 */ /* end of group CRC_Peripheral_Access_Layer */
1057 /* ----------------------------------------------------------------------------
1058 -- DAC Peripheral Access Layer
1059 ---------------------------------------------------------------------------- */
1062 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
1066 /** DAC - Register Layout Typedef */
1068 struct { /* offset: 0x0, array step: 0x2 */
1069 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
1070 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
1072 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
1073 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
1074 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
1075 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
1076 } DAC_Type, *DAC_MemMapPtr;
1078 /* ----------------------------------------------------------------------------
1079 -- DAC - Register accessor macros
1080 ---------------------------------------------------------------------------- */
1083 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
1088 /* DAC - Register accessors */
1089 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
1090 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
1091 #define DAC_SR_REG(base) ((base)->SR)
1092 #define DAC_C0_REG(base) ((base)->C0)
1093 #define DAC_C1_REG(base) ((base)->C1)
1094 #define DAC_C2_REG(base) ((base)->C2)
1098 */ /* end of group DAC_Register_Accessor_Macros */
1101 /* ----------------------------------------------------------------------------
1102 -- DAC Register Masks
1103 ---------------------------------------------------------------------------- */
1106 * @addtogroup DAC_Register_Masks DAC Register Masks
1110 /* DATL Bit Fields */
1111 #define DAC_DATL_DATA0_MASK 0xFFu
1112 #define DAC_DATL_DATA0_SHIFT 0
1113 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
1114 /* DATH Bit Fields */
1115 #define DAC_DATH_DATA1_MASK 0xFu
1116 #define DAC_DATH_DATA1_SHIFT 0
1117 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
1119 #define DAC_SR_DACBFRPBF_MASK 0x1u
1120 #define DAC_SR_DACBFRPBF_SHIFT 0
1121 #define DAC_SR_DACBFRPTF_MASK 0x2u
1122 #define DAC_SR_DACBFRPTF_SHIFT 1
1123 #define DAC_SR_DACBFWMF_MASK 0x4u
1124 #define DAC_SR_DACBFWMF_SHIFT 2
1126 #define DAC_C0_DACBBIEN_MASK 0x1u
1127 #define DAC_C0_DACBBIEN_SHIFT 0
1128 #define DAC_C0_DACBTIEN_MASK 0x2u
1129 #define DAC_C0_DACBTIEN_SHIFT 1
1130 #define DAC_C0_DACBWIEN_MASK 0x4u
1131 #define DAC_C0_DACBWIEN_SHIFT 2
1132 #define DAC_C0_LPEN_MASK 0x8u
1133 #define DAC_C0_LPEN_SHIFT 3
1134 #define DAC_C0_DACSWTRG_MASK 0x10u
1135 #define DAC_C0_DACSWTRG_SHIFT 4
1136 #define DAC_C0_DACTRGSEL_MASK 0x20u
1137 #define DAC_C0_DACTRGSEL_SHIFT 5
1138 #define DAC_C0_DACRFS_MASK 0x40u
1139 #define DAC_C0_DACRFS_SHIFT 6
1140 #define DAC_C0_DACEN_MASK 0x80u
1141 #define DAC_C0_DACEN_SHIFT 7
1143 #define DAC_C1_DACBFEN_MASK 0x1u
1144 #define DAC_C1_DACBFEN_SHIFT 0
1145 #define DAC_C1_DACBFMD_MASK 0x6u
1146 #define DAC_C1_DACBFMD_SHIFT 1
1147 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
1148 #define DAC_C1_DACBFWM_MASK 0x18u
1149 #define DAC_C1_DACBFWM_SHIFT 3
1150 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
1151 #define DAC_C1_DMAEN_MASK 0x80u
1152 #define DAC_C1_DMAEN_SHIFT 7
1154 #define DAC_C2_DACBFUP_MASK 0xFu
1155 #define DAC_C2_DACBFUP_SHIFT 0
1156 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
1157 #define DAC_C2_DACBFRP_MASK 0xF0u
1158 #define DAC_C2_DACBFRP_SHIFT 4
1159 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
1163 */ /* end of group DAC_Register_Masks */
1166 /* DAC - Peripheral instance base addresses */
1167 /** Peripheral DAC0 base address */
1168 #define DAC0_BASE (0x4003F000u)
1169 /** Peripheral DAC0 base pointer */
1170 #define DAC0 ((DAC_Type *)DAC0_BASE)
1171 #define DAC0_BASE_PTR (DAC0)
1172 /** Peripheral DAC1 base address */
1173 #define DAC1_BASE (0x40028000u)
1174 /** Peripheral DAC1 base pointer */
1175 #define DAC1 ((DAC_Type *)DAC1_BASE)
1176 #define DAC1_BASE_PTR (DAC1)
1177 /** Array initializer of DAC peripheral base addresses */
1178 #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
1179 /** Array initializer of DAC peripheral base pointers */
1180 #define DAC_BASE_PTRS { DAC0, DAC1 }
1181 /** Interrupt vectors for the DAC peripheral type */
1182 #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
1184 /* ----------------------------------------------------------------------------
1185 -- DAC - Register accessor macros
1186 ---------------------------------------------------------------------------- */
1189 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
1194 /* DAC - Register instance definitions */
1196 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
1197 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
1198 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
1199 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
1200 #define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
1201 #define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
1202 #define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
1203 #define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
1204 #define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
1205 #define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
1206 #define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
1207 #define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
1208 #define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
1209 #define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
1210 #define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
1211 #define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
1212 #define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
1213 #define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
1214 #define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
1215 #define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
1216 #define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
1217 #define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
1218 #define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
1219 #define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
1220 #define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
1221 #define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
1222 #define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
1223 #define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
1224 #define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
1225 #define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
1226 #define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
1227 #define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
1228 #define DAC0_SR DAC_SR_REG(DAC0)
1229 #define DAC0_C0 DAC_C0_REG(DAC0)
1230 #define DAC0_C1 DAC_C1_REG(DAC0)
1231 #define DAC0_C2 DAC_C2_REG(DAC0)
1233 #define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
1234 #define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
1235 #define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
1236 #define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
1237 #define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
1238 #define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
1239 #define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
1240 #define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
1241 #define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
1242 #define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
1243 #define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
1244 #define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
1245 #define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
1246 #define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
1247 #define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
1248 #define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
1249 #define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
1250 #define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
1251 #define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
1252 #define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
1253 #define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
1254 #define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
1255 #define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
1256 #define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
1257 #define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
1258 #define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
1259 #define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
1260 #define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
1261 #define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
1262 #define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
1263 #define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
1264 #define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
1265 #define DAC1_SR DAC_SR_REG(DAC1)
1266 #define DAC1_C0 DAC_C0_REG(DAC1)
1267 #define DAC1_C1 DAC_C1_REG(DAC1)
1268 #define DAC1_C2 DAC_C2_REG(DAC1)
1270 /* DAC - Register array accessors */
1271 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
1272 #define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
1273 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
1274 #define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
1278 */ /* end of group DAC_Register_Accessor_Macros */
1283 */ /* end of group DAC_Peripheral_Access_Layer */
1286 /* ----------------------------------------------------------------------------
1287 -- DMA Peripheral Access Layer
1288 ---------------------------------------------------------------------------- */
1291 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
1295 /** DMA - Register Layout Typedef */
1297 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
1298 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
1299 uint8_t RESERVED_0[4];
1300 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
1301 uint8_t RESERVED_1[4];
1302 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
1303 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
1304 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
1305 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
1306 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
1307 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
1308 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
1309 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
1310 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
1311 uint8_t RESERVED_2[4];
1312 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
1313 uint8_t RESERVED_3[4];
1314 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
1315 uint8_t RESERVED_4[4];
1316 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
1317 uint8_t RESERVED_5[12];
1318 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
1319 uint8_t RESERVED_6[184];
1320 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
1321 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
1322 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
1323 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
1324 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
1325 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
1326 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
1327 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
1328 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
1329 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
1330 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
1331 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
1332 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
1333 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
1334 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
1335 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
1336 uint8_t RESERVED_7[3824];
1337 struct { /* offset: 0x1000, array step: 0x20 */
1338 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
1339 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
1340 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
1341 union { /* offset: 0x1008, array step: 0x20 */
1342 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
1343 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
1344 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
1346 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
1347 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
1348 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
1349 union { /* offset: 0x1016, array step: 0x20 */
1350 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
1351 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
1353 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
1354 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
1355 union { /* offset: 0x101E, array step: 0x20 */
1356 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
1357 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
1360 } DMA_Type, *DMA_MemMapPtr;
1362 /* ----------------------------------------------------------------------------
1363 -- DMA - Register accessor macros
1364 ---------------------------------------------------------------------------- */
1367 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
1372 /* DMA - Register accessors */
1373 #define DMA_CR_REG(base) ((base)->CR)
1374 #define DMA_ES_REG(base) ((base)->ES)
1375 #define DMA_ERQ_REG(base) ((base)->ERQ)
1376 #define DMA_EEI_REG(base) ((base)->EEI)
1377 #define DMA_CEEI_REG(base) ((base)->CEEI)
1378 #define DMA_SEEI_REG(base) ((base)->SEEI)
1379 #define DMA_CERQ_REG(base) ((base)->CERQ)
1380 #define DMA_SERQ_REG(base) ((base)->SERQ)
1381 #define DMA_CDNE_REG(base) ((base)->CDNE)
1382 #define DMA_SSRT_REG(base) ((base)->SSRT)
1383 #define DMA_CERR_REG(base) ((base)->CERR)
1384 #define DMA_CINT_REG(base) ((base)->CINT)
1385 #define DMA_INT_REG(base) ((base)->INT)
1386 #define DMA_ERR_REG(base) ((base)->ERR)
1387 #define DMA_HRS_REG(base) ((base)->HRS)
1388 #define DMA_EARS_REG(base) ((base)->EARS)
1389 #define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
1390 #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
1391 #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
1392 #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
1393 #define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
1394 #define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
1395 #define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
1396 #define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
1397 #define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
1398 #define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
1399 #define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
1400 #define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
1401 #define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
1402 #define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
1403 #define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
1404 #define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
1405 #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
1406 #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
1407 #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
1408 #define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
1409 #define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
1410 #define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
1411 #define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
1412 #define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
1413 #define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
1414 #define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
1415 #define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
1416 #define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
1417 #define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
1418 #define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
1419 #define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
1423 */ /* end of group DMA_Register_Accessor_Macros */
1426 /* ----------------------------------------------------------------------------
1427 -- DMA Register Masks
1428 ---------------------------------------------------------------------------- */
1431 * @addtogroup DMA_Register_Masks DMA Register Masks
1436 #define DMA_CR_EDBG_MASK 0x2u
1437 #define DMA_CR_EDBG_SHIFT 1
1438 #define DMA_CR_ERCA_MASK 0x4u
1439 #define DMA_CR_ERCA_SHIFT 2
1440 #define DMA_CR_HOE_MASK 0x10u
1441 #define DMA_CR_HOE_SHIFT 4
1442 #define DMA_CR_HALT_MASK 0x20u
1443 #define DMA_CR_HALT_SHIFT 5
1444 #define DMA_CR_CLM_MASK 0x40u
1445 #define DMA_CR_CLM_SHIFT 6
1446 #define DMA_CR_EMLM_MASK 0x80u
1447 #define DMA_CR_EMLM_SHIFT 7
1448 #define DMA_CR_ECX_MASK 0x10000u
1449 #define DMA_CR_ECX_SHIFT 16
1450 #define DMA_CR_CX_MASK 0x20000u
1451 #define DMA_CR_CX_SHIFT 17
1453 #define DMA_ES_DBE_MASK 0x1u
1454 #define DMA_ES_DBE_SHIFT 0
1455 #define DMA_ES_SBE_MASK 0x2u
1456 #define DMA_ES_SBE_SHIFT 1
1457 #define DMA_ES_SGE_MASK 0x4u
1458 #define DMA_ES_SGE_SHIFT 2
1459 #define DMA_ES_NCE_MASK 0x8u
1460 #define DMA_ES_NCE_SHIFT 3
1461 #define DMA_ES_DOE_MASK 0x10u
1462 #define DMA_ES_DOE_SHIFT 4
1463 #define DMA_ES_DAE_MASK 0x20u
1464 #define DMA_ES_DAE_SHIFT 5
1465 #define DMA_ES_SOE_MASK 0x40u
1466 #define DMA_ES_SOE_SHIFT 6
1467 #define DMA_ES_SAE_MASK 0x80u
1468 #define DMA_ES_SAE_SHIFT 7
1469 #define DMA_ES_ERRCHN_MASK 0xF00u
1470 #define DMA_ES_ERRCHN_SHIFT 8
1471 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
1472 #define DMA_ES_CPE_MASK 0x4000u
1473 #define DMA_ES_CPE_SHIFT 14
1474 #define DMA_ES_ECX_MASK 0x10000u
1475 #define DMA_ES_ECX_SHIFT 16
1476 #define DMA_ES_VLD_MASK 0x80000000u
1477 #define DMA_ES_VLD_SHIFT 31
1478 /* ERQ Bit Fields */
1479 #define DMA_ERQ_ERQ0_MASK 0x1u
1480 #define DMA_ERQ_ERQ0_SHIFT 0
1481 #define DMA_ERQ_ERQ1_MASK 0x2u
1482 #define DMA_ERQ_ERQ1_SHIFT 1
1483 #define DMA_ERQ_ERQ2_MASK 0x4u
1484 #define DMA_ERQ_ERQ2_SHIFT 2
1485 #define DMA_ERQ_ERQ3_MASK 0x8u
1486 #define DMA_ERQ_ERQ3_SHIFT 3
1487 #define DMA_ERQ_ERQ4_MASK 0x10u
1488 #define DMA_ERQ_ERQ4_SHIFT 4
1489 #define DMA_ERQ_ERQ5_MASK 0x20u
1490 #define DMA_ERQ_ERQ5_SHIFT 5
1491 #define DMA_ERQ_ERQ6_MASK 0x40u
1492 #define DMA_ERQ_ERQ6_SHIFT 6
1493 #define DMA_ERQ_ERQ7_MASK 0x80u
1494 #define DMA_ERQ_ERQ7_SHIFT 7
1495 #define DMA_ERQ_ERQ8_MASK 0x100u
1496 #define DMA_ERQ_ERQ8_SHIFT 8
1497 #define DMA_ERQ_ERQ9_MASK 0x200u
1498 #define DMA_ERQ_ERQ9_SHIFT 9
1499 #define DMA_ERQ_ERQ10_MASK 0x400u
1500 #define DMA_ERQ_ERQ10_SHIFT 10
1501 #define DMA_ERQ_ERQ11_MASK 0x800u
1502 #define DMA_ERQ_ERQ11_SHIFT 11
1503 #define DMA_ERQ_ERQ12_MASK 0x1000u
1504 #define DMA_ERQ_ERQ12_SHIFT 12
1505 #define DMA_ERQ_ERQ13_MASK 0x2000u
1506 #define DMA_ERQ_ERQ13_SHIFT 13
1507 #define DMA_ERQ_ERQ14_MASK 0x4000u
1508 #define DMA_ERQ_ERQ14_SHIFT 14
1509 #define DMA_ERQ_ERQ15_MASK 0x8000u
1510 #define DMA_ERQ_ERQ15_SHIFT 15
1511 /* EEI Bit Fields */
1512 #define DMA_EEI_EEI0_MASK 0x1u
1513 #define DMA_EEI_EEI0_SHIFT 0
1514 #define DMA_EEI_EEI1_MASK 0x2u
1515 #define DMA_EEI_EEI1_SHIFT 1
1516 #define DMA_EEI_EEI2_MASK 0x4u
1517 #define DMA_EEI_EEI2_SHIFT 2
1518 #define DMA_EEI_EEI3_MASK 0x8u
1519 #define DMA_EEI_EEI3_SHIFT 3
1520 #define DMA_EEI_EEI4_MASK 0x10u
1521 #define DMA_EEI_EEI4_SHIFT 4
1522 #define DMA_EEI_EEI5_MASK 0x20u
1523 #define DMA_EEI_EEI5_SHIFT 5
1524 #define DMA_EEI_EEI6_MASK 0x40u
1525 #define DMA_EEI_EEI6_SHIFT 6
1526 #define DMA_EEI_EEI7_MASK 0x80u
1527 #define DMA_EEI_EEI7_SHIFT 7
1528 #define DMA_EEI_EEI8_MASK 0x100u
1529 #define DMA_EEI_EEI8_SHIFT 8
1530 #define DMA_EEI_EEI9_MASK 0x200u
1531 #define DMA_EEI_EEI9_SHIFT 9
1532 #define DMA_EEI_EEI10_MASK 0x400u
1533 #define DMA_EEI_EEI10_SHIFT 10
1534 #define DMA_EEI_EEI11_MASK 0x800u
1535 #define DMA_EEI_EEI11_SHIFT 11
1536 #define DMA_EEI_EEI12_MASK 0x1000u
1537 #define DMA_EEI_EEI12_SHIFT 12
1538 #define DMA_EEI_EEI13_MASK 0x2000u
1539 #define DMA_EEI_EEI13_SHIFT 13
1540 #define DMA_EEI_EEI14_MASK 0x4000u
1541 #define DMA_EEI_EEI14_SHIFT 14
1542 #define DMA_EEI_EEI15_MASK 0x8000u
1543 #define DMA_EEI_EEI15_SHIFT 15
1544 /* CEEI Bit Fields */
1545 #define DMA_CEEI_CEEI_MASK 0xFu
1546 #define DMA_CEEI_CEEI_SHIFT 0
1547 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
1548 #define DMA_CEEI_CAEE_MASK 0x40u
1549 #define DMA_CEEI_CAEE_SHIFT 6
1550 #define DMA_CEEI_NOP_MASK 0x80u
1551 #define DMA_CEEI_NOP_SHIFT 7
1552 /* SEEI Bit Fields */
1553 #define DMA_SEEI_SEEI_MASK 0xFu
1554 #define DMA_SEEI_SEEI_SHIFT 0
1555 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
1556 #define DMA_SEEI_SAEE_MASK 0x40u
1557 #define DMA_SEEI_SAEE_SHIFT 6
1558 #define DMA_SEEI_NOP_MASK 0x80u
1559 #define DMA_SEEI_NOP_SHIFT 7
1560 /* CERQ Bit Fields */
1561 #define DMA_CERQ_CERQ_MASK 0xFu
1562 #define DMA_CERQ_CERQ_SHIFT 0
1563 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
1564 #define DMA_CERQ_CAER_MASK 0x40u
1565 #define DMA_CERQ_CAER_SHIFT 6
1566 #define DMA_CERQ_NOP_MASK 0x80u
1567 #define DMA_CERQ_NOP_SHIFT 7
1568 /* SERQ Bit Fields */
1569 #define DMA_SERQ_SERQ_MASK 0xFu
1570 #define DMA_SERQ_SERQ_SHIFT 0
1571 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
1572 #define DMA_SERQ_SAER_MASK 0x40u
1573 #define DMA_SERQ_SAER_SHIFT 6
1574 #define DMA_SERQ_NOP_MASK 0x80u
1575 #define DMA_SERQ_NOP_SHIFT 7
1576 /* CDNE Bit Fields */
1577 #define DMA_CDNE_CDNE_MASK 0xFu
1578 #define DMA_CDNE_CDNE_SHIFT 0
1579 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
1580 #define DMA_CDNE_CADN_MASK 0x40u
1581 #define DMA_CDNE_CADN_SHIFT 6
1582 #define DMA_CDNE_NOP_MASK 0x80u
1583 #define DMA_CDNE_NOP_SHIFT 7
1584 /* SSRT Bit Fields */
1585 #define DMA_SSRT_SSRT_MASK 0xFu
1586 #define DMA_SSRT_SSRT_SHIFT 0
1587 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
1588 #define DMA_SSRT_SAST_MASK 0x40u
1589 #define DMA_SSRT_SAST_SHIFT 6
1590 #define DMA_SSRT_NOP_MASK 0x80u
1591 #define DMA_SSRT_NOP_SHIFT 7
1592 /* CERR Bit Fields */
1593 #define DMA_CERR_CERR_MASK 0xFu
1594 #define DMA_CERR_CERR_SHIFT 0
1595 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
1596 #define DMA_CERR_CAEI_MASK 0x40u
1597 #define DMA_CERR_CAEI_SHIFT 6
1598 #define DMA_CERR_NOP_MASK 0x80u
1599 #define DMA_CERR_NOP_SHIFT 7
1600 /* CINT Bit Fields */
1601 #define DMA_CINT_CINT_MASK 0xFu
1602 #define DMA_CINT_CINT_SHIFT 0
1603 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
1604 #define DMA_CINT_CAIR_MASK 0x40u
1605 #define DMA_CINT_CAIR_SHIFT 6
1606 #define DMA_CINT_NOP_MASK 0x80u
1607 #define DMA_CINT_NOP_SHIFT 7
1608 /* INT Bit Fields */
1609 #define DMA_INT_INT0_MASK 0x1u
1610 #define DMA_INT_INT0_SHIFT 0
1611 #define DMA_INT_INT1_MASK 0x2u
1612 #define DMA_INT_INT1_SHIFT 1
1613 #define DMA_INT_INT2_MASK 0x4u
1614 #define DMA_INT_INT2_SHIFT 2
1615 #define DMA_INT_INT3_MASK 0x8u
1616 #define DMA_INT_INT3_SHIFT 3
1617 #define DMA_INT_INT4_MASK 0x10u
1618 #define DMA_INT_INT4_SHIFT 4
1619 #define DMA_INT_INT5_MASK 0x20u
1620 #define DMA_INT_INT5_SHIFT 5
1621 #define DMA_INT_INT6_MASK 0x40u
1622 #define DMA_INT_INT6_SHIFT 6
1623 #define DMA_INT_INT7_MASK 0x80u
1624 #define DMA_INT_INT7_SHIFT 7
1625 #define DMA_INT_INT8_MASK 0x100u
1626 #define DMA_INT_INT8_SHIFT 8
1627 #define DMA_INT_INT9_MASK 0x200u
1628 #define DMA_INT_INT9_SHIFT 9
1629 #define DMA_INT_INT10_MASK 0x400u
1630 #define DMA_INT_INT10_SHIFT 10
1631 #define DMA_INT_INT11_MASK 0x800u
1632 #define DMA_INT_INT11_SHIFT 11
1633 #define DMA_INT_INT12_MASK 0x1000u
1634 #define DMA_INT_INT12_SHIFT 12
1635 #define DMA_INT_INT13_MASK 0x2000u
1636 #define DMA_INT_INT13_SHIFT 13
1637 #define DMA_INT_INT14_MASK 0x4000u
1638 #define DMA_INT_INT14_SHIFT 14
1639 #define DMA_INT_INT15_MASK 0x8000u
1640 #define DMA_INT_INT15_SHIFT 15
1641 /* ERR Bit Fields */
1642 #define DMA_ERR_ERR0_MASK 0x1u
1643 #define DMA_ERR_ERR0_SHIFT 0
1644 #define DMA_ERR_ERR1_MASK 0x2u
1645 #define DMA_ERR_ERR1_SHIFT 1
1646 #define DMA_ERR_ERR2_MASK 0x4u
1647 #define DMA_ERR_ERR2_SHIFT 2
1648 #define DMA_ERR_ERR3_MASK 0x8u
1649 #define DMA_ERR_ERR3_SHIFT 3
1650 #define DMA_ERR_ERR4_MASK 0x10u
1651 #define DMA_ERR_ERR4_SHIFT 4
1652 #define DMA_ERR_ERR5_MASK 0x20u
1653 #define DMA_ERR_ERR5_SHIFT 5
1654 #define DMA_ERR_ERR6_MASK 0x40u
1655 #define DMA_ERR_ERR6_SHIFT 6
1656 #define DMA_ERR_ERR7_MASK 0x80u
1657 #define DMA_ERR_ERR7_SHIFT 7
1658 #define DMA_ERR_ERR8_MASK 0x100u
1659 #define DMA_ERR_ERR8_SHIFT 8
1660 #define DMA_ERR_ERR9_MASK 0x200u
1661 #define DMA_ERR_ERR9_SHIFT 9
1662 #define DMA_ERR_ERR10_MASK 0x400u
1663 #define DMA_ERR_ERR10_SHIFT 10
1664 #define DMA_ERR_ERR11_MASK 0x800u
1665 #define DMA_ERR_ERR11_SHIFT 11
1666 #define DMA_ERR_ERR12_MASK 0x1000u
1667 #define DMA_ERR_ERR12_SHIFT 12
1668 #define DMA_ERR_ERR13_MASK 0x2000u
1669 #define DMA_ERR_ERR13_SHIFT 13
1670 #define DMA_ERR_ERR14_MASK 0x4000u
1671 #define DMA_ERR_ERR14_SHIFT 14
1672 #define DMA_ERR_ERR15_MASK 0x8000u
1673 #define DMA_ERR_ERR15_SHIFT 15
1674 /* HRS Bit Fields */
1675 #define DMA_HRS_HRS0_MASK 0x1u
1676 #define DMA_HRS_HRS0_SHIFT 0
1677 #define DMA_HRS_HRS1_MASK 0x2u
1678 #define DMA_HRS_HRS1_SHIFT 1
1679 #define DMA_HRS_HRS2_MASK 0x4u
1680 #define DMA_HRS_HRS2_SHIFT 2
1681 #define DMA_HRS_HRS3_MASK 0x8u
1682 #define DMA_HRS_HRS3_SHIFT 3
1683 #define DMA_HRS_HRS4_MASK 0x10u
1684 #define DMA_HRS_HRS4_SHIFT 4
1685 #define DMA_HRS_HRS5_MASK 0x20u
1686 #define DMA_HRS_HRS5_SHIFT 5
1687 #define DMA_HRS_HRS6_MASK 0x40u
1688 #define DMA_HRS_HRS6_SHIFT 6
1689 #define DMA_HRS_HRS7_MASK 0x80u
1690 #define DMA_HRS_HRS7_SHIFT 7
1691 #define DMA_HRS_HRS8_MASK 0x100u
1692 #define DMA_HRS_HRS8_SHIFT 8
1693 #define DMA_HRS_HRS9_MASK 0x200u
1694 #define DMA_HRS_HRS9_SHIFT 9
1695 #define DMA_HRS_HRS10_MASK 0x400u
1696 #define DMA_HRS_HRS10_SHIFT 10
1697 #define DMA_HRS_HRS11_MASK 0x800u
1698 #define DMA_HRS_HRS11_SHIFT 11
1699 #define DMA_HRS_HRS12_MASK 0x1000u
1700 #define DMA_HRS_HRS12_SHIFT 12
1701 #define DMA_HRS_HRS13_MASK 0x2000u
1702 #define DMA_HRS_HRS13_SHIFT 13
1703 #define DMA_HRS_HRS14_MASK 0x4000u
1704 #define DMA_HRS_HRS14_SHIFT 14
1705 #define DMA_HRS_HRS15_MASK 0x8000u
1706 #define DMA_HRS_HRS15_SHIFT 15
1707 /* EARS Bit Fields */
1708 #define DMA_EARS_EDREQ_0_MASK 0x1u
1709 #define DMA_EARS_EDREQ_0_SHIFT 0
1710 #define DMA_EARS_EDREQ_1_MASK 0x2u
1711 #define DMA_EARS_EDREQ_1_SHIFT 1
1712 #define DMA_EARS_EDREQ_2_MASK 0x4u
1713 #define DMA_EARS_EDREQ_2_SHIFT 2
1714 #define DMA_EARS_EDREQ_3_MASK 0x8u
1715 #define DMA_EARS_EDREQ_3_SHIFT 3
1716 #define DMA_EARS_EDREQ_4_MASK 0x10u
1717 #define DMA_EARS_EDREQ_4_SHIFT 4
1718 #define DMA_EARS_EDREQ_5_MASK 0x20u
1719 #define DMA_EARS_EDREQ_5_SHIFT 5
1720 #define DMA_EARS_EDREQ_6_MASK 0x40u
1721 #define DMA_EARS_EDREQ_6_SHIFT 6
1722 #define DMA_EARS_EDREQ_7_MASK 0x80u
1723 #define DMA_EARS_EDREQ_7_SHIFT 7
1724 #define DMA_EARS_EDREQ_8_MASK 0x100u
1725 #define DMA_EARS_EDREQ_8_SHIFT 8
1726 #define DMA_EARS_EDREQ_9_MASK 0x200u
1727 #define DMA_EARS_EDREQ_9_SHIFT 9
1728 #define DMA_EARS_EDREQ_10_MASK 0x400u
1729 #define DMA_EARS_EDREQ_10_SHIFT 10
1730 #define DMA_EARS_EDREQ_11_MASK 0x800u
1731 #define DMA_EARS_EDREQ_11_SHIFT 11
1732 #define DMA_EARS_EDREQ_12_MASK 0x1000u
1733 #define DMA_EARS_EDREQ_12_SHIFT 12
1734 #define DMA_EARS_EDREQ_13_MASK 0x2000u
1735 #define DMA_EARS_EDREQ_13_SHIFT 13
1736 #define DMA_EARS_EDREQ_14_MASK 0x4000u
1737 #define DMA_EARS_EDREQ_14_SHIFT 14
1738 #define DMA_EARS_EDREQ_15_MASK 0x8000u
1739 #define DMA_EARS_EDREQ_15_SHIFT 15
1740 /* DCHPRI3 Bit Fields */
1741 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
1742 #define DMA_DCHPRI3_CHPRI_SHIFT 0
1743 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
1744 #define DMA_DCHPRI3_DPA_MASK 0x40u
1745 #define DMA_DCHPRI3_DPA_SHIFT 6
1746 #define DMA_DCHPRI3_ECP_MASK 0x80u
1747 #define DMA_DCHPRI3_ECP_SHIFT 7
1748 /* DCHPRI2 Bit Fields */
1749 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
1750 #define DMA_DCHPRI2_CHPRI_SHIFT 0
1751 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
1752 #define DMA_DCHPRI2_DPA_MASK 0x40u
1753 #define DMA_DCHPRI2_DPA_SHIFT 6
1754 #define DMA_DCHPRI2_ECP_MASK 0x80u
1755 #define DMA_DCHPRI2_ECP_SHIFT 7
1756 /* DCHPRI1 Bit Fields */
1757 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
1758 #define DMA_DCHPRI1_CHPRI_SHIFT 0
1759 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
1760 #define DMA_DCHPRI1_DPA_MASK 0x40u
1761 #define DMA_DCHPRI1_DPA_SHIFT 6
1762 #define DMA_DCHPRI1_ECP_MASK 0x80u
1763 #define DMA_DCHPRI1_ECP_SHIFT 7
1764 /* DCHPRI0 Bit Fields */
1765 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
1766 #define DMA_DCHPRI0_CHPRI_SHIFT 0
1767 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
1768 #define DMA_DCHPRI0_DPA_MASK 0x40u
1769 #define DMA_DCHPRI0_DPA_SHIFT 6
1770 #define DMA_DCHPRI0_ECP_MASK 0x80u
1771 #define DMA_DCHPRI0_ECP_SHIFT 7
1772 /* DCHPRI7 Bit Fields */
1773 #define DMA_DCHPRI7_CHPRI_MASK 0xFu
1774 #define DMA_DCHPRI7_CHPRI_SHIFT 0
1775 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
1776 #define DMA_DCHPRI7_DPA_MASK 0x40u
1777 #define DMA_DCHPRI7_DPA_SHIFT 6
1778 #define DMA_DCHPRI7_ECP_MASK 0x80u
1779 #define DMA_DCHPRI7_ECP_SHIFT 7
1780 /* DCHPRI6 Bit Fields */
1781 #define DMA_DCHPRI6_CHPRI_MASK 0xFu
1782 #define DMA_DCHPRI6_CHPRI_SHIFT 0
1783 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
1784 #define DMA_DCHPRI6_DPA_MASK 0x40u
1785 #define DMA_DCHPRI6_DPA_SHIFT 6
1786 #define DMA_DCHPRI6_ECP_MASK 0x80u
1787 #define DMA_DCHPRI6_ECP_SHIFT 7
1788 /* DCHPRI5 Bit Fields */
1789 #define DMA_DCHPRI5_CHPRI_MASK 0xFu
1790 #define DMA_DCHPRI5_CHPRI_SHIFT 0
1791 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
1792 #define DMA_DCHPRI5_DPA_MASK 0x40u
1793 #define DMA_DCHPRI5_DPA_SHIFT 6
1794 #define DMA_DCHPRI5_ECP_MASK 0x80u
1795 #define DMA_DCHPRI5_ECP_SHIFT 7
1796 /* DCHPRI4 Bit Fields */
1797 #define DMA_DCHPRI4_CHPRI_MASK 0xFu
1798 #define DMA_DCHPRI4_CHPRI_SHIFT 0
1799 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
1800 #define DMA_DCHPRI4_DPA_MASK 0x40u
1801 #define DMA_DCHPRI4_DPA_SHIFT 6
1802 #define DMA_DCHPRI4_ECP_MASK 0x80u
1803 #define DMA_DCHPRI4_ECP_SHIFT 7
1804 /* DCHPRI11 Bit Fields */
1805 #define DMA_DCHPRI11_CHPRI_MASK 0xFu
1806 #define DMA_DCHPRI11_CHPRI_SHIFT 0
1807 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
1808 #define DMA_DCHPRI11_DPA_MASK 0x40u
1809 #define DMA_DCHPRI11_DPA_SHIFT 6
1810 #define DMA_DCHPRI11_ECP_MASK 0x80u
1811 #define DMA_DCHPRI11_ECP_SHIFT 7
1812 /* DCHPRI10 Bit Fields */
1813 #define DMA_DCHPRI10_CHPRI_MASK 0xFu
1814 #define DMA_DCHPRI10_CHPRI_SHIFT 0
1815 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
1816 #define DMA_DCHPRI10_DPA_MASK 0x40u
1817 #define DMA_DCHPRI10_DPA_SHIFT 6
1818 #define DMA_DCHPRI10_ECP_MASK 0x80u
1819 #define DMA_DCHPRI10_ECP_SHIFT 7
1820 /* DCHPRI9 Bit Fields */
1821 #define DMA_DCHPRI9_CHPRI_MASK 0xFu
1822 #define DMA_DCHPRI9_CHPRI_SHIFT 0
1823 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
1824 #define DMA_DCHPRI9_DPA_MASK 0x40u
1825 #define DMA_DCHPRI9_DPA_SHIFT 6
1826 #define DMA_DCHPRI9_ECP_MASK 0x80u
1827 #define DMA_DCHPRI9_ECP_SHIFT 7
1828 /* DCHPRI8 Bit Fields */
1829 #define DMA_DCHPRI8_CHPRI_MASK 0xFu
1830 #define DMA_DCHPRI8_CHPRI_SHIFT 0
1831 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
1832 #define DMA_DCHPRI8_DPA_MASK 0x40u
1833 #define DMA_DCHPRI8_DPA_SHIFT 6
1834 #define DMA_DCHPRI8_ECP_MASK 0x80u
1835 #define DMA_DCHPRI8_ECP_SHIFT 7
1836 /* DCHPRI15 Bit Fields */
1837 #define DMA_DCHPRI15_CHPRI_MASK 0xFu
1838 #define DMA_DCHPRI15_CHPRI_SHIFT 0
1839 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
1840 #define DMA_DCHPRI15_DPA_MASK 0x40u
1841 #define DMA_DCHPRI15_DPA_SHIFT 6
1842 #define DMA_DCHPRI15_ECP_MASK 0x80u
1843 #define DMA_DCHPRI15_ECP_SHIFT 7
1844 /* DCHPRI14 Bit Fields */
1845 #define DMA_DCHPRI14_CHPRI_MASK 0xFu
1846 #define DMA_DCHPRI14_CHPRI_SHIFT 0
1847 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
1848 #define DMA_DCHPRI14_DPA_MASK 0x40u
1849 #define DMA_DCHPRI14_DPA_SHIFT 6
1850 #define DMA_DCHPRI14_ECP_MASK 0x80u
1851 #define DMA_DCHPRI14_ECP_SHIFT 7
1852 /* DCHPRI13 Bit Fields */
1853 #define DMA_DCHPRI13_CHPRI_MASK 0xFu
1854 #define DMA_DCHPRI13_CHPRI_SHIFT 0
1855 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
1856 #define DMA_DCHPRI13_DPA_MASK 0x40u
1857 #define DMA_DCHPRI13_DPA_SHIFT 6
1858 #define DMA_DCHPRI13_ECP_MASK 0x80u
1859 #define DMA_DCHPRI13_ECP_SHIFT 7
1860 /* DCHPRI12 Bit Fields */
1861 #define DMA_DCHPRI12_CHPRI_MASK 0xFu
1862 #define DMA_DCHPRI12_CHPRI_SHIFT 0
1863 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
1864 #define DMA_DCHPRI12_DPA_MASK 0x40u
1865 #define DMA_DCHPRI12_DPA_SHIFT 6
1866 #define DMA_DCHPRI12_ECP_MASK 0x80u
1867 #define DMA_DCHPRI12_ECP_SHIFT 7
1868 /* SADDR Bit Fields */
1869 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
1870 #define DMA_SADDR_SADDR_SHIFT 0
1871 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
1872 /* SOFF Bit Fields */
1873 #define DMA_SOFF_SOFF_MASK 0xFFFFu
1874 #define DMA_SOFF_SOFF_SHIFT 0
1875 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
1876 /* ATTR Bit Fields */
1877 #define DMA_ATTR_DSIZE_MASK 0x7u
1878 #define DMA_ATTR_DSIZE_SHIFT 0
1879 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
1880 #define DMA_ATTR_DMOD_MASK 0xF8u
1881 #define DMA_ATTR_DMOD_SHIFT 3
1882 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
1883 #define DMA_ATTR_SSIZE_MASK 0x700u
1884 #define DMA_ATTR_SSIZE_SHIFT 8
1885 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
1886 #define DMA_ATTR_SMOD_MASK 0xF800u
1887 #define DMA_ATTR_SMOD_SHIFT 11
1888 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
1889 /* NBYTES_MLNO Bit Fields */
1890 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
1891 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
1892 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
1893 /* NBYTES_MLOFFNO Bit Fields */
1894 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
1895 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
1896 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
1897 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
1898 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
1899 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
1900 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
1901 /* NBYTES_MLOFFYES Bit Fields */
1902 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
1903 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
1904 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
1905 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
1906 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
1907 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
1908 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
1909 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
1910 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
1911 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
1912 /* SLAST Bit Fields */
1913 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
1914 #define DMA_SLAST_SLAST_SHIFT 0
1915 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
1916 /* DADDR Bit Fields */
1917 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
1918 #define DMA_DADDR_DADDR_SHIFT 0
1919 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
1920 /* DOFF Bit Fields */
1921 #define DMA_DOFF_DOFF_MASK 0xFFFFu
1922 #define DMA_DOFF_DOFF_SHIFT 0
1923 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
1924 /* CITER_ELINKNO Bit Fields */
1925 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
1926 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
1927 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
1928 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
1929 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
1930 /* CITER_ELINKYES Bit Fields */
1931 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
1932 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
1933 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
1934 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
1935 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
1936 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
1937 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
1938 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
1939 /* DLAST_SGA Bit Fields */
1940 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
1941 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
1942 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
1943 /* CSR Bit Fields */
1944 #define DMA_CSR_START_MASK 0x1u
1945 #define DMA_CSR_START_SHIFT 0
1946 #define DMA_CSR_INTMAJOR_MASK 0x2u
1947 #define DMA_CSR_INTMAJOR_SHIFT 1
1948 #define DMA_CSR_INTHALF_MASK 0x4u
1949 #define DMA_CSR_INTHALF_SHIFT 2
1950 #define DMA_CSR_DREQ_MASK 0x8u
1951 #define DMA_CSR_DREQ_SHIFT 3
1952 #define DMA_CSR_ESG_MASK 0x10u
1953 #define DMA_CSR_ESG_SHIFT 4
1954 #define DMA_CSR_MAJORELINK_MASK 0x20u
1955 #define DMA_CSR_MAJORELINK_SHIFT 5
1956 #define DMA_CSR_ACTIVE_MASK 0x40u
1957 #define DMA_CSR_ACTIVE_SHIFT 6
1958 #define DMA_CSR_DONE_MASK 0x80u
1959 #define DMA_CSR_DONE_SHIFT 7
1960 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
1961 #define DMA_CSR_MAJORLINKCH_SHIFT 8
1962 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
1963 #define DMA_CSR_BWC_MASK 0xC000u
1964 #define DMA_CSR_BWC_SHIFT 14
1965 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
1966 /* BITER_ELINKNO Bit Fields */
1967 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
1968 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
1969 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
1970 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
1971 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
1972 /* BITER_ELINKYES Bit Fields */
1973 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
1974 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
1975 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
1976 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
1977 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
1978 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
1979 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
1980 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
1984 */ /* end of group DMA_Register_Masks */
1987 /* DMA - Peripheral instance base addresses */
1988 /** Peripheral DMA base address */
1989 #define DMA_BASE (0x40008000u)
1990 /** Peripheral DMA base pointer */
1991 #define DMA0 ((DMA_Type *)DMA_BASE)
1992 #define DMA_BASE_PTR (DMA0)
1993 /** Array initializer of DMA peripheral base addresses */
1994 #define DMA_BASE_ADDRS { DMA_BASE }
1995 /** Array initializer of DMA peripheral base pointers */
1996 #define DMA_BASE_PTRS { DMA0 }
1997 /** Interrupt vectors for the DMA peripheral type */
1998 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
1999 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
2001 /* ----------------------------------------------------------------------------
2002 -- DMA - Register accessor macros
2003 ---------------------------------------------------------------------------- */
2006 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
2011 /* DMA - Register instance definitions */
2013 #define DMA_CR DMA_CR_REG(DMA0)
2014 #define DMA_ES DMA_ES_REG(DMA0)
2015 #define DMA_ERQ DMA_ERQ_REG(DMA0)
2016 #define DMA_EEI DMA_EEI_REG(DMA0)
2017 #define DMA_CEEI DMA_CEEI_REG(DMA0)
2018 #define DMA_SEEI DMA_SEEI_REG(DMA0)
2019 #define DMA_CERQ DMA_CERQ_REG(DMA0)
2020 #define DMA_SERQ DMA_SERQ_REG(DMA0)
2021 #define DMA_CDNE DMA_CDNE_REG(DMA0)
2022 #define DMA_SSRT DMA_SSRT_REG(DMA0)
2023 #define DMA_CERR DMA_CERR_REG(DMA0)
2024 #define DMA_CINT DMA_CINT_REG(DMA0)
2025 #define DMA_INT DMA_INT_REG(DMA0)
2026 #define DMA_ERR DMA_ERR_REG(DMA0)
2027 #define DMA_HRS DMA_HRS_REG(DMA0)
2028 #define DMA_EARS DMA_EARS_REG(DMA0)
2029 #define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
2030 #define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
2031 #define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
2032 #define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
2033 #define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
2034 #define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
2035 #define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
2036 #define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
2037 #define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
2038 #define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
2039 #define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
2040 #define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
2041 #define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
2042 #define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
2043 #define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
2044 #define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
2045 #define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
2046 #define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
2047 #define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
2048 #define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
2049 #define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
2050 #define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
2051 #define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
2052 #define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
2053 #define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
2054 #define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
2055 #define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
2056 #define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
2057 #define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
2058 #define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
2059 #define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
2060 #define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
2061 #define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
2062 #define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
2063 #define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
2064 #define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
2065 #define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
2066 #define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
2067 #define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
2068 #define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
2069 #define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
2070 #define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
2071 #define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
2072 #define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
2073 #define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
2074 #define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
2075 #define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
2076 #define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
2077 #define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
2078 #define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
2079 #define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
2080 #define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
2081 #define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
2082 #define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
2083 #define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
2084 #define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
2085 #define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
2086 #define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
2087 #define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
2088 #define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
2089 #define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
2090 #define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
2091 #define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
2092 #define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
2093 #define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
2094 #define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
2095 #define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
2096 #define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
2097 #define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
2098 #define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
2099 #define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
2100 #define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
2101 #define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
2102 #define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
2103 #define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
2104 #define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
2105 #define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
2106 #define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
2107 #define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
2108 #define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
2109 #define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
2110 #define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
2111 #define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
2112 #define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
2113 #define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
2114 #define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
2115 #define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
2116 #define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
2117 #define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
2118 #define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
2119 #define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
2120 #define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
2121 #define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
2122 #define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
2123 #define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
2124 #define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
2125 #define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
2126 #define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
2127 #define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
2128 #define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
2129 #define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
2130 #define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
2131 #define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
2132 #define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
2133 #define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
2134 #define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
2135 #define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
2136 #define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
2137 #define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
2138 #define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
2139 #define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
2140 #define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
2141 #define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
2142 #define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
2143 #define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
2144 #define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
2145 #define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
2146 #define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
2147 #define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
2148 #define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
2149 #define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
2150 #define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
2151 #define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
2152 #define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
2153 #define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
2154 #define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
2155 #define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
2156 #define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
2157 #define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
2158 #define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
2159 #define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
2160 #define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
2161 #define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
2162 #define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
2163 #define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
2164 #define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
2165 #define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
2166 #define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
2167 #define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
2168 #define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
2169 #define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
2170 #define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
2171 #define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
2172 #define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
2173 #define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
2174 #define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
2175 #define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
2176 #define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
2177 #define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
2178 #define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
2179 #define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
2180 #define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
2181 #define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
2182 #define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
2183 #define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
2184 #define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
2185 #define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
2186 #define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
2187 #define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
2188 #define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
2189 #define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
2190 #define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
2191 #define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
2192 #define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
2193 #define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
2194 #define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
2195 #define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
2196 #define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
2197 #define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
2198 #define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
2199 #define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
2200 #define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
2201 #define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
2202 #define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
2203 #define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
2204 #define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
2205 #define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
2206 #define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
2207 #define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
2208 #define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
2209 #define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
2210 #define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
2211 #define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
2212 #define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
2213 #define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
2214 #define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
2215 #define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
2216 #define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
2217 #define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
2218 #define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
2219 #define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
2220 #define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
2221 #define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
2222 #define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
2223 #define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
2224 #define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
2225 #define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
2226 #define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
2227 #define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
2228 #define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
2229 #define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
2230 #define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
2231 #define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
2232 #define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
2233 #define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
2234 #define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
2235 #define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
2236 #define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
2237 #define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
2238 #define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
2239 #define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
2240 #define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
2241 #define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
2242 #define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
2243 #define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
2244 #define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
2245 #define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
2246 #define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
2247 #define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
2248 #define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
2249 #define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
2250 #define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
2251 #define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
2252 #define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
2253 #define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
2254 #define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
2255 #define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
2256 #define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
2257 #define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
2258 #define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
2259 #define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
2260 #define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
2261 #define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
2262 #define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
2263 #define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
2264 #define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
2265 #define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
2266 #define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
2267 #define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
2268 #define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
2269 #define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
2270 #define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
2271 #define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
2272 #define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
2273 #define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
2274 #define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
2275 #define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
2276 #define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
2277 #define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
2278 #define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
2279 #define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
2280 #define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
2281 #define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
2282 #define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
2283 #define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
2284 #define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
2286 /* DMA - Register array accessors */
2287 #define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
2288 #define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
2289 #define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
2290 #define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
2291 #define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
2292 #define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
2293 #define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
2294 #define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
2295 #define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
2296 #define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
2297 #define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
2298 #define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
2299 #define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
2300 #define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
2301 #define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
2305 */ /* end of group DMA_Register_Accessor_Macros */
2310 */ /* end of group DMA_Peripheral_Access_Layer */
2313 /* ----------------------------------------------------------------------------
2314 -- DMAMUX Peripheral Access Layer
2315 ---------------------------------------------------------------------------- */
2318 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
2322 /** DMAMUX - Register Layout Typedef */
2324 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
2325 } DMAMUX_Type, *DMAMUX_MemMapPtr;
2327 /* ----------------------------------------------------------------------------
2328 -- DMAMUX - Register accessor macros
2329 ---------------------------------------------------------------------------- */
2332 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
2337 /* DMAMUX - Register accessors */
2338 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
2342 */ /* end of group DMAMUX_Register_Accessor_Macros */
2345 /* ----------------------------------------------------------------------------
2346 -- DMAMUX Register Masks
2347 ---------------------------------------------------------------------------- */
2350 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
2354 /* CHCFG Bit Fields */
2355 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
2356 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
2357 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
2358 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
2359 #define DMAMUX_CHCFG_TRIG_SHIFT 6
2360 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
2361 #define DMAMUX_CHCFG_ENBL_SHIFT 7
2365 */ /* end of group DMAMUX_Register_Masks */
2368 /* DMAMUX - Peripheral instance base addresses */
2369 /** Peripheral DMAMUX base address */
2370 #define DMAMUX_BASE (0x40021000u)
2371 /** Peripheral DMAMUX base pointer */
2372 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
2373 #define DMAMUX_BASE_PTR (DMAMUX)
2374 /** Array initializer of DMAMUX peripheral base addresses */
2375 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
2376 /** Array initializer of DMAMUX peripheral base pointers */
2377 #define DMAMUX_BASE_PTRS { DMAMUX }
2379 /* ----------------------------------------------------------------------------
2380 -- DMAMUX - Register accessor macros
2381 ---------------------------------------------------------------------------- */
2384 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
2389 /* DMAMUX - Register instance definitions */
2391 #define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
2392 #define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
2393 #define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
2394 #define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
2395 #define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
2396 #define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
2397 #define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
2398 #define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
2399 #define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
2400 #define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
2401 #define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
2402 #define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
2403 #define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
2404 #define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
2405 #define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
2406 #define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
2408 /* DMAMUX - Register array accessors */
2409 #define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
2413 */ /* end of group DMAMUX_Register_Accessor_Macros */
2418 */ /* end of group DMAMUX_Peripheral_Access_Layer */
2421 /* ----------------------------------------------------------------------------
2422 -- EWM Peripheral Access Layer
2423 ---------------------------------------------------------------------------- */
2426 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
2430 /** EWM - Register Layout Typedef */
2432 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
2433 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
2434 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
2435 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
2436 uint8_t RESERVED_0[1];
2437 __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
2438 } EWM_Type, *EWM_MemMapPtr;
2440 /* ----------------------------------------------------------------------------
2441 -- EWM - Register accessor macros
2442 ---------------------------------------------------------------------------- */
2445 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
2450 /* EWM - Register accessors */
2451 #define EWM_CTRL_REG(base) ((base)->CTRL)
2452 #define EWM_SERV_REG(base) ((base)->SERV)
2453 #define EWM_CMPL_REG(base) ((base)->CMPL)
2454 #define EWM_CMPH_REG(base) ((base)->CMPH)
2455 #define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER)
2459 */ /* end of group EWM_Register_Accessor_Macros */
2462 /* ----------------------------------------------------------------------------
2463 -- EWM Register Masks
2464 ---------------------------------------------------------------------------- */
2467 * @addtogroup EWM_Register_Masks EWM Register Masks
2471 /* CTRL Bit Fields */
2472 #define EWM_CTRL_EWMEN_MASK 0x1u
2473 #define EWM_CTRL_EWMEN_SHIFT 0
2474 #define EWM_CTRL_ASSIN_MASK 0x2u
2475 #define EWM_CTRL_ASSIN_SHIFT 1
2476 #define EWM_CTRL_INEN_MASK 0x4u
2477 #define EWM_CTRL_INEN_SHIFT 2
2478 #define EWM_CTRL_INTEN_MASK 0x8u
2479 #define EWM_CTRL_INTEN_SHIFT 3
2480 /* SERV Bit Fields */
2481 #define EWM_SERV_SERVICE_MASK 0xFFu
2482 #define EWM_SERV_SERVICE_SHIFT 0
2483 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
2484 /* CMPL Bit Fields */
2485 #define EWM_CMPL_COMPAREL_MASK 0xFFu
2486 #define EWM_CMPL_COMPAREL_SHIFT 0
2487 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
2488 /* CMPH Bit Fields */
2489 #define EWM_CMPH_COMPAREH_MASK 0xFFu
2490 #define EWM_CMPH_COMPAREH_SHIFT 0
2491 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
2492 /* CLKPRESCALER Bit Fields */
2493 #define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFu
2494 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT 0
2495 #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
2499 */ /* end of group EWM_Register_Masks */
2502 /* EWM - Peripheral instance base addresses */
2503 /** Peripheral EWM base address */
2504 #define EWM_BASE (0x40061000u)
2505 /** Peripheral EWM base pointer */
2506 #define EWM ((EWM_Type *)EWM_BASE)
2507 #define EWM_BASE_PTR (EWM)
2508 /** Array initializer of EWM peripheral base addresses */
2509 #define EWM_BASE_ADDRS { EWM_BASE }
2510 /** Array initializer of EWM peripheral base pointers */
2511 #define EWM_BASE_PTRS { EWM }
2512 /** Interrupt vectors for the EWM peripheral type */
2513 #define EWM_IRQS { Watchdog_IRQn }
2515 /* ----------------------------------------------------------------------------
2516 -- EWM - Register accessor macros
2517 ---------------------------------------------------------------------------- */
2520 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
2525 /* EWM - Register instance definitions */
2527 #define EWM_CTRL EWM_CTRL_REG(EWM)
2528 #define EWM_SERV EWM_SERV_REG(EWM)
2529 #define EWM_CMPL EWM_CMPL_REG(EWM)
2530 #define EWM_CMPH EWM_CMPH_REG(EWM)
2531 #define EWM_CLKPRESCALER EWM_CLKPRESCALER_REG(EWM)
2535 */ /* end of group EWM_Register_Accessor_Macros */
2540 */ /* end of group EWM_Peripheral_Access_Layer */
2543 /* ----------------------------------------------------------------------------
2544 -- FB Peripheral Access Layer
2545 ---------------------------------------------------------------------------- */
2548 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
2552 /** FB - Register Layout Typedef */
2554 struct { /* offset: 0x0, array step: 0xC */
2555 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
2556 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
2557 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
2559 uint8_t RESERVED_0[24];
2560 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
2561 } FB_Type, *FB_MemMapPtr;
2563 /* ----------------------------------------------------------------------------
2564 -- FB - Register accessor macros
2565 ---------------------------------------------------------------------------- */
2568 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
2573 /* FB - Register accessors */
2574 #define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
2575 #define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
2576 #define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
2577 #define FB_CSPMCR_REG(base) ((base)->CSPMCR)
2581 */ /* end of group FB_Register_Accessor_Macros */
2584 /* ----------------------------------------------------------------------------
2585 -- FB Register Masks
2586 ---------------------------------------------------------------------------- */
2589 * @addtogroup FB_Register_Masks FB Register Masks
2593 /* CSAR Bit Fields */
2594 #define FB_CSAR_BA_MASK 0xFFFF0000u
2595 #define FB_CSAR_BA_SHIFT 16
2596 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
2597 /* CSMR Bit Fields */
2598 #define FB_CSMR_V_MASK 0x1u
2599 #define FB_CSMR_V_SHIFT 0
2600 #define FB_CSMR_WP_MASK 0x100u
2601 #define FB_CSMR_WP_SHIFT 8
2602 #define FB_CSMR_BAM_MASK 0xFFFF0000u
2603 #define FB_CSMR_BAM_SHIFT 16
2604 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
2605 /* CSCR Bit Fields */
2606 #define FB_CSCR_BSTW_MASK 0x8u
2607 #define FB_CSCR_BSTW_SHIFT 3
2608 #define FB_CSCR_BSTR_MASK 0x10u
2609 #define FB_CSCR_BSTR_SHIFT 4
2610 #define FB_CSCR_BEM_MASK 0x20u
2611 #define FB_CSCR_BEM_SHIFT 5
2612 #define FB_CSCR_PS_MASK 0xC0u
2613 #define FB_CSCR_PS_SHIFT 6
2614 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
2615 #define FB_CSCR_AA_MASK 0x100u
2616 #define FB_CSCR_AA_SHIFT 8
2617 #define FB_CSCR_BLS_MASK 0x200u
2618 #define FB_CSCR_BLS_SHIFT 9
2619 #define FB_CSCR_WS_MASK 0xFC00u
2620 #define FB_CSCR_WS_SHIFT 10
2621 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
2622 #define FB_CSCR_WRAH_MASK 0x30000u
2623 #define FB_CSCR_WRAH_SHIFT 16
2624 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
2625 #define FB_CSCR_RDAH_MASK 0xC0000u
2626 #define FB_CSCR_RDAH_SHIFT 18
2627 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
2628 #define FB_CSCR_ASET_MASK 0x300000u
2629 #define FB_CSCR_ASET_SHIFT 20
2630 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
2631 #define FB_CSCR_EXTS_MASK 0x400000u
2632 #define FB_CSCR_EXTS_SHIFT 22
2633 #define FB_CSCR_SWSEN_MASK 0x800000u
2634 #define FB_CSCR_SWSEN_SHIFT 23
2635 #define FB_CSCR_SWS_MASK 0xFC000000u
2636 #define FB_CSCR_SWS_SHIFT 26
2637 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
2638 /* CSPMCR Bit Fields */
2639 #define FB_CSPMCR_GROUP5_MASK 0xF000u
2640 #define FB_CSPMCR_GROUP5_SHIFT 12
2641 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
2642 #define FB_CSPMCR_GROUP4_MASK 0xF0000u
2643 #define FB_CSPMCR_GROUP4_SHIFT 16
2644 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
2645 #define FB_CSPMCR_GROUP3_MASK 0xF00000u
2646 #define FB_CSPMCR_GROUP3_SHIFT 20
2647 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
2648 #define FB_CSPMCR_GROUP2_MASK 0xF000000u
2649 #define FB_CSPMCR_GROUP2_SHIFT 24
2650 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
2651 #define FB_CSPMCR_GROUP1_MASK 0xF0000000u
2652 #define FB_CSPMCR_GROUP1_SHIFT 28
2653 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
2657 */ /* end of group FB_Register_Masks */
2660 /* FB - Peripheral instance base addresses */
2661 /** Peripheral FB base address */
2662 #define FB_BASE (0x4000C000u)
2663 /** Peripheral FB base pointer */
2664 #define FB ((FB_Type *)FB_BASE)
2665 #define FB_BASE_PTR (FB)
2666 /** Array initializer of FB peripheral base addresses */
2667 #define FB_BASE_ADDRS { FB_BASE }
2668 /** Array initializer of FB peripheral base pointers */
2669 #define FB_BASE_PTRS { FB }
2671 /* ----------------------------------------------------------------------------
2672 -- FB - Register accessor macros
2673 ---------------------------------------------------------------------------- */
2676 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
2681 /* FB - Register instance definitions */
2683 #define FB_CSAR0 FB_CSAR_REG(FB,0)
2684 #define FB_CSMR0 FB_CSMR_REG(FB,0)
2685 #define FB_CSCR0 FB_CSCR_REG(FB,0)
2686 #define FB_CSAR1 FB_CSAR_REG(FB,1)
2687 #define FB_CSMR1 FB_CSMR_REG(FB,1)
2688 #define FB_CSCR1 FB_CSCR_REG(FB,1)
2689 #define FB_CSAR2 FB_CSAR_REG(FB,2)
2690 #define FB_CSMR2 FB_CSMR_REG(FB,2)
2691 #define FB_CSCR2 FB_CSCR_REG(FB,2)
2692 #define FB_CSAR3 FB_CSAR_REG(FB,3)
2693 #define FB_CSMR3 FB_CSMR_REG(FB,3)
2694 #define FB_CSCR3 FB_CSCR_REG(FB,3)
2695 #define FB_CSAR4 FB_CSAR_REG(FB,4)
2696 #define FB_CSMR4 FB_CSMR_REG(FB,4)
2697 #define FB_CSCR4 FB_CSCR_REG(FB,4)
2698 #define FB_CSAR5 FB_CSAR_REG(FB,5)
2699 #define FB_CSMR5 FB_CSMR_REG(FB,5)
2700 #define FB_CSCR5 FB_CSCR_REG(FB,5)
2701 #define FB_CSPMCR FB_CSPMCR_REG(FB)
2703 /* FB - Register array accessors */
2704 #define FB_CSAR(index) FB_CSAR_REG(FB,index)
2705 #define FB_CSMR(index) FB_CSMR_REG(FB,index)
2706 #define FB_CSCR(index) FB_CSCR_REG(FB,index)
2710 */ /* end of group FB_Register_Accessor_Macros */
2715 */ /* end of group FB_Peripheral_Access_Layer */
2718 /* ----------------------------------------------------------------------------
2719 -- FMC Peripheral Access Layer
2720 ---------------------------------------------------------------------------- */
2723 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
2727 /** FMC - Register Layout Typedef */
2729 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
2730 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
2731 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
2732 uint8_t RESERVED_0[244];
2733 __IO uint32_t TAGVDW0S[8]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
2734 __IO uint32_t TAGVDW1S[8]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
2735 __IO uint32_t TAGVDW2S[8]; /**< Cache Tag Storage, array offset: 0x140, array step: 0x4 */
2736 __IO uint32_t TAGVDW3S[8]; /**< Cache Tag Storage, array offset: 0x160, array step: 0x4 */
2737 uint8_t RESERVED_1[128];
2738 struct { /* offset: 0x200, array step: index*0x40, index2*0x8 */
2739 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
2740 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
2742 } FMC_Type, *FMC_MemMapPtr;
2744 /* ----------------------------------------------------------------------------
2745 -- FMC - Register accessor macros
2746 ---------------------------------------------------------------------------- */
2749 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
2754 /* FMC - Register accessors */
2755 #define FMC_PFAPR_REG(base) ((base)->PFAPR)
2756 #define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
2757 #define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
2758 #define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
2759 #define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
2760 #define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
2761 #define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
2762 #define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
2763 #define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
2767 */ /* end of group FMC_Register_Accessor_Macros */
2770 /* ----------------------------------------------------------------------------
2771 -- FMC Register Masks
2772 ---------------------------------------------------------------------------- */
2775 * @addtogroup FMC_Register_Masks FMC Register Masks
2779 /* PFAPR Bit Fields */
2780 #define FMC_PFAPR_M0AP_MASK 0x3u
2781 #define FMC_PFAPR_M0AP_SHIFT 0
2782 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
2783 #define FMC_PFAPR_M1AP_MASK 0xCu
2784 #define FMC_PFAPR_M1AP_SHIFT 2
2785 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
2786 #define FMC_PFAPR_M2AP_MASK 0x30u
2787 #define FMC_PFAPR_M2AP_SHIFT 4
2788 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
2789 #define FMC_PFAPR_M3AP_MASK 0xC0u
2790 #define FMC_PFAPR_M3AP_SHIFT 6
2791 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
2792 #define FMC_PFAPR_M4AP_MASK 0x300u
2793 #define FMC_PFAPR_M4AP_SHIFT 8
2794 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
2795 #define FMC_PFAPR_M5AP_MASK 0xC00u
2796 #define FMC_PFAPR_M5AP_SHIFT 10
2797 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
2798 #define FMC_PFAPR_M6AP_MASK 0x3000u
2799 #define FMC_PFAPR_M6AP_SHIFT 12
2800 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
2801 #define FMC_PFAPR_M7AP_MASK 0xC000u
2802 #define FMC_PFAPR_M7AP_SHIFT 14
2803 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
2804 #define FMC_PFAPR_M0PFD_MASK 0x10000u
2805 #define FMC_PFAPR_M0PFD_SHIFT 16
2806 #define FMC_PFAPR_M1PFD_MASK 0x20000u
2807 #define FMC_PFAPR_M1PFD_SHIFT 17
2808 #define FMC_PFAPR_M2PFD_MASK 0x40000u
2809 #define FMC_PFAPR_M2PFD_SHIFT 18
2810 #define FMC_PFAPR_M3PFD_MASK 0x80000u
2811 #define FMC_PFAPR_M3PFD_SHIFT 19
2812 #define FMC_PFAPR_M4PFD_MASK 0x100000u
2813 #define FMC_PFAPR_M4PFD_SHIFT 20
2814 #define FMC_PFAPR_M5PFD_MASK 0x200000u
2815 #define FMC_PFAPR_M5PFD_SHIFT 21
2816 #define FMC_PFAPR_M6PFD_MASK 0x400000u
2817 #define FMC_PFAPR_M6PFD_SHIFT 22
2818 #define FMC_PFAPR_M7PFD_MASK 0x800000u
2819 #define FMC_PFAPR_M7PFD_SHIFT 23
2820 /* PFB0CR Bit Fields */
2821 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
2822 #define FMC_PFB0CR_B0SEBE_SHIFT 0
2823 #define FMC_PFB0CR_B0IPE_MASK 0x2u
2824 #define FMC_PFB0CR_B0IPE_SHIFT 1
2825 #define FMC_PFB0CR_B0DPE_MASK 0x4u
2826 #define FMC_PFB0CR_B0DPE_SHIFT 2
2827 #define FMC_PFB0CR_B0ICE_MASK 0x8u
2828 #define FMC_PFB0CR_B0ICE_SHIFT 3
2829 #define FMC_PFB0CR_B0DCE_MASK 0x10u
2830 #define FMC_PFB0CR_B0DCE_SHIFT 4
2831 #define FMC_PFB0CR_CRC_MASK 0xE0u
2832 #define FMC_PFB0CR_CRC_SHIFT 5
2833 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
2834 #define FMC_PFB0CR_B0MW_MASK 0x60000u
2835 #define FMC_PFB0CR_B0MW_SHIFT 17
2836 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
2837 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
2838 #define FMC_PFB0CR_S_B_INV_SHIFT 19
2839 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
2840 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
2841 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
2842 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
2843 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
2844 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
2845 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
2846 #define FMC_PFB0CR_B0RWSC_SHIFT 28
2847 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
2848 /* PFB1CR Bit Fields */
2849 #define FMC_PFB1CR_B1SEBE_MASK 0x1u
2850 #define FMC_PFB1CR_B1SEBE_SHIFT 0
2851 #define FMC_PFB1CR_B1IPE_MASK 0x2u
2852 #define FMC_PFB1CR_B1IPE_SHIFT 1
2853 #define FMC_PFB1CR_B1DPE_MASK 0x4u
2854 #define FMC_PFB1CR_B1DPE_SHIFT 2
2855 #define FMC_PFB1CR_B1ICE_MASK 0x8u
2856 #define FMC_PFB1CR_B1ICE_SHIFT 3
2857 #define FMC_PFB1CR_B1DCE_MASK 0x10u
2858 #define FMC_PFB1CR_B1DCE_SHIFT 4
2859 #define FMC_PFB1CR_B1MW_MASK 0x60000u
2860 #define FMC_PFB1CR_B1MW_SHIFT 17
2861 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
2862 #define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
2863 #define FMC_PFB1CR_B1RWSC_SHIFT 28
2864 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
2865 /* TAGVDW0S Bit Fields */
2866 #define FMC_TAGVDW0S_valid_MASK 0x1u
2867 #define FMC_TAGVDW0S_valid_SHIFT 0
2868 #define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
2869 #define FMC_TAGVDW0S_tag_SHIFT 5
2870 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
2871 /* TAGVDW1S Bit Fields */
2872 #define FMC_TAGVDW1S_valid_MASK 0x1u
2873 #define FMC_TAGVDW1S_valid_SHIFT 0
2874 #define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
2875 #define FMC_TAGVDW1S_tag_SHIFT 5
2876 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
2877 /* TAGVDW2S Bit Fields */
2878 #define FMC_TAGVDW2S_valid_MASK 0x1u
2879 #define FMC_TAGVDW2S_valid_SHIFT 0
2880 #define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
2881 #define FMC_TAGVDW2S_tag_SHIFT 5
2882 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
2883 /* TAGVDW3S Bit Fields */
2884 #define FMC_TAGVDW3S_valid_MASK 0x1u
2885 #define FMC_TAGVDW3S_valid_SHIFT 0
2886 #define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
2887 #define FMC_TAGVDW3S_tag_SHIFT 5
2888 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
2889 /* DATA_U Bit Fields */
2890 #define FMC_DATA_U_data_MASK 0xFFFFFFFFu
2891 #define FMC_DATA_U_data_SHIFT 0
2892 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
2893 /* DATA_L Bit Fields */
2894 #define FMC_DATA_L_data_MASK 0xFFFFFFFFu
2895 #define FMC_DATA_L_data_SHIFT 0
2896 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
2900 */ /* end of group FMC_Register_Masks */
2903 /* FMC - Peripheral instance base addresses */
2904 /** Peripheral FMC base address */
2905 #define FMC_BASE (0x4001F000u)
2906 /** Peripheral FMC base pointer */
2907 #define FMC ((FMC_Type *)FMC_BASE)
2908 #define FMC_BASE_PTR (FMC)
2909 /** Array initializer of FMC peripheral base addresses */
2910 #define FMC_BASE_ADDRS { FMC_BASE }
2911 /** Array initializer of FMC peripheral base pointers */
2912 #define FMC_BASE_PTRS { FMC }
2914 /* ----------------------------------------------------------------------------
2915 -- FMC - Register accessor macros
2916 ---------------------------------------------------------------------------- */
2919 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
2924 /* FMC - Register instance definitions */
2926 #define FMC_PFAPR FMC_PFAPR_REG(FMC)
2927 #define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
2928 #define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
2929 #define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
2930 #define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
2931 #define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
2932 #define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
2933 #define FMC_TAGVDW0S4 FMC_TAGVDW0S_REG(FMC,4)
2934 #define FMC_TAGVDW0S5 FMC_TAGVDW0S_REG(FMC,5)
2935 #define FMC_TAGVDW0S6 FMC_TAGVDW0S_REG(FMC,6)
2936 #define FMC_TAGVDW0S7 FMC_TAGVDW0S_REG(FMC,7)
2937 #define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
2938 #define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
2939 #define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
2940 #define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
2941 #define FMC_TAGVDW1S4 FMC_TAGVDW1S_REG(FMC,4)
2942 #define FMC_TAGVDW1S5 FMC_TAGVDW1S_REG(FMC,5)
2943 #define FMC_TAGVDW1S6 FMC_TAGVDW1S_REG(FMC,6)
2944 #define FMC_TAGVDW1S7 FMC_TAGVDW1S_REG(FMC,7)
2945 #define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
2946 #define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
2947 #define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
2948 #define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
2949 #define FMC_TAGVDW2S4 FMC_TAGVDW2S_REG(FMC,4)
2950 #define FMC_TAGVDW2S5 FMC_TAGVDW2S_REG(FMC,5)
2951 #define FMC_TAGVDW2S6 FMC_TAGVDW2S_REG(FMC,6)
2952 #define FMC_TAGVDW2S7 FMC_TAGVDW2S_REG(FMC,7)
2953 #define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
2954 #define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
2955 #define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
2956 #define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
2957 #define FMC_TAGVDW3S4 FMC_TAGVDW3S_REG(FMC,4)
2958 #define FMC_TAGVDW3S5 FMC_TAGVDW3S_REG(FMC,5)
2959 #define FMC_TAGVDW3S6 FMC_TAGVDW3S_REG(FMC,6)
2960 #define FMC_TAGVDW3S7 FMC_TAGVDW3S_REG(FMC,7)
2961 #define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
2962 #define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
2963 #define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
2964 #define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
2965 #define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
2966 #define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
2967 #define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
2968 #define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
2969 #define FMC_DATAW0S4U FMC_DATA_U_REG(FMC,0,4)
2970 #define FMC_DATAW0S4L FMC_DATA_L_REG(FMC,0,4)
2971 #define FMC_DATAW0S5U FMC_DATA_U_REG(FMC,0,5)
2972 #define FMC_DATAW0S5L FMC_DATA_L_REG(FMC,0,5)
2973 #define FMC_DATAW0S6U FMC_DATA_U_REG(FMC,0,6)
2974 #define FMC_DATAW0S6L FMC_DATA_L_REG(FMC,0,6)
2975 #define FMC_DATAW0S7U FMC_DATA_U_REG(FMC,0,7)
2976 #define FMC_DATAW0S7L FMC_DATA_L_REG(FMC,0,7)
2977 #define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
2978 #define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
2979 #define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
2980 #define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
2981 #define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
2982 #define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
2983 #define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
2984 #define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
2985 #define FMC_DATAW1S4U FMC_DATA_U_REG(FMC,1,4)
2986 #define FMC_DATAW1S4L FMC_DATA_L_REG(FMC,1,4)
2987 #define FMC_DATAW1S5U FMC_DATA_U_REG(FMC,1,5)
2988 #define FMC_DATAW1S5L FMC_DATA_L_REG(FMC,1,5)
2989 #define FMC_DATAW1S6U FMC_DATA_U_REG(FMC,1,6)
2990 #define FMC_DATAW1S6L FMC_DATA_L_REG(FMC,1,6)
2991 #define FMC_DATAW1S7U FMC_DATA_U_REG(FMC,1,7)
2992 #define FMC_DATAW1S7L FMC_DATA_L_REG(FMC,1,7)
2993 #define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
2994 #define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
2995 #define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
2996 #define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
2997 #define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
2998 #define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
2999 #define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
3000 #define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
3001 #define FMC_DATAW2S4U FMC_DATA_U_REG(FMC,2,4)
3002 #define FMC_DATAW2S4L FMC_DATA_L_REG(FMC,2,4)
3003 #define FMC_DATAW2S5U FMC_DATA_U_REG(FMC,2,5)
3004 #define FMC_DATAW2S5L FMC_DATA_L_REG(FMC,2,5)
3005 #define FMC_DATAW2S6U FMC_DATA_U_REG(FMC,2,6)
3006 #define FMC_DATAW2S6L FMC_DATA_L_REG(FMC,2,6)
3007 #define FMC_DATAW2S7U FMC_DATA_U_REG(FMC,2,7)
3008 #define FMC_DATAW2S7L FMC_DATA_L_REG(FMC,2,7)
3009 #define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
3010 #define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
3011 #define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
3012 #define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
3013 #define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
3014 #define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
3015 #define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
3016 #define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
3017 #define FMC_DATAW3S4U FMC_DATA_U_REG(FMC,3,4)
3018 #define FMC_DATAW3S4L FMC_DATA_L_REG(FMC,3,4)
3019 #define FMC_DATAW3S5U FMC_DATA_U_REG(FMC,3,5)
3020 #define FMC_DATAW3S5L FMC_DATA_L_REG(FMC,3,5)
3021 #define FMC_DATAW3S6U FMC_DATA_U_REG(FMC,3,6)
3022 #define FMC_DATAW3S6L FMC_DATA_L_REG(FMC,3,6)
3023 #define FMC_DATAW3S7U FMC_DATA_U_REG(FMC,3,7)
3024 #define FMC_DATAW3S7L FMC_DATA_L_REG(FMC,3,7)
3026 /* FMC - Register array accessors */
3027 #define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
3028 #define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
3029 #define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
3030 #define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
3031 #define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
3032 #define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
3036 */ /* end of group FMC_Register_Accessor_Macros */
3041 */ /* end of group FMC_Peripheral_Access_Layer */
3044 /* ----------------------------------------------------------------------------
3045 -- FTFA Peripheral Access Layer
3046 ---------------------------------------------------------------------------- */
3049 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
3053 /** FTFA - Register Layout Typedef */
3055 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
3056 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
3057 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
3058 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
3059 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
3060 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
3061 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
3062 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
3063 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
3064 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
3065 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
3066 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
3067 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
3068 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
3069 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
3070 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
3071 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
3072 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
3073 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
3074 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
3075 uint8_t RESERVED_0[4];
3076 __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
3077 __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
3078 __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
3079 __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
3080 __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
3081 __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
3082 __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
3083 __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
3084 __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
3085 __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
3086 __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
3087 __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
3088 __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
3089 __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
3090 __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
3091 __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
3092 __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
3093 uint8_t RESERVED_1[2];
3094 __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
3095 } FTFA_Type, *FTFA_MemMapPtr;
3097 /* ----------------------------------------------------------------------------
3098 -- FTFA - Register accessor macros
3099 ---------------------------------------------------------------------------- */
3102 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
3107 /* FTFA - Register accessors */
3108 #define FTFA_FSTAT_REG(base) ((base)->FSTAT)
3109 #define FTFA_FCNFG_REG(base) ((base)->FCNFG)
3110 #define FTFA_FSEC_REG(base) ((base)->FSEC)
3111 #define FTFA_FOPT_REG(base) ((base)->FOPT)
3112 #define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
3113 #define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
3114 #define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
3115 #define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
3116 #define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
3117 #define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
3118 #define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
3119 #define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
3120 #define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
3121 #define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
3122 #define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
3123 #define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
3124 #define FTFA_FPROT3_REG(base) ((base)->FPROT3)
3125 #define FTFA_FPROT2_REG(base) ((base)->FPROT2)
3126 #define FTFA_FPROT1_REG(base) ((base)->FPROT1)
3127 #define FTFA_FPROT0_REG(base) ((base)->FPROT0)
3128 #define FTFA_XACCH3_REG(base) ((base)->XACCH3)
3129 #define FTFA_XACCH2_REG(base) ((base)->XACCH2)
3130 #define FTFA_XACCH1_REG(base) ((base)->XACCH1)
3131 #define FTFA_XACCH0_REG(base) ((base)->XACCH0)
3132 #define FTFA_XACCL3_REG(base) ((base)->XACCL3)
3133 #define FTFA_XACCL2_REG(base) ((base)->XACCL2)
3134 #define FTFA_XACCL1_REG(base) ((base)->XACCL1)
3135 #define FTFA_XACCL0_REG(base) ((base)->XACCL0)
3136 #define FTFA_SACCH3_REG(base) ((base)->SACCH3)
3137 #define FTFA_SACCH2_REG(base) ((base)->SACCH2)
3138 #define FTFA_SACCH1_REG(base) ((base)->SACCH1)
3139 #define FTFA_SACCH0_REG(base) ((base)->SACCH0)
3140 #define FTFA_SACCL3_REG(base) ((base)->SACCL3)
3141 #define FTFA_SACCL2_REG(base) ((base)->SACCL2)
3142 #define FTFA_SACCL1_REG(base) ((base)->SACCL1)
3143 #define FTFA_SACCL0_REG(base) ((base)->SACCL0)
3144 #define FTFA_FACSS_REG(base) ((base)->FACSS)
3145 #define FTFA_FACSN_REG(base) ((base)->FACSN)
3149 */ /* end of group FTFA_Register_Accessor_Macros */
3152 /* ----------------------------------------------------------------------------
3153 -- FTFA Register Masks
3154 ---------------------------------------------------------------------------- */
3157 * @addtogroup FTFA_Register_Masks FTFA Register Masks
3161 /* FSTAT Bit Fields */
3162 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
3163 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
3164 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
3165 #define FTFA_FSTAT_FPVIOL_SHIFT 4
3166 #define FTFA_FSTAT_ACCERR_MASK 0x20u
3167 #define FTFA_FSTAT_ACCERR_SHIFT 5
3168 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
3169 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
3170 #define FTFA_FSTAT_CCIF_MASK 0x80u
3171 #define FTFA_FSTAT_CCIF_SHIFT 7
3172 /* FCNFG Bit Fields */
3173 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
3174 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
3175 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
3176 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
3177 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
3178 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
3179 #define FTFA_FCNFG_CCIE_MASK 0x80u
3180 #define FTFA_FCNFG_CCIE_SHIFT 7
3181 /* FSEC Bit Fields */
3182 #define FTFA_FSEC_SEC_MASK 0x3u
3183 #define FTFA_FSEC_SEC_SHIFT 0
3184 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
3185 #define FTFA_FSEC_FSLACC_MASK 0xCu
3186 #define FTFA_FSEC_FSLACC_SHIFT 2
3187 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
3188 #define FTFA_FSEC_MEEN_MASK 0x30u
3189 #define FTFA_FSEC_MEEN_SHIFT 4
3190 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
3191 #define FTFA_FSEC_KEYEN_MASK 0xC0u
3192 #define FTFA_FSEC_KEYEN_SHIFT 6
3193 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
3194 /* FOPT Bit Fields */
3195 #define FTFA_FOPT_OPT_MASK 0xFFu
3196 #define FTFA_FOPT_OPT_SHIFT 0
3197 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
3198 /* FCCOB3 Bit Fields */
3199 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
3200 #define FTFA_FCCOB3_CCOBn_SHIFT 0
3201 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
3202 /* FCCOB2 Bit Fields */
3203 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
3204 #define FTFA_FCCOB2_CCOBn_SHIFT 0
3205 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
3206 /* FCCOB1 Bit Fields */
3207 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
3208 #define FTFA_FCCOB1_CCOBn_SHIFT 0
3209 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
3210 /* FCCOB0 Bit Fields */
3211 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
3212 #define FTFA_FCCOB0_CCOBn_SHIFT 0
3213 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
3214 /* FCCOB7 Bit Fields */
3215 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
3216 #define FTFA_FCCOB7_CCOBn_SHIFT 0
3217 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
3218 /* FCCOB6 Bit Fields */
3219 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
3220 #define FTFA_FCCOB6_CCOBn_SHIFT 0
3221 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
3222 /* FCCOB5 Bit Fields */
3223 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
3224 #define FTFA_FCCOB5_CCOBn_SHIFT 0
3225 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
3226 /* FCCOB4 Bit Fields */
3227 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
3228 #define FTFA_FCCOB4_CCOBn_SHIFT 0
3229 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
3230 /* FCCOBB Bit Fields */
3231 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
3232 #define FTFA_FCCOBB_CCOBn_SHIFT 0
3233 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
3234 /* FCCOBA Bit Fields */
3235 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
3236 #define FTFA_FCCOBA_CCOBn_SHIFT 0
3237 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
3238 /* FCCOB9 Bit Fields */
3239 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
3240 #define FTFA_FCCOB9_CCOBn_SHIFT 0
3241 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
3242 /* FCCOB8 Bit Fields */
3243 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
3244 #define FTFA_FCCOB8_CCOBn_SHIFT 0
3245 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
3246 /* FPROT3 Bit Fields */
3247 #define FTFA_FPROT3_PROT_MASK 0xFFu
3248 #define FTFA_FPROT3_PROT_SHIFT 0
3249 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
3250 /* FPROT2 Bit Fields */
3251 #define FTFA_FPROT2_PROT_MASK 0xFFu
3252 #define FTFA_FPROT2_PROT_SHIFT 0
3253 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
3254 /* FPROT1 Bit Fields */
3255 #define FTFA_FPROT1_PROT_MASK 0xFFu
3256 #define FTFA_FPROT1_PROT_SHIFT 0
3257 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
3258 /* FPROT0 Bit Fields */
3259 #define FTFA_FPROT0_PROT_MASK 0xFFu
3260 #define FTFA_FPROT0_PROT_SHIFT 0
3261 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
3262 /* XACCH3 Bit Fields */
3263 #define FTFA_XACCH3_XA_MASK 0xFFu
3264 #define FTFA_XACCH3_XA_SHIFT 0
3265 #define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH3_XA_SHIFT))&FTFA_XACCH3_XA_MASK)
3266 /* XACCH2 Bit Fields */
3267 #define FTFA_XACCH2_XA_MASK 0xFFu
3268 #define FTFA_XACCH2_XA_SHIFT 0
3269 #define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH2_XA_SHIFT))&FTFA_XACCH2_XA_MASK)
3270 /* XACCH1 Bit Fields */
3271 #define FTFA_XACCH1_XA_MASK 0xFFu
3272 #define FTFA_XACCH1_XA_SHIFT 0
3273 #define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH1_XA_SHIFT))&FTFA_XACCH1_XA_MASK)
3274 /* XACCH0 Bit Fields */
3275 #define FTFA_XACCH0_XA_MASK 0xFFu
3276 #define FTFA_XACCH0_XA_SHIFT 0
3277 #define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH0_XA_SHIFT))&FTFA_XACCH0_XA_MASK)
3278 /* XACCL3 Bit Fields */
3279 #define FTFA_XACCL3_XA_MASK 0xFFu
3280 #define FTFA_XACCL3_XA_SHIFT 0
3281 #define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL3_XA_SHIFT))&FTFA_XACCL3_XA_MASK)
3282 /* XACCL2 Bit Fields */
3283 #define FTFA_XACCL2_XA_MASK 0xFFu
3284 #define FTFA_XACCL2_XA_SHIFT 0
3285 #define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL2_XA_SHIFT))&FTFA_XACCL2_XA_MASK)
3286 /* XACCL1 Bit Fields */
3287 #define FTFA_XACCL1_XA_MASK 0xFFu
3288 #define FTFA_XACCL1_XA_SHIFT 0
3289 #define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL1_XA_SHIFT))&FTFA_XACCL1_XA_MASK)
3290 /* XACCL0 Bit Fields */
3291 #define FTFA_XACCL0_XA_MASK 0xFFu
3292 #define FTFA_XACCL0_XA_SHIFT 0
3293 #define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL0_XA_SHIFT))&FTFA_XACCL0_XA_MASK)
3294 /* SACCH3 Bit Fields */
3295 #define FTFA_SACCH3_SA_MASK 0xFFu
3296 #define FTFA_SACCH3_SA_SHIFT 0
3297 #define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH3_SA_SHIFT))&FTFA_SACCH3_SA_MASK)
3298 /* SACCH2 Bit Fields */
3299 #define FTFA_SACCH2_SA_MASK 0xFFu
3300 #define FTFA_SACCH2_SA_SHIFT 0
3301 #define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH2_SA_SHIFT))&FTFA_SACCH2_SA_MASK)
3302 /* SACCH1 Bit Fields */
3303 #define FTFA_SACCH1_SA_MASK 0xFFu
3304 #define FTFA_SACCH1_SA_SHIFT 0
3305 #define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH1_SA_SHIFT))&FTFA_SACCH1_SA_MASK)
3306 /* SACCH0 Bit Fields */
3307 #define FTFA_SACCH0_SA_MASK 0xFFu
3308 #define FTFA_SACCH0_SA_SHIFT 0
3309 #define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH0_SA_SHIFT))&FTFA_SACCH0_SA_MASK)
3310 /* SACCL3 Bit Fields */
3311 #define FTFA_SACCL3_SA_MASK 0xFFu
3312 #define FTFA_SACCL3_SA_SHIFT 0
3313 #define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL3_SA_SHIFT))&FTFA_SACCL3_SA_MASK)
3314 /* SACCL2 Bit Fields */
3315 #define FTFA_SACCL2_SA_MASK 0xFFu
3316 #define FTFA_SACCL2_SA_SHIFT 0
3317 #define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL2_SA_SHIFT))&FTFA_SACCL2_SA_MASK)
3318 /* SACCL1 Bit Fields */
3319 #define FTFA_SACCL1_SA_MASK 0xFFu
3320 #define FTFA_SACCL1_SA_SHIFT 0
3321 #define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL1_SA_SHIFT))&FTFA_SACCL1_SA_MASK)
3322 /* SACCL0 Bit Fields */
3323 #define FTFA_SACCL0_SA_MASK 0xFFu
3324 #define FTFA_SACCL0_SA_SHIFT 0
3325 #define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL0_SA_SHIFT))&FTFA_SACCL0_SA_MASK)
3326 /* FACSS Bit Fields */
3327 #define FTFA_FACSS_SGSIZE_MASK 0xFFu
3328 #define FTFA_FACSS_SGSIZE_SHIFT 0
3329 #define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSS_SGSIZE_SHIFT))&FTFA_FACSS_SGSIZE_MASK)
3330 /* FACSN Bit Fields */
3331 #define FTFA_FACSN_NUMSG_MASK 0xFFu
3332 #define FTFA_FACSN_NUMSG_SHIFT 0
3333 #define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSN_NUMSG_SHIFT))&FTFA_FACSN_NUMSG_MASK)
3337 */ /* end of group FTFA_Register_Masks */
3340 /* FTFA - Peripheral instance base addresses */
3341 /** Peripheral FTFA base address */
3342 #define FTFA_BASE (0x40020000u)
3343 /** Peripheral FTFA base pointer */
3344 #define FTFA ((FTFA_Type *)FTFA_BASE)
3345 #define FTFA_BASE_PTR (FTFA)
3346 /** Array initializer of FTFA peripheral base addresses */
3347 #define FTFA_BASE_ADDRS { FTFA_BASE }
3348 /** Array initializer of FTFA peripheral base pointers */
3349 #define FTFA_BASE_PTRS { FTFA }
3350 /** Interrupt vectors for the FTFA peripheral type */
3351 #define FTFA_COMMAND_COMPLETE_IRQS { FTF_IRQn }
3352 #define FTFA_READ_COLLISION_IRQS { Read_Collision_IRQn }
3354 /* ----------------------------------------------------------------------------
3355 -- FTFA - Register accessor macros
3356 ---------------------------------------------------------------------------- */
3359 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
3364 /* FTFA - Register instance definitions */
3366 #define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
3367 #define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
3368 #define FTFA_FSEC FTFA_FSEC_REG(FTFA)
3369 #define FTFA_FOPT FTFA_FOPT_REG(FTFA)
3370 #define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
3371 #define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
3372 #define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
3373 #define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
3374 #define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
3375 #define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
3376 #define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
3377 #define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
3378 #define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
3379 #define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
3380 #define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
3381 #define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
3382 #define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
3383 #define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
3384 #define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
3385 #define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
3386 #define FTFA_XACCH3 FTFA_XACCH3_REG(FTFA)
3387 #define FTFA_XACCH2 FTFA_XACCH2_REG(FTFA)
3388 #define FTFA_XACCH1 FTFA_XACCH1_REG(FTFA)
3389 #define FTFA_XACCH0 FTFA_XACCH0_REG(FTFA)
3390 #define FTFA_XACCL3 FTFA_XACCL3_REG(FTFA)
3391 #define FTFA_XACCL2 FTFA_XACCL2_REG(FTFA)
3392 #define FTFA_XACCL1 FTFA_XACCL1_REG(FTFA)
3393 #define FTFA_XACCL0 FTFA_XACCL0_REG(FTFA)
3394 #define FTFA_SACCH3 FTFA_SACCH3_REG(FTFA)
3395 #define FTFA_SACCH2 FTFA_SACCH2_REG(FTFA)
3396 #define FTFA_SACCH1 FTFA_SACCH1_REG(FTFA)
3397 #define FTFA_SACCH0 FTFA_SACCH0_REG(FTFA)
3398 #define FTFA_SACCL3 FTFA_SACCL3_REG(FTFA)
3399 #define FTFA_SACCL2 FTFA_SACCL2_REG(FTFA)
3400 #define FTFA_SACCL1 FTFA_SACCL1_REG(FTFA)
3401 #define FTFA_SACCL0 FTFA_SACCL0_REG(FTFA)
3402 #define FTFA_FACSS FTFA_FACSS_REG(FTFA)
3403 #define FTFA_FACSN FTFA_FACSN_REG(FTFA)
3407 */ /* end of group FTFA_Register_Accessor_Macros */
3412 */ /* end of group FTFA_Peripheral_Access_Layer */
3415 /* ----------------------------------------------------------------------------
3416 -- FTM Peripheral Access Layer
3417 ---------------------------------------------------------------------------- */
3420 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
3424 /** FTM - Register Layout Typedef */
3426 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
3427 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
3428 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
3429 struct { /* offset: 0xC, array step: 0x8 */
3430 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
3431 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
3433 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
3434 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
3435 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
3436 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
3437 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
3438 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
3439 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
3440 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
3441 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
3442 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
3443 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
3444 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
3445 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
3446 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
3447 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
3448 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
3449 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
3450 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
3451 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
3452 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
3453 } FTM_Type, *FTM_MemMapPtr;
3455 /* ----------------------------------------------------------------------------
3456 -- FTM - Register accessor macros
3457 ---------------------------------------------------------------------------- */
3460 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
3465 /* FTM - Register accessors */
3466 #define FTM_SC_REG(base) ((base)->SC)
3467 #define FTM_CNT_REG(base) ((base)->CNT)
3468 #define FTM_MOD_REG(base) ((base)->MOD)
3469 #define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
3470 #define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
3471 #define FTM_CNTIN_REG(base) ((base)->CNTIN)
3472 #define FTM_STATUS_REG(base) ((base)->STATUS)
3473 #define FTM_MODE_REG(base) ((base)->MODE)
3474 #define FTM_SYNC_REG(base) ((base)->SYNC)
3475 #define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
3476 #define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
3477 #define FTM_COMBINE_REG(base) ((base)->COMBINE)
3478 #define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
3479 #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
3480 #define FTM_POL_REG(base) ((base)->POL)
3481 #define FTM_FMS_REG(base) ((base)->FMS)
3482 #define FTM_FILTER_REG(base) ((base)->FILTER)
3483 #define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
3484 #define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
3485 #define FTM_CONF_REG(base) ((base)->CONF)
3486 #define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
3487 #define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
3488 #define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
3489 #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
3490 #define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
3494 */ /* end of group FTM_Register_Accessor_Macros */
3497 /* ----------------------------------------------------------------------------
3498 -- FTM Register Masks
3499 ---------------------------------------------------------------------------- */
3502 * @addtogroup FTM_Register_Masks FTM Register Masks
3507 #define FTM_SC_PS_MASK 0x7u
3508 #define FTM_SC_PS_SHIFT 0
3509 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
3510 #define FTM_SC_CLKS_MASK 0x18u
3511 #define FTM_SC_CLKS_SHIFT 3
3512 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
3513 #define FTM_SC_CPWMS_MASK 0x20u
3514 #define FTM_SC_CPWMS_SHIFT 5
3515 #define FTM_SC_TOIE_MASK 0x40u
3516 #define FTM_SC_TOIE_SHIFT 6
3517 #define FTM_SC_TOF_MASK 0x80u
3518 #define FTM_SC_TOF_SHIFT 7
3519 /* CNT Bit Fields */
3520 #define FTM_CNT_COUNT_MASK 0xFFFFu
3521 #define FTM_CNT_COUNT_SHIFT 0
3522 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
3523 /* MOD Bit Fields */
3524 #define FTM_MOD_MOD_MASK 0xFFFFu
3525 #define FTM_MOD_MOD_SHIFT 0
3526 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
3527 /* CnSC Bit Fields */
3528 #define FTM_CnSC_DMA_MASK 0x1u
3529 #define FTM_CnSC_DMA_SHIFT 0
3530 #define FTM_CnSC_ICRST_MASK 0x2u
3531 #define FTM_CnSC_ICRST_SHIFT 1
3532 #define FTM_CnSC_ELSA_MASK 0x4u
3533 #define FTM_CnSC_ELSA_SHIFT 2
3534 #define FTM_CnSC_ELSB_MASK 0x8u
3535 #define FTM_CnSC_ELSB_SHIFT 3
3536 #define FTM_CnSC_MSA_MASK 0x10u
3537 #define FTM_CnSC_MSA_SHIFT 4
3538 #define FTM_CnSC_MSB_MASK 0x20u
3539 #define FTM_CnSC_MSB_SHIFT 5
3540 #define FTM_CnSC_CHIE_MASK 0x40u
3541 #define FTM_CnSC_CHIE_SHIFT 6
3542 #define FTM_CnSC_CHF_MASK 0x80u
3543 #define FTM_CnSC_CHF_SHIFT 7
3544 /* CnV Bit Fields */
3545 #define FTM_CnV_VAL_MASK 0xFFFFu
3546 #define FTM_CnV_VAL_SHIFT 0
3547 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
3548 /* CNTIN Bit Fields */
3549 #define FTM_CNTIN_INIT_MASK 0xFFFFu
3550 #define FTM_CNTIN_INIT_SHIFT 0
3551 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
3552 /* STATUS Bit Fields */
3553 #define FTM_STATUS_CH0F_MASK 0x1u
3554 #define FTM_STATUS_CH0F_SHIFT 0
3555 #define FTM_STATUS_CH1F_MASK 0x2u
3556 #define FTM_STATUS_CH1F_SHIFT 1
3557 #define FTM_STATUS_CH2F_MASK 0x4u
3558 #define FTM_STATUS_CH2F_SHIFT 2
3559 #define FTM_STATUS_CH3F_MASK 0x8u
3560 #define FTM_STATUS_CH3F_SHIFT 3
3561 #define FTM_STATUS_CH4F_MASK 0x10u
3562 #define FTM_STATUS_CH4F_SHIFT 4
3563 #define FTM_STATUS_CH5F_MASK 0x20u
3564 #define FTM_STATUS_CH5F_SHIFT 5
3565 #define FTM_STATUS_CH6F_MASK 0x40u
3566 #define FTM_STATUS_CH6F_SHIFT 6
3567 #define FTM_STATUS_CH7F_MASK 0x80u
3568 #define FTM_STATUS_CH7F_SHIFT 7
3569 /* MODE Bit Fields */
3570 #define FTM_MODE_FTMEN_MASK 0x1u
3571 #define FTM_MODE_FTMEN_SHIFT 0
3572 #define FTM_MODE_INIT_MASK 0x2u
3573 #define FTM_MODE_INIT_SHIFT 1
3574 #define FTM_MODE_WPDIS_MASK 0x4u
3575 #define FTM_MODE_WPDIS_SHIFT 2
3576 #define FTM_MODE_PWMSYNC_MASK 0x8u
3577 #define FTM_MODE_PWMSYNC_SHIFT 3
3578 #define FTM_MODE_CAPTEST_MASK 0x10u
3579 #define FTM_MODE_CAPTEST_SHIFT 4
3580 #define FTM_MODE_FAULTM_MASK 0x60u
3581 #define FTM_MODE_FAULTM_SHIFT 5
3582 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
3583 #define FTM_MODE_FAULTIE_MASK 0x80u
3584 #define FTM_MODE_FAULTIE_SHIFT 7
3585 /* SYNC Bit Fields */
3586 #define FTM_SYNC_CNTMIN_MASK 0x1u
3587 #define FTM_SYNC_CNTMIN_SHIFT 0
3588 #define FTM_SYNC_CNTMAX_MASK 0x2u
3589 #define FTM_SYNC_CNTMAX_SHIFT 1
3590 #define FTM_SYNC_REINIT_MASK 0x4u
3591 #define FTM_SYNC_REINIT_SHIFT 2
3592 #define FTM_SYNC_SYNCHOM_MASK 0x8u
3593 #define FTM_SYNC_SYNCHOM_SHIFT 3
3594 #define FTM_SYNC_TRIG0_MASK 0x10u
3595 #define FTM_SYNC_TRIG0_SHIFT 4
3596 #define FTM_SYNC_TRIG1_MASK 0x20u
3597 #define FTM_SYNC_TRIG1_SHIFT 5
3598 #define FTM_SYNC_TRIG2_MASK 0x40u
3599 #define FTM_SYNC_TRIG2_SHIFT 6
3600 #define FTM_SYNC_SWSYNC_MASK 0x80u
3601 #define FTM_SYNC_SWSYNC_SHIFT 7
3602 /* OUTINIT Bit Fields */
3603 #define FTM_OUTINIT_CH0OI_MASK 0x1u
3604 #define FTM_OUTINIT_CH0OI_SHIFT 0
3605 #define FTM_OUTINIT_CH1OI_MASK 0x2u
3606 #define FTM_OUTINIT_CH1OI_SHIFT 1
3607 #define FTM_OUTINIT_CH2OI_MASK 0x4u
3608 #define FTM_OUTINIT_CH2OI_SHIFT 2
3609 #define FTM_OUTINIT_CH3OI_MASK 0x8u
3610 #define FTM_OUTINIT_CH3OI_SHIFT 3
3611 #define FTM_OUTINIT_CH4OI_MASK 0x10u
3612 #define FTM_OUTINIT_CH4OI_SHIFT 4
3613 #define FTM_OUTINIT_CH5OI_MASK 0x20u
3614 #define FTM_OUTINIT_CH5OI_SHIFT 5
3615 #define FTM_OUTINIT_CH6OI_MASK 0x40u
3616 #define FTM_OUTINIT_CH6OI_SHIFT 6
3617 #define FTM_OUTINIT_CH7OI_MASK 0x80u
3618 #define FTM_OUTINIT_CH7OI_SHIFT 7
3619 /* OUTMASK Bit Fields */
3620 #define FTM_OUTMASK_CH0OM_MASK 0x1u
3621 #define FTM_OUTMASK_CH0OM_SHIFT 0
3622 #define FTM_OUTMASK_CH1OM_MASK 0x2u
3623 #define FTM_OUTMASK_CH1OM_SHIFT 1
3624 #define FTM_OUTMASK_CH2OM_MASK 0x4u
3625 #define FTM_OUTMASK_CH2OM_SHIFT 2
3626 #define FTM_OUTMASK_CH3OM_MASK 0x8u
3627 #define FTM_OUTMASK_CH3OM_SHIFT 3
3628 #define FTM_OUTMASK_CH4OM_MASK 0x10u
3629 #define FTM_OUTMASK_CH4OM_SHIFT 4
3630 #define FTM_OUTMASK_CH5OM_MASK 0x20u
3631 #define FTM_OUTMASK_CH5OM_SHIFT 5
3632 #define FTM_OUTMASK_CH6OM_MASK 0x40u
3633 #define FTM_OUTMASK_CH6OM_SHIFT 6
3634 #define FTM_OUTMASK_CH7OM_MASK 0x80u
3635 #define FTM_OUTMASK_CH7OM_SHIFT 7
3636 /* COMBINE Bit Fields */
3637 #define FTM_COMBINE_COMBINE0_MASK 0x1u
3638 #define FTM_COMBINE_COMBINE0_SHIFT 0
3639 #define FTM_COMBINE_COMP0_MASK 0x2u
3640 #define FTM_COMBINE_COMP0_SHIFT 1
3641 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
3642 #define FTM_COMBINE_DECAPEN0_SHIFT 2
3643 #define FTM_COMBINE_DECAP0_MASK 0x8u
3644 #define FTM_COMBINE_DECAP0_SHIFT 3
3645 #define FTM_COMBINE_DTEN0_MASK 0x10u
3646 #define FTM_COMBINE_DTEN0_SHIFT 4
3647 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
3648 #define FTM_COMBINE_SYNCEN0_SHIFT 5
3649 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
3650 #define FTM_COMBINE_FAULTEN0_SHIFT 6
3651 #define FTM_COMBINE_COMBINE1_MASK 0x100u
3652 #define FTM_COMBINE_COMBINE1_SHIFT 8
3653 #define FTM_COMBINE_COMP1_MASK 0x200u
3654 #define FTM_COMBINE_COMP1_SHIFT 9
3655 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
3656 #define FTM_COMBINE_DECAPEN1_SHIFT 10
3657 #define FTM_COMBINE_DECAP1_MASK 0x800u
3658 #define FTM_COMBINE_DECAP1_SHIFT 11
3659 #define FTM_COMBINE_DTEN1_MASK 0x1000u
3660 #define FTM_COMBINE_DTEN1_SHIFT 12
3661 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
3662 #define FTM_COMBINE_SYNCEN1_SHIFT 13
3663 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
3664 #define FTM_COMBINE_FAULTEN1_SHIFT 14
3665 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
3666 #define FTM_COMBINE_COMBINE2_SHIFT 16
3667 #define FTM_COMBINE_COMP2_MASK 0x20000u
3668 #define FTM_COMBINE_COMP2_SHIFT 17
3669 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
3670 #define FTM_COMBINE_DECAPEN2_SHIFT 18
3671 #define FTM_COMBINE_DECAP2_MASK 0x80000u
3672 #define FTM_COMBINE_DECAP2_SHIFT 19
3673 #define FTM_COMBINE_DTEN2_MASK 0x100000u
3674 #define FTM_COMBINE_DTEN2_SHIFT 20
3675 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
3676 #define FTM_COMBINE_SYNCEN2_SHIFT 21
3677 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
3678 #define FTM_COMBINE_FAULTEN2_SHIFT 22
3679 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
3680 #define FTM_COMBINE_COMBINE3_SHIFT 24
3681 #define FTM_COMBINE_COMP3_MASK 0x2000000u
3682 #define FTM_COMBINE_COMP3_SHIFT 25
3683 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
3684 #define FTM_COMBINE_DECAPEN3_SHIFT 26
3685 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
3686 #define FTM_COMBINE_DECAP3_SHIFT 27
3687 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
3688 #define FTM_COMBINE_DTEN3_SHIFT 28
3689 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
3690 #define FTM_COMBINE_SYNCEN3_SHIFT 29
3691 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
3692 #define FTM_COMBINE_FAULTEN3_SHIFT 30
3693 /* DEADTIME Bit Fields */
3694 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
3695 #define FTM_DEADTIME_DTVAL_SHIFT 0
3696 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
3697 #define FTM_DEADTIME_DTPS_MASK 0xC0u
3698 #define FTM_DEADTIME_DTPS_SHIFT 6
3699 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
3700 /* EXTTRIG Bit Fields */
3701 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
3702 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
3703 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
3704 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
3705 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
3706 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
3707 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
3708 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
3709 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
3710 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
3711 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
3712 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
3713 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
3714 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
3715 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
3716 #define FTM_EXTTRIG_TRIGF_SHIFT 7
3717 /* POL Bit Fields */
3718 #define FTM_POL_POL0_MASK 0x1u
3719 #define FTM_POL_POL0_SHIFT 0
3720 #define FTM_POL_POL1_MASK 0x2u
3721 #define FTM_POL_POL1_SHIFT 1
3722 #define FTM_POL_POL2_MASK 0x4u
3723 #define FTM_POL_POL2_SHIFT 2
3724 #define FTM_POL_POL3_MASK 0x8u
3725 #define FTM_POL_POL3_SHIFT 3
3726 #define FTM_POL_POL4_MASK 0x10u
3727 #define FTM_POL_POL4_SHIFT 4
3728 #define FTM_POL_POL5_MASK 0x20u
3729 #define FTM_POL_POL5_SHIFT 5
3730 #define FTM_POL_POL6_MASK 0x40u
3731 #define FTM_POL_POL6_SHIFT 6
3732 #define FTM_POL_POL7_MASK 0x80u
3733 #define FTM_POL_POL7_SHIFT 7
3734 /* FMS Bit Fields */
3735 #define FTM_FMS_FAULTF0_MASK 0x1u
3736 #define FTM_FMS_FAULTF0_SHIFT 0
3737 #define FTM_FMS_FAULTF1_MASK 0x2u
3738 #define FTM_FMS_FAULTF1_SHIFT 1
3739 #define FTM_FMS_FAULTF2_MASK 0x4u
3740 #define FTM_FMS_FAULTF2_SHIFT 2
3741 #define FTM_FMS_FAULTF3_MASK 0x8u
3742 #define FTM_FMS_FAULTF3_SHIFT 3
3743 #define FTM_FMS_FAULTIN_MASK 0x20u
3744 #define FTM_FMS_FAULTIN_SHIFT 5
3745 #define FTM_FMS_WPEN_MASK 0x40u
3746 #define FTM_FMS_WPEN_SHIFT 6
3747 #define FTM_FMS_FAULTF_MASK 0x80u
3748 #define FTM_FMS_FAULTF_SHIFT 7
3749 /* FILTER Bit Fields */
3750 #define FTM_FILTER_CH0FVAL_MASK 0xFu
3751 #define FTM_FILTER_CH0FVAL_SHIFT 0
3752 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
3753 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
3754 #define FTM_FILTER_CH1FVAL_SHIFT 4
3755 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
3756 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
3757 #define FTM_FILTER_CH2FVAL_SHIFT 8
3758 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
3759 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
3760 #define FTM_FILTER_CH3FVAL_SHIFT 12
3761 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
3762 /* FLTCTRL Bit Fields */
3763 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
3764 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
3765 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
3766 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
3767 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
3768 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
3769 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
3770 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
3771 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
3772 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
3773 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
3774 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
3775 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
3776 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
3777 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
3778 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
3779 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
3780 #define FTM_FLTCTRL_FFVAL_SHIFT 8
3781 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
3782 /* QDCTRL Bit Fields */
3783 #define FTM_QDCTRL_QUADEN_MASK 0x1u
3784 #define FTM_QDCTRL_QUADEN_SHIFT 0
3785 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
3786 #define FTM_QDCTRL_TOFDIR_SHIFT 1
3787 #define FTM_QDCTRL_QUADIR_MASK 0x4u
3788 #define FTM_QDCTRL_QUADIR_SHIFT 2
3789 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
3790 #define FTM_QDCTRL_QUADMODE_SHIFT 3
3791 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
3792 #define FTM_QDCTRL_PHBPOL_SHIFT 4
3793 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
3794 #define FTM_QDCTRL_PHAPOL_SHIFT 5
3795 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
3796 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
3797 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
3798 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
3799 /* CONF Bit Fields */
3800 #define FTM_CONF_NUMTOF_MASK 0x1Fu
3801 #define FTM_CONF_NUMTOF_SHIFT 0
3802 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
3803 #define FTM_CONF_BDMMODE_MASK 0xC0u
3804 #define FTM_CONF_BDMMODE_SHIFT 6
3805 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
3806 #define FTM_CONF_GTBEEN_MASK 0x200u
3807 #define FTM_CONF_GTBEEN_SHIFT 9
3808 #define FTM_CONF_GTBEOUT_MASK 0x400u
3809 #define FTM_CONF_GTBEOUT_SHIFT 10
3810 /* FLTPOL Bit Fields */
3811 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
3812 #define FTM_FLTPOL_FLT0POL_SHIFT 0
3813 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
3814 #define FTM_FLTPOL_FLT1POL_SHIFT 1
3815 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
3816 #define FTM_FLTPOL_FLT2POL_SHIFT 2
3817 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
3818 #define FTM_FLTPOL_FLT3POL_SHIFT 3
3819 /* SYNCONF Bit Fields */
3820 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
3821 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
3822 #define FTM_SYNCONF_CNTINC_MASK 0x4u
3823 #define FTM_SYNCONF_CNTINC_SHIFT 2
3824 #define FTM_SYNCONF_INVC_MASK 0x10u
3825 #define FTM_SYNCONF_INVC_SHIFT 4
3826 #define FTM_SYNCONF_SWOC_MASK 0x20u
3827 #define FTM_SYNCONF_SWOC_SHIFT 5
3828 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
3829 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
3830 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
3831 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
3832 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
3833 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
3834 #define FTM_SYNCONF_SWOM_MASK 0x400u
3835 #define FTM_SYNCONF_SWOM_SHIFT 10
3836 #define FTM_SYNCONF_SWINVC_MASK 0x800u
3837 #define FTM_SYNCONF_SWINVC_SHIFT 11
3838 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
3839 #define FTM_SYNCONF_SWSOC_SHIFT 12
3840 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
3841 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
3842 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
3843 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
3844 #define FTM_SYNCONF_HWOM_MASK 0x40000u
3845 #define FTM_SYNCONF_HWOM_SHIFT 18
3846 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
3847 #define FTM_SYNCONF_HWINVC_SHIFT 19
3848 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
3849 #define FTM_SYNCONF_HWSOC_SHIFT 20
3850 /* INVCTRL Bit Fields */
3851 #define FTM_INVCTRL_INV0EN_MASK 0x1u
3852 #define FTM_INVCTRL_INV0EN_SHIFT 0
3853 #define FTM_INVCTRL_INV1EN_MASK 0x2u
3854 #define FTM_INVCTRL_INV1EN_SHIFT 1
3855 #define FTM_INVCTRL_INV2EN_MASK 0x4u
3856 #define FTM_INVCTRL_INV2EN_SHIFT 2
3857 #define FTM_INVCTRL_INV3EN_MASK 0x8u
3858 #define FTM_INVCTRL_INV3EN_SHIFT 3
3859 /* SWOCTRL Bit Fields */
3860 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
3861 #define FTM_SWOCTRL_CH0OC_SHIFT 0
3862 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
3863 #define FTM_SWOCTRL_CH1OC_SHIFT 1
3864 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
3865 #define FTM_SWOCTRL_CH2OC_SHIFT 2
3866 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
3867 #define FTM_SWOCTRL_CH3OC_SHIFT 3
3868 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
3869 #define FTM_SWOCTRL_CH4OC_SHIFT 4
3870 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
3871 #define FTM_SWOCTRL_CH5OC_SHIFT 5
3872 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
3873 #define FTM_SWOCTRL_CH6OC_SHIFT 6
3874 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
3875 #define FTM_SWOCTRL_CH7OC_SHIFT 7
3876 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
3877 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
3878 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
3879 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
3880 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
3881 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
3882 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
3883 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
3884 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
3885 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
3886 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
3887 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
3888 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
3889 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
3890 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
3891 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
3892 /* PWMLOAD Bit Fields */
3893 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
3894 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
3895 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
3896 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
3897 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
3898 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
3899 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
3900 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
3901 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
3902 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
3903 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
3904 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
3905 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
3906 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
3907 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
3908 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
3909 #define FTM_PWMLOAD_LDOK_MASK 0x200u
3910 #define FTM_PWMLOAD_LDOK_SHIFT 9
3914 */ /* end of group FTM_Register_Masks */
3917 /* FTM - Peripheral instance base addresses */
3918 /** Peripheral FTM0 base address */
3919 #define FTM0_BASE (0x40038000u)
3920 /** Peripheral FTM0 base pointer */
3921 #define FTM0 ((FTM_Type *)FTM0_BASE)
3922 #define FTM0_BASE_PTR (FTM0)
3923 /** Peripheral FTM1 base address */
3924 #define FTM1_BASE (0x40039000u)
3925 /** Peripheral FTM1 base pointer */
3926 #define FTM1 ((FTM_Type *)FTM1_BASE)
3927 #define FTM1_BASE_PTR (FTM1)
3928 /** Peripheral FTM2 base address */
3929 #define FTM2_BASE (0x4003A000u)
3930 /** Peripheral FTM2 base pointer */
3931 #define FTM2 ((FTM_Type *)FTM2_BASE)
3932 #define FTM2_BASE_PTR (FTM2)
3933 /** Peripheral FTM3 base address */
3934 #define FTM3_BASE (0x40026000u)
3935 /** Peripheral FTM3 base pointer */
3936 #define FTM3 ((FTM_Type *)FTM3_BASE)
3937 #define FTM3_BASE_PTR (FTM3)
3938 /** Array initializer of FTM peripheral base addresses */
3939 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
3940 /** Array initializer of FTM peripheral base pointers */
3941 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
3942 /** Interrupt vectors for the FTM peripheral type */
3943 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
3945 /* ----------------------------------------------------------------------------
3946 -- FTM - Register accessor macros
3947 ---------------------------------------------------------------------------- */
3950 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
3955 /* FTM - Register instance definitions */
3957 #define FTM0_SC FTM_SC_REG(FTM0)
3958 #define FTM0_CNT FTM_CNT_REG(FTM0)
3959 #define FTM0_MOD FTM_MOD_REG(FTM0)
3960 #define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
3961 #define FTM0_C0V FTM_CnV_REG(FTM0,0)
3962 #define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
3963 #define FTM0_C1V FTM_CnV_REG(FTM0,1)
3964 #define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
3965 #define FTM0_C2V FTM_CnV_REG(FTM0,2)
3966 #define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
3967 #define FTM0_C3V FTM_CnV_REG(FTM0,3)
3968 #define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
3969 #define FTM0_C4V FTM_CnV_REG(FTM0,4)
3970 #define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
3971 #define FTM0_C5V FTM_CnV_REG(FTM0,5)
3972 #define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
3973 #define FTM0_C6V FTM_CnV_REG(FTM0,6)
3974 #define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
3975 #define FTM0_C7V FTM_CnV_REG(FTM0,7)
3976 #define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
3977 #define FTM0_STATUS FTM_STATUS_REG(FTM0)
3978 #define FTM0_MODE FTM_MODE_REG(FTM0)
3979 #define FTM0_SYNC FTM_SYNC_REG(FTM0)
3980 #define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
3981 #define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
3982 #define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
3983 #define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
3984 #define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
3985 #define FTM0_POL FTM_POL_REG(FTM0)
3986 #define FTM0_FMS FTM_FMS_REG(FTM0)
3987 #define FTM0_FILTER FTM_FILTER_REG(FTM0)
3988 #define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
3989 #define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
3990 #define FTM0_CONF FTM_CONF_REG(FTM0)
3991 #define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
3992 #define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
3993 #define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
3994 #define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
3995 #define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
3997 #define FTM1_SC FTM_SC_REG(FTM1)
3998 #define FTM1_CNT FTM_CNT_REG(FTM1)
3999 #define FTM1_MOD FTM_MOD_REG(FTM1)
4000 #define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
4001 #define FTM1_C0V FTM_CnV_REG(FTM1,0)
4002 #define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
4003 #define FTM1_C1V FTM_CnV_REG(FTM1,1)
4004 #define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
4005 #define FTM1_STATUS FTM_STATUS_REG(FTM1)
4006 #define FTM1_MODE FTM_MODE_REG(FTM1)
4007 #define FTM1_SYNC FTM_SYNC_REG(FTM1)
4008 #define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
4009 #define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
4010 #define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
4011 #define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
4012 #define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
4013 #define FTM1_POL FTM_POL_REG(FTM1)
4014 #define FTM1_FMS FTM_FMS_REG(FTM1)
4015 #define FTM1_FILTER FTM_FILTER_REG(FTM1)
4016 #define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
4017 #define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
4018 #define FTM1_CONF FTM_CONF_REG(FTM1)
4019 #define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
4020 #define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
4021 #define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
4022 #define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
4023 #define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
4025 #define FTM2_SC FTM_SC_REG(FTM2)
4026 #define FTM2_CNT FTM_CNT_REG(FTM2)
4027 #define FTM2_MOD FTM_MOD_REG(FTM2)
4028 #define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
4029 #define FTM2_C0V FTM_CnV_REG(FTM2,0)
4030 #define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
4031 #define FTM2_C1V FTM_CnV_REG(FTM2,1)
4032 #define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
4033 #define FTM2_STATUS FTM_STATUS_REG(FTM2)
4034 #define FTM2_MODE FTM_MODE_REG(FTM2)
4035 #define FTM2_SYNC FTM_SYNC_REG(FTM2)
4036 #define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
4037 #define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
4038 #define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
4039 #define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
4040 #define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
4041 #define FTM2_POL FTM_POL_REG(FTM2)
4042 #define FTM2_FMS FTM_FMS_REG(FTM2)
4043 #define FTM2_FILTER FTM_FILTER_REG(FTM2)
4044 #define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
4045 #define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
4046 #define FTM2_CONF FTM_CONF_REG(FTM2)
4047 #define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
4048 #define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
4049 #define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
4050 #define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
4051 #define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
4053 #define FTM3_SC FTM_SC_REG(FTM3)
4054 #define FTM3_CNT FTM_CNT_REG(FTM3)
4055 #define FTM3_MOD FTM_MOD_REG(FTM3)
4056 #define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
4057 #define FTM3_C0V FTM_CnV_REG(FTM3,0)
4058 #define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
4059 #define FTM3_C1V FTM_CnV_REG(FTM3,1)
4060 #define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
4061 #define FTM3_C2V FTM_CnV_REG(FTM3,2)
4062 #define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
4063 #define FTM3_C3V FTM_CnV_REG(FTM3,3)
4064 #define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
4065 #define FTM3_C4V FTM_CnV_REG(FTM3,4)
4066 #define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
4067 #define FTM3_C5V FTM_CnV_REG(FTM3,5)
4068 #define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
4069 #define FTM3_C6V FTM_CnV_REG(FTM3,6)
4070 #define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
4071 #define FTM3_C7V FTM_CnV_REG(FTM3,7)
4072 #define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
4073 #define FTM3_STATUS FTM_STATUS_REG(FTM3)
4074 #define FTM3_MODE FTM_MODE_REG(FTM3)
4075 #define FTM3_SYNC FTM_SYNC_REG(FTM3)
4076 #define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
4077 #define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
4078 #define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
4079 #define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
4080 #define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
4081 #define FTM3_POL FTM_POL_REG(FTM3)
4082 #define FTM3_FMS FTM_FMS_REG(FTM3)
4083 #define FTM3_FILTER FTM_FILTER_REG(FTM3)
4084 #define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
4085 #define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
4086 #define FTM3_CONF FTM_CONF_REG(FTM3)
4087 #define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
4088 #define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
4089 #define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
4090 #define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
4091 #define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
4093 /* FTM - Register array accessors */
4094 #define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
4095 #define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
4096 #define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
4097 #define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
4098 #define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
4099 #define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
4100 #define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
4101 #define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
4105 */ /* end of group FTM_Register_Accessor_Macros */
4110 */ /* end of group FTM_Peripheral_Access_Layer */
4113 /* ----------------------------------------------------------------------------
4114 -- GPIO Peripheral Access Layer
4115 ---------------------------------------------------------------------------- */
4118 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
4122 /** GPIO - Register Layout Typedef */
4124 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
4125 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
4126 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
4127 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
4128 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
4129 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
4130 } GPIO_Type, *GPIO_MemMapPtr;
4132 /* ----------------------------------------------------------------------------
4133 -- GPIO - Register accessor macros
4134 ---------------------------------------------------------------------------- */
4137 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
4142 /* GPIO - Register accessors */
4143 #define GPIO_PDOR_REG(base) ((base)->PDOR)
4144 #define GPIO_PSOR_REG(base) ((base)->PSOR)
4145 #define GPIO_PCOR_REG(base) ((base)->PCOR)
4146 #define GPIO_PTOR_REG(base) ((base)->PTOR)
4147 #define GPIO_PDIR_REG(base) ((base)->PDIR)
4148 #define GPIO_PDDR_REG(base) ((base)->PDDR)
4152 */ /* end of group GPIO_Register_Accessor_Macros */
4155 /* ----------------------------------------------------------------------------
4156 -- GPIO Register Masks
4157 ---------------------------------------------------------------------------- */
4160 * @addtogroup GPIO_Register_Masks GPIO Register Masks
4164 /* PDOR Bit Fields */
4165 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
4166 #define GPIO_PDOR_PDO_SHIFT 0
4167 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
4168 /* PSOR Bit Fields */
4169 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
4170 #define GPIO_PSOR_PTSO_SHIFT 0
4171 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
4172 /* PCOR Bit Fields */
4173 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
4174 #define GPIO_PCOR_PTCO_SHIFT 0
4175 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
4176 /* PTOR Bit Fields */
4177 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
4178 #define GPIO_PTOR_PTTO_SHIFT 0
4179 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
4180 /* PDIR Bit Fields */
4181 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
4182 #define GPIO_PDIR_PDI_SHIFT 0
4183 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
4184 /* PDDR Bit Fields */
4185 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
4186 #define GPIO_PDDR_PDD_SHIFT 0
4187 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
4191 */ /* end of group GPIO_Register_Masks */
4194 /* GPIO - Peripheral instance base addresses */
4195 /** Peripheral PTA base address */
4196 #define PTA_BASE (0x400FF000u)
4197 /** Peripheral PTA base pointer */
4198 #define PTA ((GPIO_Type *)PTA_BASE)
4199 #define PTA_BASE_PTR (PTA)
4200 /** Peripheral PTB base address */
4201 #define PTB_BASE (0x400FF040u)
4202 /** Peripheral PTB base pointer */
4203 #define PTB ((GPIO_Type *)PTB_BASE)
4204 #define PTB_BASE_PTR (PTB)
4205 /** Peripheral PTC base address */
4206 #define PTC_BASE (0x400FF080u)
4207 /** Peripheral PTC base pointer */
4208 #define PTC ((GPIO_Type *)PTC_BASE)
4209 #define PTC_BASE_PTR (PTC)
4210 /** Peripheral PTD base address */
4211 #define PTD_BASE (0x400FF0C0u)
4212 /** Peripheral PTD base pointer */
4213 #define PTD ((GPIO_Type *)PTD_BASE)
4214 #define PTD_BASE_PTR (PTD)
4215 /** Peripheral PTE base address */
4216 #define PTE_BASE (0x400FF100u)
4217 /** Peripheral PTE base pointer */
4218 #define PTE ((GPIO_Type *)PTE_BASE)
4219 #define PTE_BASE_PTR (PTE)
4220 /** Array initializer of GPIO peripheral base addresses */
4221 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
4222 /** Array initializer of GPIO peripheral base pointers */
4223 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
4225 /* ----------------------------------------------------------------------------
4226 -- GPIO - Register accessor macros
4227 ---------------------------------------------------------------------------- */
4230 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
4235 /* GPIO - Register instance definitions */
4237 #define GPIOA_PDOR GPIO_PDOR_REG(PTA)
4238 #define GPIOA_PSOR GPIO_PSOR_REG(PTA)
4239 #define GPIOA_PCOR GPIO_PCOR_REG(PTA)
4240 #define GPIOA_PTOR GPIO_PTOR_REG(PTA)
4241 #define GPIOA_PDIR GPIO_PDIR_REG(PTA)
4242 #define GPIOA_PDDR GPIO_PDDR_REG(PTA)
4244 #define GPIOB_PDOR GPIO_PDOR_REG(PTB)
4245 #define GPIOB_PSOR GPIO_PSOR_REG(PTB)
4246 #define GPIOB_PCOR GPIO_PCOR_REG(PTB)
4247 #define GPIOB_PTOR GPIO_PTOR_REG(PTB)
4248 #define GPIOB_PDIR GPIO_PDIR_REG(PTB)
4249 #define GPIOB_PDDR GPIO_PDDR_REG(PTB)
4251 #define GPIOC_PDOR GPIO_PDOR_REG(PTC)
4252 #define GPIOC_PSOR GPIO_PSOR_REG(PTC)
4253 #define GPIOC_PCOR GPIO_PCOR_REG(PTC)
4254 #define GPIOC_PTOR GPIO_PTOR_REG(PTC)
4255 #define GPIOC_PDIR GPIO_PDIR_REG(PTC)
4256 #define GPIOC_PDDR GPIO_PDDR_REG(PTC)
4258 #define GPIOD_PDOR GPIO_PDOR_REG(PTD)
4259 #define GPIOD_PSOR GPIO_PSOR_REG(PTD)
4260 #define GPIOD_PCOR GPIO_PCOR_REG(PTD)
4261 #define GPIOD_PTOR GPIO_PTOR_REG(PTD)
4262 #define GPIOD_PDIR GPIO_PDIR_REG(PTD)
4263 #define GPIOD_PDDR GPIO_PDDR_REG(PTD)
4265 #define GPIOE_PDOR GPIO_PDOR_REG(PTE)
4266 #define GPIOE_PSOR GPIO_PSOR_REG(PTE)
4267 #define GPIOE_PCOR GPIO_PCOR_REG(PTE)
4268 #define GPIOE_PTOR GPIO_PTOR_REG(PTE)
4269 #define GPIOE_PDIR GPIO_PDIR_REG(PTE)
4270 #define GPIOE_PDDR GPIO_PDDR_REG(PTE)
4274 */ /* end of group GPIO_Register_Accessor_Macros */
4279 */ /* end of group GPIO_Peripheral_Access_Layer */
4282 /* ----------------------------------------------------------------------------
4283 -- I2C Peripheral Access Layer
4284 ---------------------------------------------------------------------------- */
4287 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
4291 /** I2C - Register Layout Typedef */
4293 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
4294 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
4295 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
4296 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
4297 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
4298 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
4299 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
4300 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
4301 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
4302 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
4303 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
4304 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
4305 } I2C_Type, *I2C_MemMapPtr;
4307 /* ----------------------------------------------------------------------------
4308 -- I2C - Register accessor macros
4309 ---------------------------------------------------------------------------- */
4312 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
4317 /* I2C - Register accessors */
4318 #define I2C_A1_REG(base) ((base)->A1)
4319 #define I2C_F_REG(base) ((base)->F)
4320 #define I2C_C1_REG(base) ((base)->C1)
4321 #define I2C_S_REG(base) ((base)->S)
4322 #define I2C_D_REG(base) ((base)->D)
4323 #define I2C_C2_REG(base) ((base)->C2)
4324 #define I2C_FLT_REG(base) ((base)->FLT)
4325 #define I2C_RA_REG(base) ((base)->RA)
4326 #define I2C_SMB_REG(base) ((base)->SMB)
4327 #define I2C_A2_REG(base) ((base)->A2)
4328 #define I2C_SLTH_REG(base) ((base)->SLTH)
4329 #define I2C_SLTL_REG(base) ((base)->SLTL)
4333 */ /* end of group I2C_Register_Accessor_Macros */
4336 /* ----------------------------------------------------------------------------
4337 -- I2C Register Masks
4338 ---------------------------------------------------------------------------- */
4341 * @addtogroup I2C_Register_Masks I2C Register Masks
4346 #define I2C_A1_AD_MASK 0xFEu
4347 #define I2C_A1_AD_SHIFT 1
4348 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
4350 #define I2C_F_ICR_MASK 0x3Fu
4351 #define I2C_F_ICR_SHIFT 0
4352 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
4353 #define I2C_F_MULT_MASK 0xC0u
4354 #define I2C_F_MULT_SHIFT 6
4355 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
4357 #define I2C_C1_DMAEN_MASK 0x1u
4358 #define I2C_C1_DMAEN_SHIFT 0
4359 #define I2C_C1_WUEN_MASK 0x2u
4360 #define I2C_C1_WUEN_SHIFT 1
4361 #define I2C_C1_RSTA_MASK 0x4u
4362 #define I2C_C1_RSTA_SHIFT 2
4363 #define I2C_C1_TXAK_MASK 0x8u
4364 #define I2C_C1_TXAK_SHIFT 3
4365 #define I2C_C1_TX_MASK 0x10u
4366 #define I2C_C1_TX_SHIFT 4
4367 #define I2C_C1_MST_MASK 0x20u
4368 #define I2C_C1_MST_SHIFT 5
4369 #define I2C_C1_IICIE_MASK 0x40u
4370 #define I2C_C1_IICIE_SHIFT 6
4371 #define I2C_C1_IICEN_MASK 0x80u
4372 #define I2C_C1_IICEN_SHIFT 7
4374 #define I2C_S_RXAK_MASK 0x1u
4375 #define I2C_S_RXAK_SHIFT 0
4376 #define I2C_S_IICIF_MASK 0x2u
4377 #define I2C_S_IICIF_SHIFT 1
4378 #define I2C_S_SRW_MASK 0x4u
4379 #define I2C_S_SRW_SHIFT 2
4380 #define I2C_S_RAM_MASK 0x8u
4381 #define I2C_S_RAM_SHIFT 3
4382 #define I2C_S_ARBL_MASK 0x10u
4383 #define I2C_S_ARBL_SHIFT 4
4384 #define I2C_S_BUSY_MASK 0x20u
4385 #define I2C_S_BUSY_SHIFT 5
4386 #define I2C_S_IAAS_MASK 0x40u
4387 #define I2C_S_IAAS_SHIFT 6
4388 #define I2C_S_TCF_MASK 0x80u
4389 #define I2C_S_TCF_SHIFT 7
4391 #define I2C_D_DATA_MASK 0xFFu
4392 #define I2C_D_DATA_SHIFT 0
4393 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
4395 #define I2C_C2_AD_MASK 0x7u
4396 #define I2C_C2_AD_SHIFT 0
4397 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
4398 #define I2C_C2_RMEN_MASK 0x8u
4399 #define I2C_C2_RMEN_SHIFT 3
4400 #define I2C_C2_SBRC_MASK 0x10u
4401 #define I2C_C2_SBRC_SHIFT 4
4402 #define I2C_C2_HDRS_MASK 0x20u
4403 #define I2C_C2_HDRS_SHIFT 5
4404 #define I2C_C2_ADEXT_MASK 0x40u
4405 #define I2C_C2_ADEXT_SHIFT 6
4406 #define I2C_C2_GCAEN_MASK 0x80u
4407 #define I2C_C2_GCAEN_SHIFT 7
4408 /* FLT Bit Fields */
4409 #define I2C_FLT_FLT_MASK 0xFu
4410 #define I2C_FLT_FLT_SHIFT 0
4411 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
4412 #define I2C_FLT_STARTF_MASK 0x10u
4413 #define I2C_FLT_STARTF_SHIFT 4
4414 #define I2C_FLT_SSIE_MASK 0x20u
4415 #define I2C_FLT_SSIE_SHIFT 5
4416 #define I2C_FLT_STOPF_MASK 0x40u
4417 #define I2C_FLT_STOPF_SHIFT 6
4418 #define I2C_FLT_SHEN_MASK 0x80u
4419 #define I2C_FLT_SHEN_SHIFT 7
4421 #define I2C_RA_RAD_MASK 0xFEu
4422 #define I2C_RA_RAD_SHIFT 1
4423 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
4424 /* SMB Bit Fields */
4425 #define I2C_SMB_SHTF2IE_MASK 0x1u
4426 #define I2C_SMB_SHTF2IE_SHIFT 0
4427 #define I2C_SMB_SHTF2_MASK 0x2u
4428 #define I2C_SMB_SHTF2_SHIFT 1
4429 #define I2C_SMB_SHTF1_MASK 0x4u
4430 #define I2C_SMB_SHTF1_SHIFT 2
4431 #define I2C_SMB_SLTF_MASK 0x8u
4432 #define I2C_SMB_SLTF_SHIFT 3
4433 #define I2C_SMB_TCKSEL_MASK 0x10u
4434 #define I2C_SMB_TCKSEL_SHIFT 4
4435 #define I2C_SMB_SIICAEN_MASK 0x20u
4436 #define I2C_SMB_SIICAEN_SHIFT 5
4437 #define I2C_SMB_ALERTEN_MASK 0x40u
4438 #define I2C_SMB_ALERTEN_SHIFT 6
4439 #define I2C_SMB_FACK_MASK 0x80u
4440 #define I2C_SMB_FACK_SHIFT 7
4442 #define I2C_A2_SAD_MASK 0xFEu
4443 #define I2C_A2_SAD_SHIFT 1
4444 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
4445 /* SLTH Bit Fields */
4446 #define I2C_SLTH_SSLT_MASK 0xFFu
4447 #define I2C_SLTH_SSLT_SHIFT 0
4448 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
4449 /* SLTL Bit Fields */
4450 #define I2C_SLTL_SSLT_MASK 0xFFu
4451 #define I2C_SLTL_SSLT_SHIFT 0
4452 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
4456 */ /* end of group I2C_Register_Masks */
4459 /* I2C - Peripheral instance base addresses */
4460 /** Peripheral I2C0 base address */
4461 #define I2C0_BASE (0x40066000u)
4462 /** Peripheral I2C0 base pointer */
4463 #define I2C0 ((I2C_Type *)I2C0_BASE)
4464 #define I2C0_BASE_PTR (I2C0)
4465 /** Peripheral I2C1 base address */
4466 #define I2C1_BASE (0x40067000u)
4467 /** Peripheral I2C1 base pointer */
4468 #define I2C1 ((I2C_Type *)I2C1_BASE)
4469 #define I2C1_BASE_PTR (I2C1)
4470 /** Array initializer of I2C peripheral base addresses */
4471 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
4472 /** Array initializer of I2C peripheral base pointers */
4473 #define I2C_BASE_PTRS { I2C0, I2C1 }
4474 /** Interrupt vectors for the I2C peripheral type */
4475 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
4477 /* ----------------------------------------------------------------------------
4478 -- I2C - Register accessor macros
4479 ---------------------------------------------------------------------------- */
4482 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
4487 /* I2C - Register instance definitions */
4489 #define I2C0_A1 I2C_A1_REG(I2C0)
4490 #define I2C0_F I2C_F_REG(I2C0)
4491 #define I2C0_C1 I2C_C1_REG(I2C0)
4492 #define I2C0_S I2C_S_REG(I2C0)
4493 #define I2C0_D I2C_D_REG(I2C0)
4494 #define I2C0_C2 I2C_C2_REG(I2C0)
4495 #define I2C0_FLT I2C_FLT_REG(I2C0)
4496 #define I2C0_RA I2C_RA_REG(I2C0)
4497 #define I2C0_SMB I2C_SMB_REG(I2C0)
4498 #define I2C0_A2 I2C_A2_REG(I2C0)
4499 #define I2C0_SLTH I2C_SLTH_REG(I2C0)
4500 #define I2C0_SLTL I2C_SLTL_REG(I2C0)
4502 #define I2C1_A1 I2C_A1_REG(I2C1)
4503 #define I2C1_F I2C_F_REG(I2C1)
4504 #define I2C1_C1 I2C_C1_REG(I2C1)
4505 #define I2C1_S I2C_S_REG(I2C1)
4506 #define I2C1_D I2C_D_REG(I2C1)
4507 #define I2C1_C2 I2C_C2_REG(I2C1)
4508 #define I2C1_FLT I2C_FLT_REG(I2C1)
4509 #define I2C1_RA I2C_RA_REG(I2C1)
4510 #define I2C1_SMB I2C_SMB_REG(I2C1)
4511 #define I2C1_A2 I2C_A2_REG(I2C1)
4512 #define I2C1_SLTH I2C_SLTH_REG(I2C1)
4513 #define I2C1_SLTL I2C_SLTL_REG(I2C1)
4517 */ /* end of group I2C_Register_Accessor_Macros */
4522 */ /* end of group I2C_Peripheral_Access_Layer */
4525 /* ----------------------------------------------------------------------------
4526 -- I2S Peripheral Access Layer
4527 ---------------------------------------------------------------------------- */
4530 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
4534 /** I2S - Register Layout Typedef */
4536 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
4537 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
4538 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
4539 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
4540 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
4541 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
4542 uint8_t RESERVED_0[8];
4543 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
4544 uint8_t RESERVED_1[28];
4545 __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
4546 uint8_t RESERVED_2[28];
4547 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
4548 uint8_t RESERVED_3[28];
4549 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
4550 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
4551 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
4552 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
4553 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
4554 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
4555 uint8_t RESERVED_4[8];
4556 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
4557 uint8_t RESERVED_5[28];
4558 __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
4559 uint8_t RESERVED_6[28];
4560 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
4561 uint8_t RESERVED_7[28];
4562 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
4563 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
4564 } I2S_Type, *I2S_MemMapPtr;
4566 /* ----------------------------------------------------------------------------
4567 -- I2S - Register accessor macros
4568 ---------------------------------------------------------------------------- */
4571 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
4576 /* I2S - Register accessors */
4577 #define I2S_TCSR_REG(base) ((base)->TCSR)
4578 #define I2S_TCR1_REG(base) ((base)->TCR1)
4579 #define I2S_TCR2_REG(base) ((base)->TCR2)
4580 #define I2S_TCR3_REG(base) ((base)->TCR3)
4581 #define I2S_TCR4_REG(base) ((base)->TCR4)
4582 #define I2S_TCR5_REG(base) ((base)->TCR5)
4583 #define I2S_TDR_REG(base,index) ((base)->TDR[index])
4584 #define I2S_TFR_REG(base,index) ((base)->TFR[index])
4585 #define I2S_TMR_REG(base) ((base)->TMR)
4586 #define I2S_RCSR_REG(base) ((base)->RCSR)
4587 #define I2S_RCR1_REG(base) ((base)->RCR1)
4588 #define I2S_RCR2_REG(base) ((base)->RCR2)
4589 #define I2S_RCR3_REG(base) ((base)->RCR3)
4590 #define I2S_RCR4_REG(base) ((base)->RCR4)
4591 #define I2S_RCR5_REG(base) ((base)->RCR5)
4592 #define I2S_RDR_REG(base,index) ((base)->RDR[index])
4593 #define I2S_RFR_REG(base,index) ((base)->RFR[index])
4594 #define I2S_RMR_REG(base) ((base)->RMR)
4595 #define I2S_MCR_REG(base) ((base)->MCR)
4596 #define I2S_MDR_REG(base) ((base)->MDR)
4600 */ /* end of group I2S_Register_Accessor_Macros */
4603 /* ----------------------------------------------------------------------------
4604 -- I2S Register Masks
4605 ---------------------------------------------------------------------------- */
4608 * @addtogroup I2S_Register_Masks I2S Register Masks
4612 /* TCSR Bit Fields */
4613 #define I2S_TCSR_FRDE_MASK 0x1u
4614 #define I2S_TCSR_FRDE_SHIFT 0
4615 #define I2S_TCSR_FWDE_MASK 0x2u
4616 #define I2S_TCSR_FWDE_SHIFT 1
4617 #define I2S_TCSR_FRIE_MASK 0x100u
4618 #define I2S_TCSR_FRIE_SHIFT 8
4619 #define I2S_TCSR_FWIE_MASK 0x200u
4620 #define I2S_TCSR_FWIE_SHIFT 9
4621 #define I2S_TCSR_FEIE_MASK 0x400u
4622 #define I2S_TCSR_FEIE_SHIFT 10
4623 #define I2S_TCSR_SEIE_MASK 0x800u
4624 #define I2S_TCSR_SEIE_SHIFT 11
4625 #define I2S_TCSR_WSIE_MASK 0x1000u
4626 #define I2S_TCSR_WSIE_SHIFT 12
4627 #define I2S_TCSR_FRF_MASK 0x10000u
4628 #define I2S_TCSR_FRF_SHIFT 16
4629 #define I2S_TCSR_FWF_MASK 0x20000u
4630 #define I2S_TCSR_FWF_SHIFT 17
4631 #define I2S_TCSR_FEF_MASK 0x40000u
4632 #define I2S_TCSR_FEF_SHIFT 18
4633 #define I2S_TCSR_SEF_MASK 0x80000u
4634 #define I2S_TCSR_SEF_SHIFT 19
4635 #define I2S_TCSR_WSF_MASK 0x100000u
4636 #define I2S_TCSR_WSF_SHIFT 20
4637 #define I2S_TCSR_SR_MASK 0x1000000u
4638 #define I2S_TCSR_SR_SHIFT 24
4639 #define I2S_TCSR_FR_MASK 0x2000000u
4640 #define I2S_TCSR_FR_SHIFT 25
4641 #define I2S_TCSR_BCE_MASK 0x10000000u
4642 #define I2S_TCSR_BCE_SHIFT 28
4643 #define I2S_TCSR_DBGE_MASK 0x20000000u
4644 #define I2S_TCSR_DBGE_SHIFT 29
4645 #define I2S_TCSR_STOPE_MASK 0x40000000u
4646 #define I2S_TCSR_STOPE_SHIFT 30
4647 #define I2S_TCSR_TE_MASK 0x80000000u
4648 #define I2S_TCSR_TE_SHIFT 31
4649 /* TCR1 Bit Fields */
4650 #define I2S_TCR1_TFW_MASK 0x7u
4651 #define I2S_TCR1_TFW_SHIFT 0
4652 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
4653 /* TCR2 Bit Fields */
4654 #define I2S_TCR2_DIV_MASK 0xFFu
4655 #define I2S_TCR2_DIV_SHIFT 0
4656 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
4657 #define I2S_TCR2_BCD_MASK 0x1000000u
4658 #define I2S_TCR2_BCD_SHIFT 24
4659 #define I2S_TCR2_BCP_MASK 0x2000000u
4660 #define I2S_TCR2_BCP_SHIFT 25
4661 #define I2S_TCR2_MSEL_MASK 0xC000000u
4662 #define I2S_TCR2_MSEL_SHIFT 26
4663 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
4664 #define I2S_TCR2_BCI_MASK 0x10000000u
4665 #define I2S_TCR2_BCI_SHIFT 28
4666 #define I2S_TCR2_BCS_MASK 0x20000000u
4667 #define I2S_TCR2_BCS_SHIFT 29
4668 #define I2S_TCR2_SYNC_MASK 0xC0000000u
4669 #define I2S_TCR2_SYNC_SHIFT 30
4670 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
4671 /* TCR3 Bit Fields */
4672 #define I2S_TCR3_WDFL_MASK 0xFu
4673 #define I2S_TCR3_WDFL_SHIFT 0
4674 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
4675 #define I2S_TCR3_TCE_MASK 0x10000u
4676 #define I2S_TCR3_TCE_SHIFT 16
4677 /* TCR4 Bit Fields */
4678 #define I2S_TCR4_FSD_MASK 0x1u
4679 #define I2S_TCR4_FSD_SHIFT 0
4680 #define I2S_TCR4_FSP_MASK 0x2u
4681 #define I2S_TCR4_FSP_SHIFT 1
4682 #define I2S_TCR4_ONDEM_MASK 0x4u
4683 #define I2S_TCR4_ONDEM_SHIFT 2
4684 #define I2S_TCR4_FSE_MASK 0x8u
4685 #define I2S_TCR4_FSE_SHIFT 3
4686 #define I2S_TCR4_MF_MASK 0x10u
4687 #define I2S_TCR4_MF_SHIFT 4
4688 #define I2S_TCR4_SYWD_MASK 0x1F00u
4689 #define I2S_TCR4_SYWD_SHIFT 8
4690 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
4691 #define I2S_TCR4_FRSZ_MASK 0xF0000u
4692 #define I2S_TCR4_FRSZ_SHIFT 16
4693 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
4694 #define I2S_TCR4_FPACK_MASK 0x3000000u
4695 #define I2S_TCR4_FPACK_SHIFT 24
4696 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
4697 #define I2S_TCR4_FCONT_MASK 0x10000000u
4698 #define I2S_TCR4_FCONT_SHIFT 28
4699 /* TCR5 Bit Fields */
4700 #define I2S_TCR5_FBT_MASK 0x1F00u
4701 #define I2S_TCR5_FBT_SHIFT 8
4702 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
4703 #define I2S_TCR5_W0W_MASK 0x1F0000u
4704 #define I2S_TCR5_W0W_SHIFT 16
4705 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
4706 #define I2S_TCR5_WNW_MASK 0x1F000000u
4707 #define I2S_TCR5_WNW_SHIFT 24
4708 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
4709 /* TDR Bit Fields */
4710 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
4711 #define I2S_TDR_TDR_SHIFT 0
4712 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
4713 /* TFR Bit Fields */
4714 #define I2S_TFR_RFP_MASK 0xFu
4715 #define I2S_TFR_RFP_SHIFT 0
4716 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
4717 #define I2S_TFR_WFP_MASK 0xF0000u
4718 #define I2S_TFR_WFP_SHIFT 16
4719 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
4720 /* TMR Bit Fields */
4721 #define I2S_TMR_TWM_MASK 0xFFFFu
4722 #define I2S_TMR_TWM_SHIFT 0
4723 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
4724 /* RCSR Bit Fields */
4725 #define I2S_RCSR_FRDE_MASK 0x1u
4726 #define I2S_RCSR_FRDE_SHIFT 0
4727 #define I2S_RCSR_FWDE_MASK 0x2u
4728 #define I2S_RCSR_FWDE_SHIFT 1
4729 #define I2S_RCSR_FRIE_MASK 0x100u
4730 #define I2S_RCSR_FRIE_SHIFT 8
4731 #define I2S_RCSR_FWIE_MASK 0x200u
4732 #define I2S_RCSR_FWIE_SHIFT 9
4733 #define I2S_RCSR_FEIE_MASK 0x400u
4734 #define I2S_RCSR_FEIE_SHIFT 10
4735 #define I2S_RCSR_SEIE_MASK 0x800u
4736 #define I2S_RCSR_SEIE_SHIFT 11
4737 #define I2S_RCSR_WSIE_MASK 0x1000u
4738 #define I2S_RCSR_WSIE_SHIFT 12
4739 #define I2S_RCSR_FRF_MASK 0x10000u
4740 #define I2S_RCSR_FRF_SHIFT 16
4741 #define I2S_RCSR_FWF_MASK 0x20000u
4742 #define I2S_RCSR_FWF_SHIFT 17
4743 #define I2S_RCSR_FEF_MASK 0x40000u
4744 #define I2S_RCSR_FEF_SHIFT 18
4745 #define I2S_RCSR_SEF_MASK 0x80000u
4746 #define I2S_RCSR_SEF_SHIFT 19
4747 #define I2S_RCSR_WSF_MASK 0x100000u
4748 #define I2S_RCSR_WSF_SHIFT 20
4749 #define I2S_RCSR_SR_MASK 0x1000000u
4750 #define I2S_RCSR_SR_SHIFT 24
4751 #define I2S_RCSR_FR_MASK 0x2000000u
4752 #define I2S_RCSR_FR_SHIFT 25
4753 #define I2S_RCSR_BCE_MASK 0x10000000u
4754 #define I2S_RCSR_BCE_SHIFT 28
4755 #define I2S_RCSR_DBGE_MASK 0x20000000u
4756 #define I2S_RCSR_DBGE_SHIFT 29
4757 #define I2S_RCSR_STOPE_MASK 0x40000000u
4758 #define I2S_RCSR_STOPE_SHIFT 30
4759 #define I2S_RCSR_RE_MASK 0x80000000u
4760 #define I2S_RCSR_RE_SHIFT 31
4761 /* RCR1 Bit Fields */
4762 #define I2S_RCR1_RFW_MASK 0x7u
4763 #define I2S_RCR1_RFW_SHIFT 0
4764 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
4765 /* RCR2 Bit Fields */
4766 #define I2S_RCR2_DIV_MASK 0xFFu
4767 #define I2S_RCR2_DIV_SHIFT 0
4768 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
4769 #define I2S_RCR2_BCD_MASK 0x1000000u
4770 #define I2S_RCR2_BCD_SHIFT 24
4771 #define I2S_RCR2_BCP_MASK 0x2000000u
4772 #define I2S_RCR2_BCP_SHIFT 25
4773 #define I2S_RCR2_MSEL_MASK 0xC000000u
4774 #define I2S_RCR2_MSEL_SHIFT 26
4775 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
4776 #define I2S_RCR2_BCI_MASK 0x10000000u
4777 #define I2S_RCR2_BCI_SHIFT 28
4778 #define I2S_RCR2_BCS_MASK 0x20000000u
4779 #define I2S_RCR2_BCS_SHIFT 29
4780 #define I2S_RCR2_SYNC_MASK 0xC0000000u
4781 #define I2S_RCR2_SYNC_SHIFT 30
4782 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
4783 /* RCR3 Bit Fields */
4784 #define I2S_RCR3_WDFL_MASK 0xFu
4785 #define I2S_RCR3_WDFL_SHIFT 0
4786 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
4787 #define I2S_RCR3_RCE_MASK 0x10000u
4788 #define I2S_RCR3_RCE_SHIFT 16
4789 /* RCR4 Bit Fields */
4790 #define I2S_RCR4_FSD_MASK 0x1u
4791 #define I2S_RCR4_FSD_SHIFT 0
4792 #define I2S_RCR4_FSP_MASK 0x2u
4793 #define I2S_RCR4_FSP_SHIFT 1
4794 #define I2S_RCR4_ONDEM_MASK 0x4u
4795 #define I2S_RCR4_ONDEM_SHIFT 2
4796 #define I2S_RCR4_FSE_MASK 0x8u
4797 #define I2S_RCR4_FSE_SHIFT 3
4798 #define I2S_RCR4_MF_MASK 0x10u
4799 #define I2S_RCR4_MF_SHIFT 4
4800 #define I2S_RCR4_SYWD_MASK 0x1F00u
4801 #define I2S_RCR4_SYWD_SHIFT 8
4802 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
4803 #define I2S_RCR4_FRSZ_MASK 0xF0000u
4804 #define I2S_RCR4_FRSZ_SHIFT 16
4805 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
4806 #define I2S_RCR4_FPACK_MASK 0x3000000u
4807 #define I2S_RCR4_FPACK_SHIFT 24
4808 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
4809 #define I2S_RCR4_FCONT_MASK 0x10000000u
4810 #define I2S_RCR4_FCONT_SHIFT 28
4811 /* RCR5 Bit Fields */
4812 #define I2S_RCR5_FBT_MASK 0x1F00u
4813 #define I2S_RCR5_FBT_SHIFT 8
4814 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
4815 #define I2S_RCR5_W0W_MASK 0x1F0000u
4816 #define I2S_RCR5_W0W_SHIFT 16
4817 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
4818 #define I2S_RCR5_WNW_MASK 0x1F000000u
4819 #define I2S_RCR5_WNW_SHIFT 24
4820 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
4821 /* RDR Bit Fields */
4822 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
4823 #define I2S_RDR_RDR_SHIFT 0
4824 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
4825 /* RFR Bit Fields */
4826 #define I2S_RFR_RFP_MASK 0xFu
4827 #define I2S_RFR_RFP_SHIFT 0
4828 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
4829 #define I2S_RFR_WFP_MASK 0xF0000u
4830 #define I2S_RFR_WFP_SHIFT 16
4831 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
4832 /* RMR Bit Fields */
4833 #define I2S_RMR_RWM_MASK 0xFFFFu
4834 #define I2S_RMR_RWM_SHIFT 0
4835 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
4836 /* MCR Bit Fields */
4837 #define I2S_MCR_MICS_MASK 0x3000000u
4838 #define I2S_MCR_MICS_SHIFT 24
4839 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
4840 #define I2S_MCR_MOE_MASK 0x40000000u
4841 #define I2S_MCR_MOE_SHIFT 30
4842 #define I2S_MCR_DUF_MASK 0x80000000u
4843 #define I2S_MCR_DUF_SHIFT 31
4844 /* MDR Bit Fields */
4845 #define I2S_MDR_DIVIDE_MASK 0xFFFu
4846 #define I2S_MDR_DIVIDE_SHIFT 0
4847 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
4848 #define I2S_MDR_FRACT_MASK 0xFF000u
4849 #define I2S_MDR_FRACT_SHIFT 12
4850 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
4854 */ /* end of group I2S_Register_Masks */
4857 /* I2S - Peripheral instance base addresses */
4858 /** Peripheral I2S0 base address */
4859 #define I2S0_BASE (0x4002F000u)
4860 /** Peripheral I2S0 base pointer */
4861 #define I2S0 ((I2S_Type *)I2S0_BASE)
4862 #define I2S0_BASE_PTR (I2S0)
4863 /** Array initializer of I2S peripheral base addresses */
4864 #define I2S_BASE_ADDRS { I2S0_BASE }
4865 /** Array initializer of I2S peripheral base pointers */
4866 #define I2S_BASE_PTRS { I2S0 }
4867 /** Interrupt vectors for the I2S peripheral type */
4868 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
4869 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
4871 /* ----------------------------------------------------------------------------
4872 -- I2S - Register accessor macros
4873 ---------------------------------------------------------------------------- */
4876 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
4881 /* I2S - Register instance definitions */
4883 #define I2S0_TCSR I2S_TCSR_REG(I2S0)
4884 #define I2S0_TCR1 I2S_TCR1_REG(I2S0)
4885 #define I2S0_TCR2 I2S_TCR2_REG(I2S0)
4886 #define I2S0_TCR3 I2S_TCR3_REG(I2S0)
4887 #define I2S0_TCR4 I2S_TCR4_REG(I2S0)
4888 #define I2S0_TCR5 I2S_TCR5_REG(I2S0)
4889 #define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
4890 #define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
4891 #define I2S0_TMR I2S_TMR_REG(I2S0)
4892 #define I2S0_RCSR I2S_RCSR_REG(I2S0)
4893 #define I2S0_RCR1 I2S_RCR1_REG(I2S0)
4894 #define I2S0_RCR2 I2S_RCR2_REG(I2S0)
4895 #define I2S0_RCR3 I2S_RCR3_REG(I2S0)
4896 #define I2S0_RCR4 I2S_RCR4_REG(I2S0)
4897 #define I2S0_RCR5 I2S_RCR5_REG(I2S0)
4898 #define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
4899 #define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
4900 #define I2S0_RMR I2S_RMR_REG(I2S0)
4901 #define I2S0_MCR I2S_MCR_REG(I2S0)
4902 #define I2S0_MDR I2S_MDR_REG(I2S0)
4904 /* I2S - Register array accessors */
4905 #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
4906 #define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
4907 #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
4908 #define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
4912 */ /* end of group I2S_Register_Accessor_Macros */
4917 */ /* end of group I2S_Peripheral_Access_Layer */
4920 /* ----------------------------------------------------------------------------
4921 -- LLWU Peripheral Access Layer
4922 ---------------------------------------------------------------------------- */
4925 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
4929 /** LLWU - Register Layout Typedef */
4931 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
4932 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
4933 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
4934 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
4935 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
4936 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
4937 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
4938 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
4939 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
4940 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
4941 } LLWU_Type, *LLWU_MemMapPtr;
4943 /* ----------------------------------------------------------------------------
4944 -- LLWU - Register accessor macros
4945 ---------------------------------------------------------------------------- */
4948 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
4953 /* LLWU - Register accessors */
4954 #define LLWU_PE1_REG(base) ((base)->PE1)
4955 #define LLWU_PE2_REG(base) ((base)->PE2)
4956 #define LLWU_PE3_REG(base) ((base)->PE3)
4957 #define LLWU_PE4_REG(base) ((base)->PE4)
4958 #define LLWU_ME_REG(base) ((base)->ME)
4959 #define LLWU_F1_REG(base) ((base)->F1)
4960 #define LLWU_F2_REG(base) ((base)->F2)
4961 #define LLWU_F3_REG(base) ((base)->F3)
4962 #define LLWU_FILT1_REG(base) ((base)->FILT1)
4963 #define LLWU_FILT2_REG(base) ((base)->FILT2)
4967 */ /* end of group LLWU_Register_Accessor_Macros */
4970 /* ----------------------------------------------------------------------------
4971 -- LLWU Register Masks
4972 ---------------------------------------------------------------------------- */
4975 * @addtogroup LLWU_Register_Masks LLWU Register Masks
4979 /* PE1 Bit Fields */
4980 #define LLWU_PE1_WUPE0_MASK 0x3u
4981 #define LLWU_PE1_WUPE0_SHIFT 0
4982 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
4983 #define LLWU_PE1_WUPE1_MASK 0xCu
4984 #define LLWU_PE1_WUPE1_SHIFT 2
4985 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
4986 #define LLWU_PE1_WUPE2_MASK 0x30u
4987 #define LLWU_PE1_WUPE2_SHIFT 4
4988 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
4989 #define LLWU_PE1_WUPE3_MASK 0xC0u
4990 #define LLWU_PE1_WUPE3_SHIFT 6
4991 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
4992 /* PE2 Bit Fields */
4993 #define LLWU_PE2_WUPE4_MASK 0x3u
4994 #define LLWU_PE2_WUPE4_SHIFT 0
4995 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
4996 #define LLWU_PE2_WUPE5_MASK 0xCu
4997 #define LLWU_PE2_WUPE5_SHIFT 2
4998 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
4999 #define LLWU_PE2_WUPE6_MASK 0x30u
5000 #define LLWU_PE2_WUPE6_SHIFT 4
5001 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
5002 #define LLWU_PE2_WUPE7_MASK 0xC0u
5003 #define LLWU_PE2_WUPE7_SHIFT 6
5004 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
5005 /* PE3 Bit Fields */
5006 #define LLWU_PE3_WUPE8_MASK 0x3u
5007 #define LLWU_PE3_WUPE8_SHIFT 0
5008 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
5009 #define LLWU_PE3_WUPE9_MASK 0xCu
5010 #define LLWU_PE3_WUPE9_SHIFT 2
5011 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
5012 #define LLWU_PE3_WUPE10_MASK 0x30u
5013 #define LLWU_PE3_WUPE10_SHIFT 4
5014 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
5015 #define LLWU_PE3_WUPE11_MASK 0xC0u
5016 #define LLWU_PE3_WUPE11_SHIFT 6
5017 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
5018 /* PE4 Bit Fields */
5019 #define LLWU_PE4_WUPE12_MASK 0x3u
5020 #define LLWU_PE4_WUPE12_SHIFT 0
5021 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
5022 #define LLWU_PE4_WUPE13_MASK 0xCu
5023 #define LLWU_PE4_WUPE13_SHIFT 2
5024 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
5025 #define LLWU_PE4_WUPE14_MASK 0x30u
5026 #define LLWU_PE4_WUPE14_SHIFT 4
5027 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
5028 #define LLWU_PE4_WUPE15_MASK 0xC0u
5029 #define LLWU_PE4_WUPE15_SHIFT 6
5030 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
5032 #define LLWU_ME_WUME0_MASK 0x1u
5033 #define LLWU_ME_WUME0_SHIFT 0
5034 #define LLWU_ME_WUME1_MASK 0x2u
5035 #define LLWU_ME_WUME1_SHIFT 1
5036 #define LLWU_ME_WUME2_MASK 0x4u
5037 #define LLWU_ME_WUME2_SHIFT 2
5038 #define LLWU_ME_WUME3_MASK 0x8u
5039 #define LLWU_ME_WUME3_SHIFT 3
5040 #define LLWU_ME_WUME4_MASK 0x10u
5041 #define LLWU_ME_WUME4_SHIFT 4
5042 #define LLWU_ME_WUME5_MASK 0x20u
5043 #define LLWU_ME_WUME5_SHIFT 5
5044 #define LLWU_ME_WUME6_MASK 0x40u
5045 #define LLWU_ME_WUME6_SHIFT 6
5046 #define LLWU_ME_WUME7_MASK 0x80u
5047 #define LLWU_ME_WUME7_SHIFT 7
5049 #define LLWU_F1_WUF0_MASK 0x1u
5050 #define LLWU_F1_WUF0_SHIFT 0
5051 #define LLWU_F1_WUF1_MASK 0x2u
5052 #define LLWU_F1_WUF1_SHIFT 1
5053 #define LLWU_F1_WUF2_MASK 0x4u
5054 #define LLWU_F1_WUF2_SHIFT 2
5055 #define LLWU_F1_WUF3_MASK 0x8u
5056 #define LLWU_F1_WUF3_SHIFT 3
5057 #define LLWU_F1_WUF4_MASK 0x10u
5058 #define LLWU_F1_WUF4_SHIFT 4
5059 #define LLWU_F1_WUF5_MASK 0x20u
5060 #define LLWU_F1_WUF5_SHIFT 5
5061 #define LLWU_F1_WUF6_MASK 0x40u
5062 #define LLWU_F1_WUF6_SHIFT 6
5063 #define LLWU_F1_WUF7_MASK 0x80u
5064 #define LLWU_F1_WUF7_SHIFT 7
5066 #define LLWU_F2_WUF8_MASK 0x1u
5067 #define LLWU_F2_WUF8_SHIFT 0
5068 #define LLWU_F2_WUF9_MASK 0x2u
5069 #define LLWU_F2_WUF9_SHIFT 1
5070 #define LLWU_F2_WUF10_MASK 0x4u
5071 #define LLWU_F2_WUF10_SHIFT 2
5072 #define LLWU_F2_WUF11_MASK 0x8u
5073 #define LLWU_F2_WUF11_SHIFT 3
5074 #define LLWU_F2_WUF12_MASK 0x10u
5075 #define LLWU_F2_WUF12_SHIFT 4
5076 #define LLWU_F2_WUF13_MASK 0x20u
5077 #define LLWU_F2_WUF13_SHIFT 5
5078 #define LLWU_F2_WUF14_MASK 0x40u
5079 #define LLWU_F2_WUF14_SHIFT 6
5080 #define LLWU_F2_WUF15_MASK 0x80u
5081 #define LLWU_F2_WUF15_SHIFT 7
5083 #define LLWU_F3_MWUF0_MASK 0x1u
5084 #define LLWU_F3_MWUF0_SHIFT 0
5085 #define LLWU_F3_MWUF1_MASK 0x2u
5086 #define LLWU_F3_MWUF1_SHIFT 1
5087 #define LLWU_F3_MWUF2_MASK 0x4u
5088 #define LLWU_F3_MWUF2_SHIFT 2
5089 #define LLWU_F3_MWUF3_MASK 0x8u
5090 #define LLWU_F3_MWUF3_SHIFT 3
5091 #define LLWU_F3_MWUF4_MASK 0x10u
5092 #define LLWU_F3_MWUF4_SHIFT 4
5093 #define LLWU_F3_MWUF5_MASK 0x20u
5094 #define LLWU_F3_MWUF5_SHIFT 5
5095 #define LLWU_F3_MWUF6_MASK 0x40u
5096 #define LLWU_F3_MWUF6_SHIFT 6
5097 #define LLWU_F3_MWUF7_MASK 0x80u
5098 #define LLWU_F3_MWUF7_SHIFT 7
5099 /* FILT1 Bit Fields */
5100 #define LLWU_FILT1_FILTSEL_MASK 0xFu
5101 #define LLWU_FILT1_FILTSEL_SHIFT 0
5102 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
5103 #define LLWU_FILT1_FILTE_MASK 0x60u
5104 #define LLWU_FILT1_FILTE_SHIFT 5
5105 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
5106 #define LLWU_FILT1_FILTF_MASK 0x80u
5107 #define LLWU_FILT1_FILTF_SHIFT 7
5108 /* FILT2 Bit Fields */
5109 #define LLWU_FILT2_FILTSEL_MASK 0xFu
5110 #define LLWU_FILT2_FILTSEL_SHIFT 0
5111 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
5112 #define LLWU_FILT2_FILTE_MASK 0x60u
5113 #define LLWU_FILT2_FILTE_SHIFT 5
5114 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
5115 #define LLWU_FILT2_FILTF_MASK 0x80u
5116 #define LLWU_FILT2_FILTF_SHIFT 7
5120 */ /* end of group LLWU_Register_Masks */
5123 /* LLWU - Peripheral instance base addresses */
5124 /** Peripheral LLWU base address */
5125 #define LLWU_BASE (0x4007C000u)
5126 /** Peripheral LLWU base pointer */
5127 #define LLWU ((LLWU_Type *)LLWU_BASE)
5128 #define LLWU_BASE_PTR (LLWU)
5129 /** Array initializer of LLWU peripheral base addresses */
5130 #define LLWU_BASE_ADDRS { LLWU_BASE }
5131 /** Array initializer of LLWU peripheral base pointers */
5132 #define LLWU_BASE_PTRS { LLWU }
5133 /** Interrupt vectors for the LLWU peripheral type */
5134 #define LLWU_IRQS { LLW_IRQn }
5136 /* ----------------------------------------------------------------------------
5137 -- LLWU - Register accessor macros
5138 ---------------------------------------------------------------------------- */
5141 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
5146 /* LLWU - Register instance definitions */
5148 #define LLWU_PE1 LLWU_PE1_REG(LLWU)
5149 #define LLWU_PE2 LLWU_PE2_REG(LLWU)
5150 #define LLWU_PE3 LLWU_PE3_REG(LLWU)
5151 #define LLWU_PE4 LLWU_PE4_REG(LLWU)
5152 #define LLWU_ME LLWU_ME_REG(LLWU)
5153 #define LLWU_F1 LLWU_F1_REG(LLWU)
5154 #define LLWU_F2 LLWU_F2_REG(LLWU)
5155 #define LLWU_F3 LLWU_F3_REG(LLWU)
5156 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
5157 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
5161 */ /* end of group LLWU_Register_Accessor_Macros */
5166 */ /* end of group LLWU_Peripheral_Access_Layer */
5169 /* ----------------------------------------------------------------------------
5170 -- LPTMR Peripheral Access Layer
5171 ---------------------------------------------------------------------------- */
5174 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
5178 /** LPTMR - Register Layout Typedef */
5180 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
5181 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
5182 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
5183 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
5184 } LPTMR_Type, *LPTMR_MemMapPtr;
5186 /* ----------------------------------------------------------------------------
5187 -- LPTMR - Register accessor macros
5188 ---------------------------------------------------------------------------- */
5191 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
5196 /* LPTMR - Register accessors */
5197 #define LPTMR_CSR_REG(base) ((base)->CSR)
5198 #define LPTMR_PSR_REG(base) ((base)->PSR)
5199 #define LPTMR_CMR_REG(base) ((base)->CMR)
5200 #define LPTMR_CNR_REG(base) ((base)->CNR)
5204 */ /* end of group LPTMR_Register_Accessor_Macros */
5207 /* ----------------------------------------------------------------------------
5208 -- LPTMR Register Masks
5209 ---------------------------------------------------------------------------- */
5212 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
5216 /* CSR Bit Fields */
5217 #define LPTMR_CSR_TEN_MASK 0x1u
5218 #define LPTMR_CSR_TEN_SHIFT 0
5219 #define LPTMR_CSR_TMS_MASK 0x2u
5220 #define LPTMR_CSR_TMS_SHIFT 1
5221 #define LPTMR_CSR_TFC_MASK 0x4u
5222 #define LPTMR_CSR_TFC_SHIFT 2
5223 #define LPTMR_CSR_TPP_MASK 0x8u
5224 #define LPTMR_CSR_TPP_SHIFT 3
5225 #define LPTMR_CSR_TPS_MASK 0x30u
5226 #define LPTMR_CSR_TPS_SHIFT 4
5227 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
5228 #define LPTMR_CSR_TIE_MASK 0x40u
5229 #define LPTMR_CSR_TIE_SHIFT 6
5230 #define LPTMR_CSR_TCF_MASK 0x80u
5231 #define LPTMR_CSR_TCF_SHIFT 7
5232 /* PSR Bit Fields */
5233 #define LPTMR_PSR_PCS_MASK 0x3u
5234 #define LPTMR_PSR_PCS_SHIFT 0
5235 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
5236 #define LPTMR_PSR_PBYP_MASK 0x4u
5237 #define LPTMR_PSR_PBYP_SHIFT 2
5238 #define LPTMR_PSR_PRESCALE_MASK 0x78u
5239 #define LPTMR_PSR_PRESCALE_SHIFT 3
5240 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
5241 /* CMR Bit Fields */
5242 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
5243 #define LPTMR_CMR_COMPARE_SHIFT 0
5244 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
5245 /* CNR Bit Fields */
5246 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
5247 #define LPTMR_CNR_COUNTER_SHIFT 0
5248 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
5252 */ /* end of group LPTMR_Register_Masks */
5255 /* LPTMR - Peripheral instance base addresses */
5256 /** Peripheral LPTMR0 base address */
5257 #define LPTMR0_BASE (0x40040000u)
5258 /** Peripheral LPTMR0 base pointer */
5259 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
5260 #define LPTMR0_BASE_PTR (LPTMR0)
5261 /** Array initializer of LPTMR peripheral base addresses */
5262 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
5263 /** Array initializer of LPTMR peripheral base pointers */
5264 #define LPTMR_BASE_PTRS { LPTMR0 }
5265 /** Interrupt vectors for the LPTMR peripheral type */
5266 #define LPTMR_IRQS { LPTimer_IRQn }
5268 /* ----------------------------------------------------------------------------
5269 -- LPTMR - Register accessor macros
5270 ---------------------------------------------------------------------------- */
5273 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
5278 /* LPTMR - Register instance definitions */
5280 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
5281 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
5282 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
5283 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
5287 */ /* end of group LPTMR_Register_Accessor_Macros */
5292 */ /* end of group LPTMR_Peripheral_Access_Layer */
5295 /* ----------------------------------------------------------------------------
5296 -- LPUART Peripheral Access Layer
5297 ---------------------------------------------------------------------------- */
5300 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
5304 /** LPUART - Register Layout Typedef */
5306 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
5307 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
5308 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
5309 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
5310 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
5311 __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
5312 } LPUART_Type, *LPUART_MemMapPtr;
5314 /* ----------------------------------------------------------------------------
5315 -- LPUART - Register accessor macros
5316 ---------------------------------------------------------------------------- */
5319 * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
5324 /* LPUART - Register accessors */
5325 #define LPUART_BAUD_REG(base) ((base)->BAUD)
5326 #define LPUART_STAT_REG(base) ((base)->STAT)
5327 #define LPUART_CTRL_REG(base) ((base)->CTRL)
5328 #define LPUART_DATA_REG(base) ((base)->DATA)
5329 #define LPUART_MATCH_REG(base) ((base)->MATCH)
5330 #define LPUART_MODIR_REG(base) ((base)->MODIR)
5334 */ /* end of group LPUART_Register_Accessor_Macros */
5337 /* ----------------------------------------------------------------------------
5338 -- LPUART Register Masks
5339 ---------------------------------------------------------------------------- */
5342 * @addtogroup LPUART_Register_Masks LPUART Register Masks
5346 /* BAUD Bit Fields */
5347 #define LPUART_BAUD_SBR_MASK 0x1FFFu
5348 #define LPUART_BAUD_SBR_SHIFT 0
5349 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
5350 #define LPUART_BAUD_SBNS_MASK 0x2000u
5351 #define LPUART_BAUD_SBNS_SHIFT 13
5352 #define LPUART_BAUD_RXEDGIE_MASK 0x4000u
5353 #define LPUART_BAUD_RXEDGIE_SHIFT 14
5354 #define LPUART_BAUD_LBKDIE_MASK 0x8000u
5355 #define LPUART_BAUD_LBKDIE_SHIFT 15
5356 #define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
5357 #define LPUART_BAUD_RESYNCDIS_SHIFT 16
5358 #define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
5359 #define LPUART_BAUD_BOTHEDGE_SHIFT 17
5360 #define LPUART_BAUD_MATCFG_MASK 0xC0000u
5361 #define LPUART_BAUD_MATCFG_SHIFT 18
5362 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
5363 #define LPUART_BAUD_RDMAE_MASK 0x200000u
5364 #define LPUART_BAUD_RDMAE_SHIFT 21
5365 #define LPUART_BAUD_TDMAE_MASK 0x800000u
5366 #define LPUART_BAUD_TDMAE_SHIFT 23
5367 #define LPUART_BAUD_OSR_MASK 0x1F000000u
5368 #define LPUART_BAUD_OSR_SHIFT 24
5369 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
5370 #define LPUART_BAUD_M10_MASK 0x20000000u
5371 #define LPUART_BAUD_M10_SHIFT 29
5372 #define LPUART_BAUD_MAEN2_MASK 0x40000000u
5373 #define LPUART_BAUD_MAEN2_SHIFT 30
5374 #define LPUART_BAUD_MAEN1_MASK 0x80000000u
5375 #define LPUART_BAUD_MAEN1_SHIFT 31
5376 /* STAT Bit Fields */
5377 #define LPUART_STAT_MA2F_MASK 0x4000u
5378 #define LPUART_STAT_MA2F_SHIFT 14
5379 #define LPUART_STAT_MA1F_MASK 0x8000u
5380 #define LPUART_STAT_MA1F_SHIFT 15
5381 #define LPUART_STAT_PF_MASK 0x10000u
5382 #define LPUART_STAT_PF_SHIFT 16
5383 #define LPUART_STAT_FE_MASK 0x20000u
5384 #define LPUART_STAT_FE_SHIFT 17
5385 #define LPUART_STAT_NF_MASK 0x40000u
5386 #define LPUART_STAT_NF_SHIFT 18
5387 #define LPUART_STAT_OR_MASK 0x80000u
5388 #define LPUART_STAT_OR_SHIFT 19
5389 #define LPUART_STAT_IDLE_MASK 0x100000u
5390 #define LPUART_STAT_IDLE_SHIFT 20
5391 #define LPUART_STAT_RDRF_MASK 0x200000u
5392 #define LPUART_STAT_RDRF_SHIFT 21
5393 #define LPUART_STAT_TC_MASK 0x400000u
5394 #define LPUART_STAT_TC_SHIFT 22
5395 #define LPUART_STAT_TDRE_MASK 0x800000u
5396 #define LPUART_STAT_TDRE_SHIFT 23
5397 #define LPUART_STAT_RAF_MASK 0x1000000u
5398 #define LPUART_STAT_RAF_SHIFT 24
5399 #define LPUART_STAT_LBKDE_MASK 0x2000000u
5400 #define LPUART_STAT_LBKDE_SHIFT 25
5401 #define LPUART_STAT_BRK13_MASK 0x4000000u
5402 #define LPUART_STAT_BRK13_SHIFT 26
5403 #define LPUART_STAT_RWUID_MASK 0x8000000u
5404 #define LPUART_STAT_RWUID_SHIFT 27
5405 #define LPUART_STAT_RXINV_MASK 0x10000000u
5406 #define LPUART_STAT_RXINV_SHIFT 28
5407 #define LPUART_STAT_MSBF_MASK 0x20000000u
5408 #define LPUART_STAT_MSBF_SHIFT 29
5409 #define LPUART_STAT_RXEDGIF_MASK 0x40000000u
5410 #define LPUART_STAT_RXEDGIF_SHIFT 30
5411 #define LPUART_STAT_LBKDIF_MASK 0x80000000u
5412 #define LPUART_STAT_LBKDIF_SHIFT 31
5413 /* CTRL Bit Fields */
5414 #define LPUART_CTRL_PT_MASK 0x1u
5415 #define LPUART_CTRL_PT_SHIFT 0
5416 #define LPUART_CTRL_PE_MASK 0x2u
5417 #define LPUART_CTRL_PE_SHIFT 1
5418 #define LPUART_CTRL_ILT_MASK 0x4u
5419 #define LPUART_CTRL_ILT_SHIFT 2
5420 #define LPUART_CTRL_WAKE_MASK 0x8u
5421 #define LPUART_CTRL_WAKE_SHIFT 3
5422 #define LPUART_CTRL_M_MASK 0x10u
5423 #define LPUART_CTRL_M_SHIFT 4
5424 #define LPUART_CTRL_RSRC_MASK 0x20u
5425 #define LPUART_CTRL_RSRC_SHIFT 5
5426 #define LPUART_CTRL_DOZEEN_MASK 0x40u
5427 #define LPUART_CTRL_DOZEEN_SHIFT 6
5428 #define LPUART_CTRL_LOOPS_MASK 0x80u
5429 #define LPUART_CTRL_LOOPS_SHIFT 7
5430 #define LPUART_CTRL_IDLECFG_MASK 0x700u
5431 #define LPUART_CTRL_IDLECFG_SHIFT 8
5432 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
5433 #define LPUART_CTRL_MA2IE_MASK 0x4000u
5434 #define LPUART_CTRL_MA2IE_SHIFT 14
5435 #define LPUART_CTRL_MA1IE_MASK 0x8000u
5436 #define LPUART_CTRL_MA1IE_SHIFT 15
5437 #define LPUART_CTRL_SBK_MASK 0x10000u
5438 #define LPUART_CTRL_SBK_SHIFT 16
5439 #define LPUART_CTRL_RWU_MASK 0x20000u
5440 #define LPUART_CTRL_RWU_SHIFT 17
5441 #define LPUART_CTRL_RE_MASK 0x40000u
5442 #define LPUART_CTRL_RE_SHIFT 18
5443 #define LPUART_CTRL_TE_MASK 0x80000u
5444 #define LPUART_CTRL_TE_SHIFT 19
5445 #define LPUART_CTRL_ILIE_MASK 0x100000u
5446 #define LPUART_CTRL_ILIE_SHIFT 20
5447 #define LPUART_CTRL_RIE_MASK 0x200000u
5448 #define LPUART_CTRL_RIE_SHIFT 21
5449 #define LPUART_CTRL_TCIE_MASK 0x400000u
5450 #define LPUART_CTRL_TCIE_SHIFT 22
5451 #define LPUART_CTRL_TIE_MASK 0x800000u
5452 #define LPUART_CTRL_TIE_SHIFT 23
5453 #define LPUART_CTRL_PEIE_MASK 0x1000000u
5454 #define LPUART_CTRL_PEIE_SHIFT 24
5455 #define LPUART_CTRL_FEIE_MASK 0x2000000u
5456 #define LPUART_CTRL_FEIE_SHIFT 25
5457 #define LPUART_CTRL_NEIE_MASK 0x4000000u
5458 #define LPUART_CTRL_NEIE_SHIFT 26
5459 #define LPUART_CTRL_ORIE_MASK 0x8000000u
5460 #define LPUART_CTRL_ORIE_SHIFT 27
5461 #define LPUART_CTRL_TXINV_MASK 0x10000000u
5462 #define LPUART_CTRL_TXINV_SHIFT 28
5463 #define LPUART_CTRL_TXDIR_MASK 0x20000000u
5464 #define LPUART_CTRL_TXDIR_SHIFT 29
5465 #define LPUART_CTRL_R9T8_MASK 0x40000000u
5466 #define LPUART_CTRL_R9T8_SHIFT 30
5467 #define LPUART_CTRL_R8T9_MASK 0x80000000u
5468 #define LPUART_CTRL_R8T9_SHIFT 31
5469 /* DATA Bit Fields */
5470 #define LPUART_DATA_R0T0_MASK 0x1u
5471 #define LPUART_DATA_R0T0_SHIFT 0
5472 #define LPUART_DATA_R1T1_MASK 0x2u
5473 #define LPUART_DATA_R1T1_SHIFT 1
5474 #define LPUART_DATA_R2T2_MASK 0x4u
5475 #define LPUART_DATA_R2T2_SHIFT 2
5476 #define LPUART_DATA_R3T3_MASK 0x8u
5477 #define LPUART_DATA_R3T3_SHIFT 3
5478 #define LPUART_DATA_R4T4_MASK 0x10u
5479 #define LPUART_DATA_R4T4_SHIFT 4
5480 #define LPUART_DATA_R5T5_MASK 0x20u
5481 #define LPUART_DATA_R5T5_SHIFT 5
5482 #define LPUART_DATA_R6T6_MASK 0x40u
5483 #define LPUART_DATA_R6T6_SHIFT 6
5484 #define LPUART_DATA_R7T7_MASK 0x80u
5485 #define LPUART_DATA_R7T7_SHIFT 7
5486 #define LPUART_DATA_R8T8_MASK 0x100u
5487 #define LPUART_DATA_R8T8_SHIFT 8
5488 #define LPUART_DATA_R9T9_MASK 0x200u
5489 #define LPUART_DATA_R9T9_SHIFT 9
5490 #define LPUART_DATA_IDLINE_MASK 0x800u
5491 #define LPUART_DATA_IDLINE_SHIFT 11
5492 #define LPUART_DATA_RXEMPT_MASK 0x1000u
5493 #define LPUART_DATA_RXEMPT_SHIFT 12
5494 #define LPUART_DATA_FRETSC_MASK 0x2000u
5495 #define LPUART_DATA_FRETSC_SHIFT 13
5496 #define LPUART_DATA_PARITYE_MASK 0x4000u
5497 #define LPUART_DATA_PARITYE_SHIFT 14
5498 #define LPUART_DATA_NOISY_MASK 0x8000u
5499 #define LPUART_DATA_NOISY_SHIFT 15
5500 /* MATCH Bit Fields */
5501 #define LPUART_MATCH_MA1_MASK 0x3FFu
5502 #define LPUART_MATCH_MA1_SHIFT 0
5503 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
5504 #define LPUART_MATCH_MA2_MASK 0x3FF0000u
5505 #define LPUART_MATCH_MA2_SHIFT 16
5506 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
5507 /* MODIR Bit Fields */
5508 #define LPUART_MODIR_TXCTSE_MASK 0x1u
5509 #define LPUART_MODIR_TXCTSE_SHIFT 0
5510 #define LPUART_MODIR_TXRTSE_MASK 0x2u
5511 #define LPUART_MODIR_TXRTSE_SHIFT 1
5512 #define LPUART_MODIR_TXRTSPOL_MASK 0x4u
5513 #define LPUART_MODIR_TXRTSPOL_SHIFT 2
5514 #define LPUART_MODIR_RXRTSE_MASK 0x8u
5515 #define LPUART_MODIR_RXRTSE_SHIFT 3
5516 #define LPUART_MODIR_TXCTSC_MASK 0x10u
5517 #define LPUART_MODIR_TXCTSC_SHIFT 4
5518 #define LPUART_MODIR_TXCTSSRC_MASK 0x20u
5519 #define LPUART_MODIR_TXCTSSRC_SHIFT 5
5520 #define LPUART_MODIR_TNP_MASK 0x30000u
5521 #define LPUART_MODIR_TNP_SHIFT 16
5522 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TNP_SHIFT))&LPUART_MODIR_TNP_MASK)
5523 #define LPUART_MODIR_IREN_MASK 0x40000u
5524 #define LPUART_MODIR_IREN_SHIFT 18
5528 */ /* end of group LPUART_Register_Masks */
5531 /* LPUART - Peripheral instance base addresses */
5532 /** Peripheral LPUART0 base address */
5533 #define LPUART0_BASE (0x4002A000u)
5534 /** Peripheral LPUART0 base pointer */
5535 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
5536 #define LPUART0_BASE_PTR (LPUART0)
5537 /** Array initializer of LPUART peripheral base addresses */
5538 #define LPUART_BASE_ADDRS { LPUART0_BASE }
5539 /** Array initializer of LPUART peripheral base pointers */
5540 #define LPUART_BASE_PTRS { LPUART0 }
5541 /** Interrupt vectors for the LPUART peripheral type */
5542 #define LPUART_RX_TX_IRQS { LPUART0_IRQn }
5543 #define LPUART_ERR_IRQS { LPUART0_IRQn }
5545 /* ----------------------------------------------------------------------------
5546 -- LPUART - Register accessor macros
5547 ---------------------------------------------------------------------------- */
5550 * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
5555 /* LPUART - Register instance definitions */
5557 #define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
5558 #define LPUART0_STAT LPUART_STAT_REG(LPUART0)
5559 #define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
5560 #define LPUART0_DATA LPUART_DATA_REG(LPUART0)
5561 #define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
5562 #define LPUART0_MODIR LPUART_MODIR_REG(LPUART0)
5566 */ /* end of group LPUART_Register_Accessor_Macros */
5571 */ /* end of group LPUART_Peripheral_Access_Layer */
5574 /* ----------------------------------------------------------------------------
5575 -- MCG Peripheral Access Layer
5576 ---------------------------------------------------------------------------- */
5579 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
5583 /** MCG - Register Layout Typedef */
5585 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
5586 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
5587 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
5588 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
5589 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
5590 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
5591 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
5592 uint8_t RESERVED_0[1];
5593 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
5594 uint8_t RESERVED_1[1];
5595 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
5596 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
5597 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
5598 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
5599 } MCG_Type, *MCG_MemMapPtr;
5601 /* ----------------------------------------------------------------------------
5602 -- MCG - Register accessor macros
5603 ---------------------------------------------------------------------------- */
5606 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
5611 /* MCG - Register accessors */
5612 #define MCG_C1_REG(base) ((base)->C1)
5613 #define MCG_C2_REG(base) ((base)->C2)
5614 #define MCG_C3_REG(base) ((base)->C3)
5615 #define MCG_C4_REG(base) ((base)->C4)
5616 #define MCG_C5_REG(base) ((base)->C5)
5617 #define MCG_C6_REG(base) ((base)->C6)
5618 #define MCG_S_REG(base) ((base)->S)
5619 #define MCG_SC_REG(base) ((base)->SC)
5620 #define MCG_ATCVH_REG(base) ((base)->ATCVH)
5621 #define MCG_ATCVL_REG(base) ((base)->ATCVL)
5622 #define MCG_C7_REG(base) ((base)->C7)
5623 #define MCG_C8_REG(base) ((base)->C8)
5627 */ /* end of group MCG_Register_Accessor_Macros */
5630 /* ----------------------------------------------------------------------------
5631 -- MCG Register Masks
5632 ---------------------------------------------------------------------------- */
5635 * @addtogroup MCG_Register_Masks MCG Register Masks
5640 #define MCG_C1_IREFSTEN_MASK 0x1u
5641 #define MCG_C1_IREFSTEN_SHIFT 0
5642 #define MCG_C1_IRCLKEN_MASK 0x2u
5643 #define MCG_C1_IRCLKEN_SHIFT 1
5644 #define MCG_C1_IREFS_MASK 0x4u
5645 #define MCG_C1_IREFS_SHIFT 2
5646 #define MCG_C1_FRDIV_MASK 0x38u
5647 #define MCG_C1_FRDIV_SHIFT 3
5648 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
5649 #define MCG_C1_CLKS_MASK 0xC0u
5650 #define MCG_C1_CLKS_SHIFT 6
5651 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
5653 #define MCG_C2_IRCS_MASK 0x1u
5654 #define MCG_C2_IRCS_SHIFT 0
5655 #define MCG_C2_LP_MASK 0x2u
5656 #define MCG_C2_LP_SHIFT 1
5657 #define MCG_C2_EREFS_MASK 0x4u
5658 #define MCG_C2_EREFS_SHIFT 2
5659 #define MCG_C2_HGO_MASK 0x8u
5660 #define MCG_C2_HGO_SHIFT 3
5661 #define MCG_C2_RANGE_MASK 0x30u
5662 #define MCG_C2_RANGE_SHIFT 4
5663 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
5664 #define MCG_C2_FCFTRIM_MASK 0x40u
5665 #define MCG_C2_FCFTRIM_SHIFT 6
5666 #define MCG_C2_LOCRE0_MASK 0x80u
5667 #define MCG_C2_LOCRE0_SHIFT 7
5669 #define MCG_C3_SCTRIM_MASK 0xFFu
5670 #define MCG_C3_SCTRIM_SHIFT 0
5671 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
5673 #define MCG_C4_SCFTRIM_MASK 0x1u
5674 #define MCG_C4_SCFTRIM_SHIFT 0
5675 #define MCG_C4_FCTRIM_MASK 0x1Eu
5676 #define MCG_C4_FCTRIM_SHIFT 1
5677 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
5678 #define MCG_C4_DRST_DRS_MASK 0x60u
5679 #define MCG_C4_DRST_DRS_SHIFT 5
5680 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
5681 #define MCG_C4_DMX32_MASK 0x80u
5682 #define MCG_C4_DMX32_SHIFT 7
5684 #define MCG_C5_PRDIV0_MASK 0x1Fu
5685 #define MCG_C5_PRDIV0_SHIFT 0
5686 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
5687 #define MCG_C5_PLLSTEN0_MASK 0x20u
5688 #define MCG_C5_PLLSTEN0_SHIFT 5
5689 #define MCG_C5_PLLCLKEN0_MASK 0x40u
5690 #define MCG_C5_PLLCLKEN0_SHIFT 6
5692 #define MCG_C6_VDIV0_MASK 0x1Fu
5693 #define MCG_C6_VDIV0_SHIFT 0
5694 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
5695 #define MCG_C6_CME0_MASK 0x20u
5696 #define MCG_C6_CME0_SHIFT 5
5697 #define MCG_C6_PLLS_MASK 0x40u
5698 #define MCG_C6_PLLS_SHIFT 6
5699 #define MCG_C6_LOLIE0_MASK 0x80u
5700 #define MCG_C6_LOLIE0_SHIFT 7
5702 #define MCG_S_IRCST_MASK 0x1u
5703 #define MCG_S_IRCST_SHIFT 0
5704 #define MCG_S_OSCINIT0_MASK 0x2u
5705 #define MCG_S_OSCINIT0_SHIFT 1
5706 #define MCG_S_CLKST_MASK 0xCu
5707 #define MCG_S_CLKST_SHIFT 2
5708 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
5709 #define MCG_S_IREFST_MASK 0x10u
5710 #define MCG_S_IREFST_SHIFT 4
5711 #define MCG_S_PLLST_MASK 0x20u
5712 #define MCG_S_PLLST_SHIFT 5
5713 #define MCG_S_LOCK0_MASK 0x40u
5714 #define MCG_S_LOCK0_SHIFT 6
5715 #define MCG_S_LOLS0_MASK 0x80u
5716 #define MCG_S_LOLS0_SHIFT 7
5718 #define MCG_SC_LOCS0_MASK 0x1u
5719 #define MCG_SC_LOCS0_SHIFT 0
5720 #define MCG_SC_FCRDIV_MASK 0xEu
5721 #define MCG_SC_FCRDIV_SHIFT 1
5722 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
5723 #define MCG_SC_FLTPRSRV_MASK 0x10u
5724 #define MCG_SC_FLTPRSRV_SHIFT 4
5725 #define MCG_SC_ATMF_MASK 0x20u
5726 #define MCG_SC_ATMF_SHIFT 5
5727 #define MCG_SC_ATMS_MASK 0x40u
5728 #define MCG_SC_ATMS_SHIFT 6
5729 #define MCG_SC_ATME_MASK 0x80u
5730 #define MCG_SC_ATME_SHIFT 7
5731 /* ATCVH Bit Fields */
5732 #define MCG_ATCVH_ATCVH_MASK 0xFFu
5733 #define MCG_ATCVH_ATCVH_SHIFT 0
5734 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
5735 /* ATCVL Bit Fields */
5736 #define MCG_ATCVL_ATCVL_MASK 0xFFu
5737 #define MCG_ATCVL_ATCVL_SHIFT 0
5738 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
5740 #define MCG_C7_OSCSEL_MASK 0x3u
5741 #define MCG_C7_OSCSEL_SHIFT 0
5742 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
5744 #define MCG_C8_LOCS1_MASK 0x1u
5745 #define MCG_C8_LOCS1_SHIFT 0
5746 #define MCG_C8_CME1_MASK 0x20u
5747 #define MCG_C8_CME1_SHIFT 5
5748 #define MCG_C8_LOLRE_MASK 0x40u
5749 #define MCG_C8_LOLRE_SHIFT 6
5750 #define MCG_C8_LOCRE1_MASK 0x80u
5751 #define MCG_C8_LOCRE1_SHIFT 7
5755 */ /* end of group MCG_Register_Masks */
5758 /* MCG - Peripheral instance base addresses */
5759 /** Peripheral MCG base address */
5760 #define MCG_BASE (0x40064000u)
5761 /** Peripheral MCG base pointer */
5762 #define MCG ((MCG_Type *)MCG_BASE)
5763 #define MCG_BASE_PTR (MCG)
5764 /** Array initializer of MCG peripheral base addresses */
5765 #define MCG_BASE_ADDRS { MCG_BASE }
5766 /** Array initializer of MCG peripheral base pointers */
5767 #define MCG_BASE_PTRS { MCG }
5769 /* ----------------------------------------------------------------------------
5770 -- MCG - Register accessor macros
5771 ---------------------------------------------------------------------------- */
5774 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
5779 /* MCG - Register instance definitions */
5781 #define MCG_C1 MCG_C1_REG(MCG)
5782 #define MCG_C2 MCG_C2_REG(MCG)
5783 #define MCG_C3 MCG_C3_REG(MCG)
5784 #define MCG_C4 MCG_C4_REG(MCG)
5785 #define MCG_C5 MCG_C5_REG(MCG)
5786 #define MCG_C6 MCG_C6_REG(MCG)
5787 #define MCG_S MCG_S_REG(MCG)
5788 #define MCG_SC MCG_SC_REG(MCG)
5789 #define MCG_ATCVH MCG_ATCVH_REG(MCG)
5790 #define MCG_ATCVL MCG_ATCVL_REG(MCG)
5791 #define MCG_C7 MCG_C7_REG(MCG)
5792 #define MCG_C8 MCG_C8_REG(MCG)
5796 */ /* end of group MCG_Register_Accessor_Macros */
5801 */ /* end of group MCG_Peripheral_Access_Layer */
5804 /* ----------------------------------------------------------------------------
5805 -- MCM Peripheral Access Layer
5806 ---------------------------------------------------------------------------- */
5809 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
5813 /** MCM - Register Layout Typedef */
5815 uint8_t RESERVED_0[8];
5816 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
5817 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
5818 __IO uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
5819 __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */
5820 uint8_t RESERVED_1[44];
5821 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
5822 } MCM_Type, *MCM_MemMapPtr;
5824 /* ----------------------------------------------------------------------------
5825 -- MCM - Register accessor macros
5826 ---------------------------------------------------------------------------- */
5829 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
5834 /* MCM - Register accessors */
5835 #define MCM_PLASC_REG(base) ((base)->PLASC)
5836 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
5837 #define MCM_PLACR_REG(base) ((base)->PLACR)
5838 #define MCM_ISCR_REG(base) ((base)->ISCR)
5839 #define MCM_CPO_REG(base) ((base)->CPO)
5843 */ /* end of group MCM_Register_Accessor_Macros */
5846 /* ----------------------------------------------------------------------------
5847 -- MCM Register Masks
5848 ---------------------------------------------------------------------------- */
5851 * @addtogroup MCM_Register_Masks MCM Register Masks
5855 /* PLASC Bit Fields */
5856 #define MCM_PLASC_ASC_MASK 0xFFu
5857 #define MCM_PLASC_ASC_SHIFT 0
5858 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
5859 /* PLAMC Bit Fields */
5860 #define MCM_PLAMC_AMC_MASK 0xFFu
5861 #define MCM_PLAMC_AMC_SHIFT 0
5862 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
5863 /* PLACR Bit Fields */
5864 #define MCM_PLACR_ARB_MASK 0x200u
5865 #define MCM_PLACR_ARB_SHIFT 9
5866 /* ISCR Bit Fields */
5867 #define MCM_ISCR_FIOC_MASK 0x100u
5868 #define MCM_ISCR_FIOC_SHIFT 8
5869 #define MCM_ISCR_FDZC_MASK 0x200u
5870 #define MCM_ISCR_FDZC_SHIFT 9
5871 #define MCM_ISCR_FOFC_MASK 0x400u
5872 #define MCM_ISCR_FOFC_SHIFT 10
5873 #define MCM_ISCR_FUFC_MASK 0x800u
5874 #define MCM_ISCR_FUFC_SHIFT 11
5875 #define MCM_ISCR_FIXC_MASK 0x1000u
5876 #define MCM_ISCR_FIXC_SHIFT 12
5877 #define MCM_ISCR_FIDC_MASK 0x8000u
5878 #define MCM_ISCR_FIDC_SHIFT 15
5879 #define MCM_ISCR_FIOCE_MASK 0x1000000u
5880 #define MCM_ISCR_FIOCE_SHIFT 24
5881 #define MCM_ISCR_FDZCE_MASK 0x2000000u
5882 #define MCM_ISCR_FDZCE_SHIFT 25
5883 #define MCM_ISCR_FOFCE_MASK 0x4000000u
5884 #define MCM_ISCR_FOFCE_SHIFT 26
5885 #define MCM_ISCR_FUFCE_MASK 0x8000000u
5886 #define MCM_ISCR_FUFCE_SHIFT 27
5887 #define MCM_ISCR_FIXCE_MASK 0x10000000u
5888 #define MCM_ISCR_FIXCE_SHIFT 28
5889 #define MCM_ISCR_FIDCE_MASK 0x80000000u
5890 #define MCM_ISCR_FIDCE_SHIFT 31
5891 /* CPO Bit Fields */
5892 #define MCM_CPO_CPOREQ_MASK 0x1u
5893 #define MCM_CPO_CPOREQ_SHIFT 0
5894 #define MCM_CPO_CPOACK_MASK 0x2u
5895 #define MCM_CPO_CPOACK_SHIFT 1
5896 #define MCM_CPO_CPOWOI_MASK 0x4u
5897 #define MCM_CPO_CPOWOI_SHIFT 2
5901 */ /* end of group MCM_Register_Masks */
5904 /* MCM - Peripheral instance base addresses */
5905 /** Peripheral MCM base address */
5906 #define MCM_BASE (0xE0080000u)
5907 /** Peripheral MCM base pointer */
5908 #define MCM ((MCM_Type *)MCM_BASE)
5909 #define MCM_BASE_PTR (MCM)
5910 /** Array initializer of MCM peripheral base addresses */
5911 #define MCM_BASE_ADDRS { MCM_BASE }
5912 /** Array initializer of MCM peripheral base pointers */
5913 #define MCM_BASE_PTRS { MCM }
5915 /* ----------------------------------------------------------------------------
5916 -- MCM - Register accessor macros
5917 ---------------------------------------------------------------------------- */
5920 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
5925 /* MCM - Register instance definitions */
5927 #define MCM_PLASC MCM_PLASC_REG(MCM)
5928 #define MCM_PLAMC MCM_PLAMC_REG(MCM)
5929 #define MCM_PLACR MCM_PLACR_REG(MCM)
5930 #define MCM_ISCR MCM_ISCR_REG(MCM)
5931 #define MCM_CPO MCM_CPO_REG(MCM)
5935 */ /* end of group MCM_Register_Accessor_Macros */
5940 */ /* end of group MCM_Peripheral_Access_Layer */
5943 /* ----------------------------------------------------------------------------
5944 -- NV Peripheral Access Layer
5945 ---------------------------------------------------------------------------- */
5948 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
5952 /** NV - Register Layout Typedef */
5954 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
5955 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
5956 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
5957 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
5958 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
5959 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
5960 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
5961 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
5962 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
5963 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
5964 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
5965 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
5966 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
5967 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
5968 } NV_Type, *NV_MemMapPtr;
5970 /* ----------------------------------------------------------------------------
5971 -- NV - Register accessor macros
5972 ---------------------------------------------------------------------------- */
5975 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
5980 /* NV - Register accessors */
5981 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
5982 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
5983 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
5984 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
5985 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
5986 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
5987 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
5988 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
5989 #define NV_FPROT3_REG(base) ((base)->FPROT3)
5990 #define NV_FPROT2_REG(base) ((base)->FPROT2)
5991 #define NV_FPROT1_REG(base) ((base)->FPROT1)
5992 #define NV_FPROT0_REG(base) ((base)->FPROT0)
5993 #define NV_FSEC_REG(base) ((base)->FSEC)
5994 #define NV_FOPT_REG(base) ((base)->FOPT)
5998 */ /* end of group NV_Register_Accessor_Macros */
6001 /* ----------------------------------------------------------------------------
6002 -- NV Register Masks
6003 ---------------------------------------------------------------------------- */
6006 * @addtogroup NV_Register_Masks NV Register Masks
6010 /* BACKKEY3 Bit Fields */
6011 #define NV_BACKKEY3_KEY_MASK 0xFFu
6012 #define NV_BACKKEY3_KEY_SHIFT 0
6013 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
6014 /* BACKKEY2 Bit Fields */
6015 #define NV_BACKKEY2_KEY_MASK 0xFFu
6016 #define NV_BACKKEY2_KEY_SHIFT 0
6017 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
6018 /* BACKKEY1 Bit Fields */
6019 #define NV_BACKKEY1_KEY_MASK 0xFFu
6020 #define NV_BACKKEY1_KEY_SHIFT 0
6021 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
6022 /* BACKKEY0 Bit Fields */
6023 #define NV_BACKKEY0_KEY_MASK 0xFFu
6024 #define NV_BACKKEY0_KEY_SHIFT 0
6025 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
6026 /* BACKKEY7 Bit Fields */
6027 #define NV_BACKKEY7_KEY_MASK 0xFFu
6028 #define NV_BACKKEY7_KEY_SHIFT 0
6029 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
6030 /* BACKKEY6 Bit Fields */
6031 #define NV_BACKKEY6_KEY_MASK 0xFFu
6032 #define NV_BACKKEY6_KEY_SHIFT 0
6033 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
6034 /* BACKKEY5 Bit Fields */
6035 #define NV_BACKKEY5_KEY_MASK 0xFFu
6036 #define NV_BACKKEY5_KEY_SHIFT 0
6037 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
6038 /* BACKKEY4 Bit Fields */
6039 #define NV_BACKKEY4_KEY_MASK 0xFFu
6040 #define NV_BACKKEY4_KEY_SHIFT 0
6041 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
6042 /* FPROT3 Bit Fields */
6043 #define NV_FPROT3_PROT_MASK 0xFFu
6044 #define NV_FPROT3_PROT_SHIFT 0
6045 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
6046 /* FPROT2 Bit Fields */
6047 #define NV_FPROT2_PROT_MASK 0xFFu
6048 #define NV_FPROT2_PROT_SHIFT 0
6049 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
6050 /* FPROT1 Bit Fields */
6051 #define NV_FPROT1_PROT_MASK 0xFFu
6052 #define NV_FPROT1_PROT_SHIFT 0
6053 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
6054 /* FPROT0 Bit Fields */
6055 #define NV_FPROT0_PROT_MASK 0xFFu
6056 #define NV_FPROT0_PROT_SHIFT 0
6057 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
6058 /* FSEC Bit Fields */
6059 #define NV_FSEC_SEC_MASK 0x3u
6060 #define NV_FSEC_SEC_SHIFT 0
6061 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
6062 #define NV_FSEC_FSLACC_MASK 0xCu
6063 #define NV_FSEC_FSLACC_SHIFT 2
6064 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
6065 #define NV_FSEC_MEEN_MASK 0x30u
6066 #define NV_FSEC_MEEN_SHIFT 4
6067 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
6068 #define NV_FSEC_KEYEN_MASK 0xC0u
6069 #define NV_FSEC_KEYEN_SHIFT 6
6070 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
6071 /* FOPT Bit Fields */
6072 #define NV_FOPT_LPBOOT_MASK 0x1u
6073 #define NV_FOPT_LPBOOT_SHIFT 0
6074 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
6075 #define NV_FOPT_EZPORT_DIS_SHIFT 1
6076 #define NV_FOPT_NMI_DIS_MASK 0x4u
6077 #define NV_FOPT_NMI_DIS_SHIFT 2
6078 #define NV_FOPT_FAST_INIT_MASK 0x20u
6079 #define NV_FOPT_FAST_INIT_SHIFT 5
6083 */ /* end of group NV_Register_Masks */
6086 /* NV - Peripheral instance base addresses */
6087 /** Peripheral FTFA_FlashConfig base address */
6088 #define FTFA_FlashConfig_BASE (0x400u)
6089 /** Peripheral FTFA_FlashConfig base pointer */
6090 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
6091 #define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
6092 /** Array initializer of NV peripheral base addresses */
6093 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
6094 /** Array initializer of NV peripheral base pointers */
6095 #define NV_BASE_PTRS { FTFA_FlashConfig }
6097 /* ----------------------------------------------------------------------------
6098 -- NV - Register accessor macros
6099 ---------------------------------------------------------------------------- */
6102 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
6107 /* NV - Register instance definitions */
6108 /* FTFA_FlashConfig */
6109 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
6110 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
6111 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
6112 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
6113 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
6114 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
6115 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
6116 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
6117 #define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
6118 #define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
6119 #define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
6120 #define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
6121 #define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
6122 #define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
6126 */ /* end of group NV_Register_Accessor_Macros */
6131 */ /* end of group NV_Peripheral_Access_Layer */
6134 /* ----------------------------------------------------------------------------
6135 -- OSC Peripheral Access Layer
6136 ---------------------------------------------------------------------------- */
6139 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
6143 /** OSC - Register Layout Typedef */
6145 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
6146 uint8_t RESERVED_0[1];
6147 __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
6148 } OSC_Type, *OSC_MemMapPtr;
6150 /* ----------------------------------------------------------------------------
6151 -- OSC - Register accessor macros
6152 ---------------------------------------------------------------------------- */
6155 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
6160 /* OSC - Register accessors */
6161 #define OSC_CR_REG(base) ((base)->CR)
6162 #define OSC_DIV_REG(base) ((base)->DIV)
6166 */ /* end of group OSC_Register_Accessor_Macros */
6169 /* ----------------------------------------------------------------------------
6170 -- OSC Register Masks
6171 ---------------------------------------------------------------------------- */
6174 * @addtogroup OSC_Register_Masks OSC Register Masks
6179 #define OSC_CR_SC16P_MASK 0x1u
6180 #define OSC_CR_SC16P_SHIFT 0
6181 #define OSC_CR_SC8P_MASK 0x2u
6182 #define OSC_CR_SC8P_SHIFT 1
6183 #define OSC_CR_SC4P_MASK 0x4u
6184 #define OSC_CR_SC4P_SHIFT 2
6185 #define OSC_CR_SC2P_MASK 0x8u
6186 #define OSC_CR_SC2P_SHIFT 3
6187 #define OSC_CR_EREFSTEN_MASK 0x20u
6188 #define OSC_CR_EREFSTEN_SHIFT 5
6189 #define OSC_CR_ERCLKEN_MASK 0x80u
6190 #define OSC_CR_ERCLKEN_SHIFT 7
6191 /* DIV Bit Fields */
6192 #define OSC_DIV_ERPS_MASK 0xC0u
6193 #define OSC_DIV_ERPS_SHIFT 6
6194 #define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x))<<OSC_DIV_ERPS_SHIFT))&OSC_DIV_ERPS_MASK)
6198 */ /* end of group OSC_Register_Masks */
6201 /* OSC - Peripheral instance base addresses */
6202 /** Peripheral OSC base address */
6203 #define OSC_BASE (0x40065000u)
6204 /** Peripheral OSC base pointer */
6205 #define OSC ((OSC_Type *)OSC_BASE)
6206 #define OSC_BASE_PTR (OSC)
6207 /** Array initializer of OSC peripheral base addresses */
6208 #define OSC_BASE_ADDRS { OSC_BASE }
6209 /** Array initializer of OSC peripheral base pointers */
6210 #define OSC_BASE_PTRS { OSC }
6212 /* ----------------------------------------------------------------------------
6213 -- OSC - Register accessor macros
6214 ---------------------------------------------------------------------------- */
6217 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
6222 /* OSC - Register instance definitions */
6224 #define OSC_CR OSC_CR_REG(OSC)
6225 #define OSC_DIV OSC_DIV_REG(OSC)
6229 */ /* end of group OSC_Register_Accessor_Macros */
6234 */ /* end of group OSC_Peripheral_Access_Layer */
6237 /* ----------------------------------------------------------------------------
6238 -- PDB Peripheral Access Layer
6239 ---------------------------------------------------------------------------- */
6242 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
6246 /** PDB - Register Layout Typedef */
6248 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
6249 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
6250 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
6251 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
6252 struct { /* offset: 0x10, array step: 0x28 */
6253 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
6254 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
6255 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
6256 uint8_t RESERVED_0[24];
6258 uint8_t RESERVED_0[240];
6259 struct { /* offset: 0x150, array step: 0x8 */
6260 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
6261 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
6263 uint8_t RESERVED_1[48];
6264 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
6265 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
6266 } PDB_Type, *PDB_MemMapPtr;
6268 /* ----------------------------------------------------------------------------
6269 -- PDB - Register accessor macros
6270 ---------------------------------------------------------------------------- */
6273 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
6278 /* PDB - Register accessors */
6279 #define PDB_SC_REG(base) ((base)->SC)
6280 #define PDB_MOD_REG(base) ((base)->MOD)
6281 #define PDB_CNT_REG(base) ((base)->CNT)
6282 #define PDB_IDLY_REG(base) ((base)->IDLY)
6283 #define PDB_C1_REG(base,index) ((base)->CH[index].C1)
6284 #define PDB_S_REG(base,index) ((base)->CH[index].S)
6285 #define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
6286 #define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
6287 #define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
6288 #define PDB_POEN_REG(base) ((base)->POEN)
6289 #define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
6293 */ /* end of group PDB_Register_Accessor_Macros */
6296 /* ----------------------------------------------------------------------------
6297 -- PDB Register Masks
6298 ---------------------------------------------------------------------------- */
6301 * @addtogroup PDB_Register_Masks PDB Register Masks
6306 #define PDB_SC_LDOK_MASK 0x1u
6307 #define PDB_SC_LDOK_SHIFT 0
6308 #define PDB_SC_CONT_MASK 0x2u
6309 #define PDB_SC_CONT_SHIFT 1
6310 #define PDB_SC_MULT_MASK 0xCu
6311 #define PDB_SC_MULT_SHIFT 2
6312 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
6313 #define PDB_SC_PDBIE_MASK 0x20u
6314 #define PDB_SC_PDBIE_SHIFT 5
6315 #define PDB_SC_PDBIF_MASK 0x40u
6316 #define PDB_SC_PDBIF_SHIFT 6
6317 #define PDB_SC_PDBEN_MASK 0x80u
6318 #define PDB_SC_PDBEN_SHIFT 7
6319 #define PDB_SC_TRGSEL_MASK 0xF00u
6320 #define PDB_SC_TRGSEL_SHIFT 8
6321 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
6322 #define PDB_SC_PRESCALER_MASK 0x7000u
6323 #define PDB_SC_PRESCALER_SHIFT 12
6324 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
6325 #define PDB_SC_DMAEN_MASK 0x8000u
6326 #define PDB_SC_DMAEN_SHIFT 15
6327 #define PDB_SC_SWTRIG_MASK 0x10000u
6328 #define PDB_SC_SWTRIG_SHIFT 16
6329 #define PDB_SC_PDBEIE_MASK 0x20000u
6330 #define PDB_SC_PDBEIE_SHIFT 17
6331 #define PDB_SC_LDMOD_MASK 0xC0000u
6332 #define PDB_SC_LDMOD_SHIFT 18
6333 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
6334 /* MOD Bit Fields */
6335 #define PDB_MOD_MOD_MASK 0xFFFFu
6336 #define PDB_MOD_MOD_SHIFT 0
6337 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
6338 /* CNT Bit Fields */
6339 #define PDB_CNT_CNT_MASK 0xFFFFu
6340 #define PDB_CNT_CNT_SHIFT 0
6341 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
6342 /* IDLY Bit Fields */
6343 #define PDB_IDLY_IDLY_MASK 0xFFFFu
6344 #define PDB_IDLY_IDLY_SHIFT 0
6345 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
6347 #define PDB_C1_EN_MASK 0xFFu
6348 #define PDB_C1_EN_SHIFT 0
6349 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
6350 #define PDB_C1_TOS_MASK 0xFF00u
6351 #define PDB_C1_TOS_SHIFT 8
6352 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
6353 #define PDB_C1_BB_MASK 0xFF0000u
6354 #define PDB_C1_BB_SHIFT 16
6355 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
6357 #define PDB_S_ERR_MASK 0xFFu
6358 #define PDB_S_ERR_SHIFT 0
6359 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
6360 #define PDB_S_CF_MASK 0xFF0000u
6361 #define PDB_S_CF_SHIFT 16
6362 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
6363 /* DLY Bit Fields */
6364 #define PDB_DLY_DLY_MASK 0xFFFFu
6365 #define PDB_DLY_DLY_SHIFT 0
6366 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
6367 /* INTC Bit Fields */
6368 #define PDB_INTC_TOE_MASK 0x1u
6369 #define PDB_INTC_TOE_SHIFT 0
6370 #define PDB_INTC_EXT_MASK 0x2u
6371 #define PDB_INTC_EXT_SHIFT 1
6372 /* INT Bit Fields */
6373 #define PDB_INT_INT_MASK 0xFFFFu
6374 #define PDB_INT_INT_SHIFT 0
6375 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
6376 /* POEN Bit Fields */
6377 #define PDB_POEN_POEN_MASK 0xFFu
6378 #define PDB_POEN_POEN_SHIFT 0
6379 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
6380 /* PODLY Bit Fields */
6381 #define PDB_PODLY_DLY2_MASK 0xFFFFu
6382 #define PDB_PODLY_DLY2_SHIFT 0
6383 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
6384 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
6385 #define PDB_PODLY_DLY1_SHIFT 16
6386 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
6390 */ /* end of group PDB_Register_Masks */
6393 /* PDB - Peripheral instance base addresses */
6394 /** Peripheral PDB0 base address */
6395 #define PDB0_BASE (0x40036000u)
6396 /** Peripheral PDB0 base pointer */
6397 #define PDB0 ((PDB_Type *)PDB0_BASE)
6398 #define PDB0_BASE_PTR (PDB0)
6399 /** Array initializer of PDB peripheral base addresses */
6400 #define PDB_BASE_ADDRS { PDB0_BASE }
6401 /** Array initializer of PDB peripheral base pointers */
6402 #define PDB_BASE_PTRS { PDB0 }
6403 /** Interrupt vectors for the PDB peripheral type */
6404 #define PDB_IRQS { PDB0_IRQn }
6406 /* ----------------------------------------------------------------------------
6407 -- PDB - Register accessor macros
6408 ---------------------------------------------------------------------------- */
6411 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
6416 /* PDB - Register instance definitions */
6418 #define PDB0_SC PDB_SC_REG(PDB0)
6419 #define PDB0_MOD PDB_MOD_REG(PDB0)
6420 #define PDB0_CNT PDB_CNT_REG(PDB0)
6421 #define PDB0_IDLY PDB_IDLY_REG(PDB0)
6422 #define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
6423 #define PDB0_CH0S PDB_S_REG(PDB0,0)
6424 #define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
6425 #define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
6426 #define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
6427 #define PDB0_CH1S PDB_S_REG(PDB0,1)
6428 #define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
6429 #define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
6430 #define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
6431 #define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
6432 #define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
6433 #define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
6434 #define PDB0_POEN PDB_POEN_REG(PDB0)
6435 #define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
6436 #define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
6438 /* PDB - Register array accessors */
6439 #define PDB0_C1(index) PDB_C1_REG(PDB0,index)
6440 #define PDB0_S(index) PDB_S_REG(PDB0,index)
6441 #define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
6442 #define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
6443 #define PDB0_INT(index) PDB_INT_REG(PDB0,index)
6444 #define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
6448 */ /* end of group PDB_Register_Accessor_Macros */
6453 */ /* end of group PDB_Peripheral_Access_Layer */
6456 /* ----------------------------------------------------------------------------
6457 -- PIT Peripheral Access Layer
6458 ---------------------------------------------------------------------------- */
6461 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
6465 /** PIT - Register Layout Typedef */
6467 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
6468 uint8_t RESERVED_0[252];
6469 struct { /* offset: 0x100, array step: 0x10 */
6470 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
6471 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
6472 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
6473 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
6475 } PIT_Type, *PIT_MemMapPtr;
6477 /* ----------------------------------------------------------------------------
6478 -- PIT - Register accessor macros
6479 ---------------------------------------------------------------------------- */
6482 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
6487 /* PIT - Register accessors */
6488 #define PIT_MCR_REG(base) ((base)->MCR)
6489 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
6490 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
6491 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
6492 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
6496 */ /* end of group PIT_Register_Accessor_Macros */
6499 /* ----------------------------------------------------------------------------
6500 -- PIT Register Masks
6501 ---------------------------------------------------------------------------- */
6504 * @addtogroup PIT_Register_Masks PIT Register Masks
6508 /* MCR Bit Fields */
6509 #define PIT_MCR_FRZ_MASK 0x1u
6510 #define PIT_MCR_FRZ_SHIFT 0
6511 #define PIT_MCR_MDIS_MASK 0x2u
6512 #define PIT_MCR_MDIS_SHIFT 1
6513 /* LDVAL Bit Fields */
6514 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
6515 #define PIT_LDVAL_TSV_SHIFT 0
6516 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
6517 /* CVAL Bit Fields */
6518 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
6519 #define PIT_CVAL_TVL_SHIFT 0
6520 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
6521 /* TCTRL Bit Fields */
6522 #define PIT_TCTRL_TEN_MASK 0x1u
6523 #define PIT_TCTRL_TEN_SHIFT 0
6524 #define PIT_TCTRL_TIE_MASK 0x2u
6525 #define PIT_TCTRL_TIE_SHIFT 1
6526 #define PIT_TCTRL_CHN_MASK 0x4u
6527 #define PIT_TCTRL_CHN_SHIFT 2
6528 /* TFLG Bit Fields */
6529 #define PIT_TFLG_TIF_MASK 0x1u
6530 #define PIT_TFLG_TIF_SHIFT 0
6534 */ /* end of group PIT_Register_Masks */
6537 /* PIT - Peripheral instance base addresses */
6538 /** Peripheral PIT base address */
6539 #define PIT_BASE (0x40037000u)
6540 /** Peripheral PIT base pointer */
6541 #define PIT ((PIT_Type *)PIT_BASE)
6542 #define PIT_BASE_PTR (PIT)
6543 /** Array initializer of PIT peripheral base addresses */
6544 #define PIT_BASE_ADDRS { PIT_BASE }
6545 /** Array initializer of PIT peripheral base pointers */
6546 #define PIT_BASE_PTRS { PIT }
6547 /** Interrupt vectors for the PIT peripheral type */
6548 #define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
6550 /* ----------------------------------------------------------------------------
6551 -- PIT - Register accessor macros
6552 ---------------------------------------------------------------------------- */
6555 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
6560 /* PIT - Register instance definitions */
6562 #define PIT_MCR PIT_MCR_REG(PIT)
6563 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
6564 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
6565 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
6566 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
6567 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
6568 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
6569 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
6570 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
6571 #define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
6572 #define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
6573 #define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
6574 #define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
6575 #define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
6576 #define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
6577 #define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
6578 #define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
6580 /* PIT - Register array accessors */
6581 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
6582 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
6583 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
6584 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
6588 */ /* end of group PIT_Register_Accessor_Macros */
6593 */ /* end of group PIT_Peripheral_Access_Layer */
6596 /* ----------------------------------------------------------------------------
6597 -- PMC Peripheral Access Layer
6598 ---------------------------------------------------------------------------- */
6601 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
6605 /** PMC - Register Layout Typedef */
6607 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
6608 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
6609 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
6610 } PMC_Type, *PMC_MemMapPtr;
6612 /* ----------------------------------------------------------------------------
6613 -- PMC - Register accessor macros
6614 ---------------------------------------------------------------------------- */
6617 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
6622 /* PMC - Register accessors */
6623 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
6624 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
6625 #define PMC_REGSC_REG(base) ((base)->REGSC)
6629 */ /* end of group PMC_Register_Accessor_Macros */
6632 /* ----------------------------------------------------------------------------
6633 -- PMC Register Masks
6634 ---------------------------------------------------------------------------- */
6637 * @addtogroup PMC_Register_Masks PMC Register Masks
6641 /* LVDSC1 Bit Fields */
6642 #define PMC_LVDSC1_LVDV_MASK 0x3u
6643 #define PMC_LVDSC1_LVDV_SHIFT 0
6644 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
6645 #define PMC_LVDSC1_LVDRE_MASK 0x10u
6646 #define PMC_LVDSC1_LVDRE_SHIFT 4
6647 #define PMC_LVDSC1_LVDIE_MASK 0x20u
6648 #define PMC_LVDSC1_LVDIE_SHIFT 5
6649 #define PMC_LVDSC1_LVDACK_MASK 0x40u
6650 #define PMC_LVDSC1_LVDACK_SHIFT 6
6651 #define PMC_LVDSC1_LVDF_MASK 0x80u
6652 #define PMC_LVDSC1_LVDF_SHIFT 7
6653 /* LVDSC2 Bit Fields */
6654 #define PMC_LVDSC2_LVWV_MASK 0x3u
6655 #define PMC_LVDSC2_LVWV_SHIFT 0
6656 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
6657 #define PMC_LVDSC2_LVWIE_MASK 0x20u
6658 #define PMC_LVDSC2_LVWIE_SHIFT 5
6659 #define PMC_LVDSC2_LVWACK_MASK 0x40u
6660 #define PMC_LVDSC2_LVWACK_SHIFT 6
6661 #define PMC_LVDSC2_LVWF_MASK 0x80u
6662 #define PMC_LVDSC2_LVWF_SHIFT 7
6663 /* REGSC Bit Fields */
6664 #define PMC_REGSC_BGBE_MASK 0x1u
6665 #define PMC_REGSC_BGBE_SHIFT 0
6666 #define PMC_REGSC_REGONS_MASK 0x4u
6667 #define PMC_REGSC_REGONS_SHIFT 2
6668 #define PMC_REGSC_ACKISO_MASK 0x8u
6669 #define PMC_REGSC_ACKISO_SHIFT 3
6670 #define PMC_REGSC_BGEN_MASK 0x10u
6671 #define PMC_REGSC_BGEN_SHIFT 4
6675 */ /* end of group PMC_Register_Masks */
6678 /* PMC - Peripheral instance base addresses */
6679 /** Peripheral PMC base address */
6680 #define PMC_BASE (0x4007D000u)
6681 /** Peripheral PMC base pointer */
6682 #define PMC ((PMC_Type *)PMC_BASE)
6683 #define PMC_BASE_PTR (PMC)
6684 /** Array initializer of PMC peripheral base addresses */
6685 #define PMC_BASE_ADDRS { PMC_BASE }
6686 /** Array initializer of PMC peripheral base pointers */
6687 #define PMC_BASE_PTRS { PMC }
6688 /** Interrupt vectors for the PMC peripheral type */
6689 #define PMC_IRQS { LVD_LVW_IRQn }
6691 /* ----------------------------------------------------------------------------
6692 -- PMC - Register accessor macros
6693 ---------------------------------------------------------------------------- */
6696 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
6701 /* PMC - Register instance definitions */
6703 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
6704 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
6705 #define PMC_REGSC PMC_REGSC_REG(PMC)
6709 */ /* end of group PMC_Register_Accessor_Macros */
6714 */ /* end of group PMC_Peripheral_Access_Layer */
6717 /* ----------------------------------------------------------------------------
6718 -- PORT Peripheral Access Layer
6719 ---------------------------------------------------------------------------- */
6722 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
6726 /** PORT - Register Layout Typedef */
6728 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
6729 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
6730 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
6731 uint8_t RESERVED_0[24];
6732 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
6733 uint8_t RESERVED_1[28];
6734 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
6735 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
6736 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
6737 } PORT_Type, *PORT_MemMapPtr;
6739 /* ----------------------------------------------------------------------------
6740 -- PORT - Register accessor macros
6741 ---------------------------------------------------------------------------- */
6744 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
6749 /* PORT - Register accessors */
6750 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
6751 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
6752 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
6753 #define PORT_ISFR_REG(base) ((base)->ISFR)
6754 #define PORT_DFER_REG(base) ((base)->DFER)
6755 #define PORT_DFCR_REG(base) ((base)->DFCR)
6756 #define PORT_DFWR_REG(base) ((base)->DFWR)
6760 */ /* end of group PORT_Register_Accessor_Macros */
6763 /* ----------------------------------------------------------------------------
6764 -- PORT Register Masks
6765 ---------------------------------------------------------------------------- */
6768 * @addtogroup PORT_Register_Masks PORT Register Masks
6772 /* PCR Bit Fields */
6773 #define PORT_PCR_PS_MASK 0x1u
6774 #define PORT_PCR_PS_SHIFT 0
6775 #define PORT_PCR_PE_MASK 0x2u
6776 #define PORT_PCR_PE_SHIFT 1
6777 #define PORT_PCR_SRE_MASK 0x4u
6778 #define PORT_PCR_SRE_SHIFT 2
6779 #define PORT_PCR_PFE_MASK 0x10u
6780 #define PORT_PCR_PFE_SHIFT 4
6781 #define PORT_PCR_ODE_MASK 0x20u
6782 #define PORT_PCR_ODE_SHIFT 5
6783 #define PORT_PCR_DSE_MASK 0x40u
6784 #define PORT_PCR_DSE_SHIFT 6
6785 #define PORT_PCR_MUX_MASK 0x700u
6786 #define PORT_PCR_MUX_SHIFT 8
6787 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
6788 #define PORT_PCR_LK_MASK 0x8000u
6789 #define PORT_PCR_LK_SHIFT 15
6790 #define PORT_PCR_IRQC_MASK 0xF0000u
6791 #define PORT_PCR_IRQC_SHIFT 16
6792 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
6793 #define PORT_PCR_ISF_MASK 0x1000000u
6794 #define PORT_PCR_ISF_SHIFT 24
6795 /* GPCLR Bit Fields */
6796 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
6797 #define PORT_GPCLR_GPWD_SHIFT 0
6798 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
6799 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
6800 #define PORT_GPCLR_GPWE_SHIFT 16
6801 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
6802 /* GPCHR Bit Fields */
6803 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
6804 #define PORT_GPCHR_GPWD_SHIFT 0
6805 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
6806 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
6807 #define PORT_GPCHR_GPWE_SHIFT 16
6808 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
6809 /* ISFR Bit Fields */
6810 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
6811 #define PORT_ISFR_ISF_SHIFT 0
6812 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
6813 /* DFER Bit Fields */
6814 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
6815 #define PORT_DFER_DFE_SHIFT 0
6816 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
6817 /* DFCR Bit Fields */
6818 #define PORT_DFCR_CS_MASK 0x1u
6819 #define PORT_DFCR_CS_SHIFT 0
6820 /* DFWR Bit Fields */
6821 #define PORT_DFWR_FILT_MASK 0x1Fu
6822 #define PORT_DFWR_FILT_SHIFT 0
6823 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
6827 */ /* end of group PORT_Register_Masks */
6830 /* PORT - Peripheral instance base addresses */
6831 /** Peripheral PORTA base address */
6832 #define PORTA_BASE (0x40049000u)
6833 /** Peripheral PORTA base pointer */
6834 #define PORTA ((PORT_Type *)PORTA_BASE)
6835 #define PORTA_BASE_PTR (PORTA)
6836 /** Peripheral PORTB base address */
6837 #define PORTB_BASE (0x4004A000u)
6838 /** Peripheral PORTB base pointer */
6839 #define PORTB ((PORT_Type *)PORTB_BASE)
6840 #define PORTB_BASE_PTR (PORTB)
6841 /** Peripheral PORTC base address */
6842 #define PORTC_BASE (0x4004B000u)
6843 /** Peripheral PORTC base pointer */
6844 #define PORTC ((PORT_Type *)PORTC_BASE)
6845 #define PORTC_BASE_PTR (PORTC)
6846 /** Peripheral PORTD base address */
6847 #define PORTD_BASE (0x4004C000u)
6848 /** Peripheral PORTD base pointer */
6849 #define PORTD ((PORT_Type *)PORTD_BASE)
6850 #define PORTD_BASE_PTR (PORTD)
6851 /** Peripheral PORTE base address */
6852 #define PORTE_BASE (0x4004D000u)
6853 /** Peripheral PORTE base pointer */
6854 #define PORTE ((PORT_Type *)PORTE_BASE)
6855 #define PORTE_BASE_PTR (PORTE)
6856 /** Array initializer of PORT peripheral base addresses */
6857 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
6858 /** Array initializer of PORT peripheral base pointers */
6859 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
6860 /** Interrupt vectors for the PORT peripheral type */
6861 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
6863 /* ----------------------------------------------------------------------------
6864 -- PORT - Register accessor macros
6865 ---------------------------------------------------------------------------- */
6868 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
6873 /* PORT - Register instance definitions */
6875 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
6876 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
6877 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
6878 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
6879 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
6880 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
6881 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
6882 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
6883 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
6884 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
6885 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
6886 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
6887 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
6888 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
6889 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
6890 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
6891 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
6892 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
6893 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
6894 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
6895 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
6896 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
6897 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
6898 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
6899 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
6900 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
6901 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
6902 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
6903 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
6904 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
6905 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
6906 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
6907 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
6908 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
6909 #define PORTA_ISFR PORT_ISFR_REG(PORTA)
6911 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
6912 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
6913 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
6914 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
6915 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
6916 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
6917 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
6918 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
6919 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
6920 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
6921 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
6922 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
6923 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
6924 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
6925 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
6926 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
6927 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
6928 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
6929 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
6930 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
6931 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
6932 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
6933 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
6934 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
6935 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
6936 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
6937 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
6938 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
6939 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
6940 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
6941 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
6942 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
6943 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
6944 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
6945 #define PORTB_ISFR PORT_ISFR_REG(PORTB)
6947 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
6948 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
6949 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
6950 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
6951 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
6952 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
6953 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
6954 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
6955 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
6956 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
6957 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
6958 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
6959 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
6960 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
6961 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
6962 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
6963 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
6964 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
6965 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
6966 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
6967 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
6968 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
6969 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
6970 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
6971 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
6972 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
6973 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
6974 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
6975 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
6976 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
6977 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
6978 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
6979 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
6980 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
6981 #define PORTC_ISFR PORT_ISFR_REG(PORTC)
6983 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
6984 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
6985 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
6986 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
6987 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
6988 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
6989 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
6990 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
6991 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
6992 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
6993 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
6994 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
6995 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
6996 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
6997 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
6998 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
6999 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
7000 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
7001 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
7002 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
7003 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
7004 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
7005 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
7006 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
7007 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
7008 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
7009 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
7010 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
7011 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
7012 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
7013 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
7014 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
7015 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
7016 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
7017 #define PORTD_ISFR PORT_ISFR_REG(PORTD)
7018 #define PORTD_DFER PORT_DFER_REG(PORTD)
7019 #define PORTD_DFCR PORT_DFCR_REG(PORTD)
7020 #define PORTD_DFWR PORT_DFWR_REG(PORTD)
7022 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
7023 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
7024 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
7025 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
7026 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
7027 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
7028 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
7029 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
7030 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
7031 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
7032 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
7033 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
7034 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
7035 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
7036 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
7037 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
7038 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
7039 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
7040 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
7041 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
7042 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
7043 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
7044 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
7045 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
7046 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
7047 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
7048 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
7049 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
7050 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
7051 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
7052 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
7053 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
7054 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
7055 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
7056 #define PORTE_ISFR PORT_ISFR_REG(PORTE)
7058 /* PORT - Register array accessors */
7059 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
7060 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
7061 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
7062 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
7063 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
7067 */ /* end of group PORT_Register_Accessor_Macros */
7072 */ /* end of group PORT_Peripheral_Access_Layer */
7075 /* ----------------------------------------------------------------------------
7076 -- RCM Peripheral Access Layer
7077 ---------------------------------------------------------------------------- */
7080 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
7084 /** RCM - Register Layout Typedef */
7086 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
7087 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
7088 uint8_t RESERVED_0[2];
7089 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
7090 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
7091 uint8_t RESERVED_1[1];
7092 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
7093 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
7094 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
7095 } RCM_Type, *RCM_MemMapPtr;
7097 /* ----------------------------------------------------------------------------
7098 -- RCM - Register accessor macros
7099 ---------------------------------------------------------------------------- */
7102 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
7107 /* RCM - Register accessors */
7108 #define RCM_SRS0_REG(base) ((base)->SRS0)
7109 #define RCM_SRS1_REG(base) ((base)->SRS1)
7110 #define RCM_RPFC_REG(base) ((base)->RPFC)
7111 #define RCM_RPFW_REG(base) ((base)->RPFW)
7112 #define RCM_MR_REG(base) ((base)->MR)
7113 #define RCM_SSRS0_REG(base) ((base)->SSRS0)
7114 #define RCM_SSRS1_REG(base) ((base)->SSRS1)
7118 */ /* end of group RCM_Register_Accessor_Macros */
7121 /* ----------------------------------------------------------------------------
7122 -- RCM Register Masks
7123 ---------------------------------------------------------------------------- */
7126 * @addtogroup RCM_Register_Masks RCM Register Masks
7130 /* SRS0 Bit Fields */
7131 #define RCM_SRS0_WAKEUP_MASK 0x1u
7132 #define RCM_SRS0_WAKEUP_SHIFT 0
7133 #define RCM_SRS0_LVD_MASK 0x2u
7134 #define RCM_SRS0_LVD_SHIFT 1
7135 #define RCM_SRS0_LOC_MASK 0x4u
7136 #define RCM_SRS0_LOC_SHIFT 2
7137 #define RCM_SRS0_LOL_MASK 0x8u
7138 #define RCM_SRS0_LOL_SHIFT 3
7139 #define RCM_SRS0_WDOG_MASK 0x20u
7140 #define RCM_SRS0_WDOG_SHIFT 5
7141 #define RCM_SRS0_PIN_MASK 0x40u
7142 #define RCM_SRS0_PIN_SHIFT 6
7143 #define RCM_SRS0_POR_MASK 0x80u
7144 #define RCM_SRS0_POR_SHIFT 7
7145 /* SRS1 Bit Fields */
7146 #define RCM_SRS1_JTAG_MASK 0x1u
7147 #define RCM_SRS1_JTAG_SHIFT 0
7148 #define RCM_SRS1_LOCKUP_MASK 0x2u
7149 #define RCM_SRS1_LOCKUP_SHIFT 1
7150 #define RCM_SRS1_SW_MASK 0x4u
7151 #define RCM_SRS1_SW_SHIFT 2
7152 #define RCM_SRS1_MDM_AP_MASK 0x8u
7153 #define RCM_SRS1_MDM_AP_SHIFT 3
7154 #define RCM_SRS1_EZPT_MASK 0x10u
7155 #define RCM_SRS1_EZPT_SHIFT 4
7156 #define RCM_SRS1_SACKERR_MASK 0x20u
7157 #define RCM_SRS1_SACKERR_SHIFT 5
7158 /* RPFC Bit Fields */
7159 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
7160 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
7161 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
7162 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
7163 #define RCM_RPFC_RSTFLTSS_SHIFT 2
7164 /* RPFW Bit Fields */
7165 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
7166 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
7167 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
7169 #define RCM_MR_EZP_MS_MASK 0x2u
7170 #define RCM_MR_EZP_MS_SHIFT 1
7171 /* SSRS0 Bit Fields */
7172 #define RCM_SSRS0_SWAKEUP_MASK 0x1u
7173 #define RCM_SSRS0_SWAKEUP_SHIFT 0
7174 #define RCM_SSRS0_SLVD_MASK 0x2u
7175 #define RCM_SSRS0_SLVD_SHIFT 1
7176 #define RCM_SSRS0_SLOC_MASK 0x4u
7177 #define RCM_SSRS0_SLOC_SHIFT 2
7178 #define RCM_SSRS0_SLOL_MASK 0x8u
7179 #define RCM_SSRS0_SLOL_SHIFT 3
7180 #define RCM_SSRS0_SWDOG_MASK 0x20u
7181 #define RCM_SSRS0_SWDOG_SHIFT 5
7182 #define RCM_SSRS0_SPIN_MASK 0x40u
7183 #define RCM_SSRS0_SPIN_SHIFT 6
7184 #define RCM_SSRS0_SPOR_MASK 0x80u
7185 #define RCM_SSRS0_SPOR_SHIFT 7
7186 /* SSRS1 Bit Fields */
7187 #define RCM_SSRS1_SJTAG_MASK 0x1u
7188 #define RCM_SSRS1_SJTAG_SHIFT 0
7189 #define RCM_SSRS1_SLOCKUP_MASK 0x2u
7190 #define RCM_SSRS1_SLOCKUP_SHIFT 1
7191 #define RCM_SSRS1_SSW_MASK 0x4u
7192 #define RCM_SSRS1_SSW_SHIFT 2
7193 #define RCM_SSRS1_SMDM_AP_MASK 0x8u
7194 #define RCM_SSRS1_SMDM_AP_SHIFT 3
7195 #define RCM_SSRS1_SEZPT_MASK 0x10u
7196 #define RCM_SSRS1_SEZPT_SHIFT 4
7197 #define RCM_SSRS1_SSACKERR_MASK 0x20u
7198 #define RCM_SSRS1_SSACKERR_SHIFT 5
7202 */ /* end of group RCM_Register_Masks */
7205 /* RCM - Peripheral instance base addresses */
7206 /** Peripheral RCM base address */
7207 #define RCM_BASE (0x4007F000u)
7208 /** Peripheral RCM base pointer */
7209 #define RCM ((RCM_Type *)RCM_BASE)
7210 #define RCM_BASE_PTR (RCM)
7211 /** Array initializer of RCM peripheral base addresses */
7212 #define RCM_BASE_ADDRS { RCM_BASE }
7213 /** Array initializer of RCM peripheral base pointers */
7214 #define RCM_BASE_PTRS { RCM }
7216 /* ----------------------------------------------------------------------------
7217 -- RCM - Register accessor macros
7218 ---------------------------------------------------------------------------- */
7221 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
7226 /* RCM - Register instance definitions */
7228 #define RCM_SRS0 RCM_SRS0_REG(RCM)
7229 #define RCM_SRS1 RCM_SRS1_REG(RCM)
7230 #define RCM_RPFC RCM_RPFC_REG(RCM)
7231 #define RCM_RPFW RCM_RPFW_REG(RCM)
7232 #define RCM_MR RCM_MR_REG(RCM)
7233 #define RCM_SSRS0 RCM_SSRS0_REG(RCM)
7234 #define RCM_SSRS1 RCM_SSRS1_REG(RCM)
7238 */ /* end of group RCM_Register_Accessor_Macros */
7243 */ /* end of group RCM_Peripheral_Access_Layer */
7246 /* ----------------------------------------------------------------------------
7247 -- RFSYS Peripheral Access Layer
7248 ---------------------------------------------------------------------------- */
7251 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
7255 /** RFSYS - Register Layout Typedef */
7257 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
7258 } RFSYS_Type, *RFSYS_MemMapPtr;
7260 /* ----------------------------------------------------------------------------
7261 -- RFSYS - Register accessor macros
7262 ---------------------------------------------------------------------------- */
7265 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
7270 /* RFSYS - Register accessors */
7271 #define RFSYS_REG_REG(base,index) ((base)->REG[index])
7275 */ /* end of group RFSYS_Register_Accessor_Macros */
7278 /* ----------------------------------------------------------------------------
7279 -- RFSYS Register Masks
7280 ---------------------------------------------------------------------------- */
7283 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
7287 /* REG Bit Fields */
7288 #define RFSYS_REG_LL_MASK 0xFFu
7289 #define RFSYS_REG_LL_SHIFT 0
7290 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
7291 #define RFSYS_REG_LH_MASK 0xFF00u
7292 #define RFSYS_REG_LH_SHIFT 8
7293 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
7294 #define RFSYS_REG_HL_MASK 0xFF0000u
7295 #define RFSYS_REG_HL_SHIFT 16
7296 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
7297 #define RFSYS_REG_HH_MASK 0xFF000000u
7298 #define RFSYS_REG_HH_SHIFT 24
7299 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
7303 */ /* end of group RFSYS_Register_Masks */
7306 /* RFSYS - Peripheral instance base addresses */
7307 /** Peripheral RFSYS base address */
7308 #define RFSYS_BASE (0x40041000u)
7309 /** Peripheral RFSYS base pointer */
7310 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
7311 #define RFSYS_BASE_PTR (RFSYS)
7312 /** Array initializer of RFSYS peripheral base addresses */
7313 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
7314 /** Array initializer of RFSYS peripheral base pointers */
7315 #define RFSYS_BASE_PTRS { RFSYS }
7317 /* ----------------------------------------------------------------------------
7318 -- RFSYS - Register accessor macros
7319 ---------------------------------------------------------------------------- */
7322 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
7327 /* RFSYS - Register instance definitions */
7329 #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
7330 #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
7331 #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
7332 #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
7333 #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
7334 #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
7335 #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
7336 #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
7338 /* RFSYS - Register array accessors */
7339 #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
7343 */ /* end of group RFSYS_Register_Accessor_Macros */
7348 */ /* end of group RFSYS_Peripheral_Access_Layer */
7351 /* ----------------------------------------------------------------------------
7352 -- RFVBAT Peripheral Access Layer
7353 ---------------------------------------------------------------------------- */
7356 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
7360 /** RFVBAT - Register Layout Typedef */
7362 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
7363 } RFVBAT_Type, *RFVBAT_MemMapPtr;
7365 /* ----------------------------------------------------------------------------
7366 -- RFVBAT - Register accessor macros
7367 ---------------------------------------------------------------------------- */
7370 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
7375 /* RFVBAT - Register accessors */
7376 #define RFVBAT_REG_REG(base,index) ((base)->REG[index])
7380 */ /* end of group RFVBAT_Register_Accessor_Macros */
7383 /* ----------------------------------------------------------------------------
7384 -- RFVBAT Register Masks
7385 ---------------------------------------------------------------------------- */
7388 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
7392 /* REG Bit Fields */
7393 #define RFVBAT_REG_LL_MASK 0xFFu
7394 #define RFVBAT_REG_LL_SHIFT 0
7395 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
7396 #define RFVBAT_REG_LH_MASK 0xFF00u
7397 #define RFVBAT_REG_LH_SHIFT 8
7398 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
7399 #define RFVBAT_REG_HL_MASK 0xFF0000u
7400 #define RFVBAT_REG_HL_SHIFT 16
7401 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
7402 #define RFVBAT_REG_HH_MASK 0xFF000000u
7403 #define RFVBAT_REG_HH_SHIFT 24
7404 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
7408 */ /* end of group RFVBAT_Register_Masks */
7411 /* RFVBAT - Peripheral instance base addresses */
7412 /** Peripheral RFVBAT base address */
7413 #define RFVBAT_BASE (0x4003E000u)
7414 /** Peripheral RFVBAT base pointer */
7415 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
7416 #define RFVBAT_BASE_PTR (RFVBAT)
7417 /** Array initializer of RFVBAT peripheral base addresses */
7418 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
7419 /** Array initializer of RFVBAT peripheral base pointers */
7420 #define RFVBAT_BASE_PTRS { RFVBAT }
7422 /* ----------------------------------------------------------------------------
7423 -- RFVBAT - Register accessor macros
7424 ---------------------------------------------------------------------------- */
7427 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
7432 /* RFVBAT - Register instance definitions */
7434 #define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
7435 #define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
7436 #define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
7437 #define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
7438 #define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
7439 #define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
7440 #define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
7441 #define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
7443 /* RFVBAT - Register array accessors */
7444 #define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
7448 */ /* end of group RFVBAT_Register_Accessor_Macros */
7453 */ /* end of group RFVBAT_Peripheral_Access_Layer */
7456 /* ----------------------------------------------------------------------------
7457 -- RNG Peripheral Access Layer
7458 ---------------------------------------------------------------------------- */
7461 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
7465 /** RNG - Register Layout Typedef */
7467 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
7468 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
7469 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
7470 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
7471 } RNG_Type, *RNG_MemMapPtr;
7473 /* ----------------------------------------------------------------------------
7474 -- RNG - Register accessor macros
7475 ---------------------------------------------------------------------------- */
7478 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
7483 /* RNG - Register accessors */
7484 #define RNG_CR_REG(base) ((base)->CR)
7485 #define RNG_SR_REG(base) ((base)->SR)
7486 #define RNG_ER_REG(base) ((base)->ER)
7487 #define RNG_OR_REG(base) ((base)->OR)
7491 */ /* end of group RNG_Register_Accessor_Macros */
7494 /* ----------------------------------------------------------------------------
7495 -- RNG Register Masks
7496 ---------------------------------------------------------------------------- */
7499 * @addtogroup RNG_Register_Masks RNG Register Masks
7504 #define RNG_CR_GO_MASK 0x1u
7505 #define RNG_CR_GO_SHIFT 0
7506 #define RNG_CR_HA_MASK 0x2u
7507 #define RNG_CR_HA_SHIFT 1
7508 #define RNG_CR_INTM_MASK 0x4u
7509 #define RNG_CR_INTM_SHIFT 2
7510 #define RNG_CR_CLRI_MASK 0x8u
7511 #define RNG_CR_CLRI_SHIFT 3
7512 #define RNG_CR_SLP_MASK 0x10u
7513 #define RNG_CR_SLP_SHIFT 4
7515 #define RNG_SR_SECV_MASK 0x1u
7516 #define RNG_SR_SECV_SHIFT 0
7517 #define RNG_SR_LRS_MASK 0x2u
7518 #define RNG_SR_LRS_SHIFT 1
7519 #define RNG_SR_ORU_MASK 0x4u
7520 #define RNG_SR_ORU_SHIFT 2
7521 #define RNG_SR_ERRI_MASK 0x8u
7522 #define RNG_SR_ERRI_SHIFT 3
7523 #define RNG_SR_SLP_MASK 0x10u
7524 #define RNG_SR_SLP_SHIFT 4
7525 #define RNG_SR_OREG_LVL_MASK 0xFF00u
7526 #define RNG_SR_OREG_LVL_SHIFT 8
7527 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
7528 #define RNG_SR_OREG_SIZE_MASK 0xFF0000u
7529 #define RNG_SR_OREG_SIZE_SHIFT 16
7530 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
7532 #define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
7533 #define RNG_ER_EXT_ENT_SHIFT 0
7534 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
7536 #define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
7537 #define RNG_OR_RANDOUT_SHIFT 0
7538 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
7542 */ /* end of group RNG_Register_Masks */
7545 /* RNG - Peripheral instance base addresses */
7546 /** Peripheral RNG base address */
7547 #define RNG_BASE (0x40029000u)
7548 /** Peripheral RNG base pointer */
7549 #define RNG ((RNG_Type *)RNG_BASE)
7550 #define RNG_BASE_PTR (RNG)
7551 /** Array initializer of RNG peripheral base addresses */
7552 #define RNG_BASE_ADDRS { RNG_BASE }
7553 /** Array initializer of RNG peripheral base pointers */
7554 #define RNG_BASE_PTRS { RNG }
7555 /** Interrupt vectors for the RNG peripheral type */
7556 #define RNG_IRQS { RNG_IRQn }
7558 /* ----------------------------------------------------------------------------
7559 -- RNG - Register accessor macros
7560 ---------------------------------------------------------------------------- */
7563 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
7568 /* RNG - Register instance definitions */
7570 #define RNG_CR RNG_CR_REG(RNG)
7571 #define RNG_SR RNG_SR_REG(RNG)
7572 #define RNG_ER RNG_ER_REG(RNG)
7573 #define RNG_OR RNG_OR_REG(RNG)
7577 */ /* end of group RNG_Register_Accessor_Macros */
7582 */ /* end of group RNG_Peripheral_Access_Layer */
7585 /* ----------------------------------------------------------------------------
7586 -- RTC Peripheral Access Layer
7587 ---------------------------------------------------------------------------- */
7590 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
7594 /** RTC - Register Layout Typedef */
7596 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
7597 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
7598 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
7599 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
7600 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
7601 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
7602 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
7603 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
7604 uint8_t RESERVED_0[2016];
7605 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
7606 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
7607 } RTC_Type, *RTC_MemMapPtr;
7609 /* ----------------------------------------------------------------------------
7610 -- RTC - Register accessor macros
7611 ---------------------------------------------------------------------------- */
7614 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
7619 /* RTC - Register accessors */
7620 #define RTC_TSR_REG(base) ((base)->TSR)
7621 #define RTC_TPR_REG(base) ((base)->TPR)
7622 #define RTC_TAR_REG(base) ((base)->TAR)
7623 #define RTC_TCR_REG(base) ((base)->TCR)
7624 #define RTC_CR_REG(base) ((base)->CR)
7625 #define RTC_SR_REG(base) ((base)->SR)
7626 #define RTC_LR_REG(base) ((base)->LR)
7627 #define RTC_IER_REG(base) ((base)->IER)
7628 #define RTC_WAR_REG(base) ((base)->WAR)
7629 #define RTC_RAR_REG(base) ((base)->RAR)
7633 */ /* end of group RTC_Register_Accessor_Macros */
7636 /* ----------------------------------------------------------------------------
7637 -- RTC Register Masks
7638 ---------------------------------------------------------------------------- */
7641 * @addtogroup RTC_Register_Masks RTC Register Masks
7645 /* TSR Bit Fields */
7646 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
7647 #define RTC_TSR_TSR_SHIFT 0
7648 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
7649 /* TPR Bit Fields */
7650 #define RTC_TPR_TPR_MASK 0xFFFFu
7651 #define RTC_TPR_TPR_SHIFT 0
7652 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
7653 /* TAR Bit Fields */
7654 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
7655 #define RTC_TAR_TAR_SHIFT 0
7656 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
7657 /* TCR Bit Fields */
7658 #define RTC_TCR_TCR_MASK 0xFFu
7659 #define RTC_TCR_TCR_SHIFT 0
7660 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
7661 #define RTC_TCR_CIR_MASK 0xFF00u
7662 #define RTC_TCR_CIR_SHIFT 8
7663 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
7664 #define RTC_TCR_TCV_MASK 0xFF0000u
7665 #define RTC_TCR_TCV_SHIFT 16
7666 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
7667 #define RTC_TCR_CIC_MASK 0xFF000000u
7668 #define RTC_TCR_CIC_SHIFT 24
7669 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
7671 #define RTC_CR_SWR_MASK 0x1u
7672 #define RTC_CR_SWR_SHIFT 0
7673 #define RTC_CR_WPE_MASK 0x2u
7674 #define RTC_CR_WPE_SHIFT 1
7675 #define RTC_CR_SUP_MASK 0x4u
7676 #define RTC_CR_SUP_SHIFT 2
7677 #define RTC_CR_UM_MASK 0x8u
7678 #define RTC_CR_UM_SHIFT 3
7679 #define RTC_CR_WPS_MASK 0x10u
7680 #define RTC_CR_WPS_SHIFT 4
7681 #define RTC_CR_OSCE_MASK 0x100u
7682 #define RTC_CR_OSCE_SHIFT 8
7683 #define RTC_CR_CLKO_MASK 0x200u
7684 #define RTC_CR_CLKO_SHIFT 9
7685 #define RTC_CR_SC16P_MASK 0x400u
7686 #define RTC_CR_SC16P_SHIFT 10
7687 #define RTC_CR_SC8P_MASK 0x800u
7688 #define RTC_CR_SC8P_SHIFT 11
7689 #define RTC_CR_SC4P_MASK 0x1000u
7690 #define RTC_CR_SC4P_SHIFT 12
7691 #define RTC_CR_SC2P_MASK 0x2000u
7692 #define RTC_CR_SC2P_SHIFT 13
7694 #define RTC_SR_TIF_MASK 0x1u
7695 #define RTC_SR_TIF_SHIFT 0
7696 #define RTC_SR_TOF_MASK 0x2u
7697 #define RTC_SR_TOF_SHIFT 1
7698 #define RTC_SR_TAF_MASK 0x4u
7699 #define RTC_SR_TAF_SHIFT 2
7700 #define RTC_SR_TCE_MASK 0x10u
7701 #define RTC_SR_TCE_SHIFT 4
7703 #define RTC_LR_TCL_MASK 0x8u
7704 #define RTC_LR_TCL_SHIFT 3
7705 #define RTC_LR_CRL_MASK 0x10u
7706 #define RTC_LR_CRL_SHIFT 4
7707 #define RTC_LR_SRL_MASK 0x20u
7708 #define RTC_LR_SRL_SHIFT 5
7709 #define RTC_LR_LRL_MASK 0x40u
7710 #define RTC_LR_LRL_SHIFT 6
7711 /* IER Bit Fields */
7712 #define RTC_IER_TIIE_MASK 0x1u
7713 #define RTC_IER_TIIE_SHIFT 0
7714 #define RTC_IER_TOIE_MASK 0x2u
7715 #define RTC_IER_TOIE_SHIFT 1
7716 #define RTC_IER_TAIE_MASK 0x4u
7717 #define RTC_IER_TAIE_SHIFT 2
7718 #define RTC_IER_TSIE_MASK 0x10u
7719 #define RTC_IER_TSIE_SHIFT 4
7720 #define RTC_IER_WPON_MASK 0x80u
7721 #define RTC_IER_WPON_SHIFT 7
7722 /* WAR Bit Fields */
7723 #define RTC_WAR_TSRW_MASK 0x1u
7724 #define RTC_WAR_TSRW_SHIFT 0
7725 #define RTC_WAR_TPRW_MASK 0x2u
7726 #define RTC_WAR_TPRW_SHIFT 1
7727 #define RTC_WAR_TARW_MASK 0x4u
7728 #define RTC_WAR_TARW_SHIFT 2
7729 #define RTC_WAR_TCRW_MASK 0x8u
7730 #define RTC_WAR_TCRW_SHIFT 3
7731 #define RTC_WAR_CRW_MASK 0x10u
7732 #define RTC_WAR_CRW_SHIFT 4
7733 #define RTC_WAR_SRW_MASK 0x20u
7734 #define RTC_WAR_SRW_SHIFT 5
7735 #define RTC_WAR_LRW_MASK 0x40u
7736 #define RTC_WAR_LRW_SHIFT 6
7737 #define RTC_WAR_IERW_MASK 0x80u
7738 #define RTC_WAR_IERW_SHIFT 7
7739 /* RAR Bit Fields */
7740 #define RTC_RAR_TSRR_MASK 0x1u
7741 #define RTC_RAR_TSRR_SHIFT 0
7742 #define RTC_RAR_TPRR_MASK 0x2u
7743 #define RTC_RAR_TPRR_SHIFT 1
7744 #define RTC_RAR_TARR_MASK 0x4u
7745 #define RTC_RAR_TARR_SHIFT 2
7746 #define RTC_RAR_TCRR_MASK 0x8u
7747 #define RTC_RAR_TCRR_SHIFT 3
7748 #define RTC_RAR_CRR_MASK 0x10u
7749 #define RTC_RAR_CRR_SHIFT 4
7750 #define RTC_RAR_SRR_MASK 0x20u
7751 #define RTC_RAR_SRR_SHIFT 5
7752 #define RTC_RAR_LRR_MASK 0x40u
7753 #define RTC_RAR_LRR_SHIFT 6
7754 #define RTC_RAR_IERR_MASK 0x80u
7755 #define RTC_RAR_IERR_SHIFT 7
7759 */ /* end of group RTC_Register_Masks */
7762 /* RTC - Peripheral instance base addresses */
7763 /** Peripheral RTC base address */
7764 #define RTC_BASE (0x4003D000u)
7765 /** Peripheral RTC base pointer */
7766 #define RTC ((RTC_Type *)RTC_BASE)
7767 #define RTC_BASE_PTR (RTC)
7768 /** Array initializer of RTC peripheral base addresses */
7769 #define RTC_BASE_ADDRS { RTC_BASE }
7770 /** Array initializer of RTC peripheral base pointers */
7771 #define RTC_BASE_PTRS { RTC }
7772 /** Interrupt vectors for the RTC peripheral type */
7773 #define RTC_IRQS { RTC_IRQn }
7774 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
7776 /* ----------------------------------------------------------------------------
7777 -- RTC - Register accessor macros
7778 ---------------------------------------------------------------------------- */
7781 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
7786 /* RTC - Register instance definitions */
7788 #define RTC_TSR RTC_TSR_REG(RTC)
7789 #define RTC_TPR RTC_TPR_REG(RTC)
7790 #define RTC_TAR RTC_TAR_REG(RTC)
7791 #define RTC_TCR RTC_TCR_REG(RTC)
7792 #define RTC_CR RTC_CR_REG(RTC)
7793 #define RTC_SR RTC_SR_REG(RTC)
7794 #define RTC_LR RTC_LR_REG(RTC)
7795 #define RTC_IER RTC_IER_REG(RTC)
7796 #define RTC_WAR RTC_WAR_REG(RTC)
7797 #define RTC_RAR RTC_RAR_REG(RTC)
7801 */ /* end of group RTC_Register_Accessor_Macros */
7806 */ /* end of group RTC_Peripheral_Access_Layer */
7809 /* ----------------------------------------------------------------------------
7810 -- SIM Peripheral Access Layer
7811 ---------------------------------------------------------------------------- */
7814 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
7818 /** SIM - Register Layout Typedef */
7820 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
7821 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
7822 uint8_t RESERVED_0[4092];
7823 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
7824 uint8_t RESERVED_1[4];
7825 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
7826 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
7827 uint8_t RESERVED_2[4];
7828 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
7829 __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
7830 uint8_t RESERVED_3[4];
7831 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
7832 uint8_t RESERVED_4[12];
7833 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
7834 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
7835 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
7836 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
7837 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
7838 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
7839 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
7840 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
7841 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
7842 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
7843 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
7844 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
7845 } SIM_Type, *SIM_MemMapPtr;
7847 /* ----------------------------------------------------------------------------
7848 -- SIM - Register accessor macros
7849 ---------------------------------------------------------------------------- */
7852 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
7857 /* SIM - Register accessors */
7858 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
7859 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
7860 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
7861 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
7862 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
7863 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
7864 #define SIM_SOPT8_REG(base) ((base)->SOPT8)
7865 #define SIM_SDID_REG(base) ((base)->SDID)
7866 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
7867 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
7868 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
7869 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
7870 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
7871 #define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
7872 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
7873 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
7874 #define SIM_UIDH_REG(base) ((base)->UIDH)
7875 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
7876 #define SIM_UIDML_REG(base) ((base)->UIDML)
7877 #define SIM_UIDL_REG(base) ((base)->UIDL)
7881 */ /* end of group SIM_Register_Accessor_Macros */
7884 /* ----------------------------------------------------------------------------
7885 -- SIM Register Masks
7886 ---------------------------------------------------------------------------- */
7889 * @addtogroup SIM_Register_Masks SIM Register Masks
7893 /* SOPT1 Bit Fields */
7894 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
7895 #define SIM_SOPT1_RAMSIZE_SHIFT 12
7896 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
7897 #define SIM_SOPT1_OSC32KOUT_MASK 0x30000u
7898 #define SIM_SOPT1_OSC32KOUT_SHIFT 16
7899 #define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
7900 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
7901 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
7902 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
7903 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
7904 #define SIM_SOPT1_USBVSTBY_SHIFT 29
7905 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
7906 #define SIM_SOPT1_USBSSTBY_SHIFT 30
7907 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
7908 #define SIM_SOPT1_USBREGEN_SHIFT 31
7909 /* SOPT1CFG Bit Fields */
7910 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
7911 #define SIM_SOPT1CFG_URWE_SHIFT 24
7912 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
7913 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
7914 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
7915 #define SIM_SOPT1CFG_USSWE_SHIFT 26
7916 /* SOPT2 Bit Fields */
7917 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
7918 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
7919 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
7920 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
7921 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
7922 #define SIM_SOPT2_FBSL_MASK 0x300u
7923 #define SIM_SOPT2_FBSL_SHIFT 8
7924 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
7925 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
7926 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
7927 #define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
7928 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
7929 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
7930 #define SIM_SOPT2_USBSRC_MASK 0x40000u
7931 #define SIM_SOPT2_USBSRC_SHIFT 18
7932 #define SIM_SOPT2_LPUARTSRC_MASK 0xC000000u
7933 #define SIM_SOPT2_LPUARTSRC_SHIFT 26
7934 #define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUARTSRC_SHIFT))&SIM_SOPT2_LPUARTSRC_MASK)
7935 /* SOPT4 Bit Fields */
7936 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
7937 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
7938 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
7939 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
7940 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
7941 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
7942 #define SIM_SOPT4_FTM2FLT0_MASK 0x100u
7943 #define SIM_SOPT4_FTM2FLT0_SHIFT 8
7944 #define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
7945 #define SIM_SOPT4_FTM3FLT0_SHIFT 12
7946 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
7947 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
7948 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
7949 #define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
7950 #define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
7951 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
7952 #define SIM_SOPT4_FTM2CH1SRC_MASK 0x400000u
7953 #define SIM_SOPT4_FTM2CH1SRC_SHIFT 22
7954 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
7955 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
7956 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
7957 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
7958 #define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
7959 #define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
7960 #define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
7961 #define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
7962 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
7963 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
7964 #define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
7965 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
7966 #define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
7967 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
7968 #define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
7969 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
7970 /* SOPT5 Bit Fields */
7971 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
7972 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
7973 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
7974 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
7975 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
7976 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
7977 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
7978 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
7979 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
7980 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
7981 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
7982 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
7983 #define SIM_SOPT5_LPUART0RXSRC_MASK 0xC0000u
7984 #define SIM_SOPT5_LPUART0RXSRC_SHIFT 18
7985 #define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0RXSRC_SHIFT))&SIM_SOPT5_LPUART0RXSRC_MASK)
7986 /* SOPT7 Bit Fields */
7987 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
7988 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
7989 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
7990 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
7991 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
7992 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
7993 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
7994 #define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
7995 #define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
7996 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
7997 #define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
7998 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
7999 #define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
8000 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
8001 /* SOPT8 Bit Fields */
8002 #define SIM_SOPT8_FTM0SYNCBIT_MASK 0x1u
8003 #define SIM_SOPT8_FTM0SYNCBIT_SHIFT 0
8004 #define SIM_SOPT8_FTM1SYNCBIT_MASK 0x2u
8005 #define SIM_SOPT8_FTM1SYNCBIT_SHIFT 1
8006 #define SIM_SOPT8_FTM2SYNCBIT_MASK 0x4u
8007 #define SIM_SOPT8_FTM2SYNCBIT_SHIFT 2
8008 #define SIM_SOPT8_FTM3SYNCBIT_MASK 0x8u
8009 #define SIM_SOPT8_FTM3SYNCBIT_SHIFT 3
8010 #define SIM_SOPT8_FTM0OCH0SRC_MASK 0x10000u
8011 #define SIM_SOPT8_FTM0OCH0SRC_SHIFT 16
8012 #define SIM_SOPT8_FTM0OCH1SRC_MASK 0x20000u
8013 #define SIM_SOPT8_FTM0OCH1SRC_SHIFT 17
8014 #define SIM_SOPT8_FTM0OCH2SRC_MASK 0x40000u
8015 #define SIM_SOPT8_FTM0OCH2SRC_SHIFT 18
8016 #define SIM_SOPT8_FTM0OCH3SRC_MASK 0x80000u
8017 #define SIM_SOPT8_FTM0OCH3SRC_SHIFT 19
8018 #define SIM_SOPT8_FTM0OCH4SRC_MASK 0x100000u
8019 #define SIM_SOPT8_FTM0OCH4SRC_SHIFT 20
8020 #define SIM_SOPT8_FTM0OCH5SRC_MASK 0x200000u
8021 #define SIM_SOPT8_FTM0OCH5SRC_SHIFT 21
8022 #define SIM_SOPT8_FTM0OCH6SRC_MASK 0x400000u
8023 #define SIM_SOPT8_FTM0OCH6SRC_SHIFT 22
8024 #define SIM_SOPT8_FTM0OCH7SRC_MASK 0x800000u
8025 #define SIM_SOPT8_FTM0OCH7SRC_SHIFT 23
8026 #define SIM_SOPT8_FTM3OCH0SRC_MASK 0x1000000u
8027 #define SIM_SOPT8_FTM3OCH0SRC_SHIFT 24
8028 #define SIM_SOPT8_FTM3OCH1SRC_MASK 0x2000000u
8029 #define SIM_SOPT8_FTM3OCH1SRC_SHIFT 25
8030 #define SIM_SOPT8_FTM3OCH2SRC_MASK 0x4000000u
8031 #define SIM_SOPT8_FTM3OCH2SRC_SHIFT 26
8032 #define SIM_SOPT8_FTM3OCH3SRC_MASK 0x8000000u
8033 #define SIM_SOPT8_FTM3OCH3SRC_SHIFT 27
8034 #define SIM_SOPT8_FTM3OCH4SRC_MASK 0x10000000u
8035 #define SIM_SOPT8_FTM3OCH4SRC_SHIFT 28
8036 #define SIM_SOPT8_FTM3OCH5SRC_MASK 0x20000000u
8037 #define SIM_SOPT8_FTM3OCH5SRC_SHIFT 29
8038 #define SIM_SOPT8_FTM3OCH6SRC_MASK 0x40000000u
8039 #define SIM_SOPT8_FTM3OCH6SRC_SHIFT 30
8040 #define SIM_SOPT8_FTM3OCH7SRC_MASK 0x80000000u
8041 #define SIM_SOPT8_FTM3OCH7SRC_SHIFT 31
8042 /* SDID Bit Fields */
8043 #define SIM_SDID_PINID_MASK 0xFu
8044 #define SIM_SDID_PINID_SHIFT 0
8045 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
8046 #define SIM_SDID_FAMID_MASK 0x70u
8047 #define SIM_SDID_FAMID_SHIFT 4
8048 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
8049 #define SIM_SDID_DIEID_MASK 0xF80u
8050 #define SIM_SDID_DIEID_SHIFT 7
8051 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
8052 #define SIM_SDID_REVID_MASK 0xF000u
8053 #define SIM_SDID_REVID_SHIFT 12
8054 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
8055 #define SIM_SDID_SERIESID_MASK 0xF00000u
8056 #define SIM_SDID_SERIESID_SHIFT 20
8057 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
8058 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
8059 #define SIM_SDID_SUBFAMID_SHIFT 24
8060 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
8061 #define SIM_SDID_FAMILYID_MASK 0xF0000000u
8062 #define SIM_SDID_FAMILYID_SHIFT 28
8063 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
8064 /* SCGC4 Bit Fields */
8065 #define SIM_SCGC4_EWM_MASK 0x2u
8066 #define SIM_SCGC4_EWM_SHIFT 1
8067 #define SIM_SCGC4_I2C0_MASK 0x40u
8068 #define SIM_SCGC4_I2C0_SHIFT 6
8069 #define SIM_SCGC4_I2C1_MASK 0x80u
8070 #define SIM_SCGC4_I2C1_SHIFT 7
8071 #define SIM_SCGC4_UART0_MASK 0x400u
8072 #define SIM_SCGC4_UART0_SHIFT 10
8073 #define SIM_SCGC4_UART1_MASK 0x800u
8074 #define SIM_SCGC4_UART1_SHIFT 11
8075 #define SIM_SCGC4_UART2_MASK 0x1000u
8076 #define SIM_SCGC4_UART2_SHIFT 12
8077 #define SIM_SCGC4_USBOTG_MASK 0x40000u
8078 #define SIM_SCGC4_USBOTG_SHIFT 18
8079 #define SIM_SCGC4_CMP_MASK 0x80000u
8080 #define SIM_SCGC4_CMP_SHIFT 19
8081 #define SIM_SCGC4_VREF_MASK 0x100000u
8082 #define SIM_SCGC4_VREF_SHIFT 20
8083 /* SCGC5 Bit Fields */
8084 #define SIM_SCGC5_LPTMR_MASK 0x1u
8085 #define SIM_SCGC5_LPTMR_SHIFT 0
8086 #define SIM_SCGC5_PORTA_MASK 0x200u
8087 #define SIM_SCGC5_PORTA_SHIFT 9
8088 #define SIM_SCGC5_PORTB_MASK 0x400u
8089 #define SIM_SCGC5_PORTB_SHIFT 10
8090 #define SIM_SCGC5_PORTC_MASK 0x800u
8091 #define SIM_SCGC5_PORTC_SHIFT 11
8092 #define SIM_SCGC5_PORTD_MASK 0x1000u
8093 #define SIM_SCGC5_PORTD_SHIFT 12
8094 #define SIM_SCGC5_PORTE_MASK 0x2000u
8095 #define SIM_SCGC5_PORTE_SHIFT 13
8096 /* SCGC6 Bit Fields */
8097 #define SIM_SCGC6_FTF_MASK 0x1u
8098 #define SIM_SCGC6_FTF_SHIFT 0
8099 #define SIM_SCGC6_DMAMUX_MASK 0x2u
8100 #define SIM_SCGC6_DMAMUX_SHIFT 1
8101 #define SIM_SCGC6_FTM3_MASK 0x40u
8102 #define SIM_SCGC6_FTM3_SHIFT 6
8103 #define SIM_SCGC6_ADC1_MASK 0x80u
8104 #define SIM_SCGC6_ADC1_SHIFT 7
8105 #define SIM_SCGC6_DAC1_MASK 0x100u
8106 #define SIM_SCGC6_DAC1_SHIFT 8
8107 #define SIM_SCGC6_RNGA_MASK 0x200u
8108 #define SIM_SCGC6_RNGA_SHIFT 9
8109 #define SIM_SCGC6_LPUART0_MASK 0x400u
8110 #define SIM_SCGC6_LPUART0_SHIFT 10
8111 #define SIM_SCGC6_SPI0_MASK 0x1000u
8112 #define SIM_SCGC6_SPI0_SHIFT 12
8113 #define SIM_SCGC6_SPI1_MASK 0x2000u
8114 #define SIM_SCGC6_SPI1_SHIFT 13
8115 #define SIM_SCGC6_I2S_MASK 0x8000u
8116 #define SIM_SCGC6_I2S_SHIFT 15
8117 #define SIM_SCGC6_CRC_MASK 0x40000u
8118 #define SIM_SCGC6_CRC_SHIFT 18
8119 #define SIM_SCGC6_PDB_MASK 0x400000u
8120 #define SIM_SCGC6_PDB_SHIFT 22
8121 #define SIM_SCGC6_PIT_MASK 0x800000u
8122 #define SIM_SCGC6_PIT_SHIFT 23
8123 #define SIM_SCGC6_FTM0_MASK 0x1000000u
8124 #define SIM_SCGC6_FTM0_SHIFT 24
8125 #define SIM_SCGC6_FTM1_MASK 0x2000000u
8126 #define SIM_SCGC6_FTM1_SHIFT 25
8127 #define SIM_SCGC6_FTM2_MASK 0x4000000u
8128 #define SIM_SCGC6_FTM2_SHIFT 26
8129 #define SIM_SCGC6_ADC0_MASK 0x8000000u
8130 #define SIM_SCGC6_ADC0_SHIFT 27
8131 #define SIM_SCGC6_RTC_MASK 0x20000000u
8132 #define SIM_SCGC6_RTC_SHIFT 29
8133 #define SIM_SCGC6_DAC0_MASK 0x80000000u
8134 #define SIM_SCGC6_DAC0_SHIFT 31
8135 /* SCGC7 Bit Fields */
8136 #define SIM_SCGC7_FLEXBUS_MASK 0x1u
8137 #define SIM_SCGC7_FLEXBUS_SHIFT 0
8138 #define SIM_SCGC7_DMA_MASK 0x2u
8139 #define SIM_SCGC7_DMA_SHIFT 1
8140 /* CLKDIV1 Bit Fields */
8141 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
8142 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
8143 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
8144 #define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
8145 #define SIM_CLKDIV1_OUTDIV3_SHIFT 20
8146 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
8147 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
8148 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
8149 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
8150 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
8151 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
8152 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
8153 /* CLKDIV2 Bit Fields */
8154 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
8155 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
8156 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
8157 #define SIM_CLKDIV2_USBDIV_SHIFT 1
8158 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
8159 /* FCFG1 Bit Fields */
8160 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
8161 #define SIM_FCFG1_FLASHDIS_SHIFT 0
8162 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
8163 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
8164 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
8165 #define SIM_FCFG1_PFSIZE_SHIFT 24
8166 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
8167 /* FCFG2 Bit Fields */
8168 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
8169 #define SIM_FCFG2_MAXADDR1_SHIFT 16
8170 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
8171 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
8172 #define SIM_FCFG2_MAXADDR0_SHIFT 24
8173 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
8174 /* UIDH Bit Fields */
8175 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
8176 #define SIM_UIDH_UID_SHIFT 0
8177 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
8178 /* UIDMH Bit Fields */
8179 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
8180 #define SIM_UIDMH_UID_SHIFT 0
8181 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
8182 /* UIDML Bit Fields */
8183 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
8184 #define SIM_UIDML_UID_SHIFT 0
8185 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
8186 /* UIDL Bit Fields */
8187 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
8188 #define SIM_UIDL_UID_SHIFT 0
8189 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
8193 */ /* end of group SIM_Register_Masks */
8196 /* SIM - Peripheral instance base addresses */
8197 /** Peripheral SIM base address */
8198 #define SIM_BASE (0x40047000u)
8199 /** Peripheral SIM base pointer */
8200 #define SIM ((SIM_Type *)SIM_BASE)
8201 #define SIM_BASE_PTR (SIM)
8202 /** Array initializer of SIM peripheral base addresses */
8203 #define SIM_BASE_ADDRS { SIM_BASE }
8204 /** Array initializer of SIM peripheral base pointers */
8205 #define SIM_BASE_PTRS { SIM }
8207 /* ----------------------------------------------------------------------------
8208 -- SIM - Register accessor macros
8209 ---------------------------------------------------------------------------- */
8212 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
8217 /* SIM - Register instance definitions */
8219 #define SIM_SOPT1 SIM_SOPT1_REG(SIM)
8220 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
8221 #define SIM_SOPT2 SIM_SOPT2_REG(SIM)
8222 #define SIM_SOPT4 SIM_SOPT4_REG(SIM)
8223 #define SIM_SOPT5 SIM_SOPT5_REG(SIM)
8224 #define SIM_SOPT7 SIM_SOPT7_REG(SIM)
8225 #define SIM_SOPT8 SIM_SOPT8_REG(SIM)
8226 #define SIM_SDID SIM_SDID_REG(SIM)
8227 #define SIM_SCGC4 SIM_SCGC4_REG(SIM)
8228 #define SIM_SCGC5 SIM_SCGC5_REG(SIM)
8229 #define SIM_SCGC6 SIM_SCGC6_REG(SIM)
8230 #define SIM_SCGC7 SIM_SCGC7_REG(SIM)
8231 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
8232 #define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
8233 #define SIM_FCFG1 SIM_FCFG1_REG(SIM)
8234 #define SIM_FCFG2 SIM_FCFG2_REG(SIM)
8235 #define SIM_UIDH SIM_UIDH_REG(SIM)
8236 #define SIM_UIDMH SIM_UIDMH_REG(SIM)
8237 #define SIM_UIDML SIM_UIDML_REG(SIM)
8238 #define SIM_UIDL SIM_UIDL_REG(SIM)
8242 */ /* end of group SIM_Register_Accessor_Macros */
8247 */ /* end of group SIM_Peripheral_Access_Layer */
8250 /* ----------------------------------------------------------------------------
8251 -- SMC Peripheral Access Layer
8252 ---------------------------------------------------------------------------- */
8255 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
8259 /** SMC - Register Layout Typedef */
8261 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
8262 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
8263 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
8264 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
8265 } SMC_Type, *SMC_MemMapPtr;
8267 /* ----------------------------------------------------------------------------
8268 -- SMC - Register accessor macros
8269 ---------------------------------------------------------------------------- */
8272 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
8277 /* SMC - Register accessors */
8278 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
8279 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
8280 #define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
8281 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
8285 */ /* end of group SMC_Register_Accessor_Macros */
8288 /* ----------------------------------------------------------------------------
8289 -- SMC Register Masks
8290 ---------------------------------------------------------------------------- */
8293 * @addtogroup SMC_Register_Masks SMC Register Masks
8297 /* PMPROT Bit Fields */
8298 #define SMC_PMPROT_AVLLS_MASK 0x2u
8299 #define SMC_PMPROT_AVLLS_SHIFT 1
8300 #define SMC_PMPROT_ALLS_MASK 0x8u
8301 #define SMC_PMPROT_ALLS_SHIFT 3
8302 #define SMC_PMPROT_AVLP_MASK 0x20u
8303 #define SMC_PMPROT_AVLP_SHIFT 5
8304 #define SMC_PMPROT_AHSRUN_MASK 0x80u
8305 #define SMC_PMPROT_AHSRUN_SHIFT 7
8306 /* PMCTRL Bit Fields */
8307 #define SMC_PMCTRL_STOPM_MASK 0x7u
8308 #define SMC_PMCTRL_STOPM_SHIFT 0
8309 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
8310 #define SMC_PMCTRL_STOPA_MASK 0x8u
8311 #define SMC_PMCTRL_STOPA_SHIFT 3
8312 #define SMC_PMCTRL_RUNM_MASK 0x60u
8313 #define SMC_PMCTRL_RUNM_SHIFT 5
8314 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
8315 /* STOPCTRL Bit Fields */
8316 #define SMC_STOPCTRL_LLSM_MASK 0x7u
8317 #define SMC_STOPCTRL_LLSM_SHIFT 0
8318 #define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_LLSM_SHIFT))&SMC_STOPCTRL_LLSM_MASK)
8319 #define SMC_STOPCTRL_PORPO_MASK 0x20u
8320 #define SMC_STOPCTRL_PORPO_SHIFT 5
8321 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
8322 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
8323 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
8324 /* PMSTAT Bit Fields */
8325 #define SMC_PMSTAT_PMSTAT_MASK 0xFFu
8326 #define SMC_PMSTAT_PMSTAT_SHIFT 0
8327 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
8331 */ /* end of group SMC_Register_Masks */
8334 /* SMC - Peripheral instance base addresses */
8335 /** Peripheral SMC base address */
8336 #define SMC_BASE (0x4007E000u)
8337 /** Peripheral SMC base pointer */
8338 #define SMC ((SMC_Type *)SMC_BASE)
8339 #define SMC_BASE_PTR (SMC)
8340 /** Array initializer of SMC peripheral base addresses */
8341 #define SMC_BASE_ADDRS { SMC_BASE }
8342 /** Array initializer of SMC peripheral base pointers */
8343 #define SMC_BASE_PTRS { SMC }
8345 /* ----------------------------------------------------------------------------
8346 -- SMC - Register accessor macros
8347 ---------------------------------------------------------------------------- */
8350 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
8355 /* SMC - Register instance definitions */
8357 #define SMC_PMPROT SMC_PMPROT_REG(SMC)
8358 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
8359 #define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
8360 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
8364 */ /* end of group SMC_Register_Accessor_Macros */
8369 */ /* end of group SMC_Peripheral_Access_Layer */
8372 /* ----------------------------------------------------------------------------
8373 -- SPI Peripheral Access Layer
8374 ---------------------------------------------------------------------------- */
8377 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
8381 /** SPI - Register Layout Typedef */
8383 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
8384 uint8_t RESERVED_0[4];
8385 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
8386 union { /* offset: 0xC */
8387 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
8388 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
8390 uint8_t RESERVED_1[24];
8391 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
8392 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
8393 union { /* offset: 0x34 */
8394 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
8395 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
8397 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
8398 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
8399 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
8400 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
8401 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
8402 uint8_t RESERVED_2[48];
8403 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
8404 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
8405 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
8406 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
8407 } SPI_Type, *SPI_MemMapPtr;
8409 /* ----------------------------------------------------------------------------
8410 -- SPI - Register accessor macros
8411 ---------------------------------------------------------------------------- */
8414 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
8419 /* SPI - Register accessors */
8420 #define SPI_MCR_REG(base) ((base)->MCR)
8421 #define SPI_TCR_REG(base) ((base)->TCR)
8422 #define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
8423 #define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
8424 #define SPI_SR_REG(base) ((base)->SR)
8425 #define SPI_RSER_REG(base) ((base)->RSER)
8426 #define SPI_PUSHR_REG(base) ((base)->PUSHR)
8427 #define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
8428 #define SPI_POPR_REG(base) ((base)->POPR)
8429 #define SPI_TXFR0_REG(base) ((base)->TXFR0)
8430 #define SPI_TXFR1_REG(base) ((base)->TXFR1)
8431 #define SPI_TXFR2_REG(base) ((base)->TXFR2)
8432 #define SPI_TXFR3_REG(base) ((base)->TXFR3)
8433 #define SPI_RXFR0_REG(base) ((base)->RXFR0)
8434 #define SPI_RXFR1_REG(base) ((base)->RXFR1)
8435 #define SPI_RXFR2_REG(base) ((base)->RXFR2)
8436 #define SPI_RXFR3_REG(base) ((base)->RXFR3)
8440 */ /* end of group SPI_Register_Accessor_Macros */
8443 /* ----------------------------------------------------------------------------
8444 -- SPI Register Masks
8445 ---------------------------------------------------------------------------- */
8448 * @addtogroup SPI_Register_Masks SPI Register Masks
8452 /* MCR Bit Fields */
8453 #define SPI_MCR_HALT_MASK 0x1u
8454 #define SPI_MCR_HALT_SHIFT 0
8455 #define SPI_MCR_SMPL_PT_MASK 0x300u
8456 #define SPI_MCR_SMPL_PT_SHIFT 8
8457 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
8458 #define SPI_MCR_CLR_RXF_MASK 0x400u
8459 #define SPI_MCR_CLR_RXF_SHIFT 10
8460 #define SPI_MCR_CLR_TXF_MASK 0x800u
8461 #define SPI_MCR_CLR_TXF_SHIFT 11
8462 #define SPI_MCR_DIS_RXF_MASK 0x1000u
8463 #define SPI_MCR_DIS_RXF_SHIFT 12
8464 #define SPI_MCR_DIS_TXF_MASK 0x2000u
8465 #define SPI_MCR_DIS_TXF_SHIFT 13
8466 #define SPI_MCR_MDIS_MASK 0x4000u
8467 #define SPI_MCR_MDIS_SHIFT 14
8468 #define SPI_MCR_DOZE_MASK 0x8000u
8469 #define SPI_MCR_DOZE_SHIFT 15
8470 #define SPI_MCR_PCSIS_MASK 0x3F0000u
8471 #define SPI_MCR_PCSIS_SHIFT 16
8472 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
8473 #define SPI_MCR_ROOE_MASK 0x1000000u
8474 #define SPI_MCR_ROOE_SHIFT 24
8475 #define SPI_MCR_PCSSE_MASK 0x2000000u
8476 #define SPI_MCR_PCSSE_SHIFT 25
8477 #define SPI_MCR_MTFE_MASK 0x4000000u
8478 #define SPI_MCR_MTFE_SHIFT 26
8479 #define SPI_MCR_FRZ_MASK 0x8000000u
8480 #define SPI_MCR_FRZ_SHIFT 27
8481 #define SPI_MCR_DCONF_MASK 0x30000000u
8482 #define SPI_MCR_DCONF_SHIFT 28
8483 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
8484 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
8485 #define SPI_MCR_CONT_SCKE_SHIFT 30
8486 #define SPI_MCR_MSTR_MASK 0x80000000u
8487 #define SPI_MCR_MSTR_SHIFT 31
8488 /* TCR Bit Fields */
8489 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
8490 #define SPI_TCR_SPI_TCNT_SHIFT 16
8491 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
8492 /* CTAR Bit Fields */
8493 #define SPI_CTAR_BR_MASK 0xFu
8494 #define SPI_CTAR_BR_SHIFT 0
8495 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
8496 #define SPI_CTAR_DT_MASK 0xF0u
8497 #define SPI_CTAR_DT_SHIFT 4
8498 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
8499 #define SPI_CTAR_ASC_MASK 0xF00u
8500 #define SPI_CTAR_ASC_SHIFT 8
8501 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
8502 #define SPI_CTAR_CSSCK_MASK 0xF000u
8503 #define SPI_CTAR_CSSCK_SHIFT 12
8504 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
8505 #define SPI_CTAR_PBR_MASK 0x30000u
8506 #define SPI_CTAR_PBR_SHIFT 16
8507 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
8508 #define SPI_CTAR_PDT_MASK 0xC0000u
8509 #define SPI_CTAR_PDT_SHIFT 18
8510 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
8511 #define SPI_CTAR_PASC_MASK 0x300000u
8512 #define SPI_CTAR_PASC_SHIFT 20
8513 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
8514 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
8515 #define SPI_CTAR_PCSSCK_SHIFT 22
8516 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
8517 #define SPI_CTAR_LSBFE_MASK 0x1000000u
8518 #define SPI_CTAR_LSBFE_SHIFT 24
8519 #define SPI_CTAR_CPHA_MASK 0x2000000u
8520 #define SPI_CTAR_CPHA_SHIFT 25
8521 #define SPI_CTAR_CPOL_MASK 0x4000000u
8522 #define SPI_CTAR_CPOL_SHIFT 26
8523 #define SPI_CTAR_FMSZ_MASK 0x78000000u
8524 #define SPI_CTAR_FMSZ_SHIFT 27
8525 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
8526 #define SPI_CTAR_DBR_MASK 0x80000000u
8527 #define SPI_CTAR_DBR_SHIFT 31
8528 /* CTAR_SLAVE Bit Fields */
8529 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
8530 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
8531 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
8532 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
8533 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
8534 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
8535 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
8537 #define SPI_SR_POPNXTPTR_MASK 0xFu
8538 #define SPI_SR_POPNXTPTR_SHIFT 0
8539 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
8540 #define SPI_SR_RXCTR_MASK 0xF0u
8541 #define SPI_SR_RXCTR_SHIFT 4
8542 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
8543 #define SPI_SR_TXNXTPTR_MASK 0xF00u
8544 #define SPI_SR_TXNXTPTR_SHIFT 8
8545 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
8546 #define SPI_SR_TXCTR_MASK 0xF000u
8547 #define SPI_SR_TXCTR_SHIFT 12
8548 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
8549 #define SPI_SR_RFDF_MASK 0x20000u
8550 #define SPI_SR_RFDF_SHIFT 17
8551 #define SPI_SR_RFOF_MASK 0x80000u
8552 #define SPI_SR_RFOF_SHIFT 19
8553 #define SPI_SR_TFFF_MASK 0x2000000u
8554 #define SPI_SR_TFFF_SHIFT 25
8555 #define SPI_SR_TFUF_MASK 0x8000000u
8556 #define SPI_SR_TFUF_SHIFT 27
8557 #define SPI_SR_EOQF_MASK 0x10000000u
8558 #define SPI_SR_EOQF_SHIFT 28
8559 #define SPI_SR_TXRXS_MASK 0x40000000u
8560 #define SPI_SR_TXRXS_SHIFT 30
8561 #define SPI_SR_TCF_MASK 0x80000000u
8562 #define SPI_SR_TCF_SHIFT 31
8563 /* RSER Bit Fields */
8564 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
8565 #define SPI_RSER_RFDF_DIRS_SHIFT 16
8566 #define SPI_RSER_RFDF_RE_MASK 0x20000u
8567 #define SPI_RSER_RFDF_RE_SHIFT 17
8568 #define SPI_RSER_RFOF_RE_MASK 0x80000u
8569 #define SPI_RSER_RFOF_RE_SHIFT 19
8570 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
8571 #define SPI_RSER_TFFF_DIRS_SHIFT 24
8572 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
8573 #define SPI_RSER_TFFF_RE_SHIFT 25
8574 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
8575 #define SPI_RSER_TFUF_RE_SHIFT 27
8576 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
8577 #define SPI_RSER_EOQF_RE_SHIFT 28
8578 #define SPI_RSER_TCF_RE_MASK 0x80000000u
8579 #define SPI_RSER_TCF_RE_SHIFT 31
8580 /* PUSHR Bit Fields */
8581 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
8582 #define SPI_PUSHR_TXDATA_SHIFT 0
8583 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
8584 #define SPI_PUSHR_PCS_MASK 0x3F0000u
8585 #define SPI_PUSHR_PCS_SHIFT 16
8586 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
8587 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
8588 #define SPI_PUSHR_CTCNT_SHIFT 26
8589 #define SPI_PUSHR_EOQ_MASK 0x8000000u
8590 #define SPI_PUSHR_EOQ_SHIFT 27
8591 #define SPI_PUSHR_CTAS_MASK 0x70000000u
8592 #define SPI_PUSHR_CTAS_SHIFT 28
8593 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
8594 #define SPI_PUSHR_CONT_MASK 0x80000000u
8595 #define SPI_PUSHR_CONT_SHIFT 31
8596 /* PUSHR_SLAVE Bit Fields */
8597 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
8598 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
8599 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
8600 /* POPR Bit Fields */
8601 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
8602 #define SPI_POPR_RXDATA_SHIFT 0
8603 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
8604 /* TXFR0 Bit Fields */
8605 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
8606 #define SPI_TXFR0_TXDATA_SHIFT 0
8607 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
8608 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
8609 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
8610 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
8611 /* TXFR1 Bit Fields */
8612 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
8613 #define SPI_TXFR1_TXDATA_SHIFT 0
8614 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
8615 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
8616 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
8617 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
8618 /* TXFR2 Bit Fields */
8619 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
8620 #define SPI_TXFR2_TXDATA_SHIFT 0
8621 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
8622 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
8623 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
8624 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
8625 /* TXFR3 Bit Fields */
8626 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
8627 #define SPI_TXFR3_TXDATA_SHIFT 0
8628 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
8629 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
8630 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
8631 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
8632 /* RXFR0 Bit Fields */
8633 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
8634 #define SPI_RXFR0_RXDATA_SHIFT 0
8635 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
8636 /* RXFR1 Bit Fields */
8637 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
8638 #define SPI_RXFR1_RXDATA_SHIFT 0
8639 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
8640 /* RXFR2 Bit Fields */
8641 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
8642 #define SPI_RXFR2_RXDATA_SHIFT 0
8643 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
8644 /* RXFR3 Bit Fields */
8645 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
8646 #define SPI_RXFR3_RXDATA_SHIFT 0
8647 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
8651 */ /* end of group SPI_Register_Masks */
8654 /* SPI - Peripheral instance base addresses */
8655 /** Peripheral SPI0 base address */
8656 #define SPI0_BASE (0x4002C000u)
8657 /** Peripheral SPI0 base pointer */
8658 #define SPI0 ((SPI_Type *)SPI0_BASE)
8659 #define SPI0_BASE_PTR (SPI0)
8660 /** Peripheral SPI1 base address */
8661 #define SPI1_BASE (0x4002D000u)
8662 /** Peripheral SPI1 base pointer */
8663 #define SPI1 ((SPI_Type *)SPI1_BASE)
8664 #define SPI1_BASE_PTR (SPI1)
8665 /** Array initializer of SPI peripheral base addresses */
8666 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
8667 /** Array initializer of SPI peripheral base pointers */
8668 #define SPI_BASE_PTRS { SPI0, SPI1 }
8669 /** Interrupt vectors for the SPI peripheral type */
8670 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
8672 /* ----------------------------------------------------------------------------
8673 -- SPI - Register accessor macros
8674 ---------------------------------------------------------------------------- */
8677 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
8682 /* SPI - Register instance definitions */
8684 #define SPI0_MCR SPI_MCR_REG(SPI0)
8685 #define SPI0_TCR SPI_TCR_REG(SPI0)
8686 #define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
8687 #define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
8688 #define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
8689 #define SPI0_SR SPI_SR_REG(SPI0)
8690 #define SPI0_RSER SPI_RSER_REG(SPI0)
8691 #define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
8692 #define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
8693 #define SPI0_POPR SPI_POPR_REG(SPI0)
8694 #define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
8695 #define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
8696 #define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
8697 #define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
8698 #define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
8699 #define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
8700 #define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
8701 #define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
8703 #define SPI1_MCR SPI_MCR_REG(SPI1)
8704 #define SPI1_TCR SPI_TCR_REG(SPI1)
8705 #define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
8706 #define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
8707 #define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
8708 #define SPI1_SR SPI_SR_REG(SPI1)
8709 #define SPI1_RSER SPI_RSER_REG(SPI1)
8710 #define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
8711 #define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
8712 #define SPI1_POPR SPI_POPR_REG(SPI1)
8713 #define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
8714 #define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
8715 #define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
8716 #define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
8717 #define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
8718 #define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
8719 #define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
8720 #define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
8722 /* SPI - Register array accessors */
8723 #define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
8724 #define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
8725 #define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
8726 #define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
8730 */ /* end of group SPI_Register_Accessor_Macros */
8735 */ /* end of group SPI_Peripheral_Access_Layer */
8738 /* ----------------------------------------------------------------------------
8739 -- UART Peripheral Access Layer
8740 ---------------------------------------------------------------------------- */
8743 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
8747 /** UART - Register Layout Typedef */
8749 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
8750 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
8751 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
8752 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
8753 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
8754 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
8755 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
8756 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
8757 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
8758 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
8759 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
8760 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
8761 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
8762 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
8763 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
8764 uint8_t RESERVED_0[1];
8765 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
8766 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
8767 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
8768 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
8769 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
8770 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
8771 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
8772 uint8_t RESERVED_1[1];
8773 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
8774 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
8775 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
8776 __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
8777 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
8778 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
8779 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
8780 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
8781 uint8_t RESERVED_2[26];
8782 __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
8783 __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
8784 union { /* offset: 0x3C */
8785 struct { /* offset: 0x3C */
8786 __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
8787 __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
8789 struct { /* offset: 0x3C */
8790 __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
8791 __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
8794 __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
8795 __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
8796 } UART_Type, *UART_MemMapPtr;
8798 /* ----------------------------------------------------------------------------
8799 -- UART - Register accessor macros
8800 ---------------------------------------------------------------------------- */
8803 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
8808 /* UART - Register accessors */
8809 #define UART_BDH_REG(base) ((base)->BDH)
8810 #define UART_BDL_REG(base) ((base)->BDL)
8811 #define UART_C1_REG(base) ((base)->C1)
8812 #define UART_C2_REG(base) ((base)->C2)
8813 #define UART_S1_REG(base) ((base)->S1)
8814 #define UART_S2_REG(base) ((base)->S2)
8815 #define UART_C3_REG(base) ((base)->C3)
8816 #define UART_D_REG(base) ((base)->D)
8817 #define UART_MA1_REG(base) ((base)->MA1)
8818 #define UART_MA2_REG(base) ((base)->MA2)
8819 #define UART_C4_REG(base) ((base)->C4)
8820 #define UART_C5_REG(base) ((base)->C5)
8821 #define UART_ED_REG(base) ((base)->ED)
8822 #define UART_MODEM_REG(base) ((base)->MODEM)
8823 #define UART_IR_REG(base) ((base)->IR)
8824 #define UART_PFIFO_REG(base) ((base)->PFIFO)
8825 #define UART_CFIFO_REG(base) ((base)->CFIFO)
8826 #define UART_SFIFO_REG(base) ((base)->SFIFO)
8827 #define UART_TWFIFO_REG(base) ((base)->TWFIFO)
8828 #define UART_TCFIFO_REG(base) ((base)->TCFIFO)
8829 #define UART_RWFIFO_REG(base) ((base)->RWFIFO)
8830 #define UART_RCFIFO_REG(base) ((base)->RCFIFO)
8831 #define UART_C7816_REG(base) ((base)->C7816)
8832 #define UART_IE7816_REG(base) ((base)->IE7816)
8833 #define UART_IS7816_REG(base) ((base)->IS7816)
8834 #define UART_WP7816_REG(base) ((base)->WP7816)
8835 #define UART_WN7816_REG(base) ((base)->WN7816)
8836 #define UART_WF7816_REG(base) ((base)->WF7816)
8837 #define UART_ET7816_REG(base) ((base)->ET7816)
8838 #define UART_TL7816_REG(base) ((base)->TL7816)
8839 #define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
8840 #define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
8841 #define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
8842 #define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
8843 #define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
8844 #define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
8845 #define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
8846 #define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
8850 */ /* end of group UART_Register_Accessor_Macros */
8853 /* ----------------------------------------------------------------------------
8854 -- UART Register Masks
8855 ---------------------------------------------------------------------------- */
8858 * @addtogroup UART_Register_Masks UART Register Masks
8862 /* BDH Bit Fields */
8863 #define UART_BDH_SBR_MASK 0x1Fu
8864 #define UART_BDH_SBR_SHIFT 0
8865 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
8866 #define UART_BDH_RXEDGIE_MASK 0x40u
8867 #define UART_BDH_RXEDGIE_SHIFT 6
8868 #define UART_BDH_LBKDIE_MASK 0x80u
8869 #define UART_BDH_LBKDIE_SHIFT 7
8870 /* BDL Bit Fields */
8871 #define UART_BDL_SBR_MASK 0xFFu
8872 #define UART_BDL_SBR_SHIFT 0
8873 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
8875 #define UART_C1_PT_MASK 0x1u
8876 #define UART_C1_PT_SHIFT 0
8877 #define UART_C1_PE_MASK 0x2u
8878 #define UART_C1_PE_SHIFT 1
8879 #define UART_C1_ILT_MASK 0x4u
8880 #define UART_C1_ILT_SHIFT 2
8881 #define UART_C1_WAKE_MASK 0x8u
8882 #define UART_C1_WAKE_SHIFT 3
8883 #define UART_C1_M_MASK 0x10u
8884 #define UART_C1_M_SHIFT 4
8885 #define UART_C1_RSRC_MASK 0x20u
8886 #define UART_C1_RSRC_SHIFT 5
8887 #define UART_C1_UARTSWAI_MASK 0x40u
8888 #define UART_C1_UARTSWAI_SHIFT 6
8889 #define UART_C1_LOOPS_MASK 0x80u
8890 #define UART_C1_LOOPS_SHIFT 7
8892 #define UART_C2_SBK_MASK 0x1u
8893 #define UART_C2_SBK_SHIFT 0
8894 #define UART_C2_RWU_MASK 0x2u
8895 #define UART_C2_RWU_SHIFT 1
8896 #define UART_C2_RE_MASK 0x4u
8897 #define UART_C2_RE_SHIFT 2
8898 #define UART_C2_TE_MASK 0x8u
8899 #define UART_C2_TE_SHIFT 3
8900 #define UART_C2_ILIE_MASK 0x10u
8901 #define UART_C2_ILIE_SHIFT 4
8902 #define UART_C2_RIE_MASK 0x20u
8903 #define UART_C2_RIE_SHIFT 5
8904 #define UART_C2_TCIE_MASK 0x40u
8905 #define UART_C2_TCIE_SHIFT 6
8906 #define UART_C2_TIE_MASK 0x80u
8907 #define UART_C2_TIE_SHIFT 7
8909 #define UART_S1_PF_MASK 0x1u
8910 #define UART_S1_PF_SHIFT 0
8911 #define UART_S1_FE_MASK 0x2u
8912 #define UART_S1_FE_SHIFT 1
8913 #define UART_S1_NF_MASK 0x4u
8914 #define UART_S1_NF_SHIFT 2
8915 #define UART_S1_OR_MASK 0x8u
8916 #define UART_S1_OR_SHIFT 3
8917 #define UART_S1_IDLE_MASK 0x10u
8918 #define UART_S1_IDLE_SHIFT 4
8919 #define UART_S1_RDRF_MASK 0x20u
8920 #define UART_S1_RDRF_SHIFT 5
8921 #define UART_S1_TC_MASK 0x40u
8922 #define UART_S1_TC_SHIFT 6
8923 #define UART_S1_TDRE_MASK 0x80u
8924 #define UART_S1_TDRE_SHIFT 7
8926 #define UART_S2_RAF_MASK 0x1u
8927 #define UART_S2_RAF_SHIFT 0
8928 #define UART_S2_LBKDE_MASK 0x2u
8929 #define UART_S2_LBKDE_SHIFT 1
8930 #define UART_S2_BRK13_MASK 0x4u
8931 #define UART_S2_BRK13_SHIFT 2
8932 #define UART_S2_RWUID_MASK 0x8u
8933 #define UART_S2_RWUID_SHIFT 3
8934 #define UART_S2_RXINV_MASK 0x10u
8935 #define UART_S2_RXINV_SHIFT 4
8936 #define UART_S2_MSBF_MASK 0x20u
8937 #define UART_S2_MSBF_SHIFT 5
8938 #define UART_S2_RXEDGIF_MASK 0x40u
8939 #define UART_S2_RXEDGIF_SHIFT 6
8940 #define UART_S2_LBKDIF_MASK 0x80u
8941 #define UART_S2_LBKDIF_SHIFT 7
8943 #define UART_C3_PEIE_MASK 0x1u
8944 #define UART_C3_PEIE_SHIFT 0
8945 #define UART_C3_FEIE_MASK 0x2u
8946 #define UART_C3_FEIE_SHIFT 1
8947 #define UART_C3_NEIE_MASK 0x4u
8948 #define UART_C3_NEIE_SHIFT 2
8949 #define UART_C3_ORIE_MASK 0x8u
8950 #define UART_C3_ORIE_SHIFT 3
8951 #define UART_C3_TXINV_MASK 0x10u
8952 #define UART_C3_TXINV_SHIFT 4
8953 #define UART_C3_TXDIR_MASK 0x20u
8954 #define UART_C3_TXDIR_SHIFT 5
8955 #define UART_C3_T8_MASK 0x40u
8956 #define UART_C3_T8_SHIFT 6
8957 #define UART_C3_R8_MASK 0x80u
8958 #define UART_C3_R8_SHIFT 7
8960 #define UART_D_RT_MASK 0xFFu
8961 #define UART_D_RT_SHIFT 0
8962 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
8963 /* MA1 Bit Fields */
8964 #define UART_MA1_MA_MASK 0xFFu
8965 #define UART_MA1_MA_SHIFT 0
8966 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
8967 /* MA2 Bit Fields */
8968 #define UART_MA2_MA_MASK 0xFFu
8969 #define UART_MA2_MA_SHIFT 0
8970 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
8972 #define UART_C4_BRFA_MASK 0x1Fu
8973 #define UART_C4_BRFA_SHIFT 0
8974 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
8975 #define UART_C4_M10_MASK 0x20u
8976 #define UART_C4_M10_SHIFT 5
8977 #define UART_C4_MAEN2_MASK 0x40u
8978 #define UART_C4_MAEN2_SHIFT 6
8979 #define UART_C4_MAEN1_MASK 0x80u
8980 #define UART_C4_MAEN1_SHIFT 7
8982 #define UART_C5_RDMAS_MASK 0x20u
8983 #define UART_C5_RDMAS_SHIFT 5
8984 #define UART_C5_TDMAS_MASK 0x80u
8985 #define UART_C5_TDMAS_SHIFT 7
8987 #define UART_ED_PARITYE_MASK 0x40u
8988 #define UART_ED_PARITYE_SHIFT 6
8989 #define UART_ED_NOISY_MASK 0x80u
8990 #define UART_ED_NOISY_SHIFT 7
8991 /* MODEM Bit Fields */
8992 #define UART_MODEM_TXCTSE_MASK 0x1u
8993 #define UART_MODEM_TXCTSE_SHIFT 0
8994 #define UART_MODEM_TXRTSE_MASK 0x2u
8995 #define UART_MODEM_TXRTSE_SHIFT 1
8996 #define UART_MODEM_TXRTSPOL_MASK 0x4u
8997 #define UART_MODEM_TXRTSPOL_SHIFT 2
8998 #define UART_MODEM_RXRTSE_MASK 0x8u
8999 #define UART_MODEM_RXRTSE_SHIFT 3
9001 #define UART_IR_TNP_MASK 0x3u
9002 #define UART_IR_TNP_SHIFT 0
9003 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
9004 #define UART_IR_IREN_MASK 0x4u
9005 #define UART_IR_IREN_SHIFT 2
9006 /* PFIFO Bit Fields */
9007 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
9008 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
9009 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
9010 #define UART_PFIFO_RXFE_MASK 0x8u
9011 #define UART_PFIFO_RXFE_SHIFT 3
9012 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
9013 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
9014 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
9015 #define UART_PFIFO_TXFE_MASK 0x80u
9016 #define UART_PFIFO_TXFE_SHIFT 7
9017 /* CFIFO Bit Fields */
9018 #define UART_CFIFO_RXUFE_MASK 0x1u
9019 #define UART_CFIFO_RXUFE_SHIFT 0
9020 #define UART_CFIFO_TXOFE_MASK 0x2u
9021 #define UART_CFIFO_TXOFE_SHIFT 1
9022 #define UART_CFIFO_RXOFE_MASK 0x4u
9023 #define UART_CFIFO_RXOFE_SHIFT 2
9024 #define UART_CFIFO_RXFLUSH_MASK 0x40u
9025 #define UART_CFIFO_RXFLUSH_SHIFT 6
9026 #define UART_CFIFO_TXFLUSH_MASK 0x80u
9027 #define UART_CFIFO_TXFLUSH_SHIFT 7
9028 /* SFIFO Bit Fields */
9029 #define UART_SFIFO_RXUF_MASK 0x1u
9030 #define UART_SFIFO_RXUF_SHIFT 0
9031 #define UART_SFIFO_TXOF_MASK 0x2u
9032 #define UART_SFIFO_TXOF_SHIFT 1
9033 #define UART_SFIFO_RXOF_MASK 0x4u
9034 #define UART_SFIFO_RXOF_SHIFT 2
9035 #define UART_SFIFO_RXEMPT_MASK 0x40u
9036 #define UART_SFIFO_RXEMPT_SHIFT 6
9037 #define UART_SFIFO_TXEMPT_MASK 0x80u
9038 #define UART_SFIFO_TXEMPT_SHIFT 7
9039 /* TWFIFO Bit Fields */
9040 #define UART_TWFIFO_TXWATER_MASK 0xFFu
9041 #define UART_TWFIFO_TXWATER_SHIFT 0
9042 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
9043 /* TCFIFO Bit Fields */
9044 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
9045 #define UART_TCFIFO_TXCOUNT_SHIFT 0
9046 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
9047 /* RWFIFO Bit Fields */
9048 #define UART_RWFIFO_RXWATER_MASK 0xFFu
9049 #define UART_RWFIFO_RXWATER_SHIFT 0
9050 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
9051 /* RCFIFO Bit Fields */
9052 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
9053 #define UART_RCFIFO_RXCOUNT_SHIFT 0
9054 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
9055 /* C7816 Bit Fields */
9056 #define UART_C7816_ISO_7816E_MASK 0x1u
9057 #define UART_C7816_ISO_7816E_SHIFT 0
9058 #define UART_C7816_TTYPE_MASK 0x2u
9059 #define UART_C7816_TTYPE_SHIFT 1
9060 #define UART_C7816_INIT_MASK 0x4u
9061 #define UART_C7816_INIT_SHIFT 2
9062 #define UART_C7816_ANACK_MASK 0x8u
9063 #define UART_C7816_ANACK_SHIFT 3
9064 #define UART_C7816_ONACK_MASK 0x10u
9065 #define UART_C7816_ONACK_SHIFT 4
9066 /* IE7816 Bit Fields */
9067 #define UART_IE7816_RXTE_MASK 0x1u
9068 #define UART_IE7816_RXTE_SHIFT 0
9069 #define UART_IE7816_TXTE_MASK 0x2u
9070 #define UART_IE7816_TXTE_SHIFT 1
9071 #define UART_IE7816_GTVE_MASK 0x4u
9072 #define UART_IE7816_GTVE_SHIFT 2
9073 #define UART_IE7816_ADTE_MASK 0x8u
9074 #define UART_IE7816_ADTE_SHIFT 3
9075 #define UART_IE7816_INITDE_MASK 0x10u
9076 #define UART_IE7816_INITDE_SHIFT 4
9077 #define UART_IE7816_BWTE_MASK 0x20u
9078 #define UART_IE7816_BWTE_SHIFT 5
9079 #define UART_IE7816_CWTE_MASK 0x40u
9080 #define UART_IE7816_CWTE_SHIFT 6
9081 #define UART_IE7816_WTE_MASK 0x80u
9082 #define UART_IE7816_WTE_SHIFT 7
9083 /* IS7816 Bit Fields */
9084 #define UART_IS7816_RXT_MASK 0x1u
9085 #define UART_IS7816_RXT_SHIFT 0
9086 #define UART_IS7816_TXT_MASK 0x2u
9087 #define UART_IS7816_TXT_SHIFT 1
9088 #define UART_IS7816_GTV_MASK 0x4u
9089 #define UART_IS7816_GTV_SHIFT 2
9090 #define UART_IS7816_ADT_MASK 0x8u
9091 #define UART_IS7816_ADT_SHIFT 3
9092 #define UART_IS7816_INITD_MASK 0x10u
9093 #define UART_IS7816_INITD_SHIFT 4
9094 #define UART_IS7816_BWT_MASK 0x20u
9095 #define UART_IS7816_BWT_SHIFT 5
9096 #define UART_IS7816_CWT_MASK 0x40u
9097 #define UART_IS7816_CWT_SHIFT 6
9098 #define UART_IS7816_WT_MASK 0x80u
9099 #define UART_IS7816_WT_SHIFT 7
9100 /* WP7816 Bit Fields */
9101 #define UART_WP7816_WTX_MASK 0xFFu
9102 #define UART_WP7816_WTX_SHIFT 0
9103 #define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
9104 /* WN7816 Bit Fields */
9105 #define UART_WN7816_GTN_MASK 0xFFu
9106 #define UART_WN7816_GTN_SHIFT 0
9107 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
9108 /* WF7816 Bit Fields */
9109 #define UART_WF7816_GTFD_MASK 0xFFu
9110 #define UART_WF7816_GTFD_SHIFT 0
9111 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
9112 /* ET7816 Bit Fields */
9113 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
9114 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
9115 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
9116 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
9117 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
9118 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
9119 /* TL7816 Bit Fields */
9120 #define UART_TL7816_TLEN_MASK 0xFFu
9121 #define UART_TL7816_TLEN_SHIFT 0
9122 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
9123 /* AP7816A_T0 Bit Fields */
9124 #define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
9125 #define UART_AP7816A_T0_ADTI_H_SHIFT 0
9126 #define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
9127 /* AP7816B_T0 Bit Fields */
9128 #define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
9129 #define UART_AP7816B_T0_ADTI_L_SHIFT 0
9130 #define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
9131 /* WP7816A_T0 Bit Fields */
9132 #define UART_WP7816A_T0_WI_H_MASK 0xFFu
9133 #define UART_WP7816A_T0_WI_H_SHIFT 0
9134 #define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
9135 /* WP7816B_T0 Bit Fields */
9136 #define UART_WP7816B_T0_WI_L_MASK 0xFFu
9137 #define UART_WP7816B_T0_WI_L_SHIFT 0
9138 #define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
9139 /* WP7816A_T1 Bit Fields */
9140 #define UART_WP7816A_T1_BWI_H_MASK 0xFFu
9141 #define UART_WP7816A_T1_BWI_H_SHIFT 0
9142 #define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
9143 /* WP7816B_T1 Bit Fields */
9144 #define UART_WP7816B_T1_BWI_L_MASK 0xFFu
9145 #define UART_WP7816B_T1_BWI_L_SHIFT 0
9146 #define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
9147 /* WGP7816_T1 Bit Fields */
9148 #define UART_WGP7816_T1_BGI_MASK 0xFu
9149 #define UART_WGP7816_T1_BGI_SHIFT 0
9150 #define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
9151 #define UART_WGP7816_T1_CWI1_MASK 0xF0u
9152 #define UART_WGP7816_T1_CWI1_SHIFT 4
9153 #define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
9154 /* WP7816C_T1 Bit Fields */
9155 #define UART_WP7816C_T1_CWI2_MASK 0x1Fu
9156 #define UART_WP7816C_T1_CWI2_SHIFT 0
9157 #define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
9161 */ /* end of group UART_Register_Masks */
9164 /* UART - Peripheral instance base addresses */
9165 /** Peripheral UART0 base address */
9166 #define UART0_BASE (0x4006A000u)
9167 /** Peripheral UART0 base pointer */
9168 #define UART0 ((UART_Type *)UART0_BASE)
9169 #define UART0_BASE_PTR (UART0)
9170 /** Peripheral UART1 base address */
9171 #define UART1_BASE (0x4006B000u)
9172 /** Peripheral UART1 base pointer */
9173 #define UART1 ((UART_Type *)UART1_BASE)
9174 #define UART1_BASE_PTR (UART1)
9175 /** Peripheral UART2 base address */
9176 #define UART2_BASE (0x4006C000u)
9177 /** Peripheral UART2 base pointer */
9178 #define UART2 ((UART_Type *)UART2_BASE)
9179 #define UART2_BASE_PTR (UART2)
9180 /** Array initializer of UART peripheral base addresses */
9181 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE }
9182 /** Array initializer of UART peripheral base pointers */
9183 #define UART_BASE_PTRS { UART0, UART1, UART2 }
9184 /** Interrupt vectors for the UART peripheral type */
9185 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn }
9186 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn }
9188 /* ----------------------------------------------------------------------------
9189 -- UART - Register accessor macros
9190 ---------------------------------------------------------------------------- */
9193 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
9198 /* UART - Register instance definitions */
9200 #define UART0_BDH UART_BDH_REG(UART0)
9201 #define UART0_BDL UART_BDL_REG(UART0)
9202 #define UART0_C1 UART_C1_REG(UART0)
9203 #define UART0_C2 UART_C2_REG(UART0)
9204 #define UART0_S1 UART_S1_REG(UART0)
9205 #define UART0_S2 UART_S2_REG(UART0)
9206 #define UART0_C3 UART_C3_REG(UART0)
9207 #define UART0_D UART_D_REG(UART0)
9208 #define UART0_MA1 UART_MA1_REG(UART0)
9209 #define UART0_MA2 UART_MA2_REG(UART0)
9210 #define UART0_C4 UART_C4_REG(UART0)
9211 #define UART0_C5 UART_C5_REG(UART0)
9212 #define UART0_ED UART_ED_REG(UART0)
9213 #define UART0_MODEM UART_MODEM_REG(UART0)
9214 #define UART0_IR UART_IR_REG(UART0)
9215 #define UART0_PFIFO UART_PFIFO_REG(UART0)
9216 #define UART0_CFIFO UART_CFIFO_REG(UART0)
9217 #define UART0_SFIFO UART_SFIFO_REG(UART0)
9218 #define UART0_TWFIFO UART_TWFIFO_REG(UART0)
9219 #define UART0_TCFIFO UART_TCFIFO_REG(UART0)
9220 #define UART0_RWFIFO UART_RWFIFO_REG(UART0)
9221 #define UART0_RCFIFO UART_RCFIFO_REG(UART0)
9222 #define UART0_C7816 UART_C7816_REG(UART0)
9223 #define UART0_IE7816 UART_IE7816_REG(UART0)
9224 #define UART0_IS7816 UART_IS7816_REG(UART0)
9225 #define UART0_WP7816 UART_WP7816_REG(UART0)
9226 #define UART0_WN7816 UART_WN7816_REG(UART0)
9227 #define UART0_WF7816 UART_WF7816_REG(UART0)
9228 #define UART0_ET7816 UART_ET7816_REG(UART0)
9229 #define UART0_TL7816 UART_TL7816_REG(UART0)
9230 #define UART0_AP7816A_T0 UART_AP7816A_T0_REG(UART0)
9231 #define UART0_AP7816B_T0 UART_AP7816B_T0_REG(UART0)
9232 #define UART0_WP7816A_T0 UART_WP7816A_T0_REG(UART0)
9233 #define UART0_WP7816A_T1 UART_WP7816A_T1_REG(UART0)
9234 #define UART0_WP7816B_T0 UART_WP7816B_T0_REG(UART0)
9235 #define UART0_WP7816B_T1 UART_WP7816B_T1_REG(UART0)
9236 #define UART0_WGP7816_T1 UART_WGP7816_T1_REG(UART0)
9237 #define UART0_WP7816C_T1 UART_WP7816C_T1_REG(UART0)
9239 #define UART1_BDH UART_BDH_REG(UART1)
9240 #define UART1_BDL UART_BDL_REG(UART1)
9241 #define UART1_C1 UART_C1_REG(UART1)
9242 #define UART1_C2 UART_C2_REG(UART1)
9243 #define UART1_S1 UART_S1_REG(UART1)
9244 #define UART1_S2 UART_S2_REG(UART1)
9245 #define UART1_C3 UART_C3_REG(UART1)
9246 #define UART1_D UART_D_REG(UART1)
9247 #define UART1_MA1 UART_MA1_REG(UART1)
9248 #define UART1_MA2 UART_MA2_REG(UART1)
9249 #define UART1_C4 UART_C4_REG(UART1)
9250 #define UART1_C5 UART_C5_REG(UART1)
9251 #define UART1_ED UART_ED_REG(UART1)
9252 #define UART1_MODEM UART_MODEM_REG(UART1)
9253 #define UART1_IR UART_IR_REG(UART1)
9254 #define UART1_PFIFO UART_PFIFO_REG(UART1)
9255 #define UART1_CFIFO UART_CFIFO_REG(UART1)
9256 #define UART1_SFIFO UART_SFIFO_REG(UART1)
9257 #define UART1_TWFIFO UART_TWFIFO_REG(UART1)
9258 #define UART1_TCFIFO UART_TCFIFO_REG(UART1)
9259 #define UART1_RWFIFO UART_RWFIFO_REG(UART1)
9260 #define UART1_RCFIFO UART_RCFIFO_REG(UART1)
9262 #define UART2_BDH UART_BDH_REG(UART2)
9263 #define UART2_BDL UART_BDL_REG(UART2)
9264 #define UART2_C1 UART_C1_REG(UART2)
9265 #define UART2_C2 UART_C2_REG(UART2)
9266 #define UART2_S1 UART_S1_REG(UART2)
9267 #define UART2_S2 UART_S2_REG(UART2)
9268 #define UART2_C3 UART_C3_REG(UART2)
9269 #define UART2_D UART_D_REG(UART2)
9270 #define UART2_MA1 UART_MA1_REG(UART2)
9271 #define UART2_MA2 UART_MA2_REG(UART2)
9272 #define UART2_C4 UART_C4_REG(UART2)
9273 #define UART2_C5 UART_C5_REG(UART2)
9274 #define UART2_ED UART_ED_REG(UART2)
9275 #define UART2_MODEM UART_MODEM_REG(UART2)
9276 #define UART2_IR UART_IR_REG(UART2)
9277 #define UART2_PFIFO UART_PFIFO_REG(UART2)
9278 #define UART2_CFIFO UART_CFIFO_REG(UART2)
9279 #define UART2_SFIFO UART_SFIFO_REG(UART2)
9280 #define UART2_TWFIFO UART_TWFIFO_REG(UART2)
9281 #define UART2_TCFIFO UART_TCFIFO_REG(UART2)
9282 #define UART2_RWFIFO UART_RWFIFO_REG(UART2)
9283 #define UART2_RCFIFO UART_RCFIFO_REG(UART2)
9287 */ /* end of group UART_Register_Accessor_Macros */
9292 */ /* end of group UART_Peripheral_Access_Layer */
9295 /* ----------------------------------------------------------------------------
9296 -- USB Peripheral Access Layer
9297 ---------------------------------------------------------------------------- */
9300 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
9304 /** USB - Register Layout Typedef */
9306 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
9307 uint8_t RESERVED_0[3];
9308 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
9309 uint8_t RESERVED_1[3];
9310 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
9311 uint8_t RESERVED_2[3];
9312 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
9313 uint8_t RESERVED_3[3];
9314 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
9315 uint8_t RESERVED_4[3];
9316 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
9317 uint8_t RESERVED_5[3];
9318 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
9319 uint8_t RESERVED_6[3];
9320 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
9321 uint8_t RESERVED_7[99];
9322 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
9323 uint8_t RESERVED_8[3];
9324 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
9325 uint8_t RESERVED_9[3];
9326 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
9327 uint8_t RESERVED_10[3];
9328 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
9329 uint8_t RESERVED_11[3];
9330 __I uint8_t STAT; /**< Status register, offset: 0x90 */
9331 uint8_t RESERVED_12[3];
9332 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
9333 uint8_t RESERVED_13[3];
9334 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
9335 uint8_t RESERVED_14[3];
9336 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
9337 uint8_t RESERVED_15[3];
9338 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
9339 uint8_t RESERVED_16[3];
9340 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
9341 uint8_t RESERVED_17[3];
9342 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
9343 uint8_t RESERVED_18[3];
9344 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
9345 uint8_t RESERVED_19[3];
9346 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
9347 uint8_t RESERVED_20[3];
9348 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
9349 uint8_t RESERVED_21[11];
9350 struct { /* offset: 0xC0, array step: 0x4 */
9351 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
9352 uint8_t RESERVED_0[3];
9354 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
9355 uint8_t RESERVED_22[3];
9356 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
9357 uint8_t RESERVED_23[3];
9358 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
9359 uint8_t RESERVED_24[3];
9360 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
9361 uint8_t RESERVED_25[7];
9362 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
9363 uint8_t RESERVED_26[43];
9364 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
9365 uint8_t RESERVED_27[3];
9366 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
9367 uint8_t RESERVED_28[23];
9368 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
9369 } USB_Type, *USB_MemMapPtr;
9371 /* ----------------------------------------------------------------------------
9372 -- USB - Register accessor macros
9373 ---------------------------------------------------------------------------- */
9376 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
9381 /* USB - Register accessors */
9382 #define USB_PERID_REG(base) ((base)->PERID)
9383 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
9384 #define USB_REV_REG(base) ((base)->REV)
9385 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
9386 #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
9387 #define USB_OTGICR_REG(base) ((base)->OTGICR)
9388 #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
9389 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
9390 #define USB_ISTAT_REG(base) ((base)->ISTAT)
9391 #define USB_INTEN_REG(base) ((base)->INTEN)
9392 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
9393 #define USB_ERREN_REG(base) ((base)->ERREN)
9394 #define USB_STAT_REG(base) ((base)->STAT)
9395 #define USB_CTL_REG(base) ((base)->CTL)
9396 #define USB_ADDR_REG(base) ((base)->ADDR)
9397 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
9398 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
9399 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
9400 #define USB_TOKEN_REG(base) ((base)->TOKEN)
9401 #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
9402 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
9403 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
9404 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
9405 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
9406 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
9407 #define USB_CONTROL_REG(base) ((base)->CONTROL)
9408 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
9409 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
9410 #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
9411 #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
9412 #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
9416 */ /* end of group USB_Register_Accessor_Macros */
9419 /* ----------------------------------------------------------------------------
9420 -- USB Register Masks
9421 ---------------------------------------------------------------------------- */
9424 * @addtogroup USB_Register_Masks USB Register Masks
9428 /* PERID Bit Fields */
9429 #define USB_PERID_ID_MASK 0x3Fu
9430 #define USB_PERID_ID_SHIFT 0
9431 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
9432 /* IDCOMP Bit Fields */
9433 #define USB_IDCOMP_NID_MASK 0x3Fu
9434 #define USB_IDCOMP_NID_SHIFT 0
9435 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
9436 /* REV Bit Fields */
9437 #define USB_REV_REV_MASK 0xFFu
9438 #define USB_REV_REV_SHIFT 0
9439 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
9440 /* ADDINFO Bit Fields */
9441 #define USB_ADDINFO_IEHOST_MASK 0x1u
9442 #define USB_ADDINFO_IEHOST_SHIFT 0
9443 /* OTGISTAT Bit Fields */
9444 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
9445 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
9446 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
9447 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
9448 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
9449 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
9450 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
9451 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
9452 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
9453 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
9454 #define USB_OTGISTAT_IDCHG_MASK 0x80u
9455 #define USB_OTGISTAT_IDCHG_SHIFT 7
9456 /* OTGICR Bit Fields */
9457 #define USB_OTGICR_AVBUSEN_MASK 0x1u
9458 #define USB_OTGICR_AVBUSEN_SHIFT 0
9459 #define USB_OTGICR_BSESSEN_MASK 0x4u
9460 #define USB_OTGICR_BSESSEN_SHIFT 2
9461 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
9462 #define USB_OTGICR_SESSVLDEN_SHIFT 3
9463 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
9464 #define USB_OTGICR_LINESTATEEN_SHIFT 5
9465 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
9466 #define USB_OTGICR_ONEMSECEN_SHIFT 6
9467 #define USB_OTGICR_IDEN_MASK 0x80u
9468 #define USB_OTGICR_IDEN_SHIFT 7
9469 /* OTGSTAT Bit Fields */
9470 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
9471 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
9472 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
9473 #define USB_OTGSTAT_BSESSEND_SHIFT 2
9474 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
9475 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
9476 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
9477 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
9478 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
9479 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
9480 #define USB_OTGSTAT_ID_MASK 0x80u
9481 #define USB_OTGSTAT_ID_SHIFT 7
9482 /* OTGCTL Bit Fields */
9483 #define USB_OTGCTL_OTGEN_MASK 0x4u
9484 #define USB_OTGCTL_OTGEN_SHIFT 2
9485 #define USB_OTGCTL_DMLOW_MASK 0x10u
9486 #define USB_OTGCTL_DMLOW_SHIFT 4
9487 #define USB_OTGCTL_DPLOW_MASK 0x20u
9488 #define USB_OTGCTL_DPLOW_SHIFT 5
9489 #define USB_OTGCTL_DPHIGH_MASK 0x80u
9490 #define USB_OTGCTL_DPHIGH_SHIFT 7
9491 /* ISTAT Bit Fields */
9492 #define USB_ISTAT_USBRST_MASK 0x1u
9493 #define USB_ISTAT_USBRST_SHIFT 0
9494 #define USB_ISTAT_ERROR_MASK 0x2u
9495 #define USB_ISTAT_ERROR_SHIFT 1
9496 #define USB_ISTAT_SOFTOK_MASK 0x4u
9497 #define USB_ISTAT_SOFTOK_SHIFT 2
9498 #define USB_ISTAT_TOKDNE_MASK 0x8u
9499 #define USB_ISTAT_TOKDNE_SHIFT 3
9500 #define USB_ISTAT_SLEEP_MASK 0x10u
9501 #define USB_ISTAT_SLEEP_SHIFT 4
9502 #define USB_ISTAT_RESUME_MASK 0x20u
9503 #define USB_ISTAT_RESUME_SHIFT 5
9504 #define USB_ISTAT_ATTACH_MASK 0x40u
9505 #define USB_ISTAT_ATTACH_SHIFT 6
9506 #define USB_ISTAT_STALL_MASK 0x80u
9507 #define USB_ISTAT_STALL_SHIFT 7
9508 /* INTEN Bit Fields */
9509 #define USB_INTEN_USBRSTEN_MASK 0x1u
9510 #define USB_INTEN_USBRSTEN_SHIFT 0
9511 #define USB_INTEN_ERROREN_MASK 0x2u
9512 #define USB_INTEN_ERROREN_SHIFT 1
9513 #define USB_INTEN_SOFTOKEN_MASK 0x4u
9514 #define USB_INTEN_SOFTOKEN_SHIFT 2
9515 #define USB_INTEN_TOKDNEEN_MASK 0x8u
9516 #define USB_INTEN_TOKDNEEN_SHIFT 3
9517 #define USB_INTEN_SLEEPEN_MASK 0x10u
9518 #define USB_INTEN_SLEEPEN_SHIFT 4
9519 #define USB_INTEN_RESUMEEN_MASK 0x20u
9520 #define USB_INTEN_RESUMEEN_SHIFT 5
9521 #define USB_INTEN_ATTACHEN_MASK 0x40u
9522 #define USB_INTEN_ATTACHEN_SHIFT 6
9523 #define USB_INTEN_STALLEN_MASK 0x80u
9524 #define USB_INTEN_STALLEN_SHIFT 7
9525 /* ERRSTAT Bit Fields */
9526 #define USB_ERRSTAT_PIDERR_MASK 0x1u
9527 #define USB_ERRSTAT_PIDERR_SHIFT 0
9528 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
9529 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
9530 #define USB_ERRSTAT_CRC16_MASK 0x4u
9531 #define USB_ERRSTAT_CRC16_SHIFT 2
9532 #define USB_ERRSTAT_DFN8_MASK 0x8u
9533 #define USB_ERRSTAT_DFN8_SHIFT 3
9534 #define USB_ERRSTAT_BTOERR_MASK 0x10u
9535 #define USB_ERRSTAT_BTOERR_SHIFT 4
9536 #define USB_ERRSTAT_DMAERR_MASK 0x20u
9537 #define USB_ERRSTAT_DMAERR_SHIFT 5
9538 #define USB_ERRSTAT_BTSERR_MASK 0x80u
9539 #define USB_ERRSTAT_BTSERR_SHIFT 7
9540 /* ERREN Bit Fields */
9541 #define USB_ERREN_PIDERREN_MASK 0x1u
9542 #define USB_ERREN_PIDERREN_SHIFT 0
9543 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
9544 #define USB_ERREN_CRC5EOFEN_SHIFT 1
9545 #define USB_ERREN_CRC16EN_MASK 0x4u
9546 #define USB_ERREN_CRC16EN_SHIFT 2
9547 #define USB_ERREN_DFN8EN_MASK 0x8u
9548 #define USB_ERREN_DFN8EN_SHIFT 3
9549 #define USB_ERREN_BTOERREN_MASK 0x10u
9550 #define USB_ERREN_BTOERREN_SHIFT 4
9551 #define USB_ERREN_DMAERREN_MASK 0x20u
9552 #define USB_ERREN_DMAERREN_SHIFT 5
9553 #define USB_ERREN_BTSERREN_MASK 0x80u
9554 #define USB_ERREN_BTSERREN_SHIFT 7
9555 /* STAT Bit Fields */
9556 #define USB_STAT_ODD_MASK 0x4u
9557 #define USB_STAT_ODD_SHIFT 2
9558 #define USB_STAT_TX_MASK 0x8u
9559 #define USB_STAT_TX_SHIFT 3
9560 #define USB_STAT_ENDP_MASK 0xF0u
9561 #define USB_STAT_ENDP_SHIFT 4
9562 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
9563 /* CTL Bit Fields */
9564 #define USB_CTL_USBENSOFEN_MASK 0x1u
9565 #define USB_CTL_USBENSOFEN_SHIFT 0
9566 #define USB_CTL_ODDRST_MASK 0x2u
9567 #define USB_CTL_ODDRST_SHIFT 1
9568 #define USB_CTL_RESUME_MASK 0x4u
9569 #define USB_CTL_RESUME_SHIFT 2
9570 #define USB_CTL_HOSTMODEEN_MASK 0x8u
9571 #define USB_CTL_HOSTMODEEN_SHIFT 3
9572 #define USB_CTL_RESET_MASK 0x10u
9573 #define USB_CTL_RESET_SHIFT 4
9574 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
9575 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
9576 #define USB_CTL_SE0_MASK 0x40u
9577 #define USB_CTL_SE0_SHIFT 6
9578 #define USB_CTL_JSTATE_MASK 0x80u
9579 #define USB_CTL_JSTATE_SHIFT 7
9580 /* ADDR Bit Fields */
9581 #define USB_ADDR_ADDR_MASK 0x7Fu
9582 #define USB_ADDR_ADDR_SHIFT 0
9583 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
9584 #define USB_ADDR_LSEN_MASK 0x80u
9585 #define USB_ADDR_LSEN_SHIFT 7
9586 /* BDTPAGE1 Bit Fields */
9587 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
9588 #define USB_BDTPAGE1_BDTBA_SHIFT 1
9589 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
9590 /* FRMNUML Bit Fields */
9591 #define USB_FRMNUML_FRM_MASK 0xFFu
9592 #define USB_FRMNUML_FRM_SHIFT 0
9593 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
9594 /* FRMNUMH Bit Fields */
9595 #define USB_FRMNUMH_FRM_MASK 0x7u
9596 #define USB_FRMNUMH_FRM_SHIFT 0
9597 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
9598 /* TOKEN Bit Fields */
9599 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
9600 #define USB_TOKEN_TOKENENDPT_SHIFT 0
9601 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
9602 #define USB_TOKEN_TOKENPID_MASK 0xF0u
9603 #define USB_TOKEN_TOKENPID_SHIFT 4
9604 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
9605 /* SOFTHLD Bit Fields */
9606 #define USB_SOFTHLD_CNT_MASK 0xFFu
9607 #define USB_SOFTHLD_CNT_SHIFT 0
9608 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
9609 /* BDTPAGE2 Bit Fields */
9610 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
9611 #define USB_BDTPAGE2_BDTBA_SHIFT 0
9612 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
9613 /* BDTPAGE3 Bit Fields */
9614 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
9615 #define USB_BDTPAGE3_BDTBA_SHIFT 0
9616 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
9617 /* ENDPT Bit Fields */
9618 #define USB_ENDPT_EPHSHK_MASK 0x1u
9619 #define USB_ENDPT_EPHSHK_SHIFT 0
9620 #define USB_ENDPT_EPSTALL_MASK 0x2u
9621 #define USB_ENDPT_EPSTALL_SHIFT 1
9622 #define USB_ENDPT_EPTXEN_MASK 0x4u
9623 #define USB_ENDPT_EPTXEN_SHIFT 2
9624 #define USB_ENDPT_EPRXEN_MASK 0x8u
9625 #define USB_ENDPT_EPRXEN_SHIFT 3
9626 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
9627 #define USB_ENDPT_EPCTLDIS_SHIFT 4
9628 #define USB_ENDPT_RETRYDIS_MASK 0x40u
9629 #define USB_ENDPT_RETRYDIS_SHIFT 6
9630 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
9631 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
9632 /* USBCTRL Bit Fields */
9633 #define USB_USBCTRL_PDE_MASK 0x40u
9634 #define USB_USBCTRL_PDE_SHIFT 6
9635 #define USB_USBCTRL_SUSP_MASK 0x80u
9636 #define USB_USBCTRL_SUSP_SHIFT 7
9637 /* OBSERVE Bit Fields */
9638 #define USB_OBSERVE_DMPD_MASK 0x10u
9639 #define USB_OBSERVE_DMPD_SHIFT 4
9640 #define USB_OBSERVE_DPPD_MASK 0x40u
9641 #define USB_OBSERVE_DPPD_SHIFT 6
9642 #define USB_OBSERVE_DPPU_MASK 0x80u
9643 #define USB_OBSERVE_DPPU_SHIFT 7
9644 /* CONTROL Bit Fields */
9645 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
9646 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
9647 /* USBTRC0 Bit Fields */
9648 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
9649 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
9650 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
9651 #define USB_USBTRC0_SYNC_DET_SHIFT 1
9652 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
9653 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
9654 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
9655 #define USB_USBTRC0_USBRESMEN_SHIFT 5
9656 #define USB_USBTRC0_USBRESET_MASK 0x80u
9657 #define USB_USBTRC0_USBRESET_SHIFT 7
9658 /* USBFRMADJUST Bit Fields */
9659 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
9660 #define USB_USBFRMADJUST_ADJ_SHIFT 0
9661 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
9662 /* CLK_RECOVER_CTRL Bit Fields */
9663 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
9664 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
9665 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
9666 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
9667 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
9668 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
9669 /* CLK_RECOVER_IRC_EN Bit Fields */
9670 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
9671 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
9672 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
9673 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
9674 /* CLK_RECOVER_INT_STATUS Bit Fields */
9675 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
9676 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
9680 */ /* end of group USB_Register_Masks */
9683 /* USB - Peripheral instance base addresses */
9684 /** Peripheral USB0 base address */
9685 #define USB0_BASE (0x40072000u)
9686 /** Peripheral USB0 base pointer */
9687 #define USB0 ((USB_Type *)USB0_BASE)
9688 #define USB0_BASE_PTR (USB0)
9689 /** Array initializer of USB peripheral base addresses */
9690 #define USB_BASE_ADDRS { USB0_BASE }
9691 /** Array initializer of USB peripheral base pointers */
9692 #define USB_BASE_PTRS { USB0 }
9693 /** Interrupt vectors for the USB peripheral type */
9694 #define USB_IRQS { USB0_IRQn }
9696 /* ----------------------------------------------------------------------------
9697 -- USB - Register accessor macros
9698 ---------------------------------------------------------------------------- */
9701 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
9706 /* USB - Register instance definitions */
9708 #define USB0_PERID USB_PERID_REG(USB0)
9709 #define USB0_IDCOMP USB_IDCOMP_REG(USB0)
9710 #define USB0_REV USB_REV_REG(USB0)
9711 #define USB0_ADDINFO USB_ADDINFO_REG(USB0)
9712 #define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
9713 #define USB0_OTGICR USB_OTGICR_REG(USB0)
9714 #define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
9715 #define USB0_OTGCTL USB_OTGCTL_REG(USB0)
9716 #define USB0_ISTAT USB_ISTAT_REG(USB0)
9717 #define USB0_INTEN USB_INTEN_REG(USB0)
9718 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
9719 #define USB0_ERREN USB_ERREN_REG(USB0)
9720 #define USB0_STAT USB_STAT_REG(USB0)
9721 #define USB0_CTL USB_CTL_REG(USB0)
9722 #define USB0_ADDR USB_ADDR_REG(USB0)
9723 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
9724 #define USB0_FRMNUML USB_FRMNUML_REG(USB0)
9725 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
9726 #define USB0_TOKEN USB_TOKEN_REG(USB0)
9727 #define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
9728 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
9729 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
9730 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
9731 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
9732 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
9733 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
9734 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
9735 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
9736 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
9737 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
9738 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
9739 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
9740 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
9741 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
9742 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
9743 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
9744 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
9745 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
9746 #define USB0_USBCTRL USB_USBCTRL_REG(USB0)
9747 #define USB0_OBSERVE USB_OBSERVE_REG(USB0)
9748 #define USB0_CONTROL USB_CONTROL_REG(USB0)
9749 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
9750 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
9751 #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
9752 #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
9753 #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
9755 /* USB - Register array accessors */
9756 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
9760 */ /* end of group USB_Register_Accessor_Macros */
9765 */ /* end of group USB_Peripheral_Access_Layer */
9768 /* ----------------------------------------------------------------------------
9769 -- VREF Peripheral Access Layer
9770 ---------------------------------------------------------------------------- */
9773 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
9777 /** VREF - Register Layout Typedef */
9779 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
9780 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
9781 } VREF_Type, *VREF_MemMapPtr;
9783 /* ----------------------------------------------------------------------------
9784 -- VREF - Register accessor macros
9785 ---------------------------------------------------------------------------- */
9788 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
9793 /* VREF - Register accessors */
9794 #define VREF_TRM_REG(base) ((base)->TRM)
9795 #define VREF_SC_REG(base) ((base)->SC)
9799 */ /* end of group VREF_Register_Accessor_Macros */
9802 /* ----------------------------------------------------------------------------
9803 -- VREF Register Masks
9804 ---------------------------------------------------------------------------- */
9807 * @addtogroup VREF_Register_Masks VREF Register Masks
9811 /* TRM Bit Fields */
9812 #define VREF_TRM_TRIM_MASK 0x3Fu
9813 #define VREF_TRM_TRIM_SHIFT 0
9814 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
9815 #define VREF_TRM_CHOPEN_MASK 0x40u
9816 #define VREF_TRM_CHOPEN_SHIFT 6
9818 #define VREF_SC_MODE_LV_MASK 0x3u
9819 #define VREF_SC_MODE_LV_SHIFT 0
9820 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
9821 #define VREF_SC_VREFST_MASK 0x4u
9822 #define VREF_SC_VREFST_SHIFT 2
9823 #define VREF_SC_ICOMPEN_MASK 0x20u
9824 #define VREF_SC_ICOMPEN_SHIFT 5
9825 #define VREF_SC_REGEN_MASK 0x40u
9826 #define VREF_SC_REGEN_SHIFT 6
9827 #define VREF_SC_VREFEN_MASK 0x80u
9828 #define VREF_SC_VREFEN_SHIFT 7
9832 */ /* end of group VREF_Register_Masks */
9835 /* VREF - Peripheral instance base addresses */
9836 /** Peripheral VREF base address */
9837 #define VREF_BASE (0x40074000u)
9838 /** Peripheral VREF base pointer */
9839 #define VREF ((VREF_Type *)VREF_BASE)
9840 #define VREF_BASE_PTR (VREF)
9841 /** Array initializer of VREF peripheral base addresses */
9842 #define VREF_BASE_ADDRS { VREF_BASE }
9843 /** Array initializer of VREF peripheral base pointers */
9844 #define VREF_BASE_PTRS { VREF }
9846 /* ----------------------------------------------------------------------------
9847 -- VREF - Register accessor macros
9848 ---------------------------------------------------------------------------- */
9851 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
9856 /* VREF - Register instance definitions */
9858 #define VREF_TRM VREF_TRM_REG(VREF)
9859 #define VREF_SC VREF_SC_REG(VREF)
9863 */ /* end of group VREF_Register_Accessor_Macros */
9868 */ /* end of group VREF_Peripheral_Access_Layer */
9871 /* ----------------------------------------------------------------------------
9872 -- WDOG Peripheral Access Layer
9873 ---------------------------------------------------------------------------- */
9876 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
9880 /** WDOG - Register Layout Typedef */
9882 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
9883 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
9884 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
9885 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
9886 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
9887 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
9888 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
9889 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
9890 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
9891 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
9892 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
9893 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
9894 } WDOG_Type, *WDOG_MemMapPtr;
9896 /* ----------------------------------------------------------------------------
9897 -- WDOG - Register accessor macros
9898 ---------------------------------------------------------------------------- */
9901 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
9906 /* WDOG - Register accessors */
9907 #define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
9908 #define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
9909 #define WDOG_TOVALH_REG(base) ((base)->TOVALH)
9910 #define WDOG_TOVALL_REG(base) ((base)->TOVALL)
9911 #define WDOG_WINH_REG(base) ((base)->WINH)
9912 #define WDOG_WINL_REG(base) ((base)->WINL)
9913 #define WDOG_REFRESH_REG(base) ((base)->REFRESH)
9914 #define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
9915 #define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
9916 #define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
9917 #define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
9918 #define WDOG_PRESC_REG(base) ((base)->PRESC)
9922 */ /* end of group WDOG_Register_Accessor_Macros */
9925 /* ----------------------------------------------------------------------------
9926 -- WDOG Register Masks
9927 ---------------------------------------------------------------------------- */
9930 * @addtogroup WDOG_Register_Masks WDOG Register Masks
9934 /* STCTRLH Bit Fields */
9935 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
9936 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
9937 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
9938 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
9939 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
9940 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
9941 #define WDOG_STCTRLH_WINEN_MASK 0x8u
9942 #define WDOG_STCTRLH_WINEN_SHIFT 3
9943 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
9944 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
9945 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
9946 #define WDOG_STCTRLH_DBGEN_SHIFT 5
9947 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
9948 #define WDOG_STCTRLH_STOPEN_SHIFT 6
9949 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
9950 #define WDOG_STCTRLH_WAITEN_SHIFT 7
9951 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
9952 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
9953 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
9954 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
9955 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
9956 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
9957 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
9958 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
9959 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
9960 /* STCTRLL Bit Fields */
9961 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
9962 #define WDOG_STCTRLL_INTFLG_SHIFT 15
9963 /* TOVALH Bit Fields */
9964 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
9965 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
9966 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
9967 /* TOVALL Bit Fields */
9968 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
9969 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
9970 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
9971 /* WINH Bit Fields */
9972 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
9973 #define WDOG_WINH_WINHIGH_SHIFT 0
9974 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
9975 /* WINL Bit Fields */
9976 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
9977 #define WDOG_WINL_WINLOW_SHIFT 0
9978 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
9979 /* REFRESH Bit Fields */
9980 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
9981 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
9982 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
9983 /* UNLOCK Bit Fields */
9984 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
9985 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
9986 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
9987 /* TMROUTH Bit Fields */
9988 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
9989 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
9990 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
9991 /* TMROUTL Bit Fields */
9992 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
9993 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
9994 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
9995 /* RSTCNT Bit Fields */
9996 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
9997 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
9998 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
9999 /* PRESC Bit Fields */
10000 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
10001 #define WDOG_PRESC_PRESCVAL_SHIFT 8
10002 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
10006 */ /* end of group WDOG_Register_Masks */
10009 /* WDOG - Peripheral instance base addresses */
10010 /** Peripheral WDOG base address */
10011 #define WDOG_BASE (0x40052000u)
10012 /** Peripheral WDOG base pointer */
10013 #define WDOG ((WDOG_Type *)WDOG_BASE)
10014 #define WDOG_BASE_PTR (WDOG)
10015 /** Array initializer of WDOG peripheral base addresses */
10016 #define WDOG_BASE_ADDRS { WDOG_BASE }
10017 /** Array initializer of WDOG peripheral base pointers */
10018 #define WDOG_BASE_PTRS { WDOG }
10019 /** Interrupt vectors for the WDOG peripheral type */
10020 #define WDOG_IRQS { Watchdog_IRQn }
10022 /* ----------------------------------------------------------------------------
10023 -- WDOG - Register accessor macros
10024 ---------------------------------------------------------------------------- */
10027 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
10032 /* WDOG - Register instance definitions */
10034 #define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
10035 #define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
10036 #define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
10037 #define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
10038 #define WDOG_WINH WDOG_WINH_REG(WDOG)
10039 #define WDOG_WINL WDOG_WINL_REG(WDOG)
10040 #define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
10041 #define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
10042 #define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
10043 #define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
10044 #define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
10045 #define WDOG_PRESC WDOG_PRESC_REG(WDOG)
10049 */ /* end of group WDOG_Register_Accessor_Macros */
10054 */ /* end of group WDOG_Peripheral_Access_Layer */
10058 ** End of section using anonymous unions
10061 #if defined(__ARMCC_VERSION)
10063 #elif defined(__CWCC__)
10065 #elif defined(__GNUC__)
10066 /* leave anonymous unions enabled */
10067 #elif defined(__IAR_SYSTEMS_ICC__)
10068 #pragma language=default
10070 #error Not supported compiler type
10075 */ /* end of group Peripheral_access_layer */
10078 /* ----------------------------------------------------------------------------
10079 -- Backward Compatibility
10080 ---------------------------------------------------------------------------- */
10083 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
10087 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
10088 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
10089 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
10090 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
10091 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
10092 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
10093 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
10094 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
10095 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
10096 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
10097 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
10098 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
10099 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
10100 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
10101 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
10102 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
10103 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
10104 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
10105 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
10106 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
10107 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
10108 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
10109 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
10110 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
10111 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
10112 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
10113 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
10114 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
10115 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
10116 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
10117 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
10118 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
10119 #define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated
10120 #define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated
10121 #define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated
10125 */ /* end of group Backward_Compatibility_Symbols */
10128 #else /* #if !defined(MK22F51212_H_) */
10129 /* There is already included the same memory map. Check if it is compatible (has the same major version) */
10130 #if (MCU_MEM_MAP_VERSION != 0x0200u)
10131 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
10132 #warning There are included two not compatible versions of memory maps. Please check possible differences.
10133 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
10134 #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
10135 #endif /* #if !defined(MK22F51212_H_) */
10137 /* MK22F51212.h, eof. */
projects / qmk_firmware.git / blob