1 /* mbed Microcontroller Library
2 * Copyright (c) 2006-2015 ARM Limited
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
16 #include "sleep_api.h"
22 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
24 //Normal sleep mode for ARM core:
29 //Very low-power stop mode
32 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
34 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
35 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
37 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
41 //Check if PLL/FLL is enabled:
42 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
44 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
45 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
47 //Deep sleep for ARM core:
48 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
51 //Switch back to PLL as clock source if needed
52 //The interrupt that woke up the device will run at reduced speed
55 #if defined (TARGET_K20D50M)
56 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
57 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
58 MCG->C1 &= ~MCG_C1_CLKS_MASK;
60 // MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0
61 MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
62 // MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0
63 MCG->C6 = MCG_C6_VDIV0(0);
64 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } // Check that the oscillator is running
65 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
66 // MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3
67 MCG->C5 = MCG_C5_PRDIV0(5);
68 // MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3
69 MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
70 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
71 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } // Wait until the source of the PLLS clock has switched to the PLL
72 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
73 // MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0
74 MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;;
75 while((MCG->S & 0x0Cu) != 0x0Cu) { } // Wait until output of the PLL is selected
76 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
81 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);