2 ******************************************************************************
3 * @file stm32f4xx_hal_tim.c
4 * @author MCD Application Team
7 * @brief TIM HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Timer (TIM) peripheral:
10 * + Time Base Initialization
12 * + Time Base Start Interruption
13 * + Time Base Start DMA
14 * + Time Output Compare/PWM Initialization
15 * + Time Output Compare/PWM Channel Configuration
16 * + Time Output Compare/PWM Start
17 * + Time Output Compare/PWM Start Interruption
18 * + Time Output Compare/PWM Start DMA
19 * + Time Input Capture Initialization
20 * + Time Input Capture Channel Configuration
21 * + Time Input Capture Start
22 * + Time Input Capture Start Interruption
23 * + Time Input Capture Start DMA
24 * + Time One Pulse Initialization
25 * + Time One Pulse Channel Configuration
26 * + Time One Pulse Start
27 * + Time Encoder Interface Initialization
28 * + Time Encoder Interface Start
29 * + Time Encoder Interface Start Interruption
30 * + Time Encoder Interface Start DMA
31 * + Commutation Event configuration with Interruption and DMA
32 * + Time OCRef clear configuration
33 * + Time External Clock configuration
35 ==============================================================================
36 ##### TIMER Generic features #####
37 ==============================================================================
38 [..] The Timer features include:
39 (#) 16-bit up, down, up/down auto-reload counter.
40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
41 counter clock frequency either by any factor between 1 and 65536.
42 (#) Up to 4 independent channels for:
45 (++) PWM generation (Edge and Center-aligned Mode)
46 (++) One-pulse mode output
48 ##### How to use this driver #####
49 ==============================================================================
51 (#) Initialize the TIM low level resources by implementing the following functions
52 depending from feature used :
53 (++) Time Base : HAL_TIM_Base_MspInit()
54 (++) Input Capture : HAL_TIM_IC_MspInit()
55 (++) Output Compare : HAL_TIM_OC_MspInit()
56 (++) PWM generation : HAL_TIM_PWM_MspInit()
57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
60 (#) Initialize the TIM low level resources :
61 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
62 (##) TIM pins configuration
63 (+++) Enable the clock for the TIM GPIOs using the following function:
65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
67 (#) The external Clock can be configured, if needed (the default clock is the
68 internal clock from the APBx), using the following function:
69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
72 (#) Configure the TIM in the desired functioning mode using one of the
73 initialization function of this driver:
74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
76 Output Compare signal.
77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
93 (#) The DMA Burst is managed with the two following functions:
94 HAL_TIM_DMABurst_WriteStart()
95 HAL_TIM_DMABurst_ReadStart()
98 ******************************************************************************
101 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
103 * Redistribution and use in source and binary forms, with or without modification,
104 * are permitted provided that the following conditions are met:
105 * 1. Redistributions of source code must retain the above copyright notice,
106 * this list of conditions and the following disclaimer.
107 * 2. Redistributions in binary form must reproduce the above copyright notice,
108 * this list of conditions and the following disclaimer in the documentation
109 * and/or other materials provided with the distribution.
110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
111 * may be used to endorse or promote products derived from this software
112 * without specific prior written permission.
114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
125 ******************************************************************************
128 /* Includes ------------------------------------------------------------------*/
129 #include "stm32f4xx_hal.h"
131 /** @addtogroup STM32F4xx_HAL_Driver
136 * @brief TIM HAL module driver
140 #ifdef HAL_TIM_MODULE_ENABLED
142 /* Private typedef -----------------------------------------------------------*/
143 /* Private define ------------------------------------------------------------*/
144 /* Private macro -------------------------------------------------------------*/
145 /* Private variables ---------------------------------------------------------*/
146 /* Private function prototypes -----------------------------------------------*/
147 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
148 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
149 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
151 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
152 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
153 uint32_t TIM_ICFilter);
154 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
155 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
156 uint32_t TIM_ICFilter);
157 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
158 uint32_t TIM_ICFilter);
160 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
161 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
163 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
164 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
165 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
166 /* Private functions ---------------------------------------------------------*/
168 /** @defgroup TIM_Private_Functions
172 /** @defgroup TIM_Group1 Time Base functions
173 * @brief Time Base functions
176 ==============================================================================
177 ##### Time Base functions #####
178 ==============================================================================
180 This section provides functions allowing to:
181 (+) Initialize and configure the TIM base.
182 (+) De-initialize the TIM base.
183 (+) Start the Time Base.
184 (+) Stop the Time Base.
185 (+) Start the Time Base and enable interrupt.
186 (+) Stop the Time Base and disable interrupt.
187 (+) Start the Time Base and enable DMA transfer.
188 (+) Stop the Time Base and disable DMA transfer.
194 * @brief Initializes the TIM Time base Unit according to the specified
195 * parameters in the TIM_HandleTypeDef and create the associated handle.
196 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
197 * the configuration information for TIM module.
200 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
202 /* Check the TIM handle allocation */
208 /* Check the parameters */
209 assert_param(IS_TIM_INSTANCE(htim->Instance));
210 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
211 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
213 if(htim->State == HAL_TIM_STATE_RESET)
215 /* Init the low level hardware : GPIO, CLOCK, NVIC */
216 HAL_TIM_Base_MspInit(htim);
219 /* Set the TIM state */
220 htim->State= HAL_TIM_STATE_BUSY;
222 /* Set the Time Base configuration */
223 TIM_Base_SetConfig(htim->Instance, &htim->Init);
225 /* Initialize the TIM state*/
226 htim->State= HAL_TIM_STATE_READY;
232 * @brief DeInitializes the TIM Base peripheral
233 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
234 * the configuration information for TIM module.
237 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
239 /* Check the parameters */
240 assert_param(IS_TIM_INSTANCE(htim->Instance));
242 htim->State = HAL_TIM_STATE_BUSY;
244 /* Disable the TIM Peripheral Clock */
245 __HAL_TIM_DISABLE(htim);
247 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
248 HAL_TIM_Base_MspDeInit(htim);
250 /* Change TIM state */
251 htim->State = HAL_TIM_STATE_RESET;
260 * @brief Initializes the TIM Base MSP.
261 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
262 * the configuration information for TIM module.
265 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
267 /* NOTE : This function Should not be modified, when the callback is needed,
268 the HAL_TIM_Base_MspInit could be implemented in the user file
273 * @brief DeInitializes TIM Base MSP.
274 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
275 * the configuration information for TIM module.
278 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
280 /* NOTE : This function Should not be modified, when the callback is needed,
281 the HAL_TIM_Base_MspDeInit could be implemented in the user file
286 * @brief Starts the TIM Base generation.
287 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
288 * the configuration information for TIM module.
291 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
293 /* Check the parameters */
294 assert_param(IS_TIM_INSTANCE(htim->Instance));
296 /* Set the TIM state */
297 htim->State= HAL_TIM_STATE_BUSY;
299 /* Enable the Peripheral */
300 __HAL_TIM_ENABLE(htim);
302 /* Change the TIM state*/
303 htim->State= HAL_TIM_STATE_READY;
305 /* Return function status */
310 * @brief Stops the TIM Base generation.
311 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
312 * the configuration information for TIM module.
315 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
317 /* Check the parameters */
318 assert_param(IS_TIM_INSTANCE(htim->Instance));
320 /* Set the TIM state */
321 htim->State= HAL_TIM_STATE_BUSY;
323 /* Disable the Peripheral */
324 __HAL_TIM_DISABLE(htim);
326 /* Change the TIM state*/
327 htim->State= HAL_TIM_STATE_READY;
329 /* Return function status */
334 * @brief Starts the TIM Base generation in interrupt mode.
335 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
336 * the configuration information for TIM module.
339 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
341 /* Check the parameters */
342 assert_param(IS_TIM_INSTANCE(htim->Instance));
344 /* Enable the TIM Update interrupt */
345 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
347 /* Enable the Peripheral */
348 __HAL_TIM_ENABLE(htim);
350 /* Return function status */
355 * @brief Stops the TIM Base generation in interrupt mode.
356 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
357 * the configuration information for TIM module.
360 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
362 /* Check the parameters */
363 assert_param(IS_TIM_INSTANCE(htim->Instance));
364 /* Disable the TIM Update interrupt */
365 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
367 /* Disable the Peripheral */
368 __HAL_TIM_DISABLE(htim);
370 /* Return function status */
375 * @brief Starts the TIM Base generation in DMA mode.
376 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
377 * the configuration information for TIM module.
378 * @param pData: The source Buffer address.
379 * @param Length: The length of data to be transferred from memory to peripheral.
382 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
384 /* Check the parameters */
385 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
387 if((htim->State == HAL_TIM_STATE_BUSY))
391 else if((htim->State == HAL_TIM_STATE_READY))
393 if((pData == 0 ) && (Length > 0))
399 htim->State = HAL_TIM_STATE_BUSY;
402 /* Set the DMA Period elapsed callback */
403 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
405 /* Set the DMA error callback */
406 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
408 /* Enable the DMA Stream */
409 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
411 /* Enable the TIM Update DMA request */
412 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
414 /* Enable the Peripheral */
415 __HAL_TIM_ENABLE(htim);
417 /* Return function status */
422 * @brief Stops the TIM Base generation in DMA mode.
423 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
424 * the configuration information for TIM module.
427 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
429 /* Check the parameters */
430 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
432 /* Disable the TIM Update DMA request */
433 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
435 /* Disable the Peripheral */
436 __HAL_TIM_DISABLE(htim);
438 /* Change the htim state */
439 htim->State = HAL_TIM_STATE_READY;
441 /* Return function status */
449 /** @defgroup TIM_Group2 Time Output Compare functions
450 * @brief Time Output Compare functions
453 ==============================================================================
454 ##### Time Output Compare functions #####
455 ==============================================================================
457 This section provides functions allowing to:
458 (+) Initialize and configure the TIM Output Compare.
459 (+) De-initialize the TIM Output Compare.
460 (+) Start the Time Output Compare.
461 (+) Stop the Time Output Compare.
462 (+) Start the Time Output Compare and enable interrupt.
463 (+) Stop the Time Output Compare and disable interrupt.
464 (+) Start the Time Output Compare and enable DMA transfer.
465 (+) Stop the Time Output Compare and disable DMA transfer.
471 * @brief Initializes the TIM Output Compare according to the specified
472 * parameters in the TIM_HandleTypeDef and create the associated handle.
473 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
474 * the configuration information for TIM module.
477 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
479 /* Check the TIM handle allocation */
485 /* Check the parameters */
486 assert_param(IS_TIM_INSTANCE(htim->Instance));
487 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
488 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
490 if(htim->State == HAL_TIM_STATE_RESET)
492 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
493 HAL_TIM_OC_MspInit(htim);
496 /* Set the TIM state */
497 htim->State= HAL_TIM_STATE_BUSY;
499 /* Init the base time for the Output Compare */
500 TIM_Base_SetConfig(htim->Instance, &htim->Init);
502 /* Initialize the TIM state*/
503 htim->State= HAL_TIM_STATE_READY;
509 * @brief DeInitializes the TIM peripheral
510 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
511 * the configuration information for TIM module.
514 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
516 /* Check the parameters */
517 assert_param(IS_TIM_INSTANCE(htim->Instance));
519 htim->State = HAL_TIM_STATE_BUSY;
521 /* Disable the TIM Peripheral Clock */
522 __HAL_TIM_DISABLE(htim);
524 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
525 HAL_TIM_OC_MspDeInit(htim);
527 /* Change TIM state */
528 htim->State = HAL_TIM_STATE_RESET;
537 * @brief Initializes the TIM Output Compare MSP.
538 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
539 * the configuration information for TIM module.
542 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
544 /* NOTE : This function Should not be modified, when the callback is needed,
545 the HAL_TIM_OC_MspInit could be implemented in the user file
550 * @brief DeInitializes TIM Output Compare MSP.
551 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
552 * the configuration information for TIM module.
555 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
557 /* NOTE : This function Should not be modified, when the callback is needed,
558 the HAL_TIM_OC_MspDeInit could be implemented in the user file
563 * @brief Starts the TIM Output Compare signal generation.
564 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
565 * the configuration information for TIM module.
566 * @param Channel: TIM Channel to be enabled.
567 * This parameter can be one of the following values:
568 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
569 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
570 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
571 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
574 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
576 /* Check the parameters */
577 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
579 /* Enable the Output compare channel */
580 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
582 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
584 /* Enable the main output */
585 __HAL_TIM_MOE_ENABLE(htim);
588 /* Enable the Peripheral */
589 __HAL_TIM_ENABLE(htim);
591 /* Return function status */
596 * @brief Stops the TIM Output Compare signal generation.
597 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
598 * the configuration information for TIM module.
599 * @param Channel: TIM Channel to be disabled.
600 * This parameter can be one of the following values:
601 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
602 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
603 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
604 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
607 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
609 /* Check the parameters */
610 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
612 /* Disable the Output compare channel */
613 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
615 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
617 /* Disable the Main Ouput */
618 __HAL_TIM_MOE_DISABLE(htim);
621 /* Disable the Peripheral */
622 __HAL_TIM_DISABLE(htim);
624 /* Return function status */
629 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
630 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
631 * the configuration information for TIM module.
632 * @param Channel: TIM Channel to be enabled.
633 * This parameter can be one of the following values:
634 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
635 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
636 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
637 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
640 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
642 /* Check the parameters */
643 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
649 /* Enable the TIM Capture/Compare 1 interrupt */
650 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
656 /* Enable the TIM Capture/Compare 2 interrupt */
657 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
663 /* Enable the TIM Capture/Compare 3 interrupt */
664 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
670 /* Enable the TIM Capture/Compare 4 interrupt */
671 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
679 /* Enable the Output compare channel */
680 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
682 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
684 /* Enable the main output */
685 __HAL_TIM_MOE_ENABLE(htim);
688 /* Enable the Peripheral */
689 __HAL_TIM_ENABLE(htim);
691 /* Return function status */
696 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
697 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
698 * the configuration information for TIM module.
699 * @param Channel: TIM Channel to be disabled.
700 * This parameter can be one of the following values:
701 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
702 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
703 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
704 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
707 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
709 /* Check the parameters */
710 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
716 /* Disable the TIM Capture/Compare 1 interrupt */
717 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
723 /* Disable the TIM Capture/Compare 2 interrupt */
724 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
730 /* Disable the TIM Capture/Compare 3 interrupt */
731 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
737 /* Disable the TIM Capture/Compare 4 interrupt */
738 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
746 /* Disable the Output compare channel */
747 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
749 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
751 /* Disable the Main Ouput */
752 __HAL_TIM_MOE_DISABLE(htim);
755 /* Disable the Peripheral */
756 __HAL_TIM_DISABLE(htim);
758 /* Return function status */
763 * @brief Starts the TIM Output Compare signal generation in DMA mode.
764 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
765 * the configuration information for TIM module.
766 * @param Channel: TIM Channel to be enabled.
767 * This parameter can be one of the following values:
768 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
769 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
770 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
771 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
772 * @param pData: The source Buffer address.
773 * @param Length: The length of data to be transferred from memory to TIM peripheral
776 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
778 /* Check the parameters */
779 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
781 if((htim->State == HAL_TIM_STATE_BUSY))
785 else if((htim->State == HAL_TIM_STATE_READY))
787 if(((uint32_t)pData == 0 ) && (Length > 0))
793 htim->State = HAL_TIM_STATE_BUSY;
800 /* Set the DMA Period elapsed callback */
801 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
803 /* Set the DMA error callback */
804 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
806 /* Enable the DMA Stream */
807 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
809 /* Enable the TIM Capture/Compare 1 DMA request */
810 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
816 /* Set the DMA Period elapsed callback */
817 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
819 /* Set the DMA error callback */
820 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
822 /* Enable the DMA Stream */
823 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
825 /* Enable the TIM Capture/Compare 2 DMA request */
826 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
832 /* Set the DMA Period elapsed callback */
833 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
835 /* Set the DMA error callback */
836 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
838 /* Enable the DMA Stream */
839 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
841 /* Enable the TIM Capture/Compare 3 DMA request */
842 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
848 /* Set the DMA Period elapsed callback */
849 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
851 /* Set the DMA error callback */
852 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
854 /* Enable the DMA Stream */
855 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
857 /* Enable the TIM Capture/Compare 4 DMA request */
858 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
866 /* Enable the Output compare channel */
867 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
869 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
871 /* Enable the main output */
872 __HAL_TIM_MOE_ENABLE(htim);
875 /* Enable the Peripheral */
876 __HAL_TIM_ENABLE(htim);
878 /* Return function status */
883 * @brief Stops the TIM Output Compare signal generation in DMA mode.
884 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
885 * the configuration information for TIM module.
886 * @param Channel: TIM Channel to be disabled.
887 * This parameter can be one of the following values:
888 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
889 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
890 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
891 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
894 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
896 /* Check the parameters */
897 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
903 /* Disable the TIM Capture/Compare 1 DMA request */
904 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
910 /* Disable the TIM Capture/Compare 2 DMA request */
911 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
917 /* Disable the TIM Capture/Compare 3 DMA request */
918 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
924 /* Disable the TIM Capture/Compare 4 interrupt */
925 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
933 /* Disable the Output compare channel */
934 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
936 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
938 /* Disable the Main Ouput */
939 __HAL_TIM_MOE_DISABLE(htim);
942 /* Disable the Peripheral */
943 __HAL_TIM_DISABLE(htim);
945 /* Change the htim state */
946 htim->State = HAL_TIM_STATE_READY;
948 /* Return function status */
956 /** @defgroup TIM_Group3 Time PWM functions
957 * @brief Time PWM functions
960 ==============================================================================
961 ##### Time PWM functions #####
962 ==============================================================================
964 This section provides functions allowing to:
965 (+) Initialize and configure the TIM OPWM.
966 (+) De-initialize the TIM PWM.
967 (+) Start the Time PWM.
968 (+) Stop the Time PWM.
969 (+) Start the Time PWM and enable interrupt.
970 (+) Stop the Time PWM and disable interrupt.
971 (+) Start the Time PWM and enable DMA transfer.
972 (+) Stop the Time PWM and disable DMA transfer.
978 * @brief Initializes the TIM PWM Time Base according to the specified
979 * parameters in the TIM_HandleTypeDef and create the associated handle.
980 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
981 * the configuration information for TIM module.
984 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
986 /* Check the TIM handle allocation */
992 /* Check the parameters */
993 assert_param(IS_TIM_INSTANCE(htim->Instance));
994 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
995 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
997 if(htim->State == HAL_TIM_STATE_RESET)
999 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1000 HAL_TIM_PWM_MspInit(htim);
1003 /* Set the TIM state */
1004 htim->State= HAL_TIM_STATE_BUSY;
1006 /* Init the base time for the PWM */
1007 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1009 /* Initialize the TIM state*/
1010 htim->State= HAL_TIM_STATE_READY;
1016 * @brief DeInitializes the TIM peripheral
1017 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1018 * the configuration information for TIM module.
1019 * @retval HAL status
1021 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1023 /* Check the parameters */
1024 assert_param(IS_TIM_INSTANCE(htim->Instance));
1026 htim->State = HAL_TIM_STATE_BUSY;
1028 /* Disable the TIM Peripheral Clock */
1029 __HAL_TIM_DISABLE(htim);
1031 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1032 HAL_TIM_PWM_MspDeInit(htim);
1034 /* Change TIM state */
1035 htim->State = HAL_TIM_STATE_RESET;
1044 * @brief Initializes the TIM PWM MSP.
1045 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1046 * the configuration information for TIM module.
1049 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1051 /* NOTE : This function Should not be modified, when the callback is needed,
1052 the HAL_TIM_PWM_MspInit could be implemented in the user file
1057 * @brief DeInitializes TIM PWM MSP.
1058 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1059 * the configuration information for TIM module.
1062 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1064 /* NOTE : This function Should not be modified, when the callback is needed,
1065 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1070 * @brief Starts the PWM signal generation.
1071 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1072 * the configuration information for TIM module.
1073 * @param Channel: TIM Channels to be enabled.
1074 * This parameter can be one of the following values:
1075 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1076 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1077 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1078 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1079 * @retval HAL status
1081 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1083 /* Check the parameters */
1084 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1086 /* Enable the Capture compare channel */
1087 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1089 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
1091 /* Enable the main output */
1092 __HAL_TIM_MOE_ENABLE(htim);
1095 /* Enable the Peripheral */
1096 __HAL_TIM_ENABLE(htim);
1098 /* Return function status */
1103 * @brief Stops the PWM signal generation.
1104 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1105 * the configuration information for TIM module.
1106 * @param Channel: TIM Channels to be disabled.
1107 * This parameter can be one of the following values:
1108 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1109 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1110 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1111 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1112 * @retval HAL status
1114 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1116 /* Check the parameters */
1117 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1119 /* Disable the Capture compare channel */
1120 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1122 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
1124 /* Disable the Main Ouput */
1125 __HAL_TIM_MOE_DISABLE(htim);
1128 /* Disable the Peripheral */
1129 __HAL_TIM_DISABLE(htim);
1131 /* Change the htim state */
1132 htim->State = HAL_TIM_STATE_READY;
1134 /* Return function status */
1139 * @brief Starts the PWM signal generation in interrupt mode.
1140 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1141 * the configuration information for TIM module.
1142 * @param Channel: TIM Channel to be disabled.
1143 * This parameter can be one of the following values:
1144 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1145 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1146 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1147 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1148 * @retval HAL status
1150 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1152 /* Check the parameters */
1153 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1159 /* Enable the TIM Capture/Compare 1 interrupt */
1160 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1166 /* Enable the TIM Capture/Compare 2 interrupt */
1167 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1173 /* Enable the TIM Capture/Compare 3 interrupt */
1174 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1180 /* Enable the TIM Capture/Compare 4 interrupt */
1181 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1189 /* Enable the Capture compare channel */
1190 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1192 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
1194 /* Enable the main output */
1195 __HAL_TIM_MOE_ENABLE(htim);
1198 /* Enable the Peripheral */
1199 __HAL_TIM_ENABLE(htim);
1201 /* Return function status */
1206 * @brief Stops the PWM signal generation in interrupt mode.
1207 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1208 * the configuration information for TIM module.
1209 * @param Channel: TIM Channels to be disabled.
1210 * This parameter can be one of the following values:
1211 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1212 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1213 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1214 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1215 * @retval HAL status
1217 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1219 /* Check the parameters */
1220 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1226 /* Disable the TIM Capture/Compare 1 interrupt */
1227 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1233 /* Disable the TIM Capture/Compare 2 interrupt */
1234 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1240 /* Disable the TIM Capture/Compare 3 interrupt */
1241 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1247 /* Disable the TIM Capture/Compare 4 interrupt */
1248 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1256 /* Disable the Capture compare channel */
1257 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1259 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
1261 /* Disable the Main Ouput */
1262 __HAL_TIM_MOE_DISABLE(htim);
1265 /* Disable the Peripheral */
1266 __HAL_TIM_DISABLE(htim);
1268 /* Return function status */
1273 * @brief Starts the TIM PWM signal generation in DMA mode.
1274 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1275 * the configuration information for TIM module.
1276 * @param Channel: TIM Channels to be enabled.
1277 * This parameter can be one of the following values:
1278 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1279 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1280 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1281 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1282 * @param pData: The source Buffer address.
1283 * @param Length: The length of data to be transferred from memory to TIM peripheral
1284 * @retval HAL status
1286 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1288 /* Check the parameters */
1289 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1291 if((htim->State == HAL_TIM_STATE_BUSY))
1295 else if((htim->State == HAL_TIM_STATE_READY))
1297 if(((uint32_t)pData == 0 ) && (Length > 0))
1303 htim->State = HAL_TIM_STATE_BUSY;
1310 /* Set the DMA Period elapsed callback */
1311 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1313 /* Set the DMA error callback */
1314 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
1316 /* Enable the DMA Stream */
1317 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
1319 /* Enable the TIM Capture/Compare 1 DMA request */
1320 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1326 /* Set the DMA Period elapsed callback */
1327 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1329 /* Set the DMA error callback */
1330 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
1332 /* Enable the DMA Stream */
1333 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
1335 /* Enable the TIM Capture/Compare 2 DMA request */
1336 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1342 /* Set the DMA Period elapsed callback */
1343 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1345 /* Set the DMA error callback */
1346 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
1348 /* Enable the DMA Stream */
1349 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
1351 /* Enable the TIM Output Capture/Compare 3 request */
1352 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1358 /* Set the DMA Period elapsed callback */
1359 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1361 /* Set the DMA error callback */
1362 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
1364 /* Enable the DMA Stream */
1365 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
1367 /* Enable the TIM Capture/Compare 4 DMA request */
1368 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1376 /* Enable the Capture compare channel */
1377 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1379 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
1381 /* Enable the main output */
1382 __HAL_TIM_MOE_ENABLE(htim);
1385 /* Enable the Peripheral */
1386 __HAL_TIM_ENABLE(htim);
1388 /* Return function status */
1393 * @brief Stops the TIM PWM signal generation in DMA mode.
1394 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1395 * the configuration information for TIM module.
1396 * @param Channel: TIM Channels to be disabled.
1397 * This parameter can be one of the following values:
1398 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1399 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1400 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1401 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1402 * @retval HAL status
1404 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1406 /* Check the parameters */
1407 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1413 /* Disable the TIM Capture/Compare 1 DMA request */
1414 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1420 /* Disable the TIM Capture/Compare 2 DMA request */
1421 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1427 /* Disable the TIM Capture/Compare 3 DMA request */
1428 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1434 /* Disable the TIM Capture/Compare 4 interrupt */
1435 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1443 /* Disable the Capture compare channel */
1444 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1446 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
1448 /* Disable the Main Ouput */
1449 __HAL_TIM_MOE_DISABLE(htim);
1452 /* Disable the Peripheral */
1453 __HAL_TIM_DISABLE(htim);
1455 /* Change the htim state */
1456 htim->State = HAL_TIM_STATE_READY;
1458 /* Return function status */
1466 /** @defgroup TIM_Group4 Time Input Capture functions
1467 * @brief Time Input Capture functions
1470 ==============================================================================
1471 ##### Time Input Capture functions #####
1472 ==============================================================================
1474 This section provides functions allowing to:
1475 (+) Initialize and configure the TIM Input Capture.
1476 (+) De-initialize the TIM Input Capture.
1477 (+) Start the Time Input Capture.
1478 (+) Stop the Time Input Capture.
1479 (+) Start the Time Input Capture and enable interrupt.
1480 (+) Stop the Time Input Capture and disable interrupt.
1481 (+) Start the Time Input Capture and enable DMA transfer.
1482 (+) Stop the Time Input Capture and disable DMA transfer.
1488 * @brief Initializes the TIM Input Capture Time base according to the specified
1489 * parameters in the TIM_HandleTypeDef and create the associated handle.
1490 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1491 * the configuration information for TIM module.
1492 * @retval HAL status
1494 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1496 /* Check the TIM handle allocation */
1497 if(htim == HAL_NULL)
1502 /* Check the parameters */
1503 assert_param(IS_TIM_INSTANCE(htim->Instance));
1504 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1505 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1507 if(htim->State == HAL_TIM_STATE_RESET)
1509 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1510 HAL_TIM_IC_MspInit(htim);
1513 /* Set the TIM state */
1514 htim->State= HAL_TIM_STATE_BUSY;
1516 /* Init the base time for the input capture */
1517 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1519 /* Initialize the TIM state*/
1520 htim->State= HAL_TIM_STATE_READY;
1526 * @brief DeInitializes the TIM peripheral
1527 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1528 * the configuration information for TIM module.
1529 * @retval HAL status
1531 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1533 /* Check the parameters */
1534 assert_param(IS_TIM_INSTANCE(htim->Instance));
1536 htim->State = HAL_TIM_STATE_BUSY;
1538 /* Disable the TIM Peripheral Clock */
1539 __HAL_TIM_DISABLE(htim);
1541 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1542 HAL_TIM_IC_MspDeInit(htim);
1544 /* Change TIM state */
1545 htim->State = HAL_TIM_STATE_RESET;
1554 * @brief Initializes the TIM INput Capture MSP.
1555 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1556 * the configuration information for TIM module.
1559 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1561 /* NOTE : This function Should not be modified, when the callback is needed,
1562 the HAL_TIM_IC_MspInit could be implemented in the user file
1567 * @brief DeInitializes TIM Input Capture MSP.
1568 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1569 * the configuration information for TIM module.
1572 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1574 /* NOTE : This function Should not be modified, when the callback is needed,
1575 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1580 * @brief Starts the TIM Input Capture measurement.
1581 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1582 * the configuration information for TIM module.
1583 * @param Channel: TIM Channels to be enabled.
1584 * This parameter can be one of the following values:
1585 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1586 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1587 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1588 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1589 * @retval HAL status
1591 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
1593 /* Check the parameters */
1594 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1596 /* Enable the Input Capture channel */
1597 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1599 /* Enable the Peripheral */
1600 __HAL_TIM_ENABLE(htim);
1602 /* Return function status */
1607 * @brief Stops the TIM Input Capture measurement.
1608 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1609 * the configuration information for TIM module.
1610 * @param Channel: TIM Channels to be disabled.
1611 * This parameter can be one of the following values:
1612 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1613 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1614 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1615 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1616 * @retval HAL status
1618 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1620 /* Check the parameters */
1621 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1623 /* Disable the Input Capture channel */
1624 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1626 /* Disable the Peripheral */
1627 __HAL_TIM_DISABLE(htim);
1629 /* Return function status */
1634 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1635 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1636 * the configuration information for TIM module.
1637 * @param Channel: TIM Channels to be enabled.
1638 * This parameter can be one of the following values:
1639 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1640 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1641 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1642 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1643 * @retval HAL status
1645 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1647 /* Check the parameters */
1648 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1654 /* Enable the TIM Capture/Compare 1 interrupt */
1655 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1661 /* Enable the TIM Capture/Compare 2 interrupt */
1662 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1668 /* Enable the TIM Capture/Compare 3 interrupt */
1669 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1675 /* Enable the TIM Capture/Compare 4 interrupt */
1676 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1683 /* Enable the Input Capture channel */
1684 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1686 /* Enable the Peripheral */
1687 __HAL_TIM_ENABLE(htim);
1689 /* Return function status */
1694 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1695 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1696 * the configuration information for TIM module.
1697 * @param Channel: TIM Channels to be disabled.
1698 * This parameter can be one of the following values:
1699 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1700 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1701 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1702 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1703 * @retval HAL status
1705 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1707 /* Check the parameters */
1708 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1714 /* Disable the TIM Capture/Compare 1 interrupt */
1715 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1721 /* Disable the TIM Capture/Compare 2 interrupt */
1722 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1728 /* Disable the TIM Capture/Compare 3 interrupt */
1729 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1735 /* Disable the TIM Capture/Compare 4 interrupt */
1736 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1744 /* Disable the Input Capture channel */
1745 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1747 /* Disable the Peripheral */
1748 __HAL_TIM_DISABLE(htim);
1750 /* Return function status */
1755 * @brief Starts the TIM Input Capture measurement on in DMA mode.
1756 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1757 * the configuration information for TIM module.
1758 * @param Channel: TIM Channels to be enabled.
1759 * This parameter can be one of the following values:
1760 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1761 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1762 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1763 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1764 * @param pData: The destination Buffer address.
1765 * @param Length: The length of data to be transferred from TIM peripheral to memory.
1766 * @retval HAL status
1768 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1770 /* Check the parameters */
1771 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1772 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1774 if((htim->State == HAL_TIM_STATE_BUSY))
1778 else if((htim->State == HAL_TIM_STATE_READY))
1780 if((pData == 0 ) && (Length > 0))
1786 htim->State = HAL_TIM_STATE_BUSY;
1794 /* Set the DMA Period elapsed callback */
1795 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
1797 /* Set the DMA error callback */
1798 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
1800 /* Enable the DMA Stream */
1801 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
1803 /* Enable the TIM Capture/Compare 1 DMA request */
1804 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1810 /* Set the DMA Period elapsed callback */
1811 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
1813 /* Set the DMA error callback */
1814 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
1816 /* Enable the DMA Stream */
1817 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
1819 /* Enable the TIM Capture/Compare 2 DMA request */
1820 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1826 /* Set the DMA Period elapsed callback */
1827 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
1829 /* Set the DMA error callback */
1830 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
1832 /* Enable the DMA Stream */
1833 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
1835 /* Enable the TIM Capture/Compare 3 DMA request */
1836 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1842 /* Set the DMA Period elapsed callback */
1843 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
1845 /* Set the DMA error callback */
1846 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
1848 /* Enable the DMA Stream */
1849 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
1851 /* Enable the TIM Capture/Compare 4 DMA request */
1852 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1860 /* Enable the Input Capture channel */
1861 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1863 /* Enable the Peripheral */
1864 __HAL_TIM_ENABLE(htim);
1866 /* Return function status */
1871 * @brief Stops the TIM Input Capture measurement on in DMA mode.
1872 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1873 * the configuration information for TIM module.
1874 * @param Channel: TIM Channels to be disabled.
1875 * This parameter can be one of the following values:
1876 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1877 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1878 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1879 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1880 * @retval HAL status
1882 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1884 /* Check the parameters */
1885 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1886 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1892 /* Disable the TIM Capture/Compare 1 DMA request */
1893 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1899 /* Disable the TIM Capture/Compare 2 DMA request */
1900 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1906 /* Disable the TIM Capture/Compare 3 DMA request */
1907 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1913 /* Disable the TIM Capture/Compare 4 DMA request */
1914 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1922 /* Disable the Input Capture channel */
1923 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1925 /* Disable the Peripheral */
1926 __HAL_TIM_DISABLE(htim);
1928 /* Change the htim state */
1929 htim->State = HAL_TIM_STATE_READY;
1931 /* Return function status */
1938 /** @defgroup TIM_Group5 Time One Pulse functions
1939 * @brief Time One Pulse functions
1942 ==============================================================================
1943 ##### Time One Pulse functions #####
1944 ==============================================================================
1946 This section provides functions allowing to:
1947 (+) Initialize and configure the TIM One Pulse.
1948 (+) De-initialize the TIM One Pulse.
1949 (+) Start the Time One Pulse.
1950 (+) Stop the Time One Pulse.
1951 (+) Start the Time One Pulse and enable interrupt.
1952 (+) Stop the Time One Pulse and disable interrupt.
1953 (+) Start the Time One Pulse and enable DMA transfer.
1954 (+) Stop the Time One Pulse and disable DMA transfer.
1960 * @brief Initializes the TIM One Pulse Time Base according to the specified
1961 * parameters in the TIM_HandleTypeDef and create the associated handle.
1962 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1963 * the configuration information for TIM module.
1964 * @param OnePulseMode: Select the One pulse mode.
1965 * This parameter can be one of the following values:
1966 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
1967 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
1968 * @retval HAL status
1970 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
1972 /* Check the TIM handle allocation */
1973 if(htim == HAL_NULL)
1978 /* Check the parameters */
1979 assert_param(IS_TIM_INSTANCE(htim->Instance));
1980 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1981 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1982 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
1984 if(htim->State == HAL_TIM_STATE_RESET)
1986 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1987 HAL_TIM_OnePulse_MspInit(htim);
1990 /* Set the TIM state */
1991 htim->State= HAL_TIM_STATE_BUSY;
1993 /* Configure the Time base in the One Pulse Mode */
1994 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1996 /* Reset the OPM Bit */
1997 htim->Instance->CR1 &= ~TIM_CR1_OPM;
1999 /* Configure the OPM Mode */
2000 htim->Instance->CR1 |= OnePulseMode;
2002 /* Initialize the TIM state*/
2003 htim->State= HAL_TIM_STATE_READY;
2009 * @brief DeInitializes the TIM One Pulse
2010 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2011 * the configuration information for TIM module.
2012 * @retval HAL status
2014 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2016 /* Check the parameters */
2017 assert_param(IS_TIM_INSTANCE(htim->Instance));
2019 htim->State = HAL_TIM_STATE_BUSY;
2021 /* Disable the TIM Peripheral Clock */
2022 __HAL_TIM_DISABLE(htim);
2024 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2025 HAL_TIM_OnePulse_MspDeInit(htim);
2027 /* Change TIM state */
2028 htim->State = HAL_TIM_STATE_RESET;
2037 * @brief Initializes the TIM One Pulse MSP.
2038 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2039 * the configuration information for TIM module.
2042 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2044 /* NOTE : This function Should not be modified, when the callback is needed,
2045 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2050 * @brief DeInitializes TIM One Pulse MSP.
2051 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2052 * the configuration information for TIM module.
2055 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2057 /* NOTE : This function Should not be modified, when the callback is needed,
2058 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2063 * @brief Starts the TIM One Pulse signal generation.
2064 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2065 * the configuration information for TIM module.
2066 * @param OutputChannel : TIM Channels to be enabled.
2067 * This parameter can be one of the following values:
2068 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2069 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2070 * @retval HAL status
2072 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2074 /* Enable the Capture compare and the Input Capture channels
2075 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2076 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2077 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2078 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2080 No need to enable the counter, it's enabled automatically by hardware
2081 (the counter starts in response to a stimulus and generate a pulse */
2083 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2084 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2086 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
2088 /* Enable the main output */
2089 __HAL_TIM_MOE_ENABLE(htim);
2092 /* Return function status */
2097 * @brief Stops the TIM One Pulse signal generation.
2098 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2099 * the configuration information for TIM module.
2100 * @param OutputChannel : TIM Channels to be disable.
2101 * This parameter can be one of the following values:
2102 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2103 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2104 * @retval HAL status
2106 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2108 /* Disable the Capture compare and the Input Capture channels
2109 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2110 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2111 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2112 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2114 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2115 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2117 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
2119 /* Disable the Main Ouput */
2120 __HAL_TIM_MOE_DISABLE(htim);
2123 /* Disable the Peripheral */
2124 __HAL_TIM_DISABLE(htim);
2126 /* Return function status */
2131 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2132 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2133 * the configuration information for TIM module.
2134 * @param OutputChannel : TIM Channels to be enabled.
2135 * This parameter can be one of the following values:
2136 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2137 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2138 * @retval HAL status
2140 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2142 /* Enable the Capture compare and the Input Capture channels
2143 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2144 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2145 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2146 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2148 No need to enable the counter, it's enabled automatically by hardware
2149 (the counter starts in response to a stimulus and generate a pulse */
2151 /* Enable the TIM Capture/Compare 1 interrupt */
2152 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2154 /* Enable the TIM Capture/Compare 2 interrupt */
2155 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2157 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2158 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2160 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
2162 /* Enable the main output */
2163 __HAL_TIM_MOE_ENABLE(htim);
2166 /* Return function status */
2171 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2172 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2173 * the configuration information for TIM module.
2174 * @param OutputChannel : TIM Channels to be enabled.
2175 * This parameter can be one of the following values:
2176 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2177 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2178 * @retval HAL status
2180 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2182 /* Disable the TIM Capture/Compare 1 interrupt */
2183 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2185 /* Disable the TIM Capture/Compare 2 interrupt */
2186 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2188 /* Disable the Capture compare and the Input Capture channels
2189 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2190 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2191 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2192 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2193 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2194 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2196 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
2198 /* Disable the Main Ouput */
2199 __HAL_TIM_MOE_DISABLE(htim);
2202 /* Disable the Peripheral */
2203 __HAL_TIM_DISABLE(htim);
2205 /* Return function status */
2213 /** @defgroup TIM_Group6 Time Encoder functions
2214 * @brief Time Encoder functions
2217 ==============================================================================
2218 ##### Time Encoder functions #####
2219 ==============================================================================
2221 This section provides functions allowing to:
2222 (+) Initialize and configure the TIM Encoder.
2223 (+) De-initialize the TIM Encoder.
2224 (+) Start the Time Encoder.
2225 (+) Stop the Time Encoder.
2226 (+) Start the Time Encoder and enable interrupt.
2227 (+) Stop the Time Encoder and disable interrupt.
2228 (+) Start the Time Encoder and enable DMA transfer.
2229 (+) Stop the Time Encoder and disable DMA transfer.
2235 * @brief Initializes the TIM Encoder Interface and create the associated handle.
2236 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2237 * the configuration information for TIM module.
2238 * @param sConfig: TIM Encoder Interface configuration structure
2239 * @retval HAL status
2241 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
2243 uint32_t tmpsmcr = 0;
2244 uint32_t tmpccmr1 = 0;
2245 uint32_t tmpccer = 0;
2247 /* Check the TIM handle allocation */
2248 if(htim == HAL_NULL)
2253 /* Check the parameters */
2254 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2255 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2256 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2257 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2258 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
2259 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
2260 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2261 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2262 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2263 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2265 if(htim->State == HAL_TIM_STATE_RESET)
2267 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2268 HAL_TIM_Encoder_MspInit(htim);
2271 /* Set the TIM state */
2272 htim->State= HAL_TIM_STATE_BUSY;
2274 /* Reset the SMS bits */
2275 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
2277 /* Configure the Time base in the Encoder Mode */
2278 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2280 /* Get the TIMx SMCR register value */
2281 tmpsmcr = htim->Instance->SMCR;
2283 /* Get the TIMx CCMR1 register value */
2284 tmpccmr1 = htim->Instance->CCMR1;
2286 /* Get the TIMx CCER register value */
2287 tmpccer = htim->Instance->CCER;
2289 /* Set the encoder Mode */
2290 tmpsmcr |= sConfig->EncoderMode;
2292 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2293 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2294 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
2296 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2297 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2298 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2299 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
2300 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
2302 /* Set the TI1 and the TI2 Polarities */
2303 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2304 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2305 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
2307 /* Write to TIMx SMCR */
2308 htim->Instance->SMCR = tmpsmcr;
2310 /* Write to TIMx CCMR1 */
2311 htim->Instance->CCMR1 = tmpccmr1;
2313 /* Write to TIMx CCER */
2314 htim->Instance->CCER = tmpccer;
2316 /* Initialize the TIM state*/
2317 htim->State= HAL_TIM_STATE_READY;
2323 * @brief DeInitializes the TIM Encoder interface
2324 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2325 * the configuration information for TIM module.
2326 * @retval HAL status
2328 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2330 /* Check the parameters */
2331 assert_param(IS_TIM_INSTANCE(htim->Instance));
2333 htim->State = HAL_TIM_STATE_BUSY;
2335 /* Disable the TIM Peripheral Clock */
2336 __HAL_TIM_DISABLE(htim);
2338 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2339 HAL_TIM_Encoder_MspDeInit(htim);
2341 /* Change TIM state */
2342 htim->State = HAL_TIM_STATE_RESET;
2351 * @brief Initializes the TIM Encoder Interface MSP.
2352 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2353 * the configuration information for TIM module.
2356 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
2358 /* NOTE : This function Should not be modified, when the callback is needed,
2359 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2364 * @brief DeInitializes TIM Encoder Interface MSP.
2365 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2366 * the configuration information for TIM module.
2369 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
2371 /* NOTE : This function Should not be modified, when the callback is needed,
2372 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2377 * @brief Starts the TIM Encoder Interface.
2378 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2379 * the configuration information for TIM module.
2380 * @param Channel: TIM Channels to be enabled.
2381 * This parameter can be one of the following values:
2382 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2383 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2384 * @retval HAL status
2386 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2388 /* Check the parameters */
2389 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2391 /* Enable the encoder interface channels */
2396 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2401 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2406 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2407 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2411 /* Enable the Peripheral */
2412 __HAL_TIM_ENABLE(htim);
2414 /* Return function status */
2419 * @brief Stops the TIM Encoder Interface.
2420 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2421 * the configuration information for TIM module.
2422 * @param Channel: TIM Channels to be disabled.
2423 * This parameter can be one of the following values:
2424 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2425 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2426 * @retval HAL status
2428 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2430 /* Check the parameters */
2431 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2433 /* Disable the Input Capture channels 1 and 2
2434 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2439 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2444 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2449 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2450 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2454 /* Disable the Peripheral */
2455 __HAL_TIM_DISABLE(htim);
2457 /* Return function status */
2462 * @brief Starts the TIM Encoder Interface in interrupt mode.
2463 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2464 * the configuration information for TIM module.
2465 * @param Channel: TIM Channels to be enabled.
2466 * This parameter can be one of the following values:
2467 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2468 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2469 * @retval HAL status
2471 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2473 /* Check the parameters */
2474 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2476 /* Enable the encoder interface channels */
2477 /* Enable the capture compare Interrupts 1 and/or 2 */
2482 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2483 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2488 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2489 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2494 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2495 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2496 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2497 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2502 /* Enable the Peripheral */
2503 __HAL_TIM_ENABLE(htim);
2505 /* Return function status */
2510 * @brief Stops the TIM Encoder Interface in interrupt mode.
2511 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2512 * the configuration information for TIM module.
2513 * @param Channel: TIM Channels to be disabled.
2514 * This parameter can be one of the following values:
2515 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2516 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2517 * @retval HAL status
2519 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2521 /* Check the parameters */
2522 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2524 /* Disable the Input Capture channels 1 and 2
2525 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2526 if(Channel == TIM_CHANNEL_1)
2528 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2530 /* Disable the capture compare Interrupts 1 */
2531 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2533 else if(Channel == TIM_CHANNEL_2)
2535 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2537 /* Disable the capture compare Interrupts 2 */
2538 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2542 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2543 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2545 /* Disable the capture compare Interrupts 1 and 2 */
2546 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2547 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2550 /* Disable the Peripheral */
2551 __HAL_TIM_DISABLE(htim);
2553 /* Change the htim state */
2554 htim->State = HAL_TIM_STATE_READY;
2556 /* Return function status */
2561 * @brief Starts the TIM Encoder Interface in DMA mode.
2562 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2563 * the configuration information for TIM module.
2564 * @param Channel: TIM Channels to be enabled.
2565 * This parameter can be one of the following values:
2566 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2567 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2568 * @param pData1: The destination Buffer address for IC1.
2569 * @param pData2: The destination Buffer address for IC2.
2570 * @param Length: The length of data to be transferred from TIM peripheral to memory.
2571 * @retval HAL status
2573 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
2575 /* Check the parameters */
2576 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2578 if((htim->State == HAL_TIM_STATE_BUSY))
2582 else if((htim->State == HAL_TIM_STATE_READY))
2584 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
2590 htim->State = HAL_TIM_STATE_BUSY;
2598 /* Set the DMA Period elapsed callback */
2599 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
2601 /* Set the DMA error callback */
2602 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
2604 /* Enable the DMA Stream */
2605 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
2607 /* Enable the TIM Input Capture DMA request */
2608 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2610 /* Enable the Peripheral */
2611 __HAL_TIM_ENABLE(htim);
2613 /* Enable the Capture compare channel */
2614 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2620 /* Set the DMA Period elapsed callback */
2621 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
2623 /* Set the DMA error callback */
2624 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
2625 /* Enable the DMA Stream */
2626 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2628 /* Enable the TIM Input Capture DMA request */
2629 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2631 /* Enable the Peripheral */
2632 __HAL_TIM_ENABLE(htim);
2634 /* Enable the Capture compare channel */
2635 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2639 case TIM_CHANNEL_ALL:
2641 /* Set the DMA Period elapsed callback */
2642 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
2644 /* Set the DMA error callback */
2645 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
2647 /* Enable the DMA Stream */
2648 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
2650 /* Set the DMA Period elapsed callback */
2651 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
2653 /* Set the DMA error callback */
2654 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
2656 /* Enable the DMA Stream */
2657 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2659 /* Enable the Peripheral */
2660 __HAL_TIM_ENABLE(htim);
2662 /* Enable the Capture compare channel */
2663 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2664 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2666 /* Enable the TIM Input Capture DMA request */
2667 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2668 /* Enable the TIM Input Capture DMA request */
2669 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2676 /* Return function status */
2681 * @brief Stops the TIM Encoder Interface in DMA mode.
2682 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2683 * the configuration information for TIM module.
2684 * @param Channel: TIM Channels to be enabled.
2685 * This parameter can be one of the following values:
2686 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2687 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2688 * @retval HAL status
2690 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2692 /* Check the parameters */
2693 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2695 /* Disable the Input Capture channels 1 and 2
2696 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2697 if(Channel == TIM_CHANNEL_1)
2699 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2701 /* Disable the capture compare DMA Request 1 */
2702 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2704 else if(Channel == TIM_CHANNEL_2)
2706 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2708 /* Disable the capture compare DMA Request 2 */
2709 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2713 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2714 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2716 /* Disable the capture compare DMA Request 1 and 2 */
2717 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2718 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2721 /* Disable the Peripheral */
2722 __HAL_TIM_DISABLE(htim);
2724 /* Change the htim state */
2725 htim->State = HAL_TIM_STATE_READY;
2727 /* Return function status */
2734 /** @defgroup TIM_Group7 TIM IRQ handler management
2735 * @brief IRQ handler management
2738 ==============================================================================
2739 ##### IRQ handler management #####
2740 ==============================================================================
2742 This section provides Timer IRQ handler function.
2748 * @brief This function handles TIM interrupts requests.
2749 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2750 * the configuration information for TIM module.
2753 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
2755 /* Capture compare 1 event */
2756 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
2758 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
2761 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
2762 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2764 /* Input capture event */
2765 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
2767 HAL_TIM_IC_CaptureCallback(htim);
2769 /* Output compare event */
2772 HAL_TIM_OC_DelayElapsedCallback(htim);
2773 HAL_TIM_PWM_PulseFinishedCallback(htim);
2775 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2779 /* Capture compare 2 event */
2780 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
2782 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
2784 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
2785 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2786 /* Input capture event */
2787 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
2789 HAL_TIM_IC_CaptureCallback(htim);
2791 /* Output compare event */
2794 HAL_TIM_OC_DelayElapsedCallback(htim);
2795 HAL_TIM_PWM_PulseFinishedCallback(htim);
2797 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2800 /* Capture compare 3 event */
2801 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
2803 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
2805 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
2806 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2807 /* Input capture event */
2808 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
2810 HAL_TIM_IC_CaptureCallback(htim);
2812 /* Output compare event */
2815 HAL_TIM_OC_DelayElapsedCallback(htim);
2816 HAL_TIM_PWM_PulseFinishedCallback(htim);
2818 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2821 /* Capture compare 4 event */
2822 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
2824 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
2826 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
2827 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
2828 /* Input capture event */
2829 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
2831 HAL_TIM_IC_CaptureCallback(htim);
2833 /* Output compare event */
2836 HAL_TIM_OC_DelayElapsedCallback(htim);
2837 HAL_TIM_PWM_PulseFinishedCallback(htim);
2839 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2842 /* TIM Update event */
2843 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
2845 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
2847 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
2848 HAL_TIM_PeriodElapsedCallback(htim);
2851 /* TIM Break input event */
2852 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
2854 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
2856 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
2857 HAL_TIMEx_BreakCallback(htim);
2860 /* TIM Trigger detection event */
2861 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
2863 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
2865 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
2866 HAL_TIM_TriggerCallback(htim);
2869 /* TIM commutation event */
2870 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
2872 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
2874 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
2875 HAL_TIMEx_CommutationCallback(htim);
2884 /** @defgroup TIM_Group8 Peripheral Control functions
2885 * @brief Peripheral Control functions
2888 ==============================================================================
2889 ##### Peripheral Control functions #####
2890 ==============================================================================
2892 This section provides functions allowing to:
2893 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
2894 (+) Configure External Clock source.
2895 (+) Configure Complementary channels, break features and dead time.
2896 (+) Configure Master and the Slave synchronization.
2897 (+) Configure the DMA Burst Mode.
2904 * @brief Initializes the TIM Output Compare Channels according to the specified
2905 * parameters in the TIM_OC_InitTypeDef.
2906 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2907 * the configuration information for TIM module.
2908 * @param sConfig: TIM Output Compare configuration structure
2909 * @param Channel: TIM Channels to be enabled.
2910 * This parameter can be one of the following values:
2911 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2912 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2913 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2914 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2915 * @retval HAL status
2917 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
2919 /* Check the parameters */
2920 assert_param(IS_TIM_CHANNELS(Channel));
2921 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
2922 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
2923 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
2924 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
2925 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
2926 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
2928 /* Check input state */
2931 htim->State = HAL_TIM_STATE_BUSY;
2937 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2938 /* Configure the TIM Channel 1 in Output Compare */
2939 TIM_OC1_SetConfig(htim->Instance, sConfig);
2945 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2946 /* Configure the TIM Channel 2 in Output Compare */
2947 TIM_OC2_SetConfig(htim->Instance, sConfig);
2953 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2954 /* Configure the TIM Channel 3 in Output Compare */
2955 TIM_OC3_SetConfig(htim->Instance, sConfig);
2961 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
2962 /* Configure the TIM Channel 4 in Output Compare */
2963 TIM_OC4_SetConfig(htim->Instance, sConfig);
2970 htim->State = HAL_TIM_STATE_READY;
2978 * @brief Initializes the TIM Input Capture Channels according to the specified
2979 * parameters in the TIM_IC_InitTypeDef.
2980 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2981 * the configuration information for TIM module.
2982 * @param sConfig: TIM Input Capture configuration structure
2983 * @param Channel: TIM Channels to be enabled.
2984 * This parameter can be one of the following values:
2985 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2986 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2987 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2988 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2989 * @retval HAL status
2991 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
2993 /* Check the parameters */
2994 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2995 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
2996 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
2997 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
2998 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
3002 htim->State = HAL_TIM_STATE_BUSY;
3004 if (Channel == TIM_CHANNEL_1)
3006 /* TI1 Configuration */
3007 TIM_TI1_SetConfig(htim->Instance,
3008 sConfig->ICPolarity,
3009 sConfig->ICSelection,
3012 /* Reset the IC1PSC Bits */
3013 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3015 /* Set the IC1PSC value */
3016 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
3018 else if (Channel == TIM_CHANNEL_2)
3020 /* TI2 Configuration */
3021 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3023 TIM_TI2_SetConfig(htim->Instance,
3024 sConfig->ICPolarity,
3025 sConfig->ICSelection,
3028 /* Reset the IC2PSC Bits */
3029 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3031 /* Set the IC2PSC value */
3032 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
3034 else if (Channel == TIM_CHANNEL_3)
3036 /* TI3 Configuration */
3037 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3039 TIM_TI3_SetConfig(htim->Instance,
3040 sConfig->ICPolarity,
3041 sConfig->ICSelection,
3044 /* Reset the IC3PSC Bits */
3045 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
3047 /* Set the IC3PSC value */
3048 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
3052 /* TI4 Configuration */
3053 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3055 TIM_TI4_SetConfig(htim->Instance,
3056 sConfig->ICPolarity,
3057 sConfig->ICSelection,
3060 /* Reset the IC4PSC Bits */
3061 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
3063 /* Set the IC4PSC value */
3064 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
3067 htim->State = HAL_TIM_STATE_READY;
3075 * @brief Initializes the TIM PWM channels according to the specified
3076 * parameters in the TIM_OC_InitTypeDef.
3077 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3078 * the configuration information for TIM module.
3079 * @param sConfig: TIM PWM configuration structure
3080 * @param Channel: TIM Channels to be enabled.
3081 * This parameter can be one of the following values:
3082 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3083 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3084 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3085 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3086 * @retval HAL status
3088 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
3092 /* Check the parameters */
3093 assert_param(IS_TIM_CHANNELS(Channel));
3094 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
3095 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3096 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
3097 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
3098 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
3100 htim->State = HAL_TIM_STATE_BUSY;
3106 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3107 /* Configure the Channel 1 in PWM mode */
3108 TIM_OC1_SetConfig(htim->Instance, sConfig);
3110 /* Set the Preload enable bit for channel1 */
3111 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
3113 /* Configure the Output Fast mode */
3114 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
3115 htim->Instance->CCMR1 |= sConfig->OCFastMode;
3121 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3122 /* Configure the Channel 2 in PWM mode */
3123 TIM_OC2_SetConfig(htim->Instance, sConfig);
3125 /* Set the Preload enable bit for channel2 */
3126 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
3128 /* Configure the Output Fast mode */
3129 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
3130 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
3136 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3137 /* Configure the Channel 3 in PWM mode */
3138 TIM_OC3_SetConfig(htim->Instance, sConfig);
3140 /* Set the Preload enable bit for channel3 */
3141 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
3143 /* Configure the Output Fast mode */
3144 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
3145 htim->Instance->CCMR2 |= sConfig->OCFastMode;
3151 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3152 /* Configure the Channel 4 in PWM mode */
3153 TIM_OC4_SetConfig(htim->Instance, sConfig);
3155 /* Set the Preload enable bit for channel4 */
3156 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
3158 /* Configure the Output Fast mode */
3159 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
3160 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
3168 htim->State = HAL_TIM_STATE_READY;
3176 * @brief Initializes the TIM One Pulse Channels according to the specified
3177 * parameters in the TIM_OnePulse_InitTypeDef.
3178 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3179 * the configuration information for TIM module.
3180 * @param sConfig: TIM One Pulse configuration structure
3181 * @param OutputChannel: TIM Channels to be enabled.
3182 * This parameter can be one of the following values:
3183 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3184 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3185 * @param InputChannel: TIM Channels to be enabled.
3186 * This parameter can be one of the following values:
3187 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3188 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3189 * @retval HAL status
3191 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
3193 TIM_OC_InitTypeDef temp1;
3195 /* Check the parameters */
3196 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
3197 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
3199 if(OutputChannel != InputChannel)
3203 htim->State = HAL_TIM_STATE_BUSY;
3205 /* Extract the Ouput compare configuration from sConfig structure */
3206 temp1.OCMode = sConfig->OCMode;
3207 temp1.Pulse = sConfig->Pulse;
3208 temp1.OCPolarity = sConfig->OCPolarity;
3209 temp1.OCNPolarity = sConfig->OCNPolarity;
3210 temp1.OCIdleState = sConfig->OCIdleState;
3211 temp1.OCNIdleState = sConfig->OCNIdleState;
3213 switch (OutputChannel)
3217 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3219 TIM_OC1_SetConfig(htim->Instance, &temp1);
3224 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3226 TIM_OC2_SetConfig(htim->Instance, &temp1);
3232 switch (InputChannel)
3236 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3238 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3239 sConfig->ICSelection, sConfig->ICFilter);
3241 /* Reset the IC1PSC Bits */
3242 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3244 /* Select the Trigger source */
3245 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3246 htim->Instance->SMCR |= TIM_TS_TI1FP1;
3248 /* Select the Slave Mode */
3249 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3250 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3255 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3257 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3258 sConfig->ICSelection, sConfig->ICFilter);
3260 /* Reset the IC2PSC Bits */
3261 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3263 /* Select the Trigger source */
3264 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3265 htim->Instance->SMCR |= TIM_TS_TI2FP2;
3267 /* Select the Slave Mode */
3268 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3269 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3277 htim->State = HAL_TIM_STATE_READY;
3290 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3291 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3292 * the configuration information for TIM module.
3293 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
3294 * This parameters can be on of the following values:
3295 * @arg TIM_DMABase_CR1
3296 * @arg TIM_DMABase_CR2
3297 * @arg TIM_DMABase_SMCR
3298 * @arg TIM_DMABase_DIER
3299 * @arg TIM_DMABase_SR
3300 * @arg TIM_DMABase_EGR
3301 * @arg TIM_DMABase_CCMR1
3302 * @arg TIM_DMABase_CCMR2
3303 * @arg TIM_DMABase_CCER
3304 * @arg TIM_DMABase_CNT
3305 * @arg TIM_DMABase_PSC
3306 * @arg TIM_DMABase_ARR
3307 * @arg TIM_DMABase_RCR
3308 * @arg TIM_DMABase_CCR1
3309 * @arg TIM_DMABase_CCR2
3310 * @arg TIM_DMABase_CCR3
3311 * @arg TIM_DMABase_CCR4
3312 * @arg TIM_DMABase_BDTR
3313 * @arg TIM_DMABase_DCR
3314 * @param BurstRequestSrc: TIM DMA Request sources.
3315 * This parameters can be on of the following values:
3316 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3317 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3318 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3319 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3320 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3321 * @arg TIM_DMA_COM: TIM Commutation DMA source
3322 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3323 * @param BurstBuffer: The Buffer address.
3324 * @param BurstLength: DMA Burst length. This parameter can be one value
3325 * between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
3326 * @retval HAL status
3328 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3329 uint32_t* BurstBuffer, uint32_t BurstLength)
3331 /* Check the parameters */
3332 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3333 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3334 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3335 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3337 if((htim->State == HAL_TIM_STATE_BUSY))
3341 else if((htim->State == HAL_TIM_STATE_READY))
3343 if((BurstBuffer == 0 ) && (BurstLength > 0))
3349 htim->State = HAL_TIM_STATE_BUSY;
3352 switch(BurstRequestSrc)
3354 case TIM_DMA_UPDATE:
3356 /* Set the DMA Period elapsed callback */
3357 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3359 /* Set the DMA error callback */
3360 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
3362 /* Enable the DMA Stream */
3363 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3368 /* Set the DMA Period elapsed callback */
3369 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
3371 /* Set the DMA error callback */
3372 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
3374 /* Enable the DMA Stream */
3375 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3380 /* Set the DMA Period elapsed callback */
3381 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
3383 /* Set the DMA error callback */
3384 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
3386 /* Enable the DMA Stream */
3387 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3392 /* Set the DMA Period elapsed callback */
3393 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
3395 /* Set the DMA error callback */
3396 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
3398 /* Enable the DMA Stream */
3399 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3404 /* Set the DMA Period elapsed callback */
3405 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
3407 /* Set the DMA error callback */
3408 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
3410 /* Enable the DMA Stream */
3411 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3416 /* Set the DMA Period elapsed callback */
3417 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
3419 /* Set the DMA error callback */
3420 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
3422 /* Enable the DMA Stream */
3423 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3426 case TIM_DMA_TRIGGER:
3428 /* Set the DMA Period elapsed callback */
3429 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3431 /* Set the DMA error callback */
3432 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
3434 /* Enable the DMA Stream */
3435 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3441 /* configure the DMA Burst Mode */
3442 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3444 /* Enable the TIM DMA Request */
3445 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3447 htim->State = HAL_TIM_STATE_READY;
3449 /* Return function status */
3454 * @brief Stops the TIM DMA Burst mode
3455 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3456 * the configuration information for TIM module.
3457 * @param BurstRequestSrc: TIM DMA Request sources to disable
3458 * @retval HAL status
3460 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3462 /* Check the parameters */
3463 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3465 /* Disable the TIM Update DMA request */
3466 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3468 /* Return function status */
3473 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
3474 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3475 * the configuration information for TIM module.
3476 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
3477 * This parameters can be on of the following values:
3478 * @arg TIM_DMABase_CR1
3479 * @arg TIM_DMABase_CR2
3480 * @arg TIM_DMABase_SMCR
3481 * @arg TIM_DMABase_DIER
3482 * @arg TIM_DMABase_SR
3483 * @arg TIM_DMABase_EGR
3484 * @arg TIM_DMABase_CCMR1
3485 * @arg TIM_DMABase_CCMR2
3486 * @arg TIM_DMABase_CCER
3487 * @arg TIM_DMABase_CNT
3488 * @arg TIM_DMABase_PSC
3489 * @arg TIM_DMABase_ARR
3490 * @arg TIM_DMABase_RCR
3491 * @arg TIM_DMABase_CCR1
3492 * @arg TIM_DMABase_CCR2
3493 * @arg TIM_DMABase_CCR3
3494 * @arg TIM_DMABase_CCR4
3495 * @arg TIM_DMABase_BDTR
3496 * @arg TIM_DMABase_DCR
3497 * @param BurstRequestSrc: TIM DMA Request sources.
3498 * This parameters can be on of the following values:
3499 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3500 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3501 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3502 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3503 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3504 * @arg TIM_DMA_COM: TIM Commutation DMA source
3505 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3506 * @param BurstBuffer: The Buffer address.
3507 * @param BurstLength: DMA Burst length. This parameter can be one value
3508 * between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
3509 * @retval HAL status
3511 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3512 uint32_t *BurstBuffer, uint32_t BurstLength)
3514 /* Check the parameters */
3515 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3516 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3517 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3518 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3520 if((htim->State == HAL_TIM_STATE_BUSY))
3524 else if((htim->State == HAL_TIM_STATE_READY))
3526 if((BurstBuffer == 0 ) && (BurstLength > 0))
3532 htim->State = HAL_TIM_STATE_BUSY;
3535 switch(BurstRequestSrc)
3537 case TIM_DMA_UPDATE:
3539 /* Set the DMA Period elapsed callback */
3540 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3542 /* Set the DMA error callback */
3543 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
3545 /* Enable the DMA Stream */
3546 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3551 /* Set the DMA Period elapsed callback */
3552 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
3554 /* Set the DMA error callback */
3555 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
3557 /* Enable the DMA Stream */
3558 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3563 /* Set the DMA Period elapsed callback */
3564 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
3566 /* Set the DMA error callback */
3567 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
3569 /* Enable the DMA Stream */
3570 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3575 /* Set the DMA Period elapsed callback */
3576 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
3578 /* Set the DMA error callback */
3579 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
3581 /* Enable the DMA Stream */
3582 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3587 /* Set the DMA Period elapsed callback */
3588 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
3590 /* Set the DMA error callback */
3591 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
3593 /* Enable the DMA Stream */
3594 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3599 /* Set the DMA Period elapsed callback */
3600 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
3602 /* Set the DMA error callback */
3603 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
3605 /* Enable the DMA Stream */
3606 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3609 case TIM_DMA_TRIGGER:
3611 /* Set the DMA Period elapsed callback */
3612 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3614 /* Set the DMA error callback */
3615 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
3617 /* Enable the DMA Stream */
3618 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3625 /* configure the DMA Burst Mode */
3626 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3628 /* Enable the TIM DMA Request */
3629 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3631 htim->State = HAL_TIM_STATE_READY;
3633 /* Return function status */
3638 * @brief Stop the DMA burst reading
3639 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3640 * the configuration information for TIM module.
3641 * @param BurstRequestSrc: TIM DMA Request sources to disable.
3642 * @retval HAL status
3644 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3646 /* Check the parameters */
3647 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3649 /* Disable the TIM Update DMA request */
3650 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3652 /* Return function status */
3657 * @brief Generate a software event
3658 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3659 * the configuration information for TIM module.
3660 * @param EventSource: specifies the event source.
3661 * This parameter can be one of the following values:
3662 * @arg TIM_EventSource_Update: Timer update Event source
3663 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
3664 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
3665 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
3666 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
3667 * @arg TIM_EventSource_COM: Timer COM event source
3668 * @arg TIM_EventSource_Trigger: Timer Trigger Event source
3669 * @arg TIM_EventSource_Break: Timer Break event source
3670 * @note TIM6 and TIM7 can only generate an update event.
3671 * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
3672 * @retval HAL status
3675 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
3677 /* Check the parameters */
3678 assert_param(IS_TIM_INSTANCE(htim->Instance));
3679 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
3681 /* Process Locked */
3684 /* Change the TIM state */
3685 htim->State = HAL_TIM_STATE_BUSY;
3687 /* Set the event sources */
3688 htim->Instance->EGR = EventSource;
3690 /* Change the TIM state */
3691 htim->State = HAL_TIM_STATE_READY;
3695 /* Return function status */
3700 * @brief Configures the OCRef clear feature
3701 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3702 * the configuration information for TIM module.
3703 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
3704 * contains the OCREF clear feature and parameters for the TIM peripheral.
3705 * @param Channel: specifies the TIM Channel.
3706 * This parameter can be one of the following values:
3707 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3708 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3709 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3710 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3711 * @retval HAL status
3713 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
3715 /* Check the parameters */
3716 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3717 assert_param(IS_TIM_CHANNELS(Channel));
3718 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
3719 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
3720 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
3721 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
3723 /* Process Locked */
3726 htim->State = HAL_TIM_STATE_BUSY;
3728 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
3730 TIM_ETR_SetConfig(htim->Instance,
3731 sClearInputConfig->ClearInputPrescaler,
3732 sClearInputConfig->ClearInputPolarity,
3733 sClearInputConfig->ClearInputFilter);
3740 if(sClearInputConfig->ClearInputState != RESET)
3742 /* Enable the Ocref clear feature for Channel 1 */
3743 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
3747 /* Disable the Ocref clear feature for Channel 1 */
3748 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
3754 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3755 if(sClearInputConfig->ClearInputState != RESET)
3757 /* Enable the Ocref clear feature for Channel 2 */
3758 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
3762 /* Disable the Ocref clear feature for Channel 2 */
3763 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
3769 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3770 if(sClearInputConfig->ClearInputState != RESET)
3772 /* Enable the Ocref clear feature for Channel 3 */
3773 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
3777 /* Disable the Ocref clear feature for Channel 3 */
3778 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
3784 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3785 if(sClearInputConfig->ClearInputState != RESET)
3787 /* Enable the Ocref clear feature for Channel 4 */
3788 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
3792 /* Disable the Ocref clear feature for Channel 4 */
3793 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
3801 htim->State = HAL_TIM_STATE_READY;
3809 * @brief Configures the clock source to be used
3810 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3811 * the configuration information for TIM module.
3812 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
3813 * contains the clock source information for the TIM peripheral.
3814 * @retval HAL status
3816 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
3818 uint32_t tmpsmcr = 0;
3820 /* Process Locked */
3823 htim->State = HAL_TIM_STATE_BUSY;
3825 /* Check the parameters */
3826 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
3827 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
3828 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
3829 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
3831 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
3832 tmpsmcr = htim->Instance->SMCR;
3833 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3834 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
3835 htim->Instance->SMCR = tmpsmcr;
3837 switch (sClockSourceConfig->ClockSource)
3839 case TIM_CLOCKSOURCE_INTERNAL:
3841 assert_param(IS_TIM_INSTANCE(htim->Instance));
3842 /* Disable slave mode to clock the prescaler directly with the internal clock */
3843 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3847 case TIM_CLOCKSOURCE_ETRMODE1:
3849 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
3850 /* Configure the ETR Clock source */
3851 TIM_ETR_SetConfig(htim->Instance,
3852 sClockSourceConfig->ClockPrescaler,
3853 sClockSourceConfig->ClockPolarity,
3854 sClockSourceConfig->ClockFilter);
3855 /* Get the TIMx SMCR register value */
3856 tmpsmcr = htim->Instance->SMCR;
3857 /* Reset the SMS and TS Bits */
3858 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3859 /* Select the External clock mode1 and the ETRF trigger */
3860 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
3861 /* Write to TIMx SMCR */
3862 htim->Instance->SMCR = tmpsmcr;
3866 case TIM_CLOCKSOURCE_ETRMODE2:
3868 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
3869 /* Configure the ETR Clock source */
3870 TIM_ETR_SetConfig(htim->Instance,
3871 sClockSourceConfig->ClockPrescaler,
3872 sClockSourceConfig->ClockPolarity,
3873 sClockSourceConfig->ClockFilter);
3874 /* Enable the External clock mode2 */
3875 htim->Instance->SMCR |= TIM_SMCR_ECE;
3879 case TIM_CLOCKSOURCE_TI1:
3881 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3882 TIM_TI1_ConfigInputStage(htim->Instance,
3883 sClockSourceConfig->ClockPolarity,
3884 sClockSourceConfig->ClockFilter);
3885 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
3888 case TIM_CLOCKSOURCE_TI2:
3890 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3891 TIM_TI2_ConfigInputStage(htim->Instance,
3892 sClockSourceConfig->ClockPolarity,
3893 sClockSourceConfig->ClockFilter);
3894 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
3897 case TIM_CLOCKSOURCE_TI1ED:
3899 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3900 TIM_TI1_ConfigInputStage(htim->Instance,
3901 sClockSourceConfig->ClockPolarity,
3902 sClockSourceConfig->ClockFilter);
3903 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
3906 case TIM_CLOCKSOURCE_ITR0:
3908 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3909 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
3912 case TIM_CLOCKSOURCE_ITR1:
3914 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3915 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
3918 case TIM_CLOCKSOURCE_ITR2:
3920 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3921 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
3924 case TIM_CLOCKSOURCE_ITR3:
3926 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3927 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
3934 htim->State = HAL_TIM_STATE_READY;
3942 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
3943 * or a XOR combination between CH1_input, CH2_input & CH3_input
3944 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3945 * the configuration information for TIM module..
3946 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
3947 * output of a XOR gate.
3948 * This parameter can be one of the following values:
3949 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
3950 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
3951 * pins are connected to the TI1 input (XOR combination)
3952 * @retval HAL status
3954 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
3956 uint32_t tmpcr2 = 0;
3958 /* Check the parameters */
3959 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
3960 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
3962 /* Get the TIMx CR2 register value */
3963 tmpcr2 = htim->Instance->CR2;
3965 /* Reset the TI1 selection */
3966 tmpcr2 &= ~TIM_CR2_TI1S;
3968 /* Set the the TI1 selection */
3969 tmpcr2 |= TI1_Selection;
3971 /* Write to TIMxCR2 */
3972 htim->Instance->CR2 = tmpcr2;
3978 * @brief Configures the TIM in Slave mode
3979 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3980 * the configuration information for TIM module..
3981 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
3982 * contains the selected trigger (internal trigger input, filtered
3983 * timer input or external trigger input) and the ) and the Slave
3984 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
3985 * @retval HAL status
3987 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
3989 uint32_t tmpsmcr = 0;
3990 uint32_t tmpccmr1 = 0;
3991 uint32_t tmpccer = 0;
3993 /* Check the parameters */
3994 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
3995 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
3996 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4000 htim->State = HAL_TIM_STATE_BUSY;
4002 /* Get the TIMx SMCR register value */
4003 tmpsmcr = htim->Instance->SMCR;
4005 /* Reset the Trigger Selection Bits */
4006 tmpsmcr &= ~TIM_SMCR_TS;
4007 /* Set the Input Trigger source */
4008 tmpsmcr |= sSlaveConfig->InputTrigger;
4010 /* Reset the slave mode Bits */
4011 tmpsmcr &= ~TIM_SMCR_SMS;
4012 /* Set the slave mode */
4013 tmpsmcr |= sSlaveConfig->SlaveMode;
4015 /* Write to TIMx SMCR */
4016 htim->Instance->SMCR = tmpsmcr;
4018 /* Configure the trigger prescaler, filter, and polarity */
4019 switch (sSlaveConfig->InputTrigger)
4023 /* Check the parameters */
4024 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
4025 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
4026 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4027 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4028 /* Configure the ETR Trigger source */
4029 TIM_ETR_SetConfig(htim->Instance,
4030 sSlaveConfig->TriggerPrescaler,
4031 sSlaveConfig->TriggerPolarity,
4032 sSlaveConfig->TriggerFilter);
4036 case TIM_TS_TI1F_ED:
4038 /* Check the parameters */
4039 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4040 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4042 /* Disable the Channel 1: Reset the CC1E Bit */
4043 tmpccer = htim->Instance->CCER;
4044 htim->Instance->CCER &= ~TIM_CCER_CC1E;
4045 tmpccmr1 = htim->Instance->CCMR1;
4047 /* Set the filter */
4048 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4049 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
4051 /* Write to TIMx CCMR1 and CCER registers */
4052 htim->Instance->CCMR1 = tmpccmr1;
4053 htim->Instance->CCER = tmpccer;
4060 /* Check the parameters */
4061 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4062 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4063 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4065 /* Configure TI1 Filter and Polarity */
4066 TIM_TI1_ConfigInputStage(htim->Instance,
4067 sSlaveConfig->TriggerPolarity,
4068 sSlaveConfig->TriggerFilter);
4074 /* Check the parameters */
4075 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4076 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4077 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4079 /* Configure TI2 Filter and Polarity */
4080 TIM_TI2_ConfigInputStage(htim->Instance,
4081 sSlaveConfig->TriggerPolarity,
4082 sSlaveConfig->TriggerFilter);
4088 /* Check the parameter */
4089 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4095 /* Check the parameter */
4096 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4102 /* Check the parameter */
4103 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4109 /* Check the parameter */
4110 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4118 htim->State = HAL_TIM_STATE_READY;
4126 * @brief Read the captured value from Capture Compare unit
4127 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4128 * the configuration information for TIM module..
4129 * @param Channel: TIM Channels to be enabled.
4130 * This parameter can be one of the following values:
4131 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4132 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4133 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4134 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4135 * @retval Captured value
4137 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
4139 uint32_t tmpreg = 0;
4147 /* Check the parameters */
4148 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4150 /* Return the capture 1 value */
4151 tmpreg = htim->Instance->CCR1;
4157 /* Check the parameters */
4158 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4160 /* Return the capture 2 value */
4161 tmpreg = htim->Instance->CCR2;
4168 /* Check the parameters */
4169 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4171 /* Return the capture 3 value */
4172 tmpreg = htim->Instance->CCR3;
4179 /* Check the parameters */
4180 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4182 /* Return the capture 4 value */
4183 tmpreg = htim->Instance->CCR4;
4200 /** @defgroup TIM_Group9 TIM Callbacks functions
4201 * @brief TIM Callbacks functions
4204 ==============================================================================
4205 ##### TIM Callbacks functions #####
4206 ==============================================================================
4208 This section provides TIM callback functions:
4209 (+) Timer Period elapsed callback
4210 (+) Timer Output Compare callback
4211 (+) Timer Input capture callback
4212 (+) Timer Trigger callback
4213 (+) Timer Error callback
4220 * @brief Period elapsed callback in non blocking mode
4221 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4222 * the configuration information for TIM module.
4225 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
4227 /* NOTE : This function Should not be modified, when the callback is needed,
4228 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4233 * @brief Output Compare callback in non blocking mode
4234 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4235 * the configuration information for TIM module.
4238 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
4240 /* NOTE : This function Should not be modified, when the callback is needed,
4241 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
4245 * @brief Input Capture callback in non blocking mode
4246 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4247 * the configuration information for TIM module.
4250 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
4252 /* NOTE : This function Should not be modified, when the callback is needed,
4253 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
4258 * @brief PWM Pulse finished callback in non blocking mode
4259 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4260 * the configuration information for TIM module.
4263 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
4265 /* NOTE : This function Should not be modified, when the callback is needed,
4266 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
4271 * @brief Hall Trigger detection callback in non blocking mode
4272 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4273 * the configuration information for TIM module.
4276 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
4278 /* NOTE : This function Should not be modified, when the callback is needed,
4279 the HAL_TIM_TriggerCallback could be implemented in the user file
4284 * @brief Timer error callback in non blocking mode
4285 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4286 * the configuration information for TIM module.
4289 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
4291 /* NOTE : This function Should not be modified, when the callback is needed,
4292 the HAL_TIM_ErrorCallback could be implemented in the user file
4300 /** @defgroup TIM_Group10 Peripheral State functions
4301 * @brief Peripheral State functions
4304 ==============================================================================
4305 ##### Peripheral State functions #####
4306 ==============================================================================
4308 This subsection permits to get in run-time the status of the peripheral
4316 * @brief Return the TIM Base state
4317 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4318 * the configuration information for TIM module.
4321 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
4327 * @brief Return the TIM OC state
4328 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4329 * the configuration information for TIM module.
4332 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
4338 * @brief Return the TIM PWM state
4339 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4340 * the configuration information for TIM module.
4343 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
4349 * @brief Return the TIM Input Capture state
4350 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4351 * the configuration information for TIM module.
4354 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
4360 * @brief Return the TIM One Pulse Mode state
4361 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4362 * the configuration information for TIM module.
4365 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
4371 * @brief Return the TIM Encoder Mode state
4372 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4373 * the configuration information for TIM module.
4376 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
4386 * @brief TIM DMA error callback
4387 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4388 * the configuration information for the specified DMA module.
4391 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
4393 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4395 htim->State= HAL_TIM_STATE_READY;
4397 HAL_TIM_ErrorCallback(htim);
4401 * @brief TIM DMA Delay Pulse complete callback.
4402 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4403 * the configuration information for the specified DMA module.
4406 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
4408 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4410 htim->State= HAL_TIM_STATE_READY;
4412 HAL_TIM_PWM_PulseFinishedCallback(htim);
4415 * @brief TIM DMA Capture complete callback.
4416 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4417 * the configuration information for the specified DMA module.
4420 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
4422 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4424 htim->State= HAL_TIM_STATE_READY;
4426 HAL_TIM_IC_CaptureCallback(htim);
4431 * @brief TIM DMA Period Elapse complete callback.
4432 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4433 * the configuration information for the specified DMA module.
4436 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
4438 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4440 htim->State= HAL_TIM_STATE_READY;
4442 HAL_TIM_PeriodElapsedCallback(htim);
4446 * @brief TIM DMA Trigger callback.
4447 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4448 * the configuration information for the specified DMA module.
4451 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
4453 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4455 htim->State= HAL_TIM_STATE_READY;
4457 HAL_TIM_TriggerCallback(htim);
4461 * @brief Time Base configuration
4462 * @param TIMx: TIM periheral
4465 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
4467 uint32_t tmpcr1 = 0;
4470 /* Set TIM Time Base Unit parameters ---------------------------------------*/
4471 if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
4473 /* Select the Counter Mode */
4474 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
4475 tmpcr1 |= Structure->CounterMode;
4478 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
4480 /* Set the clock division */
4481 tmpcr1 &= ~TIM_CR1_CKD;
4482 tmpcr1 |= (uint32_t)Structure->ClockDivision;
4487 /* Set the Autoreload value */
4488 TIMx->ARR = (uint32_t)Structure->Period ;
4490 /* Set the Prescaler value */
4491 TIMx->PSC = (uint32_t)Structure->Prescaler;
4493 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
4495 /* Set the Repetition Counter value */
4496 TIMx->RCR = Structure->RepetitionCounter;
4499 /* Generate an update event to reload the Prescaler
4500 and the repetition counter(only for TIM1 and TIM8) value immediatly */
4501 TIMx->EGR = TIM_EGR_UG;
4505 * @brief Time Ouput Compare 1 configuration
4506 * @param TIMx to select the TIM peripheral
4507 * @param OC_Config: The ouput configuration structure
4510 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4512 uint32_t tmpccmrx = 0;
4513 uint32_t tmpccer = 0;
4514 uint32_t tmpcr2 = 0;
4516 /* Disable the Channel 1: Reset the CC1E Bit */
4517 TIMx->CCER &= ~TIM_CCER_CC1E;
4519 /* Get the TIMx CCER register value */
4520 tmpccer = TIMx->CCER;
4521 /* Get the TIMx CR2 register value */
4524 /* Get the TIMx CCMR1 register value */
4525 tmpccmrx = TIMx->CCMR1;
4527 /* Reset the Output Compare Mode Bits */
4528 tmpccmrx &= ~TIM_CCMR1_OC1M;
4529 tmpccmrx &= ~TIM_CCMR1_CC1S;
4530 /* Select the Output Compare Mode */
4531 tmpccmrx |= OC_Config->OCMode;
4533 /* Reset the Output Polarity level */
4534 tmpccer &= ~TIM_CCER_CC1P;
4535 /* Set the Output Compare Polarity */
4536 tmpccer |= OC_Config->OCPolarity;
4539 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
4541 /* Reset the Output N Polarity level */
4542 tmpccer &= ~TIM_CCER_CC1NP;
4543 /* Set the Output N Polarity */
4544 tmpccer |= OC_Config->OCNPolarity;
4545 /* Reset the Output N State */
4546 tmpccer &= ~TIM_CCER_CC1NE;
4548 /* Reset the Output Compare and Output Compare N IDLE State */
4549 tmpcr2 &= ~TIM_CR2_OIS1;
4550 tmpcr2 &= ~TIM_CR2_OIS1N;
4551 /* Set the Output Idle state */
4552 tmpcr2 |= OC_Config->OCIdleState;
4553 /* Set the Output N Idle state */
4554 tmpcr2 |= OC_Config->OCNIdleState;
4556 /* Write to TIMx CR2 */
4559 /* Write to TIMx CCMR1 */
4560 TIMx->CCMR1 = tmpccmrx;
4562 /* Set the Capture Compare Register value */
4563 TIMx->CCR1 = OC_Config->Pulse;
4565 /* Write to TIMx CCER */
4566 TIMx->CCER = tmpccer;
4570 * @brief Time Ouput Compare 2 configuration
4571 * @param TIMx to select the TIM peripheral
4572 * @param OC_Config: The ouput configuration structure
4575 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4577 uint32_t tmpccmrx = 0;
4578 uint32_t tmpccer = 0;
4579 uint32_t tmpcr2 = 0;
4581 /* Disable the Channel 2: Reset the CC2E Bit */
4582 TIMx->CCER &= ~TIM_CCER_CC2E;
4584 /* Get the TIMx CCER register value */
4585 tmpccer = TIMx->CCER;
4586 /* Get the TIMx CR2 register value */
4589 /* Get the TIMx CCMR1 register value */
4590 tmpccmrx = TIMx->CCMR1;
4592 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4593 tmpccmrx &= ~TIM_CCMR1_OC2M;
4594 tmpccmrx &= ~TIM_CCMR1_CC2S;
4596 /* Select the Output Compare Mode */
4597 tmpccmrx |= (OC_Config->OCMode << 8);
4599 /* Reset the Output Polarity level */
4600 tmpccer &= ~TIM_CCER_CC2P;
4601 /* Set the Output Compare Polarity */
4602 tmpccer |= (OC_Config->OCPolarity << 4);
4604 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
4606 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4607 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4608 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4610 /* Reset the Output N Polarity level */
4611 tmpccer &= ~TIM_CCER_CC2NP;
4612 /* Set the Output N Polarity */
4613 tmpccer |= (OC_Config->OCNPolarity << 4);
4614 /* Reset the Output N State */
4615 tmpccer &= ~TIM_CCER_CC2NE;
4617 /* Reset the Output Compare and Output Compare N IDLE State */
4618 tmpcr2 &= ~TIM_CR2_OIS2;
4619 tmpcr2 &= ~TIM_CR2_OIS2N;
4620 /* Set the Output Idle state */
4621 tmpcr2 |= (OC_Config->OCIdleState << 2);
4622 /* Set the Output N Idle state */
4623 tmpcr2 |= (OC_Config->OCNIdleState << 2);
4625 /* Write to TIMx CR2 */
4628 /* Write to TIMx CCMR1 */
4629 TIMx->CCMR1 = tmpccmrx;
4631 /* Set the Capture Compare Register value */
4632 TIMx->CCR2 = OC_Config->Pulse;
4634 /* Write to TIMx CCER */
4635 TIMx->CCER = tmpccer;
4639 * @brief Time Ouput Compare 3 configuration
4640 * @param TIMx to select the TIM peripheral
4641 * @param OC_Config: The ouput configuration structure
4644 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4646 uint32_t tmpccmrx = 0;
4647 uint32_t tmpccer = 0;
4648 uint32_t tmpcr2 = 0;
4650 /* Disable the Channel 3: Reset the CC2E Bit */
4651 TIMx->CCER &= ~TIM_CCER_CC3E;
4653 /* Get the TIMx CCER register value */
4654 tmpccer = TIMx->CCER;
4655 /* Get the TIMx CR2 register value */
4658 /* Get the TIMx CCMR2 register value */
4659 tmpccmrx = TIMx->CCMR2;
4661 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4662 tmpccmrx &= ~TIM_CCMR2_OC3M;
4663 tmpccmrx &= ~TIM_CCMR2_CC3S;
4664 /* Select the Output Compare Mode */
4665 tmpccmrx |= OC_Config->OCMode;
4667 /* Reset the Output Polarity level */
4668 tmpccer &= ~TIM_CCER_CC3P;
4669 /* Set the Output Compare Polarity */
4670 tmpccer |= (OC_Config->OCPolarity << 8);
4672 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
4674 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4675 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4676 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4678 /* Reset the Output N Polarity level */
4679 tmpccer &= ~TIM_CCER_CC3NP;
4680 /* Set the Output N Polarity */
4681 tmpccer |= (OC_Config->OCNPolarity << 8);
4682 /* Reset the Output N State */
4683 tmpccer &= ~TIM_CCER_CC3NE;
4685 /* Reset the Output Compare and Output Compare N IDLE State */
4686 tmpcr2 &= ~TIM_CR2_OIS3;
4687 tmpcr2 &= ~TIM_CR2_OIS3N;
4688 /* Set the Output Idle state */
4689 tmpcr2 |= (OC_Config->OCIdleState << 4);
4690 /* Set the Output N Idle state */
4691 tmpcr2 |= (OC_Config->OCNIdleState << 4);
4693 /* Write to TIMx CR2 */
4696 /* Write to TIMx CCMR2 */
4697 TIMx->CCMR2 = tmpccmrx;
4699 /* Set the Capture Compare Register value */
4700 TIMx->CCR3 = OC_Config->Pulse;
4702 /* Write to TIMx CCER */
4703 TIMx->CCER = tmpccer;
4707 * @brief Time Ouput Compare 4 configuration
4708 * @param TIMx to select the TIM peripheral
4709 * @param OC_Config: The ouput configuration structure
4712 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4714 uint32_t tmpccmrx = 0;
4715 uint32_t tmpccer = 0;
4716 uint32_t tmpcr2 = 0;
4718 /* Disable the Channel 4: Reset the CC4E Bit */
4719 TIMx->CCER &= ~TIM_CCER_CC4E;
4721 /* Get the TIMx CCER register value */
4722 tmpccer = TIMx->CCER;
4723 /* Get the TIMx CR2 register value */
4726 /* Get the TIMx CCMR2 register value */
4727 tmpccmrx = TIMx->CCMR2;
4729 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4730 tmpccmrx &= ~TIM_CCMR2_OC4M;
4731 tmpccmrx &= ~TIM_CCMR2_CC4S;
4733 /* Select the Output Compare Mode */
4734 tmpccmrx |= (OC_Config->OCMode << 8);
4736 /* Reset the Output Polarity level */
4737 tmpccer &= ~TIM_CCER_CC4P;
4738 /* Set the Output Compare Polarity */
4739 tmpccer |= (OC_Config->OCPolarity << 12);
4741 /*if((TIMx == TIM1) || (TIMx == TIM8))*/
4742 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
4744 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4745 /* Reset the Output Compare IDLE State */
4746 tmpcr2 &= ~TIM_CR2_OIS4;
4747 /* Set the Output Idle state */
4748 tmpcr2 |= (OC_Config->OCIdleState << 6);
4750 /* Write to TIMx CR2 */
4753 /* Write to TIMx CCMR2 */
4754 TIMx->CCMR2 = tmpccmrx;
4756 /* Set the Capture Compare Register value */
4757 TIMx->CCR4 = OC_Config->Pulse;
4759 /* Write to TIMx CCER */
4760 TIMx->CCER = tmpccer;
4764 * @brief Configure the TI1 as Input.
4765 * @param TIMx to select the TIM peripheral.
4766 * @param TIM_ICPolarity : The Input Polarity.
4767 * This parameter can be one of the following values:
4768 * @arg TIM_ICPolarity_Rising
4769 * @arg TIM_ICPolarity_Falling
4770 * @arg TIM_ICPolarity_BothEdge
4771 * @param TIM_ICSelection: specifies the input to be used.
4772 * This parameter can be one of the following values:
4773 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
4774 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
4775 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
4776 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4777 * This parameter must be a value between 0x00 and 0x0F.
4780 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4781 uint32_t TIM_ICFilter)
4783 uint32_t tmpccmr1 = 0;
4784 uint32_t tmpccer = 0;
4786 /* Disable the Channel 1: Reset the CC1E Bit */
4787 TIMx->CCER &= ~TIM_CCER_CC1E;
4788 tmpccmr1 = TIMx->CCMR1;
4789 tmpccer = TIMx->CCER;
4791 /* Select the Input */
4792 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
4794 tmpccmr1 &= ~TIM_CCMR1_CC1S;
4795 tmpccmr1 |= TIM_ICSelection;
4799 tmpccmr1 &= ~TIM_CCMR1_CC1S;
4800 tmpccmr1 |= TIM_CCMR1_CC1S_0;
4803 /* Set the filter */
4804 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4805 tmpccmr1 |= (TIM_ICFilter << 4);
4807 /* Select the Polarity and set the CC1E Bit */
4808 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
4809 tmpccer |= TIM_ICPolarity;
4811 /* Write to TIMx CCMR1 and CCER registers */
4812 TIMx->CCMR1 = tmpccmr1;
4813 TIMx->CCER = tmpccer;
4817 * @brief Configure the Polarity and Filter for TI1.
4818 * @param TIMx to select the TIM peripheral.
4819 * @param TIM_ICPolarity : The Input Polarity.
4820 * This parameter can be one of the following values:
4821 * @arg TIM_ICPolarity_Rising
4822 * @arg TIM_ICPolarity_Falling
4823 * @arg TIM_ICPolarity_BothEdge
4824 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4825 * This parameter must be a value between 0x00 and 0x0F.
4828 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
4830 uint32_t tmpccmr1 = 0;
4831 uint32_t tmpccer = 0;
4833 /* Disable the Channel 1: Reset the CC1E Bit */
4834 tmpccer = TIMx->CCER;
4835 TIMx->CCER &= ~TIM_CCER_CC1E;
4836 tmpccmr1 = TIMx->CCMR1;
4838 /* Set the filter */
4839 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4840 tmpccmr1 |= (TIM_ICFilter << 4);
4842 /* Select the Polarity and set the CC1E Bit */
4843 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
4844 tmpccer |= TIM_ICPolarity;
4846 /* Write to TIMx CCMR1 and CCER registers */
4847 TIMx->CCMR1 = tmpccmr1;
4848 TIMx->CCER = tmpccer;
4852 * @brief Configure the TI2 as Input.
4853 * @param TIMx to select the TIM peripheral
4854 * @param TIM_ICPolarity : The Input Polarity.
4855 * This parameter can be one of the following values:
4856 * @arg TIM_ICPolarity_Rising
4857 * @arg TIM_ICPolarity_Falling
4858 * @arg TIM_ICPolarity_BothEdge
4859 * @param TIM_ICSelection: specifies the input to be used.
4860 * This parameter can be one of the following values:
4861 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
4862 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
4863 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
4864 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4865 * This parameter must be a value between 0x00 and 0x0F.
4868 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4869 uint32_t TIM_ICFilter)
4871 uint32_t tmpccmr1 = 0;
4872 uint32_t tmpccer = 0;
4874 /* Disable the Channel 2: Reset the CC2E Bit */
4875 TIMx->CCER &= ~TIM_CCER_CC2E;
4876 tmpccmr1 = TIMx->CCMR1;
4877 tmpccer = TIMx->CCER;
4879 /* Select the Input */
4880 tmpccmr1 &= ~TIM_CCMR1_CC2S;
4881 tmpccmr1 |= (TIM_ICSelection << 8);
4883 /* Set the filter */
4884 tmpccmr1 &= ~TIM_CCMR1_IC2F;
4885 tmpccmr1 |= (TIM_ICFilter << 12);
4887 /* Select the Polarity and set the CC2E Bit */
4888 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
4889 tmpccer |= (TIM_ICPolarity << 4);
4891 /* Write to TIMx CCMR1 and CCER registers */
4892 TIMx->CCMR1 = tmpccmr1 ;
4893 TIMx->CCER = tmpccer;
4897 * @brief Configure the Polarity and Filter for TI2.
4898 * @param TIMx to select the TIM peripheral.
4899 * @param TIM_ICPolarity : The Input Polarity.
4900 * This parameter can be one of the following values:
4901 * @arg TIM_ICPolarity_Rising
4902 * @arg TIM_ICPolarity_Falling
4903 * @arg TIM_ICPolarity_BothEdge
4904 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4905 * This parameter must be a value between 0x00 and 0x0F.
4908 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
4910 uint32_t tmpccmr1 = 0;
4911 uint32_t tmpccer = 0;
4913 /* Disable the Channel 2: Reset the CC2E Bit */
4914 TIMx->CCER &= ~TIM_CCER_CC2E;
4915 tmpccmr1 = TIMx->CCMR1;
4916 tmpccer = TIMx->CCER;
4918 /* Set the filter */
4919 tmpccmr1 &= ~TIM_CCMR1_IC2F;
4920 tmpccmr1 |= (TIM_ICFilter << 12);
4922 /* Select the Polarity and set the CC2E Bit */
4923 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
4924 tmpccer |= (TIM_ICPolarity << 4);
4926 /* Write to TIMx CCMR1 and CCER registers */
4927 TIMx->CCMR1 = tmpccmr1 ;
4928 TIMx->CCER = tmpccer;
4932 * @brief Configure the TI3 as Input.
4933 * @param TIMx to select the TIM peripheral
4934 * @param TIM_ICPolarity : The Input Polarity.
4935 * This parameter can be one of the following values:
4936 * @arg TIM_ICPolarity_Rising
4937 * @arg TIM_ICPolarity_Falling
4938 * @arg TIM_ICPolarity_BothEdge
4939 * @param TIM_ICSelection: specifies the input to be used.
4940 * This parameter can be one of the following values:
4941 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
4942 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
4943 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
4944 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4945 * This parameter must be a value between 0x00 and 0x0F.
4948 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4949 uint32_t TIM_ICFilter)
4951 uint32_t tmpccmr2 = 0;
4952 uint32_t tmpccer = 0;
4954 /* Disable the Channel 3: Reset the CC3E Bit */
4955 TIMx->CCER &= ~TIM_CCER_CC3E;
4956 tmpccmr2 = TIMx->CCMR2;
4957 tmpccer = TIMx->CCER;
4959 /* Select the Input */
4960 tmpccmr2 &= ~TIM_CCMR2_CC3S;
4961 tmpccmr2 |= TIM_ICSelection;
4963 /* Set the filter */
4964 tmpccmr2 &= ~TIM_CCMR2_IC3F;
4965 tmpccmr2 |= (TIM_ICFilter << 4);
4967 /* Select the Polarity and set the CC3E Bit */
4968 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
4969 tmpccer |= (TIM_ICPolarity << 8);
4971 /* Write to TIMx CCMR2 and CCER registers */
4972 TIMx->CCMR2 = tmpccmr2;
4973 TIMx->CCER = tmpccer;
4977 * @brief Configure the TI4 as Input.
4978 * @param TIMx to select the TIM peripheral
4979 * @param TIM_ICPolarity : The Input Polarity.
4980 * This parameter can be one of the following values:
4981 * @arg TIM_ICPolarity_Rising
4982 * @arg TIM_ICPolarity_Falling
4983 * @arg TIM_ICPolarity_BothEdge
4984 * @param TIM_ICSelection: specifies the input to be used.
4985 * This parameter can be one of the following values:
4986 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
4987 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
4988 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
4989 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4990 * This parameter must be a value between 0x00 and 0x0F.
4993 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4994 uint32_t TIM_ICFilter)
4996 uint32_t tmpccmr2 = 0;
4997 uint32_t tmpccer = 0;
4999 /* Disable the Channel 4: Reset the CC4E Bit */
5000 TIMx->CCER &= ~TIM_CCER_CC4E;
5001 tmpccmr2 = TIMx->CCMR2;
5002 tmpccer = TIMx->CCER;
5004 /* Select the Input */
5005 tmpccmr2 &= ~TIM_CCMR2_CC4S;
5006 tmpccmr2 |= (TIM_ICSelection << 8);
5008 /* Set the filter */
5009 tmpccmr2 &= ~TIM_CCMR2_IC4F;
5010 tmpccmr2 |= (TIM_ICFilter << 12);
5012 /* Select the Polarity and set the CC4E Bit */
5013 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
5014 tmpccer |= (TIM_ICPolarity << 12);
5016 /* Write to TIMx CCMR2 and CCER registers */
5017 TIMx->CCMR2 = tmpccmr2;
5018 TIMx->CCER = tmpccer ;
5022 * @brief Selects the Input Trigger source
5023 * @param TIMx to select the TIM peripheral
5024 * @param InputTriggerSource: The Input Trigger source.
5025 * This parameter can be one of the following values:
5026 * @arg TIM_TS_ITR0: Internal Trigger 0
5027 * @arg TIM_TS_ITR1: Internal Trigger 1
5028 * @arg TIM_TS_ITR2: Internal Trigger 2
5029 * @arg TIM_TS_ITR3: Internal Trigger 3
5030 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
5031 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
5032 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
5033 * @arg TIM_TS_ETRF: External Trigger input
5036 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
5038 uint32_t tmpsmcr = 0;
5040 /* Get the TIMx SMCR register value */
5041 tmpsmcr = TIMx->SMCR;
5042 /* Reset the TS Bits */
5043 tmpsmcr &= ~TIM_SMCR_TS;
5044 /* Set the Input Trigger source and the slave mode*/
5045 tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
5046 /* Write to TIMx SMCR */
5047 TIMx->SMCR = tmpsmcr;
5050 * @brief Configures the TIMx External Trigger (ETR).
5051 * @param TIMx to select the TIM peripheral
5052 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
5053 * This parameter can be one of the following values:
5054 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
5055 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
5056 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
5057 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
5058 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
5059 * This parameter can be one of the following values:
5060 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
5061 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
5062 * @param ExtTRGFilter: External Trigger Filter.
5063 * This parameter must be a value between 0x00 and 0x0F
5066 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
5067 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
5069 uint32_t tmpsmcr = 0;
5071 tmpsmcr = TIMx->SMCR;
5073 /* Reset the ETR Bits */
5074 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5076 /* Set the Prescaler, the Filter value and the Polarity */
5077 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
5079 /* Write to TIMx SMCR */
5080 TIMx->SMCR = tmpsmcr;
5084 * @brief Enables or disables the TIM Capture Compare Channel x.
5085 * @param TIMx to select the TIM peripheral
5086 * @param Channel: specifies the TIM Channel
5087 * This parameter can be one of the following values:
5088 * @arg TIM_Channel_1: TIM Channel 1
5089 * @arg TIM_Channel_2: TIM Channel 2
5090 * @arg TIM_Channel_3: TIM Channel 3
5091 * @arg TIM_Channel_4: TIM Channel 4
5092 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
5093 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
5096 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
5100 /* Check the parameters */
5101 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
5102 assert_param(IS_TIM_CHANNELS(Channel));
5104 tmp = TIM_CCER_CC1E << Channel;
5106 /* Reset the CCxE Bit */
5109 /* Set or reset the CCxE Bit */
5110 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
5118 #endif /* HAL_TIM_MODULE_ENABLED */
5126 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/