2 ******************************************************************************
3 * @file stm32f4xx_hal_nand.c
4 * @author MCD Application Team
7 * @brief NAND HAL module driver.
8 * This file provides a generic firmware to drive NAND memories mounted
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
16 This driver is a generic layered driver which contains a set of APIs used to
17 control NAND flash memories. It uses the FMC/FSMC layer functions to interface
18 with NAND devices. This driver is used as follows:
20 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
21 with control and timing parameters for both common and attribute spaces.
23 (+) Read NAND flash memory maker and device IDs using the function
24 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
25 structure declared by the function caller.
27 (+) Access NAND flash memory by read/write operations using the functions
28 HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
29 to read/write page(s)/spare area(s). These functions use specific device
30 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
31 structure. The read/write address information is contained by the Nand_Address_Typedef
32 structure passed as parameter.
34 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
36 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
37 The erase block address information is contained in the Nand_Address_Typedef
38 structure passed as parameter.
40 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
42 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
43 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
44 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
46 (+) You can monitor the NAND device HAL state by calling the function
50 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
51 If a NAND flash device contains different operations and/or implementations,
52 it should be implemented separately.
55 ******************************************************************************
58 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
60 * Redistribution and use in source and binary forms, with or without modification,
61 * are permitted provided that the following conditions are met:
62 * 1. Redistributions of source code must retain the above copyright notice,
63 * this list of conditions and the following disclaimer.
64 * 2. Redistributions in binary form must reproduce the above copyright notice,
65 * this list of conditions and the following disclaimer in the documentation
66 * and/or other materials provided with the distribution.
67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
68 * may be used to endorse or promote products derived from this software
69 * without specific prior written permission.
71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
82 ******************************************************************************
85 /* Includes ------------------------------------------------------------------*/
86 #include "stm32f4xx_hal.h"
88 /** @addtogroup STM32F4xx_HAL_Driver
93 * @brief NAND driver modules
96 #ifdef HAL_NAND_MODULE_ENABLED
98 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
100 /* Private typedef -----------------------------------------------------------*/
101 /* Private define ------------------------------------------------------------*/
102 /* Private macro -------------------------------------------------------------*/
103 /* Private variables ---------------------------------------------------------*/
104 /* Private function prototypes -----------------------------------------------*/
105 /* Private functions ---------------------------------------------------------*/
107 /** @defgroup NAND_Private_Functions
111 /** @defgroup NAND_Group1 Initialization and de-initialization functions
112 * @brief Initialization and Configuration functions
115 ==============================================================================
116 ##### NAND Initialization and de-initialization functions #####
117 ==============================================================================
119 This section provides functions allowing to initialize/de-initialize
127 * @brief Perform NAND memory Initialization sequence
128 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
129 * the configuration information for NAND module.
130 * @param ComSpace_Timing: pointer to Common space timing structure
131 * @param AttSpace_Timing: pointer to Attribute space timing structure
134 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
136 /* Check the NAND handle state */
137 if(hnand == HAL_NULL)
142 if(hnand->State == HAL_NAND_STATE_RESET)
144 /* Initialize the low level hardware (MSP) */
145 HAL_NAND_MspInit(hnand);
148 /* Initialize NAND control Interface */
149 FMC_NAND_Init(hnand->Instance, &(hnand->Init));
151 /* Initialize NAND common space timing Interface */
152 FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
154 /* Initialize NAND attribute space timing Interface */
155 FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
157 /* Enable the NAND device */
158 __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
160 /* Update the NAND controller state */
161 hnand->State = HAL_NAND_STATE_READY;
167 * @brief Perform NAND memory De-Initialization sequence
168 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
169 * the configuration information for NAND module.
172 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
174 /* Initialize the low level hardware (MSP) */
175 HAL_NAND_MspDeInit(hnand);
177 /* Configure the NAND registers with their reset values */
178 FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
180 /* Reset the NAND controller state */
181 hnand->State = HAL_NAND_STATE_RESET;
190 * @brief NAND MSP Init
191 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
192 * the configuration information for NAND module.
195 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
197 /* NOTE : This function Should not be modified, when the callback is needed,
198 the HAL_NAND_MspInit could be implemented in the user file
203 * @brief NAND MSP DeInit
204 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
205 * the configuration information for NAND module.
208 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
210 /* NOTE : This function Should not be modified, when the callback is needed,
211 the HAL_NAND_MspDeInit could be implemented in the user file
217 * @brief This function handles NAND device interrupt request.
218 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
219 * the configuration information for NAND module.
222 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
224 /* Check NAND interrupt Rising edge flag */
225 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
227 /* NAND interrupt callback*/
228 HAL_NAND_ITCallback(hnand);
230 /* Clear NAND interrupt Rising edge pending bit */
231 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
234 /* Check NAND interrupt Level flag */
235 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
237 /* NAND interrupt callback*/
238 HAL_NAND_ITCallback(hnand);
240 /* Clear NAND interrupt Level pending bit */
241 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
244 /* Check NAND interrupt Falling edge flag */
245 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
247 /* NAND interrupt callback*/
248 HAL_NAND_ITCallback(hnand);
250 /* Clear NAND interrupt Falling edge pending bit */
251 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
254 /* Check NAND interrupt FIFO empty flag */
255 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
257 /* NAND interrupt callback*/
258 HAL_NAND_ITCallback(hnand);
260 /* Clear NAND interrupt FIFO empty pending bit */
261 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
267 * @brief NAND interrupt feature callback
268 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
269 * the configuration information for NAND module.
272 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
274 /* NOTE : This function Should not be modified, when the callback is needed,
275 the HAL_NAND_ITCallback could be implemented in the user file
283 /** @defgroup NAND_Group2 Input and Output functions
284 * @brief Input Output and memory control functions
287 ==============================================================================
288 ##### NAND Input and Output functions #####
289 ==============================================================================
291 This section provides functions allowing to use and control the NAND
299 * @brief Read the NAND memory electronic signature
300 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
301 * the configuration information for NAND module.
302 * @param pNAND_ID: NAND ID structure
305 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
307 __IO uint32_t data = 0;
308 uint32_t deviceAddress = 0;
313 /* Check the NAND controller state */
314 if(hnand->State == HAL_NAND_STATE_BUSY)
319 /* Identify the device address */
320 if(hnand->Init.NandBank == FMC_NAND_BANK2)
322 deviceAddress = NAND_DEVICE1;
326 deviceAddress = NAND_DEVICE2;
329 /* Update the NAND controller state */
330 hnand->State = HAL_NAND_STATE_BUSY;
332 /* Send Read ID command sequence */
333 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
334 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
336 /* Read the electronic signature from NAND flash */
337 data = *(__IO uint32_t *)deviceAddress;
339 /* Return the data read */
340 pNAND_ID->Maker_Id = __ADDR_1st_CYCLE(data);
341 pNAND_ID->Device_Id = __ADDR_2nd_CYCLE(data);
342 pNAND_ID->Third_Id = __ADDR_3rd_CYCLE(data);
343 pNAND_ID->Fourth_Id = __ADDR_4th_CYCLE(data);
345 /* Update the NAND controller state */
346 hnand->State = HAL_NAND_STATE_READY;
348 /* Process unlocked */
355 * @brief NAND memory reset
356 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
357 * the configuration information for NAND module.
360 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
362 uint32_t deviceAddress = 0;
367 /* Check the NAND controller state */
368 if(hnand->State == HAL_NAND_STATE_BUSY)
373 /* Identify the device address */
374 if(hnand->Init.NandBank == FMC_NAND_BANK2)
376 deviceAddress = NAND_DEVICE1;
380 deviceAddress = NAND_DEVICE2;
383 /* Update the NAND controller state */
384 hnand->State = HAL_NAND_STATE_BUSY;
386 /* Send NAND reset command */
387 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
390 /* Update the NAND controller state */
391 hnand->State = HAL_NAND_STATE_READY;
393 /* Process unlocked */
402 * @brief Read Page(s) from NAND memory block
403 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
404 * the configuration information for NAND module.
405 * @param pAddress : pointer to NAND address structure
406 * @param pBuffer : pointer to destination read buffer
407 * @param NumPageToRead : number of pages to read from block
410 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
412 __IO uint32_t index = 0;
413 uint32_t deviceAddress = 0, numPagesRead = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
418 /* Check the NAND controller state */
419 if(hnand->State == HAL_NAND_STATE_BUSY)
424 /* Identify the device address */
425 if(hnand->Init.NandBank == FMC_NAND_BANK2)
427 deviceAddress = NAND_DEVICE1;
431 deviceAddress = NAND_DEVICE2;
434 /* Update the NAND controller state */
435 hnand->State = HAL_NAND_STATE_BUSY;
437 /* Page(s) read loop */
438 while((NumPageToRead != 0) && (addressStatus == NAND_VALID_ADDRESS))
440 /* NAND raw address calculation */
441 nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
443 /* Send read page command sequence */
444 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
446 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
447 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
448 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
449 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
451 /* for 512 and 1 GB devices, 4th cycle is required */
452 if(hnand->Info.BlockNbr > 1024)
454 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
457 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
459 /* Get Data into Buffer */
460 for(index = 0 ; index < hnand->Info.PageSize; index++)
462 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
465 /* Increment read pages number */
468 /* Decrement pages to read */
471 /* Increment the NAND address */
472 HAL_NAND_Address_Inc(hnand, pAddress);
476 /* Update the NAND controller state */
477 hnand->State = HAL_NAND_STATE_READY;
479 /* Process unlocked */
487 * @brief Write Page(s) to NAND memory block
488 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
489 * the configuration information for NAND module.
490 * @param pAddress : pointer to NAND address structure
491 * @param pBuffer : pointer to source buffer to write
492 * @param NumPageToWrite : number of pages to write to block
495 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
497 __IO uint32_t index = 0;
498 uint32_t tickstart = 0;
499 uint32_t deviceAddress = 0 , numPagesWritten = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
504 /* Check the NAND controller state */
505 if(hnand->State == HAL_NAND_STATE_BUSY)
510 /* Identify the device address */
511 if(hnand->Init.NandBank == FMC_NAND_BANK2)
513 deviceAddress = NAND_DEVICE1;
517 deviceAddress = NAND_DEVICE2;
520 /* Update the NAND controller state */
521 hnand->State = HAL_NAND_STATE_BUSY;
523 /* Page(s) write loop */
524 while((NumPageToWrite != 0) && (addressStatus == NAND_VALID_ADDRESS))
526 /* NAND raw address calculation */
527 nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
529 /* Send write page command sequence */
530 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
531 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
533 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
534 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
535 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
536 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
538 /* for 512 and 1 GB devices, 4th cycle is required */
539 if(hnand->Info.BlockNbr > 1024)
541 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
544 /* Write data to memory */
545 for(index = 0 ; index < hnand->Info.PageSize; index++)
547 *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
550 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
552 /* Read status until NAND is ready */
553 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
556 tickstart = HAL_GetTick();
558 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
564 /* Increment written pages number */
567 /* Decrement pages to write */
570 /* Increment the NAND address */
571 HAL_NAND_Address_Inc(hnand, pAddress);
575 /* Update the NAND controller state */
576 hnand->State = HAL_NAND_STATE_READY;
578 /* Process unlocked */
586 * @brief Read Spare area(s) from NAND memory
587 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
588 * the configuration information for NAND module.
589 * @param pAddress : pointer to NAND address structure
590 * @param pBuffer: pointer to source buffer to write
591 * @param NumSpareAreaToRead: Number of spare area to read
594 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
596 __IO uint32_t index = 0;
597 uint32_t deviceAddress = 0, numSpareAreaRead = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
602 /* Check the NAND controller state */
603 if(hnand->State == HAL_NAND_STATE_BUSY)
608 /* Identify the device address */
609 if(hnand->Init.NandBank == FMC_NAND_BANK2)
611 deviceAddress = NAND_DEVICE1;
615 deviceAddress = NAND_DEVICE2;
618 /* Update the NAND controller state */
619 hnand->State = HAL_NAND_STATE_BUSY;
621 /* Spare area(s) read loop */
622 while((NumSpareAreaToRead != 0) && (addressStatus == NAND_VALID_ADDRESS))
624 /* NAND raw address calculation */
625 nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
627 /* Send read spare area command sequence */
628 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
630 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
631 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
632 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
633 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
635 /* for 512 and 1 GB devices, 4th cycle is required */
636 if(hnand->Info.BlockNbr > 1024)
638 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
641 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
643 /* Get Data into Buffer */
644 for(index = 0 ; index < hnand->Info.SpareAreaSize; index++)
646 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
649 /* Increment read spare areas number */
652 /* Decrement spare areas to read */
653 NumSpareAreaToRead--;
655 /* Increment the NAND address */
656 HAL_NAND_Address_Inc(hnand, pAddress);
659 /* Update the NAND controller state */
660 hnand->State = HAL_NAND_STATE_READY;
662 /* Process unlocked */
669 * @brief Write Spare area(s) to NAND memory
670 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
671 * the configuration information for NAND module.
672 * @param pAddress : pointer to NAND address structure
673 * @param pBuffer : pointer to source buffer to write
674 * @param NumSpareAreaTowrite : number of spare areas to write to block
677 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
679 __IO uint32_t index = 0;
680 uint32_t tickstart = 0;
681 uint32_t deviceAddress = 0, numSpareAreaWritten = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
686 /* Check the NAND controller state */
687 if(hnand->State == HAL_NAND_STATE_BUSY)
692 /* Identify the device address */
693 if(hnand->Init.NandBank == FMC_NAND_BANK2)
695 deviceAddress = NAND_DEVICE1;
699 deviceAddress = NAND_DEVICE2;
702 /* Update the FMC_NAND controller state */
703 hnand->State = HAL_NAND_STATE_BUSY;
705 /* Spare area(s) write loop */
706 while((NumSpareAreaTowrite != 0) && (addressStatus == NAND_VALID_ADDRESS))
708 /* NAND raw address calculation */
709 nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
711 /* Send write Spare area command sequence */
712 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
713 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
715 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
716 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
717 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
718 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
720 /* for 512 and 1 GB devices, 4th cycle is required */
721 if(hnand->Info.BlockNbr >= 1024)
723 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
726 /* Write data to memory */
727 for(index = 0 ; index < hnand->Info.SpareAreaSize; index++)
729 *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
732 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
735 /* Read status until NAND is ready */
736 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
739 tickstart = HAL_GetTick();
741 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
747 /* Increment written spare areas number */
748 numSpareAreaWritten++;
750 /* Decrement spare areas to write */
751 NumSpareAreaTowrite--;
753 /* Increment the NAND address */
754 HAL_NAND_Address_Inc(hnand, pAddress);
758 /* Update the NAND controller state */
759 hnand->State = HAL_NAND_STATE_READY;
761 /* Process unlocked */
768 * @brief NAND memory Block erase
769 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
770 * the configuration information for NAND module.
771 * @param pAddress : pointer to NAND address structure
774 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress)
776 uint32_t DeviceAddress = 0;
781 /* Check the NAND controller state */
782 if(hnand->State == HAL_NAND_STATE_BUSY)
787 /* Identify the device address */
788 if(hnand->Init.NandBank == FMC_NAND_BANK2)
790 DeviceAddress = NAND_DEVICE1;
794 DeviceAddress = NAND_DEVICE2;
797 /* Update the NAND controller state */
798 hnand->State = HAL_NAND_STATE_BUSY;
800 /* Send Erase block command sequence */
801 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
803 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
804 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
805 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
807 /* for 512 and 1 GB devices, 4th cycle is required */
808 if(hnand->Info.BlockNbr >= 1024)
810 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
813 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
815 /* Update the NAND controller state */
816 hnand->State = HAL_NAND_STATE_READY;
818 /* Process unlocked */
826 * @brief NAND memory read status
827 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
828 * the configuration information for NAND module.
829 * @retval NAND status
831 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
834 uint32_t DeviceAddress = 0;
836 /* Identify the device address */
837 if(hnand->Init.NandBank == FMC_NAND_BANK2)
839 DeviceAddress = NAND_DEVICE1;
843 DeviceAddress = NAND_DEVICE2;
846 /* Send Read status operation command */
847 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
849 /* Read status register data */
850 data = *(__IO uint8_t *)DeviceAddress;
852 /* Return the status */
853 if((data & NAND_ERROR) == NAND_ERROR)
857 else if((data & NAND_READY) == NAND_READY)
867 * @brief Increment the NAND memory address
868 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
869 * the configuration information for NAND module.
870 * @param pAddress: pointer to NAND adress structure
871 * @retval The new status of the increment address operation. It can be:
872 * - NAND_VALID_ADDRESS: When the new address is valid address
873 * - NAND_INVALID_ADDRESS: When the new address is invalid address
875 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress)
877 uint32_t status = NAND_VALID_ADDRESS;
879 /* Increment page address */
882 /* Check NAND address is valid */
883 if(pAddress->Page == hnand->Info.BlockSize)
888 if(pAddress->Block == hnand->Info.ZoneSize)
893 if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
895 status = NAND_INVALID_ADDRESS;
908 /** @defgroup NAND_Group3 Control functions
909 * @brief management functions
912 ==============================================================================
913 ##### NAND Control functions #####
914 ==============================================================================
916 This subsection provides a set of functions allowing to control dynamically
925 * @brief Enables dynamically NAND ECC feature.
926 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
927 * the configuration information for NAND module.
930 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
932 /* Check the NAND controller state */
933 if(hnand->State == HAL_NAND_STATE_BUSY)
938 /* Update the NAND state */
939 hnand->State = HAL_NAND_STATE_BUSY;
941 /* Enable ECC feature */
942 FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
944 /* Update the NAND state */
945 hnand->State = HAL_NAND_STATE_READY;
952 * @brief Disables dynamically FMC_NAND ECC feature.
953 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
954 * the configuration information for NAND module.
957 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
959 /* Check the NAND controller state */
960 if(hnand->State == HAL_NAND_STATE_BUSY)
965 /* Update the NAND state */
966 hnand->State = HAL_NAND_STATE_BUSY;
968 /* Disable ECC feature */
969 FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
971 /* Update the NAND state */
972 hnand->State = HAL_NAND_STATE_READY;
978 * @brief Disables dynamically NAND ECC feature.
979 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
980 * the configuration information for NAND module.
981 * @param ECCval: pointer to ECC value
982 * @param Timeout: maximum timeout to wait
985 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
987 HAL_StatusTypeDef status = HAL_OK;
989 /* Check the NAND controller state */
990 if(hnand->State == HAL_NAND_STATE_BUSY)
995 /* Update the NAND state */
996 hnand->State = HAL_NAND_STATE_BUSY;
998 /* Get NAND ECC value */
999 status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
1001 /* Update the NAND state */
1002 hnand->State = HAL_NAND_STATE_READY;
1012 /** @defgroup NAND_Group4 State functions
1013 * @brief Peripheral State functions
1016 ==============================================================================
1017 ##### NAND State functions #####
1018 ==============================================================================
1020 This subsection permits to get in run-time the status of the NAND controller
1028 * @brief return the NAND state
1029 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
1030 * the configuration information for NAND module.
1033 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
1035 return hnand->State;
1045 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1046 #endif /* HAL_NAND_MODULE_ENABLED */
1056 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/