tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_ll_fmc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_ll_fmc.h
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    12-Sept-2014
   7   * @brief   Header file of FMC HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F3xx_LL_FMC_H
  40 #define __STM32F3xx_LL_FMC_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
  47
  48 /* Includes ------------------------------------------------------------------*/
  49 #include "stm32f3xx_hal_def.h"
  50
  51 /** @addtogroup STM32F3xx_HAL_Driver
  52   * @{
  53   */
  54
  55 /** @addtogroup FMC
  56   * @{
  57   */
  58
  59 /* Exported typedef ----------------------------------------------------------*/
  60 #define FMC_NORSRAM_TypeDef            FMC_Bank1_TypeDef
  61 #define FMC_NORSRAM_EXTENDED_TypeDef   FMC_Bank1E_TypeDef
  62 #define FMC_NAND_TypeDef               FMC_Bank2_3_TypeDef
  63 #define FMC_PCCARD_TypeDef             FMC_Bank4_TypeDef
  64
  65 #define FMC_NORSRAM_DEVICE             FMC_Bank1
  66 #define FMC_NORSRAM_EXTENDED_DEVICE    FMC_Bank1E
  67 #define FMC_NAND_DEVICE                FMC_Bank2_3
  68 #define FMC_PCCARD_DEVICE              FMC_Bank4
  69
  70 /**
  71   * @brief  FMC_NORSRAM Configuration Structure definition
  72   */
  73 typedef struct
  74 {
  75   uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
  76                                               This parameter can be a value of @ref FMC_NORSRAM_Bank                     */
  77
  78   uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
  79                                               multiplexed on the data bus or not.
  80                                               This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing    */
  81
  82   uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
  83                                               the corresponding memory device.
  84                                               This parameter can be a value of @ref FMC_Memory_Type                      */
  85
  86   uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
  87                                               This parameter can be a value of @ref FMC_NORSRAM_Data_Width               */
  88
  89   uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
  90                                               valid only with synchronous burst Flash memories.
  91                                               This parameter can be a value of @ref FMC_Burst_Access_Mode                */
  92
  93   uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
  94                                               the Flash memory in burst mode.
  95                                               This parameter can be a value of @ref FMC_Wait_Signal_Polarity             */
  96
  97   uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
  98                                               memory, valid only when accessing Flash memories in burst mode.
  99                                               This parameter can be a value of @ref FMC_Wrap_Mode                        */
 100
 101   uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
 102                                               clock cycle before the wait state or during the wait state,
 103                                               valid only when accessing memories in burst mode.
 104                                               This parameter can be a value of @ref FMC_Wait_Timing                      */
 105
 106   uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FMC.
 107                                               This parameter can be a value of @ref FMC_Write_Operation                  */
 108
 109   uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
 110                                               signal, valid for Flash memory access in burst mode.
 111                                               This parameter can be a value of @ref FMC_Wait_Signal                      */
 112
 113   uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
 114                                               This parameter can be a value of @ref FMC_Extended_Mode                    */
 115
 116   uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
 117                                               valid only with asynchronous Flash memories.
 118                                               This parameter can be a value of @ref FMC_AsynchronousWait                 */
 119
 120   uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
 121                                               This parameter can be a value of @ref FMC_Write_Burst                      */
 122
 123   uint32_t ContinuousClock;              /*!< Enables or disables the FMC clock output to external memory devices.
 124                                               This parameter is only enabled through the FMC_BCR1 register, and don't care
 125                                               through FMC_BCR2..4 registers.
 126                                               This parameter can be a value of @ref FMC_Continous_Clock                  */
 127
 128 }FMC_NORSRAM_InitTypeDef;
 129
 130 /**
 131   * @brief  FMC_NORSRAM Timing parameters structure definition
 132   */
 133 typedef struct
 134 {
 135   uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
 136                                               the duration of the address setup time.
 137                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
 138                                               @note This parameter is not used with synchronous NOR Flash memories.      */
 139
 140   uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
 141                                               the duration of the address hold time.
 142                                               This parameter can be a value between Min_Data = 1 and Max_Data = 15.
 143                                               @note This parameter is not used with synchronous NOR Flash memories.      */
 144
 145   uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
 146                                               the duration of the data setup time.
 147                                               This parameter can be a value between Min_Data = 1 and Max_Data = 255.
 148                                               @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
 149                                               NOR Flash memories.                                                        */
 150
 151   uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
 152                                               the duration of the bus turnaround.
 153                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
 154                                               @note This parameter is only used for multiplexed NOR Flash memories.      */
 155
 156   uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
 157                                               HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
 158                                               @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
 159                                               accesses.                                                                  */
 160
 161   uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
 162                                               to the memory before getting the first data.
 163                                               The parameter value depends on the memory type as shown below:
 164                                               - It must be set to 0 in case of a CRAM
 165                                               - It is don't care in asynchronous NOR, SRAM or ROM accesses
 166                                               - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
 167                                                 with synchronous burst mode enable                                       */
 168
 169   uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
 170                                               This parameter can be a value of @ref FMC_Access_Mode                      */
 171
 172 }FMC_NORSRAM_TimingTypeDef;
 173
 174 /**
 175   * @brief  FMC_NAND Configuration Structure definition
 176   */
 177 typedef struct
 178 {
 179   uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
 180                                         This parameter can be a value of @ref FMC_NAND_Bank                    */
 181
 182   uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
 183                                         This parameter can be any value of @ref FMC_Wait_feature               */
 184
 185   uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
 186                                         This parameter can be any value of @ref FMC_NAND_Data_Width            */
 187
 188   uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
 189                                         This parameter can be any value of @ref FMC_ECC                        */
 190
 191   uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
 192                                         This parameter can be any value of @ref FMC_ECC_Page_Size              */
 193
 194   uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
 195                                         delay between CLE low and RE low.
 196                                         This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
 197
 198   uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
 199                                         delay between ALE low and RE low.
 200                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
 201
 202 }FMC_NAND_InitTypeDef;
 203
 204 /**
 205   * @brief  FMC_NAND_PCCARD Timing parameters structure definition
 206   */
 207 typedef struct
 208 {
 209   uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
 210                                       the command assertion for NAND-Flash read or write access
 211                                       to common/Attribute or I/O memory space (depending on
 212                                       the memory space timing to be configured).
 213                                       This parameter can be a value between Min_Data = 0 and Max_Data = 255    */
 214
 215   uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
 216                                       command for NAND-Flash read or write access to
 217                                       common/Attribute or I/O memory space (depending on the
 218                                       memory space timing to be configured).
 219                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
 220
 221   uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
 222                                       (and data for write access) after the command de-assertion
 223                                       for NAND-Flash read or write access to common/Attribute
 224                                       or I/O memory space (depending on the memory space timing
 225                                       to be configured).
 226                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
 227
 228   uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
 229                                       data bus is kept in HiZ after the start of a NAND-Flash
 230                                       write access to common/Attribute or I/O memory space (depending
 231                                       on the memory space timing to be configured).
 232                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
 233
 234 }FMC_NAND_PCC_TimingTypeDef;
 235
 236 /**
 237   * @brief  FMC_NAND Configuration Structure definition
 238   */
 239 typedef struct
 240 {
 241   uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the PCCARD Memory device.
 242                                         This parameter can be any value of @ref FMC_Wait_feature               */
 243
 244   uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
 245                                         delay between CLE low and RE low.
 246                                         This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
 247
 248   uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
 249                                         delay between ALE low and RE low.
 250                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
 251
 252 }FMC_PCCARD_InitTypeDef;
 253
 254 /* Exported constants --------------------------------------------------------*/
 255
 256 /** @defgroup FMC_NOR_SRAM_Controller
 257   * @{
 258   */
 259
 260 /** @defgroup FMC_NORSRAM_Bank
 261   * @{
 262   */
 263 #define FMC_NORSRAM_BANK1                       ((uint32_t)0x00000000)
 264 #define FMC_NORSRAM_BANK2                       ((uint32_t)0x00000002)
 265 #define FMC_NORSRAM_BANK3                       ((uint32_t)0x00000004)
 266 #define FMC_NORSRAM_BANK4                       ((uint32_t)0x00000006)
 267
 268 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
 269                                    ((BANK) == FMC_NORSRAM_BANK2) || \
 270                                    ((BANK) == FMC_NORSRAM_BANK3) || \
 271                                    ((BANK) == FMC_NORSRAM_BANK4))
 272 /**
 273   * @}
 274   */
 275
 276 /** @defgroup FMC_Data_Address_Bus_Multiplexing
 277   * @{
 278   */
 279 #define FMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
 280 #define FMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)0x00000002)
 281
 282 #define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
 283                          ((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
 284 /**
 285   * @}
 286   */
 287
 288 /** @defgroup FMC_Memory_Type
 289   * @{
 290   */
 291 #define FMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)
 292 #define FMC_MEMORY_TYPE_PSRAM                   ((uint32_t)0x00000004)
 293 #define FMC_MEMORY_TYPE_NOR                     ((uint32_t)0x00000008)
 294
 295 #define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) || \
 296                                ((MEMORY) == FMC_MEMORY_TYPE_PSRAM)|| \
 297                                ((MEMORY) == FMC_MEMORY_TYPE_NOR))
 298 /**
 299   * @}
 300   */
 301
 302 /** @defgroup FMC_NORSRAM_Data_Width
 303   * @{
 304   */
 305 #define FMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
 306 #define FMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)0x00000010)
 307 #define FMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)0x00000020)
 308
 309 #define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
 310                                             ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
 311                                             ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
 312 /**
 313   * @}
 314   */
 315
 316 /** @defgroup FMC_NORSRAM_Flash_Access
 317   * @{
 318   */
 319 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)0x00000040)
 320 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)
 321 /**
 322   * @}
 323   */
 324
 325 /** @defgroup FMC_Burst_Access_Mode
 326   * @{
 327   */
 328 #define FMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000)
 329 #define FMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)0x00000100)
 330
 331 #define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) || \
 332                                  ((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
 333 /**
 334   * @}
 335   */
 336
 337
 338 /** @defgroup FMC_Wait_Signal_Polarity
 339   * @{
 340   */
 341 #define FMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
 342 #define FMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)0x00000200)
 343
 344 #define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
 345                                         ((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
 346 /**
 347   * @}
 348   */
 349
 350 /** @defgroup FMC_Wrap_Mode
 351   * @{
 352   */
 353 #define FMC_WRAP_MODE_DISABLE                   ((uint32_t)0x00000000)
 354 #define FMC_WRAP_MODE_ENABLE                    ((uint32_t)0x00000400)
 355
 356 #define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) || \
 357                                 ((MODE) == FMC_WRAP_MODE_ENABLE))
 358 /**
 359   * @}
 360   */
 361
 362 /** @defgroup FMC_Wait_Timing
 363   * @{
 364   */
 365 #define FMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
 366 #define FMC_WAIT_TIMING_DURING_WS               ((uint32_t)0x00000800)
 367
 368 #define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) || \
 369                                            ((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
 370 /**
 371   * @}
 372   */
 373
 374 /** @defgroup FMC_Write_Operation
 375   * @{
 376   */
 377 #define FMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
 378 #define FMC_WRITE_OPERATION_ENABLE              ((uint32_t)0x00001000)
 379
 380 #define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) || \
 381                                            ((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
 382 /**
 383   * @}
 384   */
 385
 386 /** @defgroup FMC_Wait_Signal
 387   * @{
 388   */
 389 #define FMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
 390 #define FMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)0x00002000)
 391
 392 #define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) || \
 393                                      ((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
 394 /**
 395   * @}
 396   */
 397
 398 /** @defgroup FMC_Extended_Mode
 399   * @{
 400   */
 401 #define FMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
 402 #define FMC_EXTENDED_MODE_ENABLE                ((uint32_t)0x00004000)
 403
 404 #define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) || \
 405                                     ((MODE) == FMC_EXTENDED_MODE_ENABLE))
 406 /**
 407   * @}
 408   */
 409
 410 /** @defgroup FMC_AsynchronousWait
 411   * @{
 412   */
 413 #define FMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
 414 #define FMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)0x00008000)
 415
 416 #define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
 417                                 ((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
 418 /**
 419   * @}
 420   */
 421
 422 /** @defgroup FMC_Write_Burst
 423   * @{
 424   */
 425 #define FMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
 426 #define FMC_WRITE_BURST_ENABLE                  ((uint32_t)0x00080000)
 427
 428 #define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) || \
 429                                    ((BURST) == FMC_WRITE_BURST_ENABLE))
 430 /**
 431   * @}
 432   */
 433
 434 /** @defgroup FMC_Continous_Clock
 435   * @{
 436   */
 437 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000)
 438 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC         ((uint32_t)0x00100000)
 439
 440 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
 441                                         ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
 442 /**
 443   * @}
 444   */
 445
 446 /** @defgroup FMC_Address_Setup_Time
 447   * @{
 448   */
 449 #define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
 450 /**
 451   * @}
 452   */
 453
 454 /** @defgroup FMC_Address_Hold_Time
 455   * @{
 456   */
 457 #define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
 458 /**
 459   * @}
 460   */
 461
 462 /** @defgroup FMC_Data_Setup_Time
 463   * @{
 464   */
 465 #define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
 466 /**
 467   * @}
 468   */
 469
 470 /** @defgroup FMC_Bus_Turn_around_Duration
 471   * @{
 472   */
 473 #define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
 474 /**
 475   * @}
 476   */
 477
 478 /** @defgroup FMC_CLK_Division
 479   * @{
 480   */
 481 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
 482 /**
 483   * @}
 484   */
 485
 486 /** @defgroup FMC_Data_Latency
 487   * @{
 488   */
 489 #define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
 490 /**
 491   * @}
 492   */
 493
 494 /** @defgroup FMC_Access_Mode
 495   * @{
 496   */
 497 #define FMC_ACCESS_MODE_A                        ((uint32_t)0x00000000)
 498 #define FMC_ACCESS_MODE_B                        ((uint32_t)0x10000000)
 499 #define FMC_ACCESS_MODE_C                        ((uint32_t)0x20000000)
 500 #define FMC_ACCESS_MODE_D                        ((uint32_t)0x30000000)
 501
 502 #define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) || \
 503                                   ((MODE) == FMC_ACCESS_MODE_B) || \
 504                                   ((MODE) == FMC_ACCESS_MODE_C) || \
 505                                   ((MODE) == FMC_ACCESS_MODE_D))
 506 /**
 507   * @}
 508   */
 509
 510 /**
 511   * @}
 512   */
 513
 514 /** @defgroup FMC_NAND_Controller
 515   * @{
 516   */
 517
 518 /** @defgroup FMC_NAND_Bank
 519   * @{
 520   */
 521 #define FMC_NAND_BANK2                          ((uint32_t)0x00000010)
 522 #define FMC_NAND_BANK3                          ((uint32_t)0x00000100)
 523
 524 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
 525                                 ((BANK) == FMC_NAND_BANK3))
 526 /**
 527   * @}
 528   */
 529
 530 /** @defgroup FMC_Wait_feature
 531   * @{
 532   */
 533 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000)
 534 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE            ((uint32_t)0x00000002)
 535
 536 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
 537                                       ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
 538 /**
 539   * @}
 540   */
 541
 542 /** @defgroup FMC_PCR_Memory_Type
 543   * @{
 544   */
 545 #define FMC_PCR_MEMORY_TYPE_PCCARD        ((uint32_t)0x00000000)
 546 #define FMC_PCR_MEMORY_TYPE_NAND          ((uint32_t)0x00000008)
 547 /**
 548   * @}
 549   */
 550
 551 /** @defgroup FMC_NAND_Data_Width
 552   * @{
 553   */
 554 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000)
 555 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16               ((uint32_t)0x00000010)
 556
 557 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
 558                                          ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
 559 /**
 560   * @}
 561   */
 562
 563 /** @defgroup FMC_ECC
 564   * @{
 565   */
 566 #define FMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000)
 567 #define FMC_NAND_ECC_ENABLE                     ((uint32_t)0x00000040)
 568
 569 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
 570                                  ((STATE) == FMC_NAND_ECC_ENABLE))
 571 /**
 572   * @}
 573   */
 574
 575 /** @defgroup FMC_ECC_Page_Size
 576   * @{
 577   */
 578 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000)
 579 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)0x00020000)
 580 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)0x00040000)
 581 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)0x00060000)
 582 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)0x00080000)
 583 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)0x000A0000)
 584
 585 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
 586                                    ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
 587                                    ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
 588                                    ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
 589                                    ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
 590                                    ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
 591 /**
 592   * @}
 593   */
 594
 595 /** @defgroup FMC_TCLR_Setup_Time
 596   * @{
 597   */
 598 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
 599 /**
 600   * @}
 601   */
 602
 603 /** @defgroup FMC_TAR_Setup_Time
 604   * @{
 605   */
 606 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
 607 /**
 608   * @}
 609   */
 610
 611 /** @defgroup FMC_Setup_Time
 612   * @{
 613   */
 614 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
 615 /**
 616   * @}
 617   */
 618
 619 /** @defgroup FMC_Wait_Setup_Time
 620   * @{
 621   */
 622 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
 623 /**
 624   * @}
 625   */
 626
 627 /** @defgroup FMC_Hold_Setup_Time
 628   * @{
 629   */
 630 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
 631 /**
 632   * @}
 633   */
 634
 635 /** @defgroup FMC_HiZ_Setup_Time
 636   * @{
 637   */
 638 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
 639 /**
 640   * @}
 641   */
 642
 643 /**
 644   * @}
 645   */
 646
 647 /** @defgroup FMC_NORSRAM_Device_Instance
 648   * @{
 649   */
 650 #define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
 651 /**
 652   * @}
 653   */
 654
 655 /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
 656   * @{
 657   */
 658 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
 659 /**
 660   * @}
 661   */
 662
 663 /** @defgroup FMC_NAND_Device_Instance
 664   * @{
 665   */
 666 #define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
 667 /**
 668   * @}
 669   */
 670
 671 /** @defgroup FMC_PCCARD_Device_Instance
 672   * @{
 673   */
 674 #define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
 675
 676 /**
 677   * @}
 678   */
 679
 680 /** @defgroup FMC_Interrupt_definition
 681   * @brief FMC Interrupt definition
 682   * @{
 683   */
 684 #define FMC_IT_RISING_EDGE                ((uint32_t)0x00000008)
 685 #define FMC_IT_LEVEL                      ((uint32_t)0x00000010)
 686 #define FMC_IT_FALLING_EDGE               ((uint32_t)0x00000020)
 687 #define FMC_IT_REFRESH_ERROR              ((uint32_t)0x00004000)
 688
 689 #define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
 690
 691 #define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE)   || \
 692                            ((IT) == FMC_IT_LEVEL)         || \
 693                            ((IT) == FMC_IT_FALLING_EDGE)  || \
 694                            ((IT) == FMC_IT_REFRESH_ERROR))
 695 /**
 696   * @}
 697   */
 698
 699 /** @defgroup FMC_Flag_definition
 700   * @brief FMC Flag definition
 701   * @{
 702   */
 703 #define FMC_FLAG_RISING_EDGE                    ((uint32_t)0x00000001)
 704 #define FMC_FLAG_LEVEL                          ((uint32_t)0x00000002)
 705 #define FMC_FLAG_FALLING_EDGE                   ((uint32_t)0x00000004)
 706 #define FMC_FLAG_FEMPT                          ((uint32_t)0x00000040)
 707
 708 #define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE)      || \
 709                                ((FLAG) == FMC_FLAG_LEVEL)            || \
 710                                ((FLAG) == FMC_FLAG_FALLING_EDGE)     || \
 711                                ((FLAG) == FMC_FLAG_FEMPT))
 712
 713 #define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
 714 /**
 715   * @}
 716   */
 717
 718 /* Exported macro ------------------------------------------------------------*/
 719
 720 /** @defgroup FMC_NOR_Macros
 721  *  @brief macros to handle NOR device enable/disable and read/write operations
 722  *  @{
 723  */
 724
 725 /**
 726   * @brief  Enable the NORSRAM device access.
 727   * @param  __INSTANCE__: FMC_NORSRAM Instance
 728   * @param  __BANK__: FMC_NORSRAM Bank
 729   * @retval None
 730   */
 731 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
 732
 733 /**
 734   * @brief  Disable the NORSRAM device access.
 735   * @param  __INSTANCE__: FMC_NORSRAM Instance
 736   * @param  __BANK__: FMC_NORSRAM Bank
 737   * @retval None
 738   */
 739 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
 740
 741 /**
 742   * @}
 743   */
 744
 745 /** @defgroup FMC_NAND_Macros
 746  *  @brief macros to handle NAND device enable/disable
 747  *  @{
 748  */
 749
 750 /**
 751   * @brief  Enable the NAND device access.
 752   * @param  __INSTANCE__: FMC_NAND Instance
 753   * @param  __BANK__: FMC_NAND Bank
 754   * @retval None
 755   */
 756 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__)  (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
 757                                                     ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
 758
 759 /**
 760   * @brief  Disable the NAND device access.
 761   * @param  __INSTANCE__: FMC_NAND Instance
 762   * @param  __BANK__: FMC_NAND Bank
 763   * @retval None
 764   */
 765 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
 766                                                    ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
 767 /**
 768   * @}
 769   */
 770
 771 /** @defgroup FMC_PCCARD_Macros
 772  *  @brief macros to handle SRAM read/write operations
 773  *  @{
 774  */
 775
 776 /**
 777   * @brief  Enable the PCCARD device access.
 778   * @param  __INSTANCE__: FMC_PCCARD Instance
 779   * @retval None
 780   */
 781 #define __FMC_PCCARD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
 782
 783 /**
 784   * @brief  Disable the PCCARD device access.
 785   * @param  __INSTANCE__: FMC_PCCARD Instance
 786   * @retval None
 787   */
 788 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
 789 /**
 790   * @}
 791   */
 792
 793 /** @defgroup FMC_Interrupt
 794  *  @brief macros to handle FMC interrupts
 795  * @{
 796  */
 797
 798 /**
 799   * @brief  Enable the NAND device interrupt.
 800   * @param  __INSTANCE__:  FMC_NAND Instance
 801   * @param  __BANK__:      FMC_NAND Bank
 802   * @param  __INTERRUPT__: FMC_NAND interrupt
 803   *         This parameter can be any combination of the following values:
 804   *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
 805   *            @arg FMC_IT_LEVEL: Interrupt level.
 806   *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
 807   * @retval None
 808   */
 809 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
 810                                                                                                       ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
 811
 812 /**
 813   * @brief  Disable the NAND device interrupt.
 814   * @param  __INSTANCE__:  FMC_NAND Instance
 815   * @param  __BANK__:      FMC_NAND Bank
 816   * @param  __INTERRUPT__: FMC_NAND interrupt
 817   *         This parameter can be any combination of the following values:
 818   *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
 819   *            @arg FMC_IT_LEVEL: Interrupt level.
 820   *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
 821   * @retval None
 822   */
 823 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
 824                                                                                                       ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
 825
 826 /**
 827   * @brief  Get flag status of the NAND device.
 828   * @param  __INSTANCE__: FMC_NAND Instance
 829   * @param  __BANK__:     FMC_NAND Bank
 830   * @param  __FLAG__: FMC_NAND flag
 831   *         This parameter can be any combination of the following values:
 832   *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
 833   *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
 834   *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
 835   *            @arg FMC_FLAG_FEMPT: FIFO empty flag.
 836   * @retval The state of FLAG (SET or RESET).
 837   */
 838 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
 839                                                                                                 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
 840 /**
 841   * @brief  Clear flag status of the NAND device.
 842   * @param  __INSTANCE__: FMC_NAND Instance
 843   * @param  __BANK__:     FMC_NAND Bank
 844   * @param  __FLAG__: FMC_NAND flag
 845   *         This parameter can be any combination of the following values:
 846   *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
 847   *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
 848   *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
 849   *            @arg FMC_FLAG_FEMPT: FIFO empty flag.
 850   * @retval None
 851   */
 852 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
 853                                                                                                   ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
 854 /**
 855   * @brief  Enable the PCCARD device interrupt.
 856   * @param  __INSTANCE__: FMC_PCCARD Instance
 857   * @param  __INTERRUPT__: FMC_PCCARD interrupt
 858   *         This parameter can be any combination of the following values:
 859   *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
 860   *            @arg FMC_IT_LEVEL: Interrupt level.
 861   *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
 862   * @retval None
 863   */
 864 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
 865
 866 /**
 867   * @brief  Disable the PCCARD device interrupt.
 868   * @param  __INSTANCE__: FMC_PCCARD Instance
 869   * @param  __INTERRUPT__: FMC_PCCARD interrupt
 870   *         This parameter can be any combination of the following values:
 871   *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
 872   *            @arg FMC_IT_LEVEL: Interrupt level.
 873   *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
 874   * @retval None
 875   */
 876 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
 877
 878 /**
 879   * @brief  Get flag status of the PCCARD device.
 880   * @param  __INSTANCE__: FMC_PCCARD Instance
 881   * @param  __FLAG__: FMC_PCCARD flag
 882   *         This parameter can be any combination of the following values:
 883   *            @arg  FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
 884   *            @arg  FMC_FLAG_LEVEL: Interrupt level edge flag.
 885   *            @arg  FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
 886   *            @arg  FMC_FLAG_FEMPT: FIFO empty flag.
 887   * @retval The state of FLAG (SET or RESET).
 888   */
 889 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
 890
 891 /**
 892   * @brief  Clear flag status of the PCCARD device.
 893   * @param  __INSTANCE__: FMC_PCCARD Instance
 894   * @param  __FLAG__: FMC_PCCARD flag
 895   *         This parameter can be any combination of the following values:
 896   *            @arg  FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
 897   *            @arg  FMC_FLAG_LEVEL: Interrupt level edge flag.
 898   *            @arg  FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
 899   *            @arg  FMC_FLAG_FEMPT: FIFO empty flag.
 900   * @retval None
 901   */
 902 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SR4 &= ~(__FLAG__))
 903
 904 /**
 905   * @}
 906   */
 907
 908 /* Exported functions --------------------------------------------------------*/
 909
 910 /* FMC_NORSRAM Controller functions *******************************************/
 911 /* Initialization/de-initialization functions */
 912 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
 913 HAL_StatusTypeDef  FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
 914 HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
 915 HAL_StatusTypeDef  FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
 916
 917 /* FMC_NORSRAM Control functions */
 918 HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
 919 HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
 920
 921 /* FMC_NAND Controller functions **********************************************/
 922 /* Initialization/de-initialization functions */
 923 HAL_StatusTypeDef  FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
 924 HAL_StatusTypeDef  FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
 925 HAL_StatusTypeDef  FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
 926 HAL_StatusTypeDef  FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
 927
 928 /* FMC_NAND Control functions */
 929 HAL_StatusTypeDef  FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
 930 HAL_StatusTypeDef  FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
 931 HAL_StatusTypeDef  FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
 932
 933 /* FMC_PCCARD Controller functions ********************************************/
 934 /* Initialization/de-initialization functions */
 935 HAL_StatusTypeDef  FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
 936 HAL_StatusTypeDef  FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
 937 HAL_StatusTypeDef  FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
 938 HAL_StatusTypeDef  FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
 939 HAL_StatusTypeDef  FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
 940
 941 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
 942 /**
 943   * @}
 944   */
 945
 946 /**
 947   * @}
 948   */
 949
 950 #ifdef __cplusplus
 951 }
 952 #endif
 953
 954 #endif /* __STM32F3xx_LL_FMC_H */
 955
 956 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/