2 ******************************************************************************
3 * @file system_stm32f3xx.c
4 * @author MCD Application Team
7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
9 * 1. This file provides two functions and one global variable to be called from
11 * - SystemInit(): This function is called at startup just after reset and
12 * before branch to main program. This call is made inside
13 * the "startup_stm32f3xx.s" file.
15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
16 * by the user application to setup the SysTick
17 * timer or configure other parameters.
19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
20 * be called whenever the core clock is changed
21 * during program execution.
23 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
24 * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
25 * configure the system clock before to branch to main program.
27 * 3. This file configures the system clock as follows:
28 *-----------------------------------------------------------------------------
29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
30 * | (external 8 MHz clock) | (internal 8 MHz)
32 * | (external 8 MHz xtal) |
33 *-----------------------------------------------------------------------------
34 * SYSCLK(MHz) | 72 | 64
35 *-----------------------------------------------------------------------------
36 * AHBCLK (MHz) | 72 | 64
37 *-----------------------------------------------------------------------------
38 * APB1CLK (MHz) | 36 | 32
39 *-----------------------------------------------------------------------------
40 * APB2CLK (MHz) | 72 | 64
41 *-----------------------------------------------------------------------------
42 * USB capable (48 MHz precise clock) | NO | NO
43 *-----------------------------------------------------------------------------
44 ******************************************************************************
47 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
49 * Redistribution and use in source and binary forms, with or without modification,
50 * are permitted provided that the following conditions are met:
51 * 1. Redistributions of source code must retain the above copyright notice,
52 * this list of conditions and the following disclaimer.
53 * 2. Redistributions in binary form must reproduce the above copyright notice,
54 * this list of conditions and the following disclaimer in the documentation
55 * and/or other materials provided with the distribution.
56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
57 * may be used to endorse or promote products derived from this software
58 * without specific prior written permission.
60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
71 ******************************************************************************
78 /** @addtogroup stm32f3xx_system
82 /** @addtogroup STM32F3xx_System_Private_Includes
86 #include "stm32f3xx.h"
89 #include "stm32f3xx_hal.h"
95 /** @addtogroup STM32F3xx_System_Private_TypesDefinitions
103 /** @addtogroup STM32F3xx_System_Private_Defines
106 #if !defined (HSE_VALUE)
107 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
108 This value can be provided and adapted by the user application. */
109 #endif /* HSE_VALUE */
111 #if !defined (HSI_VALUE)
112 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
113 This value can be provided and adapted by the user application. */
114 #endif /* HSI_VALUE */
116 /*!< Uncomment the following line if you need to relocate your vector Table in
118 /* #define VECT_TAB_SRAM */
119 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
120 This value must be a multiple of 0x200. */
125 /** @addtogroup STM32F3xx_System_Private_Macros
129 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
130 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
131 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
137 /** @addtogroup STM32F3xx_System_Private_Variables
140 /* This variable is updated in three ways:
141 1) by calling CMSIS function SystemCoreClockUpdate()
142 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
143 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
144 Note: If you use this function to configure the system clock there is no need to
145 call the 2 first functions listed above, since SystemCoreClock variable is
146 updated automatically.
148 uint32_t SystemCoreClock = 72000000;
149 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
155 /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
159 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
160 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
163 uint8_t SetSysClock_PLL_HSI(void);
169 /** @addtogroup STM32F3xx_System_Private_Functions
174 * @brief Setup the microcontroller system
175 * Initialize the FPU setting, vector table location and the PLL configuration is reset.
179 void SystemInit(void)
181 /* FPU settings ------------------------------------------------------------*/
182 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
183 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
186 /* Reset the RCC clock configuration to the default reset state ------------*/
188 RCC->CR |= (uint32_t)0x00000001;
190 /* Reset CFGR register */
191 RCC->CFGR &= 0xF87FC00C;
193 /* Reset HSEON, CSSON and PLLON bits */
194 RCC->CR &= (uint32_t)0xFEF6FFFF;
196 /* Reset HSEBYP bit */
197 RCC->CR &= (uint32_t)0xFFFBFFFF;
199 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
200 RCC->CFGR &= (uint32_t)0xFF80FFFF;
202 /* Reset PREDIV1[3:0] bits */
203 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
205 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
206 RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
208 /* Disable all interrupts */
209 RCC->CIR = 0x00000000;
212 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
214 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
217 /* Configure the Cube driver */
218 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
221 /* Configure the System clock source, PLL Multiplier and Divider factors,
222 AHB/APBx prescalers and Flash settings */
225 /* Reset the timer to avoid issues after the RAM initialization */
231 * @brief Update SystemCoreClock variable according to Clock Register Values.
232 * The SystemCoreClock variable contains the core clock (HCLK), it can
233 * be used by the user application to setup the SysTick timer or configure
236 * @note Each time the core clock (HCLK) changes, this function must be called
237 * to update SystemCoreClock variable value. Otherwise, any configuration
238 * based on this variable will be incorrect.
240 * @note - The system frequency computed by this function is not the real
241 * frequency in the chip. It is calculated based on the predefined
242 * constant and the selected clock source:
244 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
246 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
248 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
249 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
251 * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
252 * 8 MHz) but the real value may vary depending on the variations
253 * in voltage and temperature.
255 * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
256 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
257 * frequency of the crystal used. Otherwise, this function may
260 * - The result of this function could be not correct when using fractional
261 * value for HSE crystal.
266 void SystemCoreClockUpdate (void)
268 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
270 /* Get SYSCLK source -------------------------------------------------------*/
271 tmp = RCC->CFGR & RCC_CFGR_SWS;
275 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
276 SystemCoreClock = HSI_VALUE;
278 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
279 SystemCoreClock = HSE_VALUE;
281 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
282 /* Get PLL clock source and multiplication factor ----------------------*/
283 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
284 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
285 pllmull = ( pllmull >> 18) + 2;
287 #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
288 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
289 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
291 /* HSE oscillator clock selected as PREDIV1 clock entry */
292 SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
296 /* HSI oscillator clock selected as PREDIV1 clock entry */
297 SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
300 if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
302 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
303 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
307 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
308 /* HSE oscillator clock selected as PREDIV1 clock entry */
309 SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
311 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
313 default: /* HSI used as system clock */
314 SystemCoreClock = HSI_VALUE;
317 /* Compute HCLK clock frequency ----------------*/
318 /* Get HCLK prescaler */
319 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
320 /* HCLK clock frequency */
321 SystemCoreClock >>= tmp;
325 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
326 * AHB/APBx prescalers and Flash settings
327 * @note This function should be called only once the RCC clock configuration
328 * is reset to the default reset state (done in SystemInit() function).
332 void SetSysClock(void)
334 /* 1- Try to start with HSE and external clock */
335 #if USE_PLL_HSE_EXTC != 0
336 if (SetSysClock_PLL_HSE(1) == 0)
339 /* 2- If fail try to start with HSE and external xtal */
340 #if USE_PLL_HSE_XTAL != 0
341 if (SetSysClock_PLL_HSE(0) == 0)
344 /* 3- If fail start with HSI clock */
345 if (SetSysClock_PLL_HSI() == 0)
349 // [TODO] Put something here to tell the user that a problem occured...
355 /* Output clock on MCO1 pin(PA8) for debugging purpose */
356 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
359 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
360 /******************************************************************************/
361 /* PLL (clocked by HSE) used as System clock source */
362 /******************************************************************************/
363 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
365 RCC_ClkInitTypeDef RCC_ClkInitStruct;
366 RCC_OscInitTypeDef RCC_OscInitStruct;
368 /* Enable HSE oscillator and activate PLL with HSE as source */
369 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
372 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
376 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
378 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
379 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
380 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
381 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
382 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
387 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
388 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
389 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
390 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
391 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
392 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
393 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
398 /* Output clock on MCO1 pin(PA8) for debugging purpose */
400 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
402 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
408 /******************************************************************************/
409 /* PLL (clocked by HSI) used as System clock source */
410 /******************************************************************************/
411 uint8_t SetSysClock_PLL_HSI(void)
413 RCC_ClkInitTypeDef RCC_ClkInitStruct;
414 RCC_OscInitTypeDef RCC_OscInitStruct;
416 /* Enable HSI oscillator and activate PLL with HSI as source */
417 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
418 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
419 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
420 RCC_OscInitStruct.HSICalibrationValue = 16;
421 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
422 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
423 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
424 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
429 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
430 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
431 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
432 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz
433 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz
434 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
435 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
440 /* Output clock on MCO1 pin(PA8) for debugging purpose */
441 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/