2 *************** (C) COPYRIGHT 2014 STMicroelectronics ************************
3 * @file startup_stm32f100xb.s
4 * @author MCD Application Team
6 * @date 16-December-2014
7 * @brief STM32F100xB Devices vector table for Atollic toolchain.
8 * This module performs:
10 * - Set the initial PC == Reset_Handler,
11 * - Set the vector table entries with the exceptions ISR address
12 * - Configure the clock system
13 * - Branches to main in the C library (which eventually
15 * After Reset the Cortex-M3 processor is in Thread mode,
16 * priority is Privileged, and the Stack is set to Main.
17 ******************************************************************************
19 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
21 * Redistribution and use in source and binary forms, with or without modification,
22 * are permitted provided that the following conditions are met:
23 * 1. Redistributions of source code must retain the above copyright notice,
24 * this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright notice,
26 * this list of conditions and the following disclaimer in the documentation
27 * and/or other materials provided with the distribution.
28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
29 * may be used to endorse or promote products derived from this software
30 * without specific prior written permission.
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ******************************************************************************
52 .global Default_Handler
54 /* start address for the initialization values of the .data section.
55 defined in linker script */
57 /* start address for the .data section. defined in linker script */
59 /* end address for the .data section. defined in linker script */
61 /* start address for the .bss section. defined in linker script */
63 /* end address for the .bss section. defined in linker script */
66 .equ BootRAM, 0xF108F85F
68 * @brief This is the code that gets called when the processor first
69 * starts execution following a reset event. Only the absolutely
70 * necessary set is performed, after which the application
71 * supplied main() routine is called.
76 .section .text.Reset_Handler
78 .type Reset_Handler, %function
81 /* Copy the data segment initializers from flash to SRAM */
99 /* Zero fill the bss segment. */
109 /* Call the clock system intitialization function.*/
111 /* Call static constructors */
112 /* bl __libc_init_array */
113 /* Call the application's entry point.*/
117 .size Reset_Handler, .-Reset_Handler
120 * @brief This is the code that gets called when the processor receives an
121 * unexpected interrupt. This simply enters an infinite loop, preserving
122 * the system state for examination by a debugger.
127 .section .text.Default_Handler,"ax",%progbits
131 .size Default_Handler, .-Default_Handler
132 /******************************************************************************
134 * The minimal vector table for a Cortex M3. Note that the proper constructs
135 * must be placed on this to ensure that it ends up at physical address
138 ******************************************************************************/
139 .section .isr_vector,"a",%progbits
140 .type g_pfnVectors, %object
141 .size g_pfnVectors, .-g_pfnVectors
148 .word HardFault_Handler
149 .word MemManage_Handler
150 .word BusFault_Handler
151 .word UsageFault_Handler
157 .word DebugMon_Handler
160 .word SysTick_Handler
161 .word WWDG_IRQHandler
163 .word TAMPER_IRQHandler
165 .word FLASH_IRQHandler
167 .word EXTI0_IRQHandler
168 .word EXTI1_IRQHandler
169 .word EXTI2_IRQHandler
170 .word EXTI3_IRQHandler
171 .word EXTI4_IRQHandler
172 .word DMA1_Channel1_IRQHandler
173 .word DMA1_Channel2_IRQHandler
174 .word DMA1_Channel3_IRQHandler
175 .word DMA1_Channel4_IRQHandler
176 .word DMA1_Channel5_IRQHandler
177 .word DMA1_Channel6_IRQHandler
178 .word DMA1_Channel7_IRQHandler
179 .word ADC1_IRQHandler
184 .word EXTI9_5_IRQHandler
185 .word TIM1_BRK_TIM15_IRQHandler
186 .word TIM1_UP_TIM16_IRQHandler
187 .word TIM1_TRG_COM_TIM17_IRQHandler
188 .word TIM1_CC_IRQHandler
189 .word TIM2_IRQHandler
190 .word TIM3_IRQHandler
191 .word TIM4_IRQHandler
192 .word I2C1_EV_IRQHandler
193 .word I2C1_ER_IRQHandler
194 .word I2C2_EV_IRQHandler
195 .word I2C2_ER_IRQHandler
196 .word SPI1_IRQHandler
197 .word SPI2_IRQHandler
198 .word USART1_IRQHandler
199 .word USART2_IRQHandler
200 .word USART3_IRQHandler
201 .word EXTI15_10_IRQHandler
202 .word RTC_Alarm_IRQHandler
215 .word TIM6_DAC_IRQHandler
216 .word TIM7_IRQHandler
260 .word BootRAM /* @0x01CC. This is for boot in RAM mode for
261 STM32F10xB Value Line devices. */
263 /*******************************************************************************
265 * Provide weak aliases for each Exception handler to the Default_Handler.
266 * As they are weak aliases, any function with the same name will override
269 *******************************************************************************/
273 .thumb_set NMI_Handler,Default_Handler
275 .weak HardFault_Handler
276 .thumb_set HardFault_Handler,Default_Handler
278 .weak MemManage_Handler
279 .thumb_set MemManage_Handler,Default_Handler
281 .weak BusFault_Handler
282 .thumb_set BusFault_Handler,Default_Handler
284 .weak UsageFault_Handler
285 .thumb_set UsageFault_Handler,Default_Handler
288 .thumb_set SVC_Handler,Default_Handler
290 .weak DebugMon_Handler
291 .thumb_set DebugMon_Handler,Default_Handler
294 .thumb_set PendSV_Handler,Default_Handler
296 .weak SysTick_Handler
297 .thumb_set SysTick_Handler,Default_Handler
299 .weak WWDG_IRQHandler
300 .thumb_set WWDG_IRQHandler,Default_Handler
303 .thumb_set PVD_IRQHandler,Default_Handler
305 .weak TAMPER_IRQHandler
306 .thumb_set TAMPER_IRQHandler,Default_Handler
309 .thumb_set RTC_IRQHandler,Default_Handler
311 .weak FLASH_IRQHandler
312 .thumb_set FLASH_IRQHandler,Default_Handler
315 .thumb_set RCC_IRQHandler,Default_Handler
317 .weak EXTI0_IRQHandler
318 .thumb_set EXTI0_IRQHandler,Default_Handler
320 .weak EXTI1_IRQHandler
321 .thumb_set EXTI1_IRQHandler,Default_Handler
323 .weak EXTI2_IRQHandler
324 .thumb_set EXTI2_IRQHandler,Default_Handler
326 .weak EXTI3_IRQHandler
327 .thumb_set EXTI3_IRQHandler,Default_Handler
329 .weak EXTI4_IRQHandler
330 .thumb_set EXTI4_IRQHandler,Default_Handler
332 .weak DMA1_Channel1_IRQHandler
333 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
335 .weak DMA1_Channel2_IRQHandler
336 .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
338 .weak DMA1_Channel3_IRQHandler
339 .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
341 .weak DMA1_Channel4_IRQHandler
342 .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
344 .weak DMA1_Channel5_IRQHandler
345 .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
347 .weak DMA1_Channel6_IRQHandler
348 .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
350 .weak DMA1_Channel7_IRQHandler
351 .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
353 .weak ADC1_IRQHandler
354 .thumb_set ADC1_IRQHandler,Default_Handler
356 .weak EXTI9_5_IRQHandler
357 .thumb_set EXTI9_5_IRQHandler,Default_Handler
359 .weak TIM1_BRK_TIM15_IRQHandler
360 .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
362 .weak TIM1_UP_TIM16_IRQHandler
363 .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
365 .weak TIM1_TRG_COM_TIM17_IRQHandler
366 .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
368 .weak TIM1_CC_IRQHandler
369 .thumb_set TIM1_CC_IRQHandler,Default_Handler
371 .weak TIM2_IRQHandler
372 .thumb_set TIM2_IRQHandler,Default_Handler
374 .weak TIM3_IRQHandler
375 .thumb_set TIM3_IRQHandler,Default_Handler
377 .weak TIM4_IRQHandler
378 .thumb_set TIM4_IRQHandler,Default_Handler
380 .weak I2C1_EV_IRQHandler
381 .thumb_set I2C1_EV_IRQHandler,Default_Handler
383 .weak I2C1_ER_IRQHandler
384 .thumb_set I2C1_ER_IRQHandler,Default_Handler
386 .weak I2C2_EV_IRQHandler
387 .thumb_set I2C2_EV_IRQHandler,Default_Handler
389 .weak I2C2_ER_IRQHandler
390 .thumb_set I2C2_ER_IRQHandler,Default_Handler
392 .weak SPI1_IRQHandler
393 .thumb_set SPI1_IRQHandler,Default_Handler
395 .weak SPI2_IRQHandler
396 .thumb_set SPI2_IRQHandler,Default_Handler
398 .weak USART1_IRQHandler
399 .thumb_set USART1_IRQHandler,Default_Handler
401 .weak USART2_IRQHandler
402 .thumb_set USART2_IRQHandler,Default_Handler
404 .weak USART3_IRQHandler
405 .thumb_set USART3_IRQHandler,Default_Handler
407 .weak EXTI15_10_IRQHandler
408 .thumb_set EXTI15_10_IRQHandler,Default_Handler
410 .weak RTC_Alarm_IRQHandler
411 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
414 .thumb_set CEC_IRQHandler,Default_Handler
416 .weak TIM6_DAC_IRQHandler
417 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
419 .weak TIM7_IRQHandler
420 .thumb_set TIM7_IRQHandler,Default_Handler
422 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/