1 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
2 ;* File Name : startup_stm32f091xc.s
3 ;* Author : MCD Application Team
6 ;* Description : STM32F091xc/STM32F098xc devices vector table for EWARM toolchain.
7 ;* This module performs:
8 ;* - Set the initial SP
9 ;* - Set the initial PC == __iar_program_start,
10 ;* - Set the vector table entries with the exceptions ISR
12 ;* - Branches to main in the C library (which eventually
14 ;* After Reset the Cortex-M0 processor is in Thread mode,
15 ;* priority is Privileged, and the Stack is set to Main.
16 ;*******************************************************************************
18 ;* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
20 ;* Redistribution and use in source and binary forms, with or without modification,
21 ;* are permitted provided that the following conditions are met:
22 ;* 1. Redistributions of source code must retain the above copyright notice,
23 ;* this list of conditions and the following disclaimer.
24 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
25 ;* this list of conditions and the following disclaimer in the documentation
26 ;* and/or other materials provided with the distribution.
27 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
28 ;* may be used to endorse or promote products derived from this software
29 ;* without specific prior written permission.
31 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
32 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
35 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
37 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
38 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 ;*******************************************************************************
45 ; The modules in this file are included in the libraries, and may be replaced
46 ; by any user-defined modules that define the PUBLIC symbol _program_start or
47 ; a user defined start symbol.
48 ; To override the cstartup defined in the library, simply add your modified
49 ; version to the workbench project.
51 ; The vector table is normally located at address 0.
52 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
53 ; The name "__vector_table" has special meaning for C-SPY:
54 ; it is where the SP start value is found, and the NVIC vector
55 ; table register (VTOR) is initialized to this address if != 0.
62 ;; Forward declaration of sections.
63 SECTION CSTACK:DATA:NOROOT(3)
65 SECTION .intvec:CODE:NOROOT(2)
67 EXTERN __iar_program_start
74 DCD Reset_Handler ; Reset Handler
76 DCD NMI_Handler ; NMI Handler
77 DCD HardFault_Handler ; Hard Fault Handler
85 DCD SVC_Handler ; SVCall Handler
88 DCD PendSV_Handler ; PendSV Handler
89 DCD SysTick_Handler ; SysTick Handler
92 DCD WWDG_IRQHandler ; Window Watchdog
93 DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect
94 DCD RTC_IRQHandler ; RTC through EXTI Line
95 DCD FLASH_IRQHandler ; FLASH
96 DCD RCC_CRS_IRQHandler ; RCC and CRS
97 DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
98 DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
99 DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
100 DCD TSC_IRQHandler ; TS
101 DCD DMA1_Ch1_IRQHandler ; DMA1 Channel 1
102 DCD DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
103 DCD DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5
104 DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
105 DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
106 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
107 DCD TIM2_IRQHandler ; TIM2
108 DCD TIM3_IRQHandler ; TIM3
109 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
110 DCD TIM7_IRQHandler ; TIM7
111 DCD TIM14_IRQHandler ; TIM14
112 DCD TIM15_IRQHandler ; TIM15
113 DCD TIM16_IRQHandler ; TIM16
114 DCD TIM17_IRQHandler ; TIM17
115 DCD I2C1_IRQHandler ; I2C1
116 DCD I2C2_IRQHandler ; I2C2
117 DCD SPI1_IRQHandler ; SPI1
118 DCD SPI2_IRQHandler ; SPI2
119 DCD USART1_IRQHandler ; USART1
120 DCD USART2_IRQHandler ; USART2
121 DCD USART3_8_IRQHandler ; USART3, USART4, USART5, USART6, USART7, USART8
122 DCD CEC_CAN_IRQHandler ; CEC and CAN
124 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
126 ;; Default interrupt handlers.
130 PUBWEAK Reset_Handler
131 SECTION .text:CODE:NOROOT:REORDER(2)
135 LDR R0, =__iar_program_start
139 SECTION .text:CODE:NOROOT:REORDER(1)
143 PUBWEAK HardFault_Handler
144 SECTION .text:CODE:NOROOT:REORDER(1)
149 SECTION .text:CODE:NOROOT:REORDER(1)
153 PUBWEAK PendSV_Handler
154 SECTION .text:CODE:NOROOT:REORDER(1)
158 PUBWEAK SysTick_Handler
159 SECTION .text:CODE:NOROOT:REORDER(1)
163 PUBWEAK WWDG_IRQHandler
164 SECTION .text:CODE:NOROOT:REORDER(1)
168 PUBWEAK PVD_VDDIO2_IRQHandler
169 SECTION .text:CODE:NOROOT:REORDER(1)
170 PVD_VDDIO2_IRQHandler
171 B PVD_VDDIO2_IRQHandler
173 PUBWEAK RTC_IRQHandler
174 SECTION .text:CODE:NOROOT:REORDER(1)
178 PUBWEAK FLASH_IRQHandler
179 SECTION .text:CODE:NOROOT:REORDER(1)
183 PUBWEAK RCC_CRS_IRQHandler
184 SECTION .text:CODE:NOROOT:REORDER(1)
188 PUBWEAK EXTI0_1_IRQHandler
189 SECTION .text:CODE:NOROOT:REORDER(1)
193 PUBWEAK EXTI2_3_IRQHandler
194 SECTION .text:CODE:NOROOT:REORDER(1)
198 PUBWEAK EXTI4_15_IRQHandler
199 SECTION .text:CODE:NOROOT:REORDER(1)
201 B EXTI4_15_IRQHandler
203 PUBWEAK TSC_IRQHandler
204 SECTION .text:CODE:NOROOT:REORDER(1)
208 PUBWEAK DMA1_Ch1_IRQHandler
209 SECTION .text:CODE:NOROOT:REORDER(1)
211 B DMA1_Ch1_IRQHandler
213 PUBWEAK DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
214 SECTION .text:CODE:NOROOT:REORDER(1)
215 DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
216 B DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
218 PUBWEAK DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
219 SECTION .text:CODE:NOROOT:REORDER(1)
220 DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
221 B DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
223 PUBWEAK ADC1_COMP_IRQHandler
224 SECTION .text:CODE:NOROOT:REORDER(1)
226 B ADC1_COMP_IRQHandler
228 PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
229 SECTION .text:CODE:NOROOT:REORDER(1)
230 TIM1_BRK_UP_TRG_COM_IRQHandler
231 B TIM1_BRK_UP_TRG_COM_IRQHandler
233 PUBWEAK TIM1_CC_IRQHandler
234 SECTION .text:CODE:NOROOT:REORDER(1)
238 PUBWEAK TIM2_IRQHandler
239 SECTION .text:CODE:NOROOT:REORDER(1)
243 PUBWEAK TIM3_IRQHandler
244 SECTION .text:CODE:NOROOT:REORDER(1)
248 PUBWEAK TIM6_DAC_IRQHandler
249 SECTION .text:CODE:NOROOT:REORDER(1)
251 B TIM6_DAC_IRQHandler
253 PUBWEAK TIM7_IRQHandler
254 SECTION .text:CODE:NOROOT:REORDER(1)
258 PUBWEAK TIM14_IRQHandler
259 SECTION .text:CODE:NOROOT:REORDER(1)
263 PUBWEAK TIM15_IRQHandler
264 SECTION .text:CODE:NOROOT:REORDER(1)
268 PUBWEAK TIM16_IRQHandler
269 SECTION .text:CODE:NOROOT:REORDER(1)
273 PUBWEAK TIM17_IRQHandler
274 SECTION .text:CODE:NOROOT:REORDER(1)
278 PUBWEAK I2C1_IRQHandler
279 SECTION .text:CODE:NOROOT:REORDER(1)
283 PUBWEAK I2C2_IRQHandler
284 SECTION .text:CODE:NOROOT:REORDER(1)
288 PUBWEAK SPI1_IRQHandler
289 SECTION .text:CODE:NOROOT:REORDER(1)
293 PUBWEAK SPI2_IRQHandler
294 SECTION .text:CODE:NOROOT:REORDER(1)
298 PUBWEAK USART1_IRQHandler
299 SECTION .text:CODE:NOROOT:REORDER(1)
303 PUBWEAK USART2_IRQHandler
304 SECTION .text:CODE:NOROOT:REORDER(1)
308 PUBWEAK USART3_8_IRQHandler
309 SECTION .text:CODE:NOROOT:REORDER(1)
311 B USART3_8_IRQHandler
313 PUBWEAK CEC_CAN_IRQHandler
314 SECTION .text:CODE:NOROOT:REORDER(1)
319 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****